JP2003224098A - Design method of wiring, program and recording medium which records the program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To propose a model wherein influence of dishing and erosion is considered as a simulation model which is to be used when a wiring of damascene structure is formed, by embedding wiring material in a trench for wiring which is formed on an insulating film and polishing the whole body. <P>SOLUTION: Thickness of the insulating film and thickness of a wiring film are calculated respectively in each calculation unit region defined on a chip, and mean film thickness is obtained by calculating weighted average of the thickness of the insulating film and the thickness of the wiring film. Response film thickness is obtained by superposition of the mean film thickness and a prescribed stress response function. Polishing speed of a wiring is obtained as a value wherein a value in which the response film thickness is subtracted from the thickness of the wiring is multiplied by a constant, and polishing speed of the insulating film is obtained as a value wherein a value in which the response film thickness is subtracted from the thickness of the insulating film is multiplied by a constant. On the basis of the obtained respective polishing speeds, dishing amount of the wiring and erosion amount of the insulating film are calculated, and arrangement of a dummy pattern which optimizes values of dishing amount and erosion amount is determined. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to CMP (Chemical).
Mechanical Polishing: A method for designing a dummy pattern required when forming a damascene structure wiring, a design program for implementing the method, and a computer-readable recording medium recording the program .

[0002]

2. Description of the Related Art In recent years, with the miniaturization of semiconductor devices,
CMP technology has come to be used in many processes in the manufacturing process. Since local planarization is easy in CMP, it is used not only for polishing an interlayer film of a multilayer wiring but also for polishing a wiring metal and an oxide film in an STI (Shallow Trench Isolation) process. However, on the other hand, it has been pointed out that a surface step called a global step remains when the pattern density to be polished is non-uniform.

In the copper wiring process, which has become increasingly important in recent years, the CMP technique is used when forming a so-called damascene structure. Two problems have been pointed out in addition to the above-mentioned problem of the global step in CMP when forming a damascene structure. The first problem is that when polishing a wide copper wiring, the central portion of the wiring is excessively cut, which is generally called dishing. Another problem is that in a pattern with a constant line / space, not only the wiring portion but also the interlayer film becomes thin,
Generally called erosion.

As a method for solving the problem of global step difference, a dummy pattern having no function as a wiring is formed separately from the wiring pattern on the wiring layer to make the pattern density uniform, thereby flattening after polishing. There is known a method of improving the sex.

The problems of dishing and erosion are unique to the copper wiring process and require different simulation models. For a simulation model that takes into account the effects of dishing and erosion, see Tamba Tugbawa et al.
tical Model of Pattern Dependencies in Cu CMP Proc
esses ”, CMP Symposium, Electrochemical Society Me
There is a method presented in eting, Honolulu, HA, Oct. 1999. This method obtains an effective pattern density by superimposing a predetermined filter function on the pattern density of a polishing object, and the polishing rate in the CMP process of copper wiring is inversely proportional to the effective density. This is a method of estimating the dishing speed and the erosion speed.

[0006]

In the conventional simulation model for the copper wiring process, the polishing rate in the CMP process is calculated as changing exponentially with respect to the polishing time. However, since a temporal change in the polishing rate when the polishing of the interlayer film is started is not taken into consideration, a large error may occur in the estimation of dishing and erosion.

The present invention proposes a new simulation model for a copper wiring process in order to solve such a problem.

[0008]

The method and program of the present invention are a method of designing a damascene structure wiring formed by embedding a wiring material in a wiring groove formed on an insulating film and polishing the whole. Therefore, in each calculation unit area defined on the chip, the insulating film thickness that represents the height from the predetermined reference surface to the polished surface of the insulating film, and the height from the reference surface to the polished surface of the wiring. The thickness of the wiring is calculated and the average thickness is obtained by weighted averaging the thickness of the insulating film and the thickness of the wiring, and the polishing pad is deformed by superimposing the average thickness and a predetermined stress response function. Then, the polishing rate of the wiring is determined by multiplying a value obtained by subtracting the response thickness from the thickness of the wiring by a constant, and the polishing rate of the insulating film is set to the polishing rate of the insulating film. Value obtained by subtracting the response film thickness from the thickness Obtained as a value multiplied by a constant, based on each polishing rate obtained, calculates the dishing amount of the wiring and the erosion amount of the insulating film, and a dummy pattern for optimizing the values of the dishing amount and the erosion amount Is determined.

It is more preferable that the optimization is performed so that the difference between the insulating film thickness and the wiring film thickness is kept below a predetermined value in each calculation unit area.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be described below.
Will be described with reference to the drawings. First, the "membrane
Explain the definition of the word "thickness". In this specification
For convenience of explanation, in order to express the step of the polishing surface,
Use the term "film thickness". In other words, "membrane
The word "thickness" means the thickness of the film in a strict sense.
Not as a distance from the given reference surface to the polishing surface
Used as a word for (height). For example, in FIG.
A wiring groove 21 is formed in the insulating film 20, and a wiring material is formed on the wiring groove 21.
After forming 19 (copper or the like), polishing is performed to form an insulating film 20.
FIG. 6 is a cross-sectional view of a chip showing a state in which is exposed. In this figure
If the reference plane is plane X, the film thickness at point A is h
_aAnd the film thickness at point B is h_bIs. Also, the reference plane
Is not limited to plane X in FIG. 6 and can be any plane.
It

First Embodiment FIG. 1 is a flow chart showing an outline of a dummy pattern designing method and program processing according to an embodiment of the present invention. First, the pattern density of the copper wiring before placing the dummy pattern is calculated (S101). Next, the CMP simulation is executed based on the pattern density to calculate the film thickness when the CMP is performed without forming the dummy pattern (S102). As a result of evaluating the surface step, dishing, and erosion amount of the polishing surface based on the simulation result (S103), if those values are within the allowable range, it is not necessary to add the dummy pattern, and thus the original layout data is unchanged. It becomes the final layout data (S
105). On the other hand, when those values are not within the allowable range, the value of the pattern density is corrected (S104), and the simulation evaluation is performed again based on the corrected value (S102, S103). The same process is repeated until those values are within the allowable range, and the pattern density at the time when the values are finally within the allowable range is determined as the pattern density after the dummy pattern is formed. Further, final layout data in which dummy patterns of a predetermined shape (for example, mesh shape) are arranged so that the pattern density becomes the determined pattern density is generated (S105).

The above is the overall flow of the processing. Next, the pattern density correction processing (S104) will be further described. FIG. 2 is a block diagram showing the structure of a design program for implementing the above method. In FIG. 2, the pattern density calculation means 2 is a means (means for executing step S101) for calculating the density of the wiring pattern before the dummy pattern arrangement based on the layout data 1.
The CMP simulation means 3 is means for performing the simulation of step S102, and the surface step / dishing amount / erosion amount evaluation means 4 is means for determining whether or not each amount is within an allowable range (means for executing step S103). ), And the layout data correction means 5 is
This is means for modifying the original layout data 1 to generate modified layout data in which dummy patterns are added (means for executing step S105). Also,
The means surrounded by the frame 6 in FIG. 2 corresponds to the means for correcting the pattern density (means for executing step S104).

The means 6 for modifying the pattern density is
By the dummy pattern allowable area extracting means 7 for extracting the dummy pattern allowable area based on the layout data 1, the allowable pattern density calculating means 8 for calculating the allowable pattern density based on the extracted dummy pattern allowable area, and the evaluating means 4. When it is determined that the surface level difference, the dishing amount, or the erosion amount is not within the allowable range, the target film that sets the target copper wiring film thickness and the interlayer film thickness based on the simulation result of the judgment The thickness setting means 11, the proper pattern density calculating means 9 for obtaining the proper pattern density from the set target film thickness, the allowable pattern density obtained by the allowable pattern density calculating means 8 and the proper pattern density calculating means 9 are obtained. The corrected pattern density is determined based on the appropriate pattern density and the CM
The correction pattern density determination means 10 is transferred to the P simulation means 3.

Here, the "dummy pattern allowable area" means an area which does not adversely affect the function of the semiconductor device even if a dummy pattern is formed in that area. That is, it means a region in which the inter-wiring capacitance generated between the dummy pattern formed in that region and the original wiring pattern is sufficiently small. The “dummy pattern allowable area” can be extracted based on the layout data 1. The "allowable pattern density" refers to the pattern density when as many dummy patterns as possible are formed within a range that does not affect the function of the semiconductor device. In other words, it is the pattern density when the dummy patterns are formed so as to fill the “dummy pattern allowable area”. The “allowable pattern density” can be obtained based on the extraction result of the “dummy pattern allowable area”. Further, the “appropriate pattern density” refers to an appropriate pattern density in performing CMP flattening. In other words, the pattern density is determined so that the surface level difference of the polished surface is simply within the allowable range without considering the problem of the capacitance between wirings at all. In the present embodiment, the “appropriate pattern density” is not calculated from the layout data 1, but is calculated by back calculation from the set target film thickness. At this time, the target film thickness is set based on the result of the CMP simulation so that the surface step of the polished surface, the dishing amount, and the erosion amount are reduced.

In the present embodiment, the corrected pattern density determining means 10 compares the allowable pattern density with the appropriate pattern density, and if the appropriate pattern density is less than the allowable pattern density, the appropriate pattern density is set as the corrected pattern density, If the proper pattern density is higher, the allowable pattern density is set as the corrected pattern density. That is, the corrected pattern density may be set to the proper pattern density in order to bring the surface step of the polished surface within the allowable range. However, when the proper pattern density is larger than the permitted pattern density, problems such as inter-wiring capacitance may occur. Therefore, priority is given to avoiding problems, and the allowable pattern density is adopted. The determined corrected pattern density is input to the CMP simulation means 3, and the CMP simulation is executed again.

The overall flow of the processing of the present invention and the processing executed by each processing step or each means have been described above. Next, the specific calculation processing will be described in more detail.

FIG. 3 is a diagram for explaining an example of a chip layout and a pattern density calculation method. The above-mentioned pattern density calculation and CMP simulation are shown in FIG.
As shown in FIG. 5, a region 12 (hereinafter, referred to as a calculation unit region) having a predetermined size which is a unit of calculation is defined on the LSI chip 1 and is executed for each calculation unit region. In this embodiment, the actual size is 100 μm × 100.
The area of μm is used as the calculation unit area. However, since the size of the calculation unit area is only one of the design matters, it may be a larger (or smaller) area. In the following description, each calculation unit area is represented by a symbol i = 1, 2, 3, ..., For example, the pattern density ρ of the calculation unit area _i is represented by ρ _i .

First, the processing of the pattern density calculation means 2 of FIG. 2 will be described. The pattern density can be obtained as the area ratio of the region representing the wiring. For example, as shown in FIG. 3, in the case of a layout in which six wirings 13 are arranged, the pattern density of this calculation unit area 12 is obtained by calculating the total area of the areas representing the six wirings 13 as the calculation unit area. It can be obtained as a value divided by the total area.

Next, the processing of the CMP simulation means 3 of FIG. 2 will be described with reference to FIG. Figure 4
(A) and (b) are CM in a damascene process
It is a figure which shows the simulation model of P, and the wiring material (copper wiring) 19 is formed into a film on the insulating film 20 in which the wiring groove was formed, and the polishing cloth 18 (henceforth a "pad") attached to the polishing apparatus 17 is shown. .) Is used for polishing. In addition, in FIG. 4B, as the polishing progresses, the wiring material 19
Shows that the wiring material 19 and the insulating film 20 are simultaneously polished and the film thickness of is reduced.

At the stage of FIG. 4A, the wiring material 19 is uniformly distributed, and the film thickness thereof is given as an initial value for calculation. The present invention proposes a simulation model for the stage of FIG. 4 (b).

In the simulation model of this embodiment, firstly, the pad 1 is formed by the unevenness of the surface of the wiring material 19.
Since 8 deforms and stress is applied to the pad, it is assumed that the stress is given by the convolution of the step distribution on the surface of the wiring material 19 and the stress response function. The stress response function f is determined by finding the stress response function value so as to match the actual measurement result based on the tensile stress obtained by the elastic analysis when only the central coordinate point is displacement constrained using the axisymmetric model. To do. For the elasticity analysis, for example, the finite element method analysis program “ANSYS” of Cybernet System Co., Ltd.
To use. However, it may be determined by a method of fitting the function parameter, a method of performing an experiment by using a test pattern, and fitting.

After the stress response function is determined, the average copper wiring film thickness hi corresponding to the dishing amount when the film thickness becomes equal to or less than a predetermined constant value for each calculation unit area
H and an average interlayer film thickness hiL corresponding to the amount of erosion are defined, and both film thicknesses are weighted and averaged for each time step Dt to obtain the average film thickness hi of each calculation unit region. Next, the amount of deformation (response film thickness) of the polishing pad is calculated by superimposing the average film thickness and the stress response function at each time step. Further, the polishing rate of the wiring material 19 in each time step is proportional to the value obtained by subtracting the response film thickness from the average value of the copper film thickness,
The polishing rate is calculated as being proportional to the value obtained by subtracting the response film thickness from the average film thickness of the interlayer film.

The above calculation is performed using the following equations (1) to (3).

[Equation 1]

[Equation 2]

[Equation 3]

Here, assuming that the number of the calculation unit area is i, hiL is the average value of the film thickness of the copper wiring 19, hiH is the average value of the film thickness of the interlayer insulating film 20, and C is flat (without pattern). The polishing rate of the copper wiring film, F is the polishing rate of a flat (non-patterned) insulating film, and A is a correction constant for the polishing rate. Further, hi is the average film thickness in each calculation unit region. E is the elastic modulus of the pad, l is the thickness of the pad, f (x)
Is the stress response function and ρi is the pattern density of each calculation unit area. Further, n is an index used for weighting both the copper wiring film thickness and the interlayer film thickness, and k is a correction coefficient of Preston's equation. A fast Fourier transform (FFT) algorithm is preferably used for the superposition calculation. This can significantly reduce the calculation time.

In the present embodiment, the elastic modulus E of the pad, the polishing rate correction constant A, the stress response function f, the weighting index n, and the correction coefficient k of the Preston's equation are adjusted based on the actual measurement results. Determined by doing. Specifically, a pattern is formed on a wafer using a mask including a pattern in which the width of copper wiring and the pitch of lines / spaces are changed, and polishing is actually performed. Each parameter is determined so that the sum of squares of the error with respect to the value obtained by the actual measurement result and the simulation calculation becomes the minimum. Furthermore, not only the wiring width and the pitch but also a sample in which the polishing time is changed may be prepared, and based on this, correction may be performed in consideration of time dependency. In this case, for example, the time step is set according to the preset actual measurement time, and the error between the actual measurement value and the simulation result is calculated at each coordinate position.

Next, the surface level difference in FIG. 2, the dishing amount,
The processing of the erosion amount evaluation means 4 will be described.
In the present embodiment, for the surface step of the polished surface, the maximum value and the minimum value are selected from the copper wiring film thickness and the interlayer film film thickness of each calculation unit region obtained by the CMP simulation,
The difference is compared with a predetermined target step to evaluate whether it is within the allowable range. In the present embodiment, this target step DH
Is defined by the following equation (4).

[Equation 4]

However, h _max is the maximum value of the copper wiring film thickness or the interlayer film film thickness obtained by the CMP simulation,
h _min is the minimum value. In addition, an average value of the pattern densities in a 500 μm square area centering on the calculation unit area where the film thickness is the minimum is defined as D _min, and in this area, dummy patterns are formed in all the dummy pattern permissible areas. The increase amount of the pattern density is Δd _min . However, it goes without saying that the definition of the target step ΔH is not limited to the definition by the above equation (4).

Next, the processing of the target film thickness setting means 11 of FIG. 2 will be described. In the present embodiment, based on the target step difference ΔH, the value represented by the following equation (5) is
The target film thickness h _gi of each calculation unit area is set.

[Equation 5] It goes without saying that the target film thickness h _gi may be defined by another formula.

Next, the proper pattern density calculation means 9 of FIG.
The process will be described. In the present embodiment, the appropriate pattern density D _pi of each calculation unit area is calculated back from the target film thickness h _g obtained by the equation (5) using the following equation (6).

[Equation 6] However, the function F is a filter function obtained as a time integral of the stress response function f. Note that the equation (6) may also be calculated using the fast Fourier transform algorithm.

Next, the processing of the dummy pattern permissible area extracting means 7 of FIG. 2 will be described. FIG. 5 is a diagram for explaining a method of extracting a dummy pattern allowable area and a method of obtaining an allowable dummy pattern density. As described above, the dummy pattern permissible area is an area in which the problem of the inter-wiring capacitance with the original wiring does not occur even if the dummy pattern is formed. Therefore, in the present embodiment, conversely, a region where a problem occurs when a dummy pattern is formed is obtained, and the other region is extracted by a logical operation to be a dummy pattern allowable region. First, as shown in FIG. 5A, data processing is performed to increase the width 14 of the wiring 13 to form an area in which a dummy pattern cannot be formed (hereinafter referred to as a dummy pattern non-allowable area). This is because the inter-wiring capacitance does not matter even if the dummy pattern is formed at a position separated from the wiring by a certain distance or more. When the process of increasing the wiring width 14 is performed for all wirings, a dummy pattern non-permissible area 15 is obtained as shown in FIG. If the NOR operation for inverting the layout data is executed, the dummy pattern allowing area 16 can be extracted as a result.

However, the method for extracting the dummy pattern allowable area 16 is not limited to the above method. For example, if there is no problem of inter-wiring capacitance with some selected wirings, the dummy pattern allowance region 16 is
It does not necessarily have to be a certain distance or more from all the wirings, and may be a certain distance or more from some target wirings.

Next, the allowable pattern density calculation means 8 in FIG.
The process will be described with reference to FIG. As described above, in the present embodiment, the allowable pattern density is the pattern density when the dummy pattern is formed so as to fill the dummy pattern allowable area. Therefore,
A value obtained by dividing the value obtained by adding the area area of the wiring 13 shown in FIG. 5C and the area of the dummy pattern allowable area 16 by the area of the calculation unit area is the allowable pattern density.

The processing of the modified pattern density determining means 10 of FIG. 2 is as described above. That is, if the proper pattern density is larger than the allowable pattern density, the allowable pattern density is set as the corrected pattern density of the calculation unit area,
In other cases, the proper pattern density is the corrected pattern density. However, the method for determining the corrected pattern density is also
The method is not limited to the method of this embodiment. For example, a method in which a value obtained by multiplying the allowable pattern density and the appropriate pattern density by a weighting coefficient and adding the values is used as the modified pattern density may be used.

In this embodiment, the dummy pattern layout is determined by performing a simulation in consideration of the effects of dishing and erosion that occur in CMP in the damascene process. Therefore, in the CMP process,
Dishing and erosion can be minimized, and high quality semiconductor devices and the like can be manufactured.

Further, when the above simulation model is adopted, the calculation to be executed is limited to a simple logical operation and several convolution operations, so that the calculation amount is much smaller than that of the conventional method. The result can be obtained in a short time. For example, in a standard chip, if the size of the calculation unit area is 100 μm square and the calculation is performed by a CPU with a clock frequency of 500 MHx, 20
It has been confirmed that the calculation will be completed within minutes.

Embodiment 2. In the present embodiment, in the process of the simulation calculation of the first embodiment, the copper wiring film thickness hi
When the difference between L and the film thickness hiH of the interlayer film becomes more than hD,
Instead of the above equations (1) to (3), the following (7) to (1
This is a form using the equation (0). That is, when the difference is larger than the predetermined value, the simulation accuracy is improved by performing the adjustment. Since the other points are the same as those of the first embodiment, the description thereof will be omitted.

[Equation 7]

[Equation 8]

[Equation 9]

[Equation 10]

[Equation 11] Here, hD is a correction parameter. DhiH 'Dhi
L'is a film thickness used for calculation during the process.

According to the present embodiment, the contact of the pad with the polishing surface can be modeled more accurately, so that the accuracy of simulation is significantly improved, and the standard system configuration has five times the conventional method. It has been confirmed that the accuracy is improved.

Although the above-described embodiment is a CMP simulation performed when forming a copper wiring having a damascene structure, the method and program of the present invention use the copper wiring in the above-described embodiment as an oxide film. Further, if the interlayer film is replaced with a nitride film, it can be applied to the STI process.

[0039]

According to the method, program, and recording medium of the present invention, an appropriate dummy pattern arrangement is performed by performing a simulation in consideration of the effects of dishing or erosion that occur when CMP is performed in a damascene process. You can decide. This improves the flatness during CMP.

[Brief description of drawings]

FIG. 1 is a flowchart showing an outline of processing of a design method and a program according to the present invention.

FIG. 2 is a block diagram showing the structure of a design program of the present invention.

FIG. 3 is a diagram for explaining an example of a layout and a method of calculating a pattern density.

FIG. 4 is a diagram for explaining a CMP simulation model.

FIG. 5 is a diagram for explaining a method of extracting a dummy pattern allowable area and a method of obtaining an allowable dummy pattern density.

FIG. 6 is a diagram for explaining the definition of “film thickness”.

[Explanation of symbols]

1 layout data, 12 calculation unit area,
13 wirings, 14 wiring widths, 15 dummy pattern non-permissible areas, 16 dummy pattern permissible areas,
17 CMP equipment, 18 polishing cloth (pad),
19 wiring material, 20 insulating film, 21 wiring groove.

Claims (5)

[Claims] 1. A method of designing a damascene structure wiring formed by embedding a wiring material in a wiring groove formed on an insulating film and polishing the whole, wherein each calculation unit defined on a chip. In the region, the insulating film thickness representing the height from the predetermined reference surface to the polished surface of the insulating film, and the wiring film thickness representing the height from the reference surface to the polished surface of the wiring, respectively, An average film thickness is obtained by weighted averaging the insulating film thickness and the wiring film thickness, and a response film thickness indicating a deformation amount of the polishing pad is obtained by superimposing the average film thickness and a predetermined stress response function. The polishing rate is the value obtained by subtracting the response film thickness from the wiring film thickness by a constant, and the polishing rate of the insulating film is obtained by multiplying the value obtained by subtracting the response film thickness from the insulating film film thickness by a constant. Each polishing rate found Based on the amount of erosion of dishing amount and the insulating film of the wiring was calculated, method of designing the wiring and determines the arrangement of the dummy patterns to optimize the value of the dishing amount and erosion amount. 2. In each of the calculation unit regions, the difference between the insulating film thickness and the wiring film thickness is kept below a predetermined value,
The wiring design method according to claim 1, wherein the optimization is performed. 3. A damascene structure wiring design program formed by embedding a wiring material in a wiring groove formed on an insulating film and polishing the whole, which is defined on a chip by a computer. In each calculation unit area, an insulating film thickness representing the height from a predetermined reference surface to the polished surface of the insulating film and a wiring film thickness representing the height from the reference surface to the polished surface of the wiring are respectively calculated. And a process of obtaining an average film thickness by performing a weighted average of the insulating film film thickness and the wiring film film thickness, and a response film indicating the amount of deformation of the polishing pad by superimposing the average film thickness and a predetermined stress response function. The process of obtaining the thickness, the polishing rate of the wiring as a value obtained by multiplying the value obtained by subtracting the response film thickness from the wiring film thickness by a constant, and the polishing rate of the insulating film from the insulating film thickness to the response film To the value minus the thickness A process for obtaining a value multiplied by a number, a process for calculating the dishing amount of the wiring and the erosion amount of the insulating film based on the obtained polishing rates, and optimizing the values of the dishing amount and the erosion amount A wiring design program, which executes a process for determining the layout of such dummy patterns. 4. The computer is caused to perform the optimization so as to keep a difference between the insulating film thickness and the wiring film thickness below a predetermined value in each of the calculation unit areas. 3. The wiring design program described in 3. 5. A computer-readable recording medium in which the design program according to claim 3 or 4 is recorded.