JP2003204065A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2003204065A JP2003204065A JP2002001282A JP2002001282A JP2003204065A JP 2003204065 A JP2003204065 A JP 2003204065A JP 2002001282 A JP2002001282 A JP 2002001282A JP 2002001282 A JP2002001282 A JP 2002001282A JP 2003204065 A JP2003204065 A JP 2003204065A
- Authority
- JP
- Japan
- Prior art keywords
- vertical
- conductivity type
- parallel
- main surface
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
【0001】[0001]
【発明の属する技術分野】本発明は、MOSFET(絶
縁ゲート型電界効果トランジスタ)、IGBT(伝導度
変調型MOSFET)、バイポーラトンラジスタ等の能
動素子やダイオード等の受動素子に適用可能で高耐圧化
と大電流容量化が両立する縦形パワー半導体装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention can be applied to active elements such as MOSFET (insulated gate field effect transistor), IGBT (conductivity modulation type MOSFET) and bipolar transistor and passive elements such as diode, and has a high breakdown voltage. The present invention relates to a vertical power semiconductor device that achieves both high performance and large current capacity.
【0002】基板の両面に電極部を備えてその基板の厚
さ方向に電流が流れる縦形ドリフト部を持つ縦形半導体
装置においては、オン抵抗(電流容量)と耐圧との間に
はトレードオフ関係が存在することから、縦形ドリフト
部として、不純物濃度を高めた縦形n型領域と縦形p型
領域とを基板の沿面方向へ交互に繰り返して成る並列p
n構造を採用することが知られている。しかし、この並
列pn構造の縦形ドリフト部では速く空乏化するもの
の、ドリフト部の周りで電流が実質上流れない耐圧構造
部では空乏層が外方向や基板深部へは拡がり難く、電界
強度がシリコンの臨界電界強度に速く達するため、耐圧
構造部で耐圧が制限されてしまう。設計耐圧を得るに
は、耐圧構造部にも並列pn構造を採用した縦形半導体
装置とすることが望ましい。In a vertical semiconductor device having a vertical drift portion in which a current flows in the thickness direction of the substrate provided with electrode portions on both sides of the substrate, there is a trade-off relationship between on-resistance (current capacity) and withstand voltage. Since they exist, the vertical p-type regions are formed by alternately repeating vertical n-type regions and vertical p-type regions having an increased impurity concentration in the creeping direction of the substrate.
It is known to adopt an n structure. However, although the vertical drift portion of the parallel pn structure is depleted quickly, in the breakdown voltage structure portion where the current does not substantially flow around the drift portion, the depletion layer is difficult to spread outward or to the deep portion of the substrate, and the electric field strength is silicon. Since the critical electric field strength is reached quickly, the breakdown voltage is limited in the breakdown voltage structure portion. In order to obtain a designed breakdown voltage, it is desirable to use a vertical semiconductor device that employs a parallel pn structure also in the breakdown voltage structure portion.
【0003】図9は縦形MOSFETにおけるドリフト
部及び素子外周部(耐圧構造部)を示す平面図、図10
は図9中のA−A′線に沿って切断した状態を示す縦断
面図、図11は図9中のB−B′線に沿って切断した状
態を示す縦断面図である。なお、図9ではドリフト部の
1/4を斜線部分で示してある。FIG. 9 is a plan view showing a drift portion and an element outer peripheral portion (breakdown voltage structure portion) in a vertical MOSFET, and FIG.
9 is a vertical sectional view showing a state cut along the line AA 'in FIG. 9, and FIG. 11 is a vertical sectional view showing a state cut along the line BB' in FIG. In addition, in FIG. 9, 1/4 of the drift portion is shown by a hatched portion.
【0004】このnチャネル縦形MOSFETは、裏側
のドレイン電極18が導電接触した低抵抗のn+ ドレ
イン層(コンタクト層)11の上に形成された第1の並
列pn構造のドレイン・ドリフト部22と、このドリフ
ト部22の表面層に選択的に形成された素子活性領域た
る高不純物濃度のpベース領域(pウェル,チャネル領
域)13aと、そのpベース領域13a内の表面側に選
択的に形成された高不純物濃度のn+ ソース領域14
と、基板表面上にゲート絶縁膜15を介して設けられた
ポリシリコン等のゲート電極層16と、層間絶縁膜19
aに開けたコンタクト孔を介してpベース領域13a及
びn+ ソース領域14に跨って導電接触するソース電
極17とを有している。ウェル状のpベース領域13a
の中にn + ソース領域14が浅く形成されており、2
重拡散型MOS部を構成している。なお、26はp+
コンタクト領域で、また、図示しない部分でゲート電極
層16の上に金属膜のゲート配線が導電接触している。This n-channel vertical MOSFET has a backside
N of low resistance in which the drain electrode 18 of+Drain
The first layer formed on the in layer (contact layer) 11
Drain / drift section 22 of column pn structure and this drift
Of the device active region selectively formed on the surface layer of the gate portion 22.
High impurity concentration p base region (p well, channel region
Area) 13a and the surface side in the p base region 13a.
Selectively formed high impurity concentration n+Source region 14
And provided on the surface of the substrate via the gate insulating film 15.
A gate electrode layer 16 made of polysilicon or the like and an interlayer insulating film 19
through the contact hole formed in a to the p base region 13a and
And n+A source electrode that makes conductive contact across the source region 14.
Poles 17 and. Well-shaped p base region 13a
In n +The source region 14 is shallowly formed, and 2
It constitutes a heavy diffusion type MOS part. Note that 26 is p+
Gate electrode in the contact region and in a portion not shown
A metal film gate line is in conductive contact with the layer 16.
【0005】第1の並列pn構造のドレイン・ドリフト
部22は、基板の厚み方向に配向する第1の層状縦形の
n型領域22aと基板の厚み方向に配向する第1の層状
縦形のp型領域22bとを交互に繰り返して接合した構
造である。上端がpベース領域13aの挾間領域12e
に達する第1の層状縦形のn型領域22aが実質的な電
路領域となっている。第1の層状縦形のn型領域22a
の下端はn+ ドレイン層11に接している。また、第
1の層状縦形のp型領域22bは、その上端がpベース
領域13aのウェル底面に接し、その下端がn+ ドレ
イン層11に接している。The drain / drift portion 22 of the first parallel pn structure has a first layered vertical n-type region 22a oriented in the thickness direction of the substrate and a first layered vertical p-type oriented in the thickness direction of the substrate. This is a structure in which the regions 22b are alternately and repeatedly joined. The upper end is the interstitial region 12e of the p base region 13a.
The first layered vertical n-type region 22a which reaches the position is a substantial electric path region. First layered vertical n-type region 22a
Is in contact with the n + drain layer 11. The upper end of the first layered vertical p-type region 22b is in contact with the bottom surface of the well of the p base region 13a, and the lower end thereof is in contact with the n + drain layer 11.
【0006】基板表面とn+ ドレイン層11との間で
縦形ドレイン・ドリフト部22の周りの耐圧構造部20
にも、基板の厚さ方向に配向する第2の層状縦形のn型
領域20aと、基板の厚さ方向に配向する第2の層状縦
形のp型領域20bとを基板の沿面方向へ交互に繰り返
して接合して成る第2の並列pn構造が形成されてい
る。耐圧構造部20の第2の並列pn構造の表面上に
は、表面保護及び安定化のために、熱酸化膜又は燐シリ
カガラス(PSG)から成る酸化膜(絶縁膜)23が成
膜されている。第2の並列pn構造では空乏層が拡がり
易くするために、第2の並列pn構造の不純物濃度を第
1の並列pn構造の不純物濃度に比して低下するか、或
いは第2の並列pn構造の繰り返しピッチP2を第1の
並列pn構造の繰り返しピッチP1よりも小さくしてあ
る。The breakdown voltage structure portion 20 around the vertical drain / drift portion 22 between the substrate surface and the n + drain layer 11.
Also, the second layered vertical n-type regions 20a oriented in the thickness direction of the substrate and the second layered vertical p-type regions 20b oriented in the thickness direction of the substrate are alternately arranged in the creeping direction of the substrate. A second parallel pn structure formed by repeatedly joining is formed. An oxide film (insulating film) 23 made of a thermal oxide film or phosphor silica glass (PSG) is formed on the surface of the second parallel pn structure of the breakdown voltage structure portion 20 for surface protection and stabilization. There is. In the second parallel pn structure, the impurity concentration of the second parallel pn structure is lower than the impurity concentration of the first parallel pn structure or the second parallel pn structure is used in order to facilitate the expansion of the depletion layer. Of the first parallel pn structure is smaller than the repeating pitch P1 of the first parallel pn structure.
【0007】[0007]
【発明が解決しようとする課題】しかしながら、図9乃
至図11に示す縦形MOSFETにあっては、次のよう
な問題点があった。However, the vertical MOSFETs shown in FIGS. 9 to 11 have the following problems.
【0008】即ち、ドレイン・ドリフト部22である第
1の並列pn構造の最外側における第1の層状縦形のn
型領域22aaの周りに、これとは不純物濃度又は繰り
返しピッチの異なる第2の並列pn構造の最内側におけ
る第2の縦形層状のp型領域20bbが存在するため、
n型領域22aaとp型領域20bbとのチャージバラ
ンスがどうしても崩れる。そのため、第1の並列pn構
造と第2の並列pn構造との境界の表面X付近では電界
集中を招き、耐圧を低下させてしまう。このような構造
においては、設計耐圧を得ることが困難であって、耐圧
構造部20に第2の並列pn構造を設けることの意義が
没却している。That is, the first layered vertical n on the outermost side of the first parallel pn structure which is the drain / drift portion 22.
Since the second vertical layered p-type region 20bb at the innermost side of the second parallel pn structure having a different impurity concentration or a different repeating pitch is present around the mold region 22aa,
The charge balance between the n-type region 22aa and the p-type region 20bb is destroyed. Therefore, electric field concentration occurs near the surface X at the boundary between the first parallel pn structure and the second parallel pn structure, and the breakdown voltage is reduced. In such a structure, it is difficult to obtain the designed breakdown voltage, and the significance of providing the second parallel pn structure in the breakdown voltage structure portion 20 is lost.
【0009】そこで、上記問題点に鑑み、本発明の課題
は、第1の並列pn構造であるドリフト部の周りにも耐
圧構造部として第2の並列pn構造を有する半導体装置
において、耐圧構造部での表面電界を緩和することによ
り、高耐圧化及び大電流化を一層図り得る半導体装置を
提供することにある。In view of the above problems, an object of the present invention is to provide a withstand voltage structure portion in a semiconductor device having a second parallel pn structure as a withstand voltage structure portion around the drift portion which is the first parallel pn structure. The purpose of the present invention is to provide a semiconductor device capable of further increasing the withstand voltage and the large current by relaxing the surface electric field in the above.
【0010】[0010]
【課題を解決するための手段】上記課題を解決するため
に、本発明に係る半導体装置の基本構造は、基板の第1
主面側に形成されて成る素子活性部に導電接続する第1
の電極層と、基板の第2主面側に形成されて成る第1導
電型の低抵抗層に導電接続する第2の電極層と、素子活
性部と低抵抗層との間に介在し、オン状態ではドリフト
電流が縦方向に流れると共にオフ状態では空乏化する縦
形ドリフト部と、縦形ドリフト部の周りで第1主面と低
抵抗層との間に介在し、オン状態では概ね非電路領域で
あってオフ状態では空乏化する耐圧構造部とを有するも
のである。縦形ドリフト部は基板の厚み方向に配向する
第1の縦形第1導電型領域と基板の厚み方向に配向する
第1の縦形第2導電型領域とを交互に繰り返して接合し
て成る第1の並列pn構造である。また、耐圧構造部は
基板の厚み方向に配向する第2の縦形第1導電型領域と
基板の厚み方向に配向する第2の縦形第2導電型領域と
を交互に繰り返して接合して成る第2の並列pn構造を
有している。そして、第2の並列pn構造の不純物濃度
が第1の並列pn構造の不純物濃度よりも低くなってい
るか、及び/又は、第2の並列pn構造の繰り返しピッ
チが第1の並列pn構造の繰り返しピッチよりも小さく
なっている。なお、基板の第1主面側に形成された素子
活性部とは、例えば縦型MOSFETの場合は第1主面
側で反転層を形成するチャネル拡散層とソース領域を含
むスイッチング部、バイポーラトランジスタの場合はエ
ミッタ又はコレクタ領域を含むスイッチング部であり、
ドリフト部の第1主面側で導通と非導通の選択機能を持
つ能動部分又は受動部分を指す。In order to solve the above problems, the basic structure of a semiconductor device according to the present invention is the first structure of a substrate.
First conductively connected to an element active portion formed on the main surface side
Intervening between the element active portion and the low resistance layer, the second electrode layer conductively connected to the first conductivity type low resistance layer formed on the second main surface side of the substrate, The drift current flows in the vertical direction in the on-state and is depleted in the off-state, and is interposed between the first main surface and the low resistance layer around the vertical drift part. In addition, the breakdown voltage structure portion is depleted in the off state. The vertical drift portion is formed by alternately repeating and joining first vertical first conductivity type regions oriented in the thickness direction of the substrate and first vertical second conductivity type regions oriented in the thickness direction of the substrate. It is a parallel pn structure. The breakdown voltage structure portion is formed by alternately and repeatedly joining second vertical first conductivity type regions oriented in the thickness direction of the substrate and second vertical second conductivity type regions oriented in the thickness direction of the substrate. It has two parallel pn structures. The impurity concentration of the second parallel pn structure is lower than the impurity concentration of the first parallel pn structure, and / or the repetition pitch of the second parallel pn structure is the repetition pitch of the first parallel pn structure. It is smaller than the pitch. The element active portion formed on the first main surface side of the substrate is, for example, in the case of a vertical MOSFET, a switching portion including a channel diffusion layer forming an inversion layer and a source region on the first main surface side, and a bipolar transistor. In the case of, it is a switching part including the emitter or collector region,
The active portion or the passive portion having a function of selecting conduction or non-conduction on the first main surface side of the drift portion.
【0011】斯かる基本構造において、本発明における
ドリフト部の周りの耐圧構造部は、第2の並列pn構造
のみから成るのではなく、ドリフト部に隣接して繰り返
しピッチが当該ドリフト部から引き続き1ピッチ以上外
側へ延長された第1の並列pn構造の一部分である内周
構造部と、この内周構造部に隣接した第2の並列pn構
造である外周構造部とを有するものである。このため、
ドリフト部の隣接周辺部分には第1の並列pn構造と第
2の並列pn構造との境界が存在せず、その境界は耐圧
構造部の内周構造部と外周構造部との間に存在すること
になるため、ドリフト部の隣接外周部分では並列pn構
造のチャージバランスの崩れが起こらず、それ故、ドリ
フト部の隣接外周部分での表面電界を抑制でき、高耐圧
化を図ることができる。In such a basic structure, the breakdown voltage structure portion around the drift portion in the present invention is not only composed of the second parallel pn structure, but the repeating pitch adjacent to the drift portion is 1 from the drift portion. It has an inner peripheral structure part which is a part of the first parallel pn structure extended outward by a pitch or more, and an outer peripheral structure part which is a second parallel pn structure adjacent to the inner peripheral structure part. For this reason,
There is no boundary between the first parallel pn structure and the second parallel pn structure in the adjacent peripheral portion of the drift part, and the boundary exists between the inner peripheral structure part and the outer peripheral structure part of the breakdown voltage structure part. Therefore, the charge balance of the parallel pn structure does not collapse in the outer peripheral portion adjacent to the drift portion, and therefore, the surface electric field in the outer peripheral portion adjacent to the drift portion can be suppressed and the breakdown voltage can be increased.
【0012】また、本発明では、耐圧構造部の第1主面
上の絶縁膜の上には内周構造部を覆って先端が外周構造
部の上にまで張り出て成るフィールドプレートを有す
る。このため、フィールドプレートが長く張り出し、そ
の先端直下の電界集中部分がドリフト部の隣接外周部分
から外れて外周構造部になるので、内周構造部での表面
電界を更に抑制でき、一層の高耐圧化を図ることができ
る。Further, according to the present invention, a field plate is formed on the insulating film on the first main surface of the breakdown voltage structure portion so as to cover the inner peripheral structure portion and have a tip protruding over the outer peripheral structure portion. As a result, the field plate overhangs for a long time, and the electric field concentrated portion immediately below the tip of the field plate deviates from the adjacent outer peripheral portion of the drift portion to become the outer peripheral structure portion, so that the surface electric field at the inner peripheral structure portion can be further suppressed, and the higher withstand voltage Can be realized.
【0013】このとき、絶縁膜で十分に耐圧を確保すれ
ば、絶縁膜下の並列pn構造部分での耐圧分担が小さく
なる。そうすれば仮に第1と第2の並列pn構造の境界
部分でチャージバランスが崩れたとしても、それによる
耐圧の低下分は絶縁膜が保持する耐圧で補われるので、
素子全体としては影響を受けずに済む。また、フィール
ドプレートの先端より外側に位置する耐圧構造部におい
ても、耐圧の分担が小さくなれば表面電界の集中が抑え
られる。そこで本発明では、絶縁膜の膜厚をドリフト部
側から外周構造部側に向けて厚く形成することで、高耐
圧化を図ることができる。At this time, if a sufficient withstand voltage is ensured by the insulating film, the withstand voltage share in the parallel pn structure portion under the insulating film becomes small. Then, even if the charge balance is broken at the boundary between the first and second parallel pn structures, the decrease in breakdown voltage due to the breakdown is compensated by the breakdown voltage held by the insulating film.
The element as a whole is not affected. Further, also in the breakdown voltage structure portion located outside the tip of the field plate, the concentration of the breakdown voltage is reduced, so that the concentration of the surface electric field can be suppressed. Therefore, in the present invention, by increasing the film thickness of the insulating film from the drift portion side toward the outer peripheral structure portion side, high breakdown voltage can be achieved.
【0014】この絶縁膜はその膜厚がドリフト部側から
外周構造部側に向けて漸増するものが望ましい。しかし
ながら、このような絶縁膜の成膜は困難であることか
ら、その絶縁膜はドリフト部側から外周構造部側にかけ
て段階的に厚く形成する。設計耐圧700Vクラスで
は、絶縁膜の膜厚段数は2以上とすることが望ましい。
しかしながら、膜厚の急変部分でフィールドプレートに
は段差が生じるので、その直下で電界集中が生じる。It is desirable that this insulating film has a film thickness that gradually increases from the drift portion side toward the outer peripheral structure portion side. However, since it is difficult to form such an insulating film, the insulating film is formed gradually thicker from the drift portion side to the outer peripheral structure side. In the design withstand voltage of 700 V class, it is desirable that the number of film thickness steps of the insulating film is two or more.
However, since a step is formed on the field plate at the portion where the film thickness changes abruptly, electric field concentration occurs directly under the step.
【0015】この問題を解決するため、本発明では、内
周構造部の第1の並列pn構造のうちで第1の縦形第2
導電型領域を外側に持つpn接合面の第1主面側位置と
フィールドプレートの段差位置とを合致させてある。第
1の縦形第2導電型領域は凡そ電位浮遊状態であるが、
第1の縦形第2導電型領域が第1の縦形第1導電型領域
よりも外側にあるので第1主面側で互いに接近する等電
位線のうち高電位側の等電位線を第1の縦形第2導電型
領域の外側へ振り分ける。このため、フィールドプレー
トの段差直下での等電位線同士の密集が解消し、電界集
中を有効的に緩和することができ、高耐圧化を図ること
ができる。In order to solve this problem, according to the present invention, the first vertical second type among the first parallel pn structures of the inner peripheral structure portion is used.
The position on the first main surface side of the pn junction surface having the conductivity type region on the outside and the step position of the field plate are matched. The first vertical second conductivity type region is in a potential floating state,
Since the first vertical second conductivity type region is outside the first vertical first conductivity type region, the equipotential line on the high potential side among the equipotential lines approaching each other on the first main surface side is the first It is distributed to the outside of the vertical second conductivity type region. Therefore, the concentration of equipotential lines immediately below the step of the field plate is eliminated, the electric field concentration can be effectively alleviated, and a high breakdown voltage can be achieved.
【0016】このように、第1の並列pn構造と第2の
並列pn構造との境界のチャージバランスの崩れによる
電界集中やフィールドプレートの段差直下の電界集中を
緩和できるが、耐圧構造部の外周構造部でのフィールド
プレートの先端直下で生じる電界集中も緩和することが
必要である。例えば、外周構造部における第2の並列p
n構造の第1の主面側に第1導電型の高抵抗層を形成
し、その第1の主面側に第2導電型のガードリングを正
規に形成しても構わないが、本発明では、正規のガード
リングを形成する代わりに、第2の並列pn構造のうち
で第2の縦形第2導電型領域を外側に持つpn接合面の
第1主面側位置とフィールドプレートの先端位置とを合
致させてある。第2の縦形第2導電型領域は凡そ電位浮
遊状態であるが、第2の縦形第2導電型領域が第2の縦
形第1導電型領域よりも外側にあるので、第1主面側で
互いに接近する等電位線のうち高電位側の等電位線を第
2の第2導電型領域の外側へ振り分ける。このため、フ
ィールドプレートの先端直下での等電位線同士の密集が
解消し、電界集中を緩和することができ、高耐圧化を図
ることができる。As described above, the electric field concentration due to the collapse of the charge balance at the boundary between the first parallel pn structure and the second parallel pn structure and the electric field concentration just below the step of the field plate can be alleviated, but the outer periphery of the breakdown voltage structure portion. It is also necessary to mitigate the electric field concentration that occurs just below the tip of the field plate in the structure. For example, the second parallel p in the outer peripheral structure portion
It is also possible to form a high-resistance layer of the first conductivity type on the first principal surface side of the n structure and form a second conductivity type guard ring on the first principal surface side of the n-structure. Then, instead of forming a regular guard ring, the first main surface side position of the pn junction surface having the second vertical second conductivity type region on the outside of the second parallel pn structure and the tip position of the field plate. And are matched. The second vertical second conductivity type region is in a potential floating state, but since the second vertical second conductivity type region is outside the second vertical first conductivity type region, on the first main surface side. The equipotential lines on the high potential side among the equipotential lines that approach each other are distributed to the outside of the second second conductivity type region. For this reason, the concentration of equipotential lines immediately below the tip of the field plate can be eliminated, electric field concentration can be relieved, and high breakdown voltage can be achieved.
【0017】なお、このフィールドプレートの先端と第
2の縦形第2導電型領域を外側に持つpn接合面の第1
主面側位置とを合致させる構成は、内周構造を持たない
耐圧構造部であっても有効である。The first pn junction surface having the tip of the field plate and the second vertical second conductivity type region on the outer side.
The configuration in which the position on the main surface side is matched is effective even for the pressure resistant structure portion having no inner peripheral structure.
【0018】また、フィールドプレートの先端よりも外
側に位置する耐圧構造部での表面電界を緩和する必要も
ある。本発明は、第2の並列pn構造のうちでフィール
ドプレートの先端よりも外側に位置する第2の縦形第2
導電型領域の第1主面側の不純物濃度が隣接する第2の
縦形第1導電型領域の第1主面側の不純物濃度に比して
高いことを特徴とする。その第2の縦形第1導電型領域
の第1主面側が空欠化しても、隣接する第2の縦形第2
導電型領域の第1主面側は完全には空欠化せず、第2導
電型領域としてキャリアが幾分残るため、これがガード
リングとして機能し、また第2の縦形第2導電型領域が
第2の縦形第1導電型領域よりも外側にあるので、第1
主面側で互いに接近する等電位線のうち高電位側の等電
位線を第2の第2導電型領域の外側へ振り分ける。この
ため、フィールドプレートの先端よりも外側に位置する
耐圧構造部での表面電界が緩和し、高耐圧化を図ること
ができる。It is also necessary to relax the surface electric field in the breakdown voltage structure portion located outside the tip of the field plate. The present invention relates to a second vertical type second structure which is located outside the tip of the field plate in the second parallel pn structure.
The impurity concentration on the first main surface side of the conductivity type region is higher than the impurity concentration on the first main surface side of the adjacent second vertical first conductivity type region. Even if the first main surface side of the second vertical first conductivity type region is void, the adjacent second vertical second
The first major surface side of the conductivity type region is not completely vacant, and some carriers remain as the second conductivity type region, which functions as a guard ring, and the second vertical second conductivity type region is formed. Since it is outside the second vertical first conductivity type region,
The equipotential lines on the high potential side among the equipotential lines that are close to each other on the main surface side are distributed to the outside of the second second conductivity type region. Therefore, the surface electric field in the breakdown voltage structure portion located outside the tip of the field plate is relaxed, and the breakdown voltage can be increased.
【0019】このように、第2の第2導電型領域の第1
主面側をガードリングとして機能させるためには、第2
の縦形第2導電型領域の第1主面側の幅寸法が隣接する
第2の縦形第1導電型領域の第1主面側の幅寸法に比し
て広くても良いし、また、第2の縦形第1導電型領域の
第1主面側の不純物濃度が隣接する第2の第2導電型領
域の第1主面側の不純物濃度に比して低くても良い。な
お、このようなフィールドプレートの先端よりも外側に
位置する耐圧構造部での表面電界を緩和させる構成は、
内周構造を持たない耐圧構造部であっても有効である。As described above, the first of the second second conductivity type region is formed.
In order to make the main surface side function as a guard ring, the second
The width dimension of the vertical second conductivity type region on the first main surface side may be wider than the width dimension of the adjacent second vertical first conductivity type region on the first main surface side. The impurity concentration on the first main surface side of the second vertical first conductivity type region may be lower than the impurity concentration on the first main surface side of the adjacent second second conductivity type region. Note that the structure for relaxing the surface electric field in the breakdown voltage structure portion located outside the tip of the field plate is as follows.
It is effective even if the pressure-resistant structure portion does not have an inner peripheral structure.
【0020】第1の並列pn構造における繰り返しピッ
チの方向と第2の並列pn構造における繰り返しピッチ
の方向とが同じである場合に限らず、略直交していても
構わない。The direction of the repeating pitch in the first parallel pn structure and the direction of the repeating pitch in the second parallel pn structure are not limited to the same direction, but may be substantially orthogonal to each other.
【0021】また、外周構造部を取り囲む第1導電型囲
繞領域と、この第1主面側に導電接触する第3の電極部
を設けることにより、漏れ電流を抑制することができ
る。By providing the first conductivity type surrounding area surrounding the outer peripheral structure portion and the third electrode portion in conductive contact with the first main surface side, the leakage current can be suppressed.
【0022】[0022]
【発明の実施の形態】以下に本発明の実施形態を説明す
る。以下でn又はpを冠記した層や領域では、ぞれぞれ
電子又は正孔が多数キャリアであることを意味する。ま
た+は比較的高不純物濃度であることを意味している。
すべての実施例において第1導電型にnを、第2導電型
にpを選んでいるが、これが逆の場合であっても良い。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. In the following, in layers and regions prefixed with n or p, it is meant that electrons or holes are majority carriers, respectively. Further, + means that the impurity concentration is relatively high.
Although n is selected as the first conductivity type and p is selected as the second conductivity type in all of the embodiments, the opposite case is also possible.
【0023】[実施例1]図1は本発明の実施例1に係
る縦形MOSFET素子のチップを示す概略平面図、図
2は図1中のA−A′線に沿って切断した状態を示す縦
断面図である。なお、図1ではドレイン・ドリフト部の
1/4を示してある。[Embodiment 1] FIG. 1 is a schematic plan view showing a chip of a vertical MOSFET device according to Embodiment 1 of the present invention, and FIG. 2 shows a state cut along the line AA 'in FIG. FIG. Note that FIG. 1 shows 1/4 of the drain / drift portion.
【0024】本例の縦形MOSFETは、裏側のドレイ
ン電極18が導電接触した低抵抗のn+ ドレイン層
(コンタクト層)11の上に形成された第1の並列pn
構造のドレイン・ドリフト部22と、このドレイン・ド
リフト部22の表面層に選択的に形成された素子活性領
域たる高不純物濃度のpベース領域(pウェル)13a
と、そのpベース領域13a内の表面側に選択的に形成
された高不純物濃度のn + ソース領域14と、基板表
面上にゲート絶縁膜15を介して設けられたポリシリコ
ン等のゲート電極層16と、層間絶縁膜19aに開けた
コンタクト孔を介してpベース領域13a及びn+ ソ
ース領域14に跨って導電接触するソース電極17とを
有している。ウェル状のpベース領域13aの中にn
+ ソース領域14が浅く形成されており、2重拡散型
MOS部を構成している。なお、26はp+ コンタク
ト領域で、また、図示しない部分でゲート電極層16の
上に金属膜のゲート配線が導電接触している。The vertical MOSFET of this example has a backside drain.
N having a low resistance in which the electrode 18 is in conductive contact+Drain layer
First parallel pn formed on (contact layer) 11
The drain / drift part 22 of the structure and this drain / drift part
An element active region selectively formed on the surface layer of the lift portion 22.
Area of high impurity concentration p base region (p well) 13a
And selectively formed on the surface side in the p base region 13a.
N of high impurity concentration +Source region 14 and substrate surface
Polysilicon provided on the surface through the gate insulating film 15
And the gate electrode layer 16 such as an insulating film and the interlayer insulating film 19a.
P base regions 13a and n through the contact holes+So
The source electrode 17 that is in conductive contact across the source region 14.
Have N in the well-shaped p base region 13a
+The source region 14 is shallowly formed, and is a double diffusion type.
It constitutes the MOS section. Note that 26 is p+Contact
Of the gate electrode layer 16 in a region not shown.
The metal film gate wiring is in conductive contact therewith.
【0025】ドレイン・ドリフト部22は、素子活性領
域たる複数ウェルのpベース領域13の直下部分に相当
し、基板の厚み方向に配向する層状縦形の第1のn型領
域22aと基板の厚み方向に配向する層状縦形の第1の
p型領域22bとを繰り返しピッチP1で基板の沿面方
向へ交互に繰り返して接合して成る第1の並列pn構造
である。いずれかの第1のn型領域22aは、その上端
がpベース領域13の挾間領域12eに達し、その下端
がn+ ドレイン層11に接している。挾間領域12e
に達する第1のn型領域22aはオン状態では電路領域
であるが、その余の第1のn型領域22aは概ね非電路
領域となっている。また第1のp型領域22bは、その
上端がpベース領域13aのウェル底面に接し、その下
端がn+ ドレイン層11に接している。The drain / drift portion 22 is a device activation region.
Corresponding to the area directly under the p-base region 13 of a plurality of wells
And the first layered vertical n-type region oriented in the thickness direction of the substrate.
The first layer-shaped vertical layer oriented in the thickness direction of the region 22a and the substrate.
Repeating the p-type region 22b with the pitch P1
First parallel pn structure formed by alternately and repeatedly joining
Is. One of the first n-type regions 22a has an upper end
Reaches the interstitial region 12e of the p base region 13 and its lower end
Is n+It is in contact with the drain layer 11. Hama area 12e
The first n-type region 22a reaching the
However, the remaining first n-type region 22a is almost a non-electric path.
It has become an area. In addition, the first p-type region 22b is
The upper end is in contact with the bottom surface of the well of the p base region 13a,
The edge is n+ It is in contact with the drain layer 11.
【0026】ドレイン・ドリフト部22の周りは並列p
n構造から成る耐圧構造部(素子周縁部)となっている
が、この耐圧構造部は、ドレイン・ドリフト部22の第
1の並列pn構造に隣接して繰り返しピッチ及び不純物
濃度が同じである内周構造部30と、この内周構造部3
0に隣接した第2の並列pn構造である外周構造部40
とを有する。内周構造部30に属する第1の並列pn構
造の繰り返しピッチは数ピッチとなっている。外周構造
部40に属する第2の並列pn構造は、基板の厚み方向
に配向する層状縦形の第2のn型領域41と基板の厚み
方向に配向する層状縦形の第2のp型領域42とを交互
に繰り返して接合して成る。本例では、第2の並列pn
構造での空欠層をより拡がり易くするため、第2の並列
pn構造の不純物濃度は第1の並列pn構造の不純物濃
度よりも低く、また第2の並列pn構造の繰り返しピッ
チP2は第1の並列pn構造の繰り返しピッチP1より
も狭くなっている。しかし、いずれか一方の条件を満足
するだけでも、第2の並列pn構造での空欠層を拡がり
易くできることは言う迄もない。Around the drain / drift unit 22, a parallel p
The breakdown voltage structure portion (element peripheral portion) is composed of the n structure, but this breakdown voltage structure portion is adjacent to the first parallel pn structure of the drain / drift portion 22 and has the same repeating pitch and the same impurity concentration. The circumferential structure portion 30 and the inner circumferential structure portion 3
Peripheral structure portion 40 that is a second parallel pn structure adjacent to 0
Have and. The repeating pitch of the first parallel pn structure belonging to the inner peripheral structure portion 30 is several pitches. The second parallel pn structure belonging to the outer peripheral structure portion 40 has a layered vertical second n-type region 41 oriented in the thickness direction of the substrate and a layered vertical second p-type region 42 oriented in the substrate thickness direction. And are joined alternately. In this example, the second parallel pn
The impurity concentration of the second parallel pn structure is lower than the impurity concentration of the first parallel pn structure, and the repetition pitch P2 of the second parallel pn structure is first It is narrower than the repeating pitch P1 of the parallel pn structure. However, it is needless to say that it is possible to easily expand the depletion layer in the second parallel pn structure only by satisfying one of the conditions.
【0027】内周構造部30及び外周構造部40の表面
には絶縁膜主面には酸化膜(絶縁膜)123が形成され
ている。この酸化膜123はその膜厚がドリフト部22
から外周構造部40にかけて厚くなるように形成されて
おり、内周構造部30の上では段階的に厚くなってい
る。即ち、酸化膜123は、内周構造部30の上でドリ
フト部22に隣接して形成された最小厚の内周域酸化膜
123aと、内周構造部30の上に形成された中間域酸
化膜123bと、内周構造部30の上から外周構造部4
0にかけて形成された最大厚の外周域酸化膜123cと
を一体的に有し、膜厚段数は2となっている。そして、
ソース電極17から延長され、耐圧構造部の酸化膜12
3の上には内周構造部30を覆って先端が外周構造部4
0の上にまで張り出て成るフィールドプレートFPが形
成されている。このフィールドプレートFPは酸化膜1
23の段差を反映して段差S1,S2を有している。内
周域酸化膜123aと中間域酸化膜123bとの段差、
即ち、フィールドプレートFPの段差S1は内周構造部
30に属する第1の並列pn構造の一部分のうちで第1
のp型領域22bを外側に持つpn接合面の表面側位置
T1に合致している。また、中間域酸化膜123bと外
周域酸化膜123cとの段差、即ち、フィールドプレー
トFPの段差S2は内周構造部30に属する第1の並列
pn構造の一部分のうちで第2のp型領域22bを外側
に持つpn接合面の表面側位置T2に合致している。更
に、フィールドプレートFPの先端S3は第2の並列p
n構造のうちで第2のp型領域42を外側に持つpn接
合面の表面側位置T3に合致している。An oxide film (insulating film) 123 is formed on the main surface of the insulating film on the surfaces of the inner peripheral structure portion 30 and the outer peripheral structure portion 40. The oxide film 123 has a film thickness of the drift portion 22.
It is formed so that it becomes thicker from the outer peripheral structure part 40 to the outer peripheral structure part 40, and becomes thicker stepwise on the inner peripheral structure part 30. That is, the oxide film 123 includes an inner region oxide film 123 a having a minimum thickness formed on the inner structure portion 30 adjacent to the drift portion 22 and an intermediate region oxide film formed on the inner structure portion 30. From the top of the membrane 123b and the inner peripheral structure 30 to the outer peripheral structure 4
The outer peripheral region oxide film 123c having the maximum thickness formed over 0 is integrally formed, and the number of film thickness steps is two. And
The oxide film 12 extending from the source electrode 17 in the breakdown voltage structure portion
3, the inner peripheral structure portion 30 is covered with the tip of the outer peripheral structure portion 4
A field plate FP is formed so as to extend to above 0. This field plate FP is an oxide film 1
It has steps S1 and S2 reflecting the step of No. 23. A step between the inner region oxide film 123a and the middle region oxide film 123b,
That is, the step S1 of the field plate FP is the first part of the first parallel pn structure belonging to the inner peripheral structure portion 30.
It coincides with the surface side position T1 of the pn junction surface having the p-type region 22b on the outside. Further, the step between the intermediate oxide film 123b and the outer oxide film 123c, that is, the step S2 of the field plate FP is the second p-type region in a part of the first parallel pn structure belonging to the inner peripheral structure portion 30. It coincides with the surface side position T2 of the pn junction surface having 22b on the outside. Further, the tip S3 of the field plate FP is connected to the second parallel p
In the n structure, it coincides with the surface side position T3 of the pn junction surface having the second p-type region 42 on the outside.
【0028】そして、外周構造部40の外側にはチャネ
ルストッパーとしてn型囲繞領域50が形成され、この
n型囲繞領域50の表面側にはストッパー電極51が導
電接触している。An n-type surrounding region 50 is formed as a channel stopper outside the outer peripheral structure 40, and a stopper electrode 51 is in conductive contact with the surface side of the n-type surrounding region 50.
【0029】本例の縦形MOSFETは耐圧600Vク
ラスであり、n+ ドレイン層11の不純物濃度は2×
1018cm−3、第1のn型領域22a及び第1のp
型領域22bの不純物濃度は2.57×1015cm
−3で、その基板深さ(厚さ)は44μm、第1の繰り
返しピッチP1は16μmであって、第2のp型領域4
1及び第2のp型領域42の不純物濃度は1.2×10
15cm−3で、その基板深さ(厚さ)は44μm、第
2の繰り返しピッチP2は8μmである。酸化膜123
の内周域酸化膜123aの膜厚は0.1μm、中間域酸
化膜123bの膜厚は0.8μm、外周域酸化膜123
cの膜厚は3.0μmである。The vertical MOSFET of this example has a breakdown voltage of 600 V class, and the impurity concentration of the n + drain layer 11 is 2 ×.
10 18 cm −3 , first n-type region 22a and first p
The impurity concentration of the mold region 22b is 2.57 × 10 15 cm
-3 , the substrate depth (thickness) is 44 μm, the first repeating pitch P1 is 16 μm, and the second p-type region 4 is
The impurity concentration of the first and second p-type regions 42 is 1.2 × 10
At 15 cm −3 , the substrate depth (thickness) is 44 μm, and the second repeating pitch P2 is 8 μm. Oxide film 123
The inner peripheral oxide film 123a has a thickness of 0.1 μm, the intermediate oxide film 123b has a thickness of 0.8 μm, and the outer peripheral oxide film 123 has a thickness of 0.8 μm.
The film thickness of c is 3.0 μm.
【0030】このように、ドレイン・ドリフト部22の
周りの耐圧構造部は、第2の並列pn構造である外周構
造部40のみから成るのではなく、ドレイン・ドリフト
部22と外周構造部40との間にドレイン・ドリフト部
22に隣接して繰り返しピッチが当該ドリフト部から引
き続き1ピッチ以上外側へ延長された第1の並列pn構
造の一部分である内周構造部30を有している。このた
め、ドレイン・ドリフト部22の隣接周辺部分には第1
の並列pn構造と第2の並列pn構造との境界の表面位
置が存在せず、その境界の表面位置T4は内周構造部3
0と外周構造部40との間に存在することになる。ドレ
イン・ドリフト部22の隣接外周部分T5では並列pn
構造のチャージバランスの崩れが起こらず、それ故、ド
レイン・ドリフト部の隣接外周部分での表面電界を抑制
でき、高耐圧化を図ることができる。As described above, the breakdown voltage structure portion around the drain / drift portion 22 is not limited to the outer peripheral structure portion 40, which is the second parallel pn structure, but the drain / drift portion 22 and the outer peripheral structure portion 40. In the meantime, adjacent to the drain / drift portion 22, there is an inner peripheral structure portion 30 which is a part of the first parallel pn structure in which the repeating pitch is continuously extended from the drift portion to the outside by one pitch or more. Therefore, the first peripheral portion of the drain / drift portion 22 is adjacent to the first peripheral portion.
The surface position of the boundary between the parallel pn structure and the second parallel pn structure does not exist, and the surface position T4 of the boundary is the inner peripheral structure portion 3
0 and the outer peripheral structure 40. In the outer peripheral portion T5 adjacent to the drain / drift portion 22, parallel pn
The charge balance of the structure is not disturbed, and therefore, the surface electric field at the adjacent outer peripheral portion of the drain / drift portion can be suppressed and the breakdown voltage can be increased.
【0031】また、フィールドプレートFPはその先端
S3が内周構造部30を覆って外周構造部40の上にま
で長く張り出ているため、その先端S3直下の電界集中
部分がドレイン・ドリフト部22の隣接外周部分から外
れて外周構造部40になるので、内周構造部30での表
面電界を更に抑制でき、一層の高耐圧化を図ることがで
きる。Further, since the tip S3 of the field plate FP extends over the inner circumferential structure portion 30 and extends over the outer circumferential structure portion 40, the electric field concentrated portion immediately below the tip end S3 of the field plate FP is the drain / drift portion 22. Since the outer peripheral structure portion 40 is separated from the adjacent outer peripheral portion, the surface electric field in the inner peripheral structure portion 30 can be further suppressed, and the breakdown voltage can be further increased.
【0032】このとき、酸化膜123で十分に耐圧を確
保すれば、酸化膜123下の並列pn構造部分での耐圧
分担が小さくなる。そうすれば仮に第1と第2の並列p
n構造の境界部分でチャージバランスが崩れたとして
も、それによる耐圧の低下分は酸化膜123が保持する
耐圧で補われるので、素子全体としては影響を受けずに
済む。また、フィールドプレートFPの先端S3より外
側に位置する耐圧構造部においても、耐圧の分担が小さ
くなれば表面電界の集中が抑えられる。そこで、酸化膜
123の膜厚をドリフト部22側から外周構造部40側
に向けて厚く形成することで、高耐圧化を図ることがで
きる。At this time, if the breakdown voltage is sufficiently secured by the oxide film 123, the breakdown voltage sharing in the parallel pn structure portion below the oxide film 123 becomes small. Then, if the first and second parallel p
Even if the charge balance is lost at the boundary of the n structure, the decrease in breakdown voltage due to the breakdown is compensated for by the breakdown voltage held by the oxide film 123, so that the entire device is not affected. Further, also in the breakdown voltage structure portion located outside the tip S3 of the field plate FP, the concentration of the breakdown voltage is reduced, so that the concentration of the surface electric field can be suppressed. Therefore, by increasing the thickness of the oxide film 123 from the drift portion 22 side toward the outer peripheral structure portion 40 side, it is possible to increase the breakdown voltage.
【0033】ただ、酸化膜123は段階的に厚く形成さ
れているため、その膜厚の急変部分でフィールドプレー
トFPには段差S1,S2が生じるので、その直下で電
界集中が生じる。この問題を解決するため、フィールド
プレートFPの段差S1は内周構造部30に属する第1
の並列pn構造の一部分のうちで第1のp型領域22b
を外側に持つpn接合面の表面側位置T1に合致し、フ
ィールドプレートFPの段差S2は内周構造部30に属
する第1の並列pn構造の一部分のうちで第2のp型領
域22bを外側に持つpn接合面の表面側位置T2に合
致している。第1のp型領域22bは凡そ電位浮遊状態
であるが、第1のp型領域22bが第1のN型領域22
aよりも外側にあるので、表面側で互いに接近する等電
位線のうち高電位側の等電位線を第1のp型領域22b
の外側へ振り分ける。このため、フィールドプレートF
Pの段差S1,S2直下での等電位線同士の密集が解消
し、電界集中を有効的に緩和することができ、高耐圧化
を図ることができる。However, since the oxide film 123 is formed thicker stepwise, the field plate FP has steps S1 and S2 at a portion where the film thickness suddenly changes. In order to solve this problem, the step S1 of the field plate FP includes the first step S1 belonging to the inner peripheral structure portion 30.
First p-type region 22b of a portion of the parallel pn structure of
Corresponding to the position T1 on the front surface side of the pn junction surface having the outside, and the step S2 of the field plate FP is located outside the second p-type region 22b in a part of the first parallel pn structure belonging to the inner peripheral structure portion 30. It coincides with the position T2 on the front surface side of the pn junction surface held in. The first p-type region 22b is almost in a floating state, but the first p-type region 22b is the first N-type region 22.
Since it is outside a, the equipotential lines on the high potential side among the equipotential lines that are close to each other on the surface side are the first p-type region 22b.
To the outside of. Therefore, the field plate F
The concentration of equipotential lines immediately below the steps S1 and S2 of P is eliminated, electric field concentration can be effectively mitigated, and high breakdown voltage can be achieved.
【0034】このように、第1の並列pn構造と第2の
並列pn構造との境界のチャージバランスの崩れによる
電界集中やフィールドプレートFPの段差S1,S2直
下の電界集中を緩和できるが、耐圧構造部の外周構造部
40でのフィールドプレートFPの先端S3直下で生じ
る電界集中も緩和することが必要である。本例では、外
周構造部40の表面側に正規のガードリングを形成する
代わりに、第2の並列pn構造のうちで第2のp型領域
42を外側に持つpn接合面の第1主面側位置T3とフ
ィールドプレートFPの先端位置S3とを合致させてあ
る。第2のp型領域42は凡そ電位浮遊状態であるが、
第2のp型領域42が第2のn型領域41よりも外側に
あるので、表面側で互いに接近する等電位線のうち高電
位側の等電位線を第2のp型領域42の外側へ振り分け
る。このため、フィールドプレートFPの先端S3直下
での等電位線同士の密集が解消し、電界集中を緩和する
ことができ、高耐圧化を図ることができる。As described above, the electric field concentration due to the collapse of the charge balance at the boundary between the first parallel pn structure and the second parallel pn structure and the electric field concentration immediately below the steps S1 and S2 of the field plate FP can be relaxed, but the breakdown voltage is reduced. It is also necessary to reduce the electric field concentration that occurs in the outer peripheral structure 40 of the structure just below the tip S3 of the field plate FP. In this example, instead of forming a regular guard ring on the front surface side of the outer peripheral structure portion 40, the first main surface of the pn junction surface of the second parallel pn structure having the second p-type region 42 on the outer side. The side position T3 and the tip position S3 of the field plate FP are matched. The second p-type region 42 is in a potential floating state,
Since the second p-type region 42 is outside the second n-type region 41, the equipotential lines on the high potential side of the equipotential lines that are close to each other on the surface side are outside the second p-type region 42. Sort to. Therefore, the concentration of equipotential lines immediately below the tip S3 of the field plate FP is eliminated, the electric field concentration can be alleviated, and a high breakdown voltage can be achieved.
【0035】更に本例では、外周構造部40を取り囲む
n型囲繞領域50と、ストッパー電極51とが形成され
ているため、漏れ電流を抑制することができる。Further, in this example, since the n-type surrounding region 50 surrounding the outer peripheral structure portion 40 and the stopper electrode 51 are formed, the leakage current can be suppressed.
【0036】[実施例2]図3は本発明の実施例2に係
る縦形MOSFETを示す部分縦断面図である。図3は
同じく図1のA−A′線に沿って切断した状態を示す縦
断面図である。[Embodiment 2] FIG. 3 is a partial vertical sectional view showing a vertical MOSFET according to Embodiment 2 of the present invention. FIG. 3 is a longitudinal sectional view showing a state similarly cut along the line AA ′ in FIG.
【0037】本例において実施例1の構成と異なる点
は、外周構造部40の第2の並列pn構造のうちでフィ
ールドプレートFPの先端よりも外側に位置する第2の
p型領域42は表面側部分42aを有し、この表面側部
分42aは、その不純物濃度が隣接する第2のn型領域
41の表面側の不純物濃度に比して高く、しかもその幅
寸法が隣接する第2のn型領域41の表面側の幅寸法に
比して広くなっているところにある。換言すれば、表面
側部分42aは、その不純物濃度が第2のp型領域42
の不純物濃度に比して高く、またその幅寸法が隣接する
第2のp型領域42の幅寸法に比して広くなっている。
なお、表面側部分42aは不純物濃度が高く、しかも幅
寸法を広く形成してあるが、いずれか一方でも構わな
い。In this example, the difference from the configuration of the first embodiment is that in the second parallel pn structure of the outer peripheral structure 40, the second p-type region 42 located outside the tip of the field plate FP is the surface. The second side portion 42a has a side portion 42a. The surface side portion 42a has a higher impurity concentration than that of the adjacent second n-type region 41 and has a width dimension adjacent to the second n portion. It is wider than the width dimension of the mold region 41 on the front surface side. In other words, the surface-side portion 42a has the impurity concentration of the second p-type region 42.
Of the second p-type region 42 adjacent to the second p-type region 42 adjacent thereto.
Although the front surface side portion 42a has a high impurity concentration and a wide width, it may be formed on either side.
【0038】オフ状態において、第2のn型領域41の
表面側が空欠化しても、隣接する表面側部分42aは完
全には空欠化せず、p型領域としてキャリアが幾分残る
ため、これがガードリングとして機能し、表面側で互い
に接近する等電位線のうち高電位側の等電位線を表面側
部分42aの外側へ振り分ける。このため、フィールド
プレートFPの先端よりも外側に位置する耐圧構造部4
0での表面電界が緩和し、高耐圧化を図ることができ
る。In the off state, even if the surface side of the second n-type region 41 is vacant, the adjacent surface side portion 42a is not completely vacant, and some carriers remain as the p-type region. This functions as a guard ring, and distributes the equipotential lines on the high potential side among the equipotential lines approaching each other on the surface side to the outside of the surface side portion 42a. Therefore, the pressure-resistant structure portion 4 located outside the tip of the field plate FP.
The surface electric field at 0 is relaxed, and high breakdown voltage can be achieved.
【0039】[実施例3]図4は本発明の実施例3に係
る縦形MOSFET素子のチップを示す概略平面図、図
5は図4中のA−A′線に沿って切断した状態を示す縦
断面図である。なお、図4ではドレイン・ドリフト部の
1/4を示してある。[Embodiment 3] FIG. 4 is a schematic plan view showing a chip of a vertical MOSFET device according to Embodiment 3 of the present invention, and FIG. 5 shows a state cut along the line AA 'in FIG. FIG. Note that FIG. 4 shows 1/4 of the drain / drift portion.
【0040】本例において実施例1の構成と異なる点
は、外側構造部40の第2の並列pn構造の繰り返しピ
ッチP2は第1の並列pn構造の繰り返しピッチP1と
同じになっており、第2の並列pn構造の不純物濃度は
第1の並列pn構造の不純物濃度よりも十分低くなって
いるところにある。なお、第2の並列pn構造の不純物
濃度が第1の並列pn構造の不純物濃度よりも十分低け
れば、繰り返しピッチP2は繰り返しピッチP1よりも
広くても構わない。In this example, the difference from the configuration of Example 1 is that the repeating pitch P2 of the second parallel pn structure of the outer structure 40 is the same as the repeating pitch P1 of the first parallel pn structure. The impurity concentration of the second parallel pn structure is sufficiently lower than the impurity concentration of the first parallel pn structure. If the impurity concentration of the second parallel pn structure is sufficiently lower than the impurity concentration of the first parallel pn structure, the repeating pitch P2 may be wider than the repeating pitch P1.
【0041】また本例では、外側耐圧部40のうちでフ
ィールドプレートFPの先端よりも外側に位置する第2
のn型領域41の表面側部分41aは、その不純物濃度
が隣接する第2のp型領域42の表面側の不純物濃度に
比して低くなっている。斯かる場合でも、オフ状態にお
いて第2のn型領域41の表面側部分41aが空欠化し
ても、隣接する第2のp型領域42の表面側は完全には
空欠化せず、p型領域としてキャリアが幾分残るため、
これがガードリングとして機能し、表面側で互いに接近
する等電位線のうち高電位側の等電位線を第2のp型領
域42の表面側部分の外側へ振り分ける。このため、フ
ィールドプレートFPの先端よりも外側に位置する耐圧
構造部40での表面電界が緩和し、高耐圧化を図ること
ができる。Further, in the present embodiment, the second outer pressure-resistant portion 40 is located outside the tip of the field plate FP.
The impurity concentration of the surface side portion 41a of the n-type region 41 is lower than the impurity concentration of the adjacent second p-type region 42 on the surface side. Even in such a case, even if the surface side portion 41a of the second n-type region 41 is vacant in the off state, the surface side of the adjacent second p-type region 42 is not completely vacant, and p Since some carrier remains as the mold area,
This functions as a guard ring, and among the equipotential lines that are close to each other on the surface side, the equipotential lines on the high potential side are distributed to the outside of the surface side portion of the second p-type region 42. For this reason, the surface electric field in the breakdown voltage structure portion 40 located outside the tip of the field plate FP is relaxed, and a high breakdown voltage can be achieved.
【0042】このように本例では、第2の並列pn構造
のうち第2のp型領域42の表面側部分42aのように
幅広に形成する必要がなく、不純物の調節で済むから、
不純物導入マスクを減らすことができる。なお、第2の
p型領域42の表面側部分の不純物濃度は第2のn型領
域41の表面側部分の不純物濃度よりも高くしても良
い。As described above, in this example, it is not necessary to form the second side-by-side pn structure as wide as the surface side portion 42a of the second p-type region 42, and the adjustment of impurities is sufficient.
The impurity introduction mask can be reduced. The impurity concentration of the surface side portion of the second p-type region 42 may be higher than the impurity concentration of the surface side portion of the second n-type region 41.
【0043】[実施例4]図6は本発明の実施例4に係
る縦形MOSFET素子のチップを示す概略平面図、図
7は図6中のA−A′線に沿って切断した状態を示す縦
断面図、図8は図6中のB−B′線に沿って切断した状
態を示す縦断面図である。[Embodiment 4] FIG. 6 is a schematic plan view showing a chip of a vertical MOSFET device according to Embodiment 4 of the present invention, and FIG. 7 shows a state cut along the line AA 'in FIG. FIG. 8 is a vertical sectional view showing a state of being cut along the line BB ′ in FIG.
【0044】実施例1では、第1の並列pn構造におけ
る繰り返しピッチP1の方向と第2の並列pn構造にお
ける繰り返しピッチP2の方向とが同方向なっている
が、本例では、第1の並列pn構造における繰り返しピ
ッチP1の方向と第2の並列pn構造における繰り返し
ピッチP2の方向とが直交している。即ち、第1の並列
pn構造の平面的ストライプと第2の並列pn構造の平
面的ストライプとが直交している。ストライプ方向が変
わっても、逆電圧印加時に空乏化して耐圧を維持できる
ことにか変わりが無く、またストライプ方向の変わり目
でのチャージバランスが崩れた場合でも、内側耐圧部3
0が存在しているため、高耐圧化を図ることができる。In the first embodiment, the direction of the repeating pitch P1 in the first parallel pn structure is the same as the direction of the repeating pitch P2 in the second parallel pn structure. The direction of the repeating pitch P1 in the pn structure and the direction of the repeating pitch P2 in the second parallel pn structure are orthogonal to each other. That is, the planar stripes of the first parallel pn structure and the planar stripes of the second parallel pn structure are orthogonal to each other. Even if the stripe direction changes, there is no difference in that the breakdown voltage can be maintained when the reverse voltage is applied and the breakdown voltage can be maintained. Even if the charge balance at the transition of the stripe direction is lost, the inner breakdown voltage portion 3
Since 0 exists, high breakdown voltage can be achieved.
【0045】なお、本発明は、上記実施例は縦形MOS
FET素子について説明したが、縦形ドリフト部を持つ
半導体装置一般に適用できることは言う迄もない。In the present invention, the above embodiment is based on the vertical MOS.
Although the FET element has been described, it goes without saying that it can be applied to general semiconductor devices having a vertical drift portion.
【0046】[0046]
【発明の効果】以上説明したように、本発明において、
ドリフト部の周りの耐圧構造部は、ドリフト部に隣接し
て繰り返しピッチが当該ドリフト部から引き続き1ピッ
チ以上外側へ延長された第1の並列pn構造一部分であ
る内周構造部と、この内周構造部に隣接した第2の並列
pn構造である外周構造部とを有することを特徴として
いるため、ドリフト部の隣接周辺部分には第1の並列p
n構造と第2の並列pn構造との境界が存在せず、その
境界は耐圧構造部の内周構造部と外周構造部との間に存
在することになるため、ドリフト部の隣接外周部分では
並列pn構造のチャージバランスの崩れが起こらず、そ
れ故、ドリフト部の隣接外周部分での表面電界を抑制で
き、高耐圧化及び大電流化を図ることができる。As described above, in the present invention,
The withstand voltage structure portion around the drift portion includes an inner peripheral structure portion which is a portion of a first parallel pn structure in which a repeating pitch is continuously extended from the drift portion to the outside by one pitch or more adjacent to the drift portion, and the inner peripheral structure portion. It has a second parallel pn structure and an outer peripheral structure part adjacent to the structure part. Therefore, the first parallel p structure is provided in the peripheral portion adjacent to the drift part.
Since there is no boundary between the n structure and the second parallel pn structure, and the boundary exists between the inner peripheral structure part and the outer peripheral structure part of the breakdown voltage structure part, in the outer peripheral part adjacent to the drift part. The charge balance of the parallel pn structure does not collapse, and therefore, the surface electric field at the adjacent outer peripheral portion of the drift portion can be suppressed, and high breakdown voltage and large current can be achieved.
【図1】本発明の実施例1に係る縦形MOSFET素子
のチップを示す概略平面図である。FIG. 1 is a schematic plan view showing a chip of a vertical MOSFET device according to a first embodiment of the present invention.
【図2】図1中のA−A′線に沿って切断した状態を示
す縦断面図である。FIG. 2 is a vertical cross-sectional view showing a state cut along line AA ′ in FIG.
【図3】本発明の実施例2に係る縦形MOSFETを示
す部分縦断面図である。FIG. 3 is a partial vertical sectional view showing a vertical MOSFET according to a second embodiment of the present invention.
【図4】本発明の実施例3に係る縦形MOSFET素子
のチップを示す概略平面図である。FIG. 4 is a schematic plan view showing a chip of a vertical MOSFET device according to a third embodiment of the present invention.
【図5】図4中のA−A′線に沿って切断した状態を示
す縦断面図である。5 is a vertical cross-sectional view showing a state cut along the line AA 'in FIG.
【図6】本発明の実施例4に係る縦形MOSFET素子
のチップを示す概略平面図である。FIG. 6 is a schematic plan view showing a chip of a vertical MOSFET device according to a fourth embodiment of the present invention.
【図7】図6中のA−A′線に沿って切断した状態を示
す縦断面図である。FIG. 7 is a vertical cross-sectional view showing a state cut along the line AA ′ in FIG.
【図8】図6中のB−B′線に沿って切断した状態を示
す縦断面図である。FIG. 8 is a vertical cross-sectional view showing a state of being cut along the line BB ′ in FIG.
【図9】縦形MOSFETにおけるドリフト部及び素子
外周部(耐圧構造部)を示す平面図である。FIG. 9 is a plan view showing a drift portion and an element outer peripheral portion (breakdown voltage structure portion) in a vertical MOSFET.
【図10】図9中のA−A′線に沿って切断した状態を
示す縦断面図である。10 is a vertical cross-sectional view showing a state of being cut along the line AA ′ in FIG.
【図11】図9中のB−B′線に沿って切断した状態を
示す縦断面図である。FIG. 11 is a vertical cross-sectional view showing a state cut along the line BB ′ in FIG. 9.
11…n+ ドレイン層(コンタクト層) 12e…挾間領域 13a…pベース領域(pウェル) 14…n+ ソース領域 15…ゲート絶縁膜 16…ゲート電極層 17…ソース電極 18…ドレイン電極 19a…層間絶縁膜 22…ドレイン・ドリフト部 22a…第1のn型領域 22b…第1のp型領域 26…p+ コンタクト領域 30…内周構造部 40…外周構造部 41…第2のn型領域 41a,42a…表面側部分 42…第2のp型領域 50…n型囲繞領域 51…ストッパー電極 123…酸化膜 123a…内周域酸化膜 123b…中間域酸化膜 123c…外周域酸化膜 P1…第1の並列pn構造の繰り返しピッチ P2…第2の並列pn構造の繰り返しピッチ FP…フィールドプレート S1,S2…段差 S3…フィールドプレートの先端 T1〜T5…pn接合面の表面側位置11 ... n + drain layer (contact layer) 12e ... interleaved region 13a ... p base region (p well) 14 ... n + source region 15 ... gate insulating film 16 ... gate electrode layer 17 ... source electrode 18 ... drain electrode 19a ... interlayer Insulating film 22 ... Drain / drift part 22a ... First n-type region 22b ... First p-type region 26 ... P + contact region 30 ... Inner peripheral structure part 40 ... Outer peripheral structure part 41 ... Second n-type region 41a , 42a ... Surface-side portion 42 ... Second p-type region 50 ... N-type surrounding region 51 ... Stopper electrode 123 ... Oxide film 123a ... Inner region oxide film 123b ... Intermediate region oxide film 123c ... Outer region oxide film P1 ... Repeat pitch P2 of one parallel pn structure ... Repeat pitch FP of second parallel pn structure ... Field plates S1, S2 ... Step S3 ... Tip of field plate T1 to T5 Surface-side position of the pn junction surface
Claims (19)
活性部に導電接続する第1の電極層と、前記基板の第2
主面側に形成されて成る第1導電型の低抵抗層に導電接
続する第2の電極層と、前記素子活性部と前記低抵抗層
との間に介在し、オン状態ではドリフト電流が縦方向に
流れると共にオフ状態では空乏化する縦形ドリフト部
と、前記縦形ドリフト部の周りで前記第1主面と前記低
抵抗層との間に介在し、オン状態では概ね非電路領域で
あってオフ状態では空乏化する耐圧構造部とを有し、前
記縦形ドリフト部は前記基板の厚み方向に配向する第1
の縦形第1導電型領域と前記基板の厚み方向に配向する
第1の縦形第2導電型領域とを交互に繰り返して接合し
て成る第1の並列pn構造であると共に、前記耐圧構造
部は前記基板の厚み方向に配向する第2の縦形第1導電
型領域と前記基板の厚み方向に配向する第2の縦形第2
導電型領域とを交互に繰り返して接合して成る第2の並
列pn構造を有し、前記第2の並列pn構造の不純物濃
度が前記第1の並列pn構造の不純物濃度よりも低くな
っている半導体装置において、 前記耐圧構造部は、前記ドリフト部に隣接して繰り返し
ピッチが当該ドリフト部から引き続き1ピッチ以上外側
へ延長された前記第1の並列pn構造の一部分である内
周構造部と、この内周構造部に隣接した前記第2の並列
pn構造である外周構造部とを有することを特徴とする
半導体装置。1. A first electrode layer conductively connected to an element active portion formed on a first main surface side of a substrate, and a second electrode layer of the substrate.
The second electrode layer formed on the main surface side and conductively connected to the low-resistance layer of the first conductivity type is interposed between the element active portion and the low-resistance layer. Flowing in the direction and depleted in the off state, and interposed between the first main surface and the low resistance layer around the vertical drift part, and in the on state, it is a non-electric path region and is off. The vertical drift portion is oriented in the thickness direction of the substrate.
Of the first parallel type pn structure in which the first vertical conductivity type regions and the first vertical second conductivity type regions oriented in the thickness direction of the substrate are alternately and repeatedly joined, and the breakdown voltage structure portion is A second vertical first conductivity type region oriented in the thickness direction of the substrate and a second vertical second region oriented in the thickness direction of the substrate.
It has a second parallel pn structure formed by alternately repeating and joining conductive type regions, and the impurity concentration of the second parallel pn structure is lower than the impurity concentration of the first parallel pn structure. In the semiconductor device, the breakdown voltage structure portion is an inner peripheral structure portion that is adjacent to the drift portion and is a part of the first parallel pn structure in which a repeating pitch is continuously extended outward from the drift portion by one pitch or more, A semiconductor device having an outer peripheral structure part that is the second parallel pn structure adjacent to the inner peripheral structure part.
活性部に導電接続する第1の電極層と、前記基板の第2
主面側に形成されて成る第1導電型の低抵抗層に導電接
続する第2の電極層と、前記素子活性部と前記低抵抗層
との間に介在し、オン状態ではドリフト電流を縦方向に
流れると共にオフ状態では空乏化する縦形ドリフト部
と、前記縦形ドリフト部の周りで前記第1主面と前記低
抵抗層との間に介在し、オン状態では概ね非電路領域で
あってオフ状態では空乏化する耐圧構造部とを有し、前
記縦形ドリフト部は前記基板の厚み方向に配向する第1
の縦形第1導電型領域と前記基板の厚み方向に配向する
第1の縦形第2導電型領域とを交互に繰り返して接合し
て成る第1の並列pn構造であると共に、前記耐圧構造
部は前記基板の厚み方向に配向する第2の縦形第1導電
型領域と前記基板の厚み方向に配向する第2の縦形第2
導電型領域とを交互に繰り返して接合して成る第2の並
列pn構造を有し、前記第2の並列pn構造の繰り返し
ピッチが前記第1の並列pn構造の繰り返しピッチより
も小さくなっている半導体装置において、 前記耐圧構造部は、前記ドリフト部に隣接して繰り返し
ピッチが当該ドリフト部から引き続き1ピッチ以上外側
へ延長された前記第1の並列pn構造の一部分である内
周構造部と、この内周構造部に隣接した前記第2の並列
pn構造である外周構造部とを有することを特徴とする
半導体装置。2. A first electrode layer conductively connected to an element active portion formed on the first main surface side of the substrate, and a second electrode layer of the substrate.
The second electrode layer formed on the main surface side and conductively connected to the low-resistance layer of the first conductivity type is interposed between the element active portion and the low-resistance layer, and a drift current is vertically generated in the ON state. Flowing in the direction and depleted in the off state, and interposed between the first main surface and the low resistance layer around the vertical drift part, and in the on state, it is a non-electric path region and is off. The vertical drift portion is oriented in the thickness direction of the substrate.
Of the first parallel type pn structure in which the first vertical conductivity type regions and the first vertical second conductivity type regions oriented in the thickness direction of the substrate are alternately and repeatedly joined, and the breakdown voltage structure portion is A second vertical first conductivity type region oriented in the thickness direction of the substrate and a second vertical second region oriented in the thickness direction of the substrate.
A second parallel pn structure is formed by alternately and repeatedly joining conductive type regions, and the repeating pitch of the second parallel pn structure is smaller than the repeating pitch of the first parallel pn structure. In the semiconductor device, the breakdown voltage structure portion is an inner peripheral structure portion that is adjacent to the drift portion and is a part of the first parallel pn structure in which a repeating pitch is continuously extended outward by one pitch or more from the drift portion, A semiconductor device having an outer peripheral structure part that is the second parallel pn structure adjacent to the inner peripheral structure part.
圧構造部の前記第1主面上に絶縁膜を有し、前記絶縁膜
の上には前記内周構造部を覆って先端が前記外周構造部
の上にまで張り出て成るフィールドプレートを有するこ
とを特徴する半導体装置。3. The insulating film is formed on the first main surface of the pressure-resistant structure portion, and the tip covers the inner peripheral structure portion on the insulating film. A semiconductor device having a field plate formed so as to extend above the peripheral structure portion.
厚が前記ドリフト部側から前記外周構造部側に向けて厚
くなっていることを特徴とする半導体装置。4. The semiconductor device according to claim 3, wherein the insulating film has a film thickness that increases from the drift portion side toward the outer peripheral structure portion side.
厚が前記ドリフト部側から前記外周構造部側に向けて段
階的に厚くなっていることを特徴とする半導体装置。5. The semiconductor device according to claim 4, wherein the insulating film has a film thickness that gradually increases from the drift portion side toward the outer peripheral structure portion side.
数は2以上であることを特徴とする半導体装置。6. The semiconductor device according to claim 5, wherein the number of steps of film thickness of the insulating film is 2 or more.
周構造部に属する前記第1の並列pn構造の一部分のう
ちで前記第1の縦形第2導電型領域を外側に持つpn接
合面の第1主面側位置と前記フィールドプレートの段差
位置とが合致していることを特徴とする半導体装置。7. The pn junction surface according to claim 5 or 6, wherein the first vertical second conductivity type region is provided outside of a portion of the first parallel pn structure belonging to the inner peripheral structure portion. The semiconductor device, wherein the position on the first main surface side and the step position of the field plate are matched.
おいて、前記第2の並列pn構造のうちで前記第2の縦
形第2導電型領域を外側に持つpn接合面の第1主面側
位置と前記フィールドプレートの先端位置とが合致して
いることを特徴とする半導体装置。8. The first main pn junction surface according to claim 3, wherein the second vertical pn junction surface of the second parallel pn structure has the second vertical second conductivity type region outside. A semiconductor device, wherein a surface side position and a tip position of the field plate coincide with each other.
おいて、前記第2の並列pn構造のうちで前記フィール
ドプレートの先端よりも外側に位置する前記第2の縦形
第2導電型領域の第1主面側の不純物濃度が隣接する前
記第2の縦形第1導電型領域の第1主面側の不純物濃度
に比して高いことを特徴とする半導体装置。9. The second vertical second conductivity type region according to any one of claims 3 to 8, wherein the second vertical second conductivity type region is located outside the tip of the field plate in the second parallel pn structure. The semiconductor device is characterized in that the impurity concentration on the first main surface side is higher than the impurity concentration on the first main surface side of the adjacent second vertical first conductivity type region.
において、前記第2の並列pn構造のうちで前記フィー
ルドプレートの先端よりも外側に位置する前記第2の縦
形第2導電型領域の第1主面側の幅寸法が隣接する前記
第2の縦形第1導電型領域の第1主面側の幅寸法に比し
て広いことを特徴とする半導体装置。10. The second vertical second conductivity type region according to any one of claims 3 to 8, wherein the second vertical second conductivity type region is located outside the tip of the field plate in the second parallel pn structure. The semiconductor device is characterized in that the width dimension on the first main surface side is wider than the width dimension on the first main surface side of the adjacent second vertical first conductivity type regions.
において、前記第2の並列pn構造のうちで前記フィー
ルドプレートの先端よりも外側に位置する前記第2の縦
形第1導電型領域の第1主面側の不純物濃度が隣接する
前記第2の第2導電型領域の第1主面側の不純物濃度に
比して低いことを特徴とする半導体装置。11. The second vertical first conductivity type region according to any one of claims 3 to 8, wherein the second vertical first conductivity type region is located outside the tip of the field plate in the second parallel pn structure. The semiconductor device is characterized in that the impurity concentration on the first main surface side is lower than the impurity concentration on the first main surface side of the adjacent second second conductivity type region.
項において、前記第1の並列pn構造及び前記第2の並
列pn構造が平面的にストライプ状であることを特徴と
する半導体装置。12. The semiconductor device according to claim 1, wherein the first parallel pn structure and the second parallel pn structure are planar stripes.
項において、前記第1の並列pn構造における繰り返し
ピッチの方向と前記第2の並列pn構造における繰り返
しピッチの方向とが略直交していることを特徴とする半
導体装置。13. The repetitive pitch direction in the first parallel pn structure and the repetitive pitch direction in the second parallel pn structure are substantially orthogonal to each other according to any one of claims 1 to 12. A semiconductor device characterized in that
項において、前記外周構造部を取り囲む第1導電型囲繞
領域を有することを特徴とする半導体装置。14. The semiconductor device according to claim 1, further comprising a first conductivity type surrounding region surrounding the outer peripheral structure portion.
囲繞領域の第1主面側に導電接触する第3の電極部を有
することを特徴とする半導体装置。15. The semiconductor device according to claim 14, further comprising a third electrode portion that is in conductive contact with a side of the first main surface of the first conductivity type surrounding area.
子活性部に導電接続する第1の電極層と、前記基板の第
2主面側に形成されて成る第1導電型の低抵抗層に導電
接続する第2の電極層と、前記素子活性部と前記低抵抗
層との間に介在し、オン状態ではドリフト電流が縦方向
に流れると共にオフ状態では空乏化する縦形ドリフト部
と、前記縦形ドリフト部の周りで前記第1主面と前記低
抵抗層との間に介在し、オン状態では概ね非電路領域で
あってオフ状態では空乏化する耐圧構造部とを有し、前
記縦形ドリフト部は前記基板の厚み方向に配向する第1
の縦形第1導電型ドリフト領域と前記基板の厚み方向に
配向する第1の縦形第2導電型仕切領域とを交互に繰り
返して接合して成る第1の並列pn構造であると共に、
前記耐圧構造部は前記基板の厚み方向に配向する第2の
縦形第1導電型領域と前記基板の厚み方向に配向する第
2の縦形第2導電型領域とを交互に繰り返して接合して
成る第2の並列pn構造を有し、前記耐圧構造部の第1
主面上の絶縁膜の上に形成されて成るフィールドプレー
トを有する半導体装置において、 前記第2の並列pn構造のうちで前記第2の縦形第2導
電型領域を外側に持つpn接合面の第1主面側位置と前
記フィールドプレートの先端位置とが合致していること
を特徴とする半導体装置。16. A first conductive layer formed on the first main surface side of the substrate and conductively connected to an element active portion, and a first conductivity type low layer formed on the second main surface side of the substrate. A second electrode layer that is conductively connected to the resistance layer; and a vertical drift portion that is interposed between the element active portion and the low resistance layer and that has a drift current flowing in the vertical direction in the on state and depleted in the off state. A breakdown voltage structure portion that is interposed between the first main surface and the low resistance layer around the vertical drift portion and that is substantially a non-electric path region in an on state and is depleted in an off state, The vertical drift portion has a first orientation oriented in the thickness direction of the substrate.
And a first parallel pn structure formed by alternately and repeatedly joining the vertical first conductivity type drift regions and the first vertical second conductivity type partition regions oriented in the thickness direction of the substrate.
The breakdown voltage structure portion is formed by alternately and repeatedly joining second vertical first conductivity type regions oriented in the thickness direction of the substrate and second vertical second conductivity type regions oriented in the thickness direction of the substrate. It has a second parallel pn structure,
In a semiconductor device having a field plate formed on an insulating film on a main surface, a second pn junction surface having the second vertical second conductivity type region on the outside of the second parallel pn structure is provided. 1. A semiconductor device characterized in that the position on the main surface side and the position of the tip of the field plate coincide with each other.
子活性部に導電接続する第1の電極層と、前記基板の第
2主面側に形成されて成る第1導電型の低抵抗層に導電
接続する第2の電極層と、前記素子活性部と前記低抵抗
層との間に介在し、オン状態ではドリフト電流が縦方向
に流れると共にオフ状態では空乏化する縦形ドリフト部
と、前記縦形ドリフト部の周りで前記第1主面と前記低
抵抗層との間に介在し、オン状態では概ね非電路領域で
あってオフ状態では空乏化する耐圧構造部とを有し、前
記縦形ドリフト部は前記基板の厚み方向に配向する第1
の縦形第1導電型ドリフト領域と前記基板の厚み方向に
配向する第1の縦形第2導電型仕切領域とを交互に繰り
返して接合して成る第1の並列pn構造であると共に、
前記耐圧構造部は前記基板の厚み方向に配向する第2の
縦形第1導電型領域と前記基板の厚み方向に配向する第
2の縦形第2導電型領域とを交互に繰り返して接合して
成る第2の並列pn構造を有し、前記耐圧構造部の第1
主面上の絶縁膜の上に形成されて成るフィールドプレー
トを有する半導体装置において、 前記第2の並列pn構造のうちで前記フィールドプレー
トの先端よりも外側に位置する前記第2の縦形第2導電
型領域の第1主面側の不純物濃度が隣接する前記第2の
縦形第1導電型領域の第1主面側の不純物濃度に比して
高いことを特徴とする半導体装置。17. A first conductive layer formed on the first main surface side of the substrate and conductively connected to an element active portion, and a first conductivity type low layer formed on the second main surface side of the substrate. A second electrode layer that is conductively connected to the resistance layer; and a vertical drift portion that is interposed between the element active portion and the low resistance layer and that has a drift current flowing in the vertical direction in the on state and depleted in the off state. A breakdown voltage structure portion that is interposed between the first main surface and the low resistance layer around the vertical drift portion and that is substantially a non-electric path region in an on state and is depleted in an off state, The vertical drift portion has a first orientation oriented in the thickness direction of the substrate.
And a first parallel pn structure in which the vertical first conductivity type drift regions and the first vertical second conductivity type partition regions oriented in the thickness direction of the substrate are alternately and repeatedly joined.
The breakdown voltage structure portion is formed by alternately and repeatedly joining second vertical first conductivity type regions oriented in the thickness direction of the substrate and second vertical second conductivity type regions oriented in the thickness direction of the substrate. It has a second parallel pn structure,
In a semiconductor device having a field plate formed on an insulating film on a main surface, in the second parallel pn structure, the second vertical second conductive member located outside an end of the field plate. A semiconductor device, wherein the impurity concentration on the first main surface side of the type region is higher than the impurity concentration on the first main surface side of the adjacent second vertical first conductivity type region.
子活性部に導電接続する第1の電極層と、前記基板の第
2主面側に形成されて成る第1導電型の低抵抗層に導電
接続する第2の電極層と、前記素子活性部と前記低抵抗
層との間に介在し、オン状態ではドリフト電流が縦方向
に流れると共にオフ状態では空乏化する縦形ドリフト部
と、前記縦形ドリフト部の周りで前記第1主面と前記低
抵抗層との間に介在し、オン状態では概ね非電路領域で
あってオフ状態では空乏化する耐圧構造部とを有し、前
記縦形ドリフト部は前記基板の厚み方向に配向する第1
の縦形第1導電型ドリフト領域と前記基板の厚み方向に
配向する第1の縦形第2導電型仕切領域とを交互に繰り
返して接合して成る第1の並列pn構造であると共に、
前記耐圧構造部は前記基板の厚み方向に配向する第2の
縦形第1導電型領域と前記基板の厚み方向に配向する第
2の縦形第2導電型領域とを交互に繰り返して接合して
成る第2の並列pn構造を有し、前記耐圧構造部の第1
主面上の絶縁膜の上に形成されて成るフィールドプレー
トを有する半導体装置において、 前記第2の並列pn構造のうちで前記フィールドプレー
トの先端よりも外側に位置する前記第2の縦形第2導電
型領域の第1主面側の幅寸法が隣接する前記第2の縦形
第1導電型領域の第1主面側の幅寸法に比して広いこと
を特徴とする半導体装置。18. A first conductive layer formed on the side of the first main surface of the substrate and conductively connected to an element active portion, and a first conductivity type low layer formed on the side of the second main surface of the substrate. A second electrode layer that is conductively connected to the resistance layer; and a vertical drift portion that is interposed between the element active portion and the low resistance layer and that has a drift current flowing in the vertical direction in the on state and depleted in the off state. A breakdown voltage structure portion that is interposed between the first main surface and the low resistance layer around the vertical drift portion and that is substantially a non-electric path region in an on state and is depleted in an off state, The vertical drift portion has a first orientation oriented in the thickness direction of the substrate.
And a first parallel pn structure formed by alternately and repeatedly joining the vertical first conductivity type drift regions and the first vertical second conductivity type partition regions oriented in the thickness direction of the substrate.
The breakdown voltage structure portion is formed by alternately and repeatedly joining second vertical first conductivity type regions oriented in the thickness direction of the substrate and second vertical second conductivity type regions oriented in the thickness direction of the substrate. It has a second parallel pn structure,
In a semiconductor device having a field plate formed on an insulating film on a main surface, in the second parallel pn structure, the second vertical second conductive member located outside an end of the field plate. A semiconductor device, wherein the width dimension of the first main surface side of the mold region is wider than the width dimension of the adjacent second vertical first conductivity type region on the first main surface side.
子活性部に導電接続する第1の電極層と、前記基板の第
2主面側に形成されて成る第1導電型の低抵抗層に導電
接続する第2の電極層と、前記素子活性部と前記低抵抗
層との間に介在し、オン状態ではドリフト電流が縦方向
に流れると共にオフ状態では空乏化する縦形ドリフト部
と、前記縦形ドリフト部の周りで前記第1主面と前記低
抵抗層との間に介在し、オン状態では概ね非電路領域で
あってオフ状態では空乏化する耐圧構造部とを有し、前
記縦形ドリフト部は前記基板の厚み方向に配向する第1
の縦形第1導電型ドリフト領域と前記基板の厚み方向に
配向する第1の縦形第2導電型仕切領域とを交互に繰り
返して接合して成る第1の並列pn構造であると共に、
前記耐圧構造部は前記基板の厚み方向に配向する第2の
縦形第1導電型領域と前記基板の厚み方向に配向する第
2の縦形第2導電型領域とを交互に繰り返して接合して
成る第2の並列pn構造を有し、前記耐圧構造部の第1
主面上の絶縁膜の上に形成されて成るフィールドプレー
トを有する半導体装置において、 前記第2の並列pn構造のうちで前記フィールドプレー
トの先端よりも外側に位置する前記第2の縦形第1導電
型領域の第1主面側の不純物濃度が隣接する前記第2の
第2導電型領域の第1主面側の不純物濃度に比して低い
ことを特徴とする半導体装置。19. A first electrode layer conductively connected to an element active portion formed on a first main surface side of a substrate, and a first conductivity type low layer formed on a second main surface side of the substrate. A second electrode layer that is conductively connected to the resistance layer; and a vertical drift portion that is interposed between the element active portion and the low resistance layer and that has a drift current flowing in the vertical direction in the on state and depleted in the off state. A breakdown voltage structure portion that is interposed between the first main surface and the low resistance layer around the vertical drift portion and that is substantially a non-electric path region in an on state and is depleted in an off state, The vertical drift portion has a first orientation oriented in the thickness direction of the substrate.
And a first parallel pn structure formed by alternately and repeatedly joining the vertical first conductivity type drift regions and the first vertical second conductivity type partition regions oriented in the thickness direction of the substrate.
The breakdown voltage structure portion is formed by alternately and repeatedly joining second vertical first conductivity type regions oriented in the thickness direction of the substrate and second vertical second conductivity type regions oriented in the thickness direction of the substrate. It has a second parallel pn structure,
In a semiconductor device having a field plate formed on an insulating film on a main surface, the second vertical first conductive member located outside the tip of the field plate in the second parallel pn structure. A semiconductor device, wherein the impurity concentration on the first main surface side of the type region is lower than the impurity concentration on the first main surface side of the adjacent second second conductivity type region.
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005203565A (en) * | 2004-01-15 | 2005-07-28 | Fuji Electric Holdings Co Ltd | Semiconductor device and its manufacturing method |
| JP2005260199A (en) * | 2004-02-09 | 2005-09-22 | Fuji Electric Holdings Co Ltd | Semiconductor device and manufacturing method of semiconductor device |
| JP2007005516A (en) * | 2005-06-23 | 2007-01-11 | Toyota Central Res & Dev Lab Inc | Semiconductor device and manufacturing method thereof |
| JP2008235547A (en) * | 2007-03-20 | 2008-10-02 | Denso Corp | Semiconductor device and semiconductor chip used therefor |
| US7541643B2 (en) | 2005-04-07 | 2009-06-02 | Kabushiki Kaisha Toshiba | Semiconductor device |
| WO2011013379A1 (en) * | 2009-07-31 | 2011-02-03 | Fuji Electric Systems Co., Ltd. | Semiconductor apparatus |
| WO2013046544A1 (en) * | 2011-09-27 | 2013-04-04 | 株式会社デンソー | Semiconductor device |
| JP2013084912A (en) * | 2011-09-27 | 2013-05-09 | Denso Corp | Semiconductor device |
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| US9478621B2 (en) | 2011-09-27 | 2016-10-25 | Denso Corporation | Semiconductor device |
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2002
- 2002-01-08 JP JP2002001282A patent/JP4126910B2/en not_active Expired - Lifetime
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005203565A (en) * | 2004-01-15 | 2005-07-28 | Fuji Electric Holdings Co Ltd | Semiconductor device and its manufacturing method |
| JP2005260199A (en) * | 2004-02-09 | 2005-09-22 | Fuji Electric Holdings Co Ltd | Semiconductor device and manufacturing method of semiconductor device |
| US7541643B2 (en) | 2005-04-07 | 2009-06-02 | Kabushiki Kaisha Toshiba | Semiconductor device |
| JP2007005516A (en) * | 2005-06-23 | 2007-01-11 | Toyota Central Res & Dev Lab Inc | Semiconductor device and manufacturing method thereof |
| JP2008235547A (en) * | 2007-03-20 | 2008-10-02 | Denso Corp | Semiconductor device and semiconductor chip used therefor |
| CN102473721A (en) * | 2009-07-31 | 2012-05-23 | 富士电机株式会社 | Semiconductor apparatus |
| WO2011013379A1 (en) * | 2009-07-31 | 2011-02-03 | Fuji Electric Systems Co., Ltd. | Semiconductor apparatus |
| JP2012533167A (en) * | 2009-07-31 | 2012-12-20 | 富士電機株式会社 | Semiconductor device |
| CN102473721B (en) * | 2009-07-31 | 2015-05-06 | 富士电机株式会社 | Semiconductor apparatus |
| US9577087B2 (en) | 2009-07-31 | 2017-02-21 | Fui Electric Co., Ltd. | Semiconductor apparatus |
| US8735982B2 (en) | 2010-11-09 | 2014-05-27 | Fuji Electric Co., Ltd. | Semiconductor device with superjunction structure |
| WO2013046544A1 (en) * | 2011-09-27 | 2013-04-04 | 株式会社デンソー | Semiconductor device |
| JP2013084912A (en) * | 2011-09-27 | 2013-05-09 | Denso Corp | Semiconductor device |
| US9478621B2 (en) | 2011-09-27 | 2016-10-25 | Denso Corporation | Semiconductor device |
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