JP2003289119A - Manufacturing method of ceramic multilayer wiring board - Google Patents
Manufacturing method of ceramic multilayer wiring boardInfo
- Publication number
- JP2003289119A JP2003289119A JP2002092344A JP2002092344A JP2003289119A JP 2003289119 A JP2003289119 A JP 2003289119A JP 2002092344 A JP2002092344 A JP 2002092344A JP 2002092344 A JP2002092344 A JP 2002092344A JP 2003289119 A JP2003289119 A JP 2003289119A
- Authority
- JP
- Japan
- Prior art keywords
- cavity
- ceramic
- laminate
- green sheet
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】
【課題】 セラミックス積層体の表面に凹設されたキャ
ビティの底面に電子部品が搭載されているセラミックス
多層配線基板の製造方法において、セラミックス積層体
のキャビティの底面に高い平面度を得る。
【解決手段】 本発明に係るセラミックス多層配線基板
の製造方法においては、キャビティ21を有するグリーン
シート積層体24を作製した後、該グリーンシート積層体
24の表面に、キャビティ21を覆ってゴム硬度が３０度以
下の弾性シート７を被せ、該弾性シート７を介してグリ
ーンシート積層体24に静水圧による熱プレスを施す。そ
の後、グリーンシート積層体24に焼成及び分断を施し、
これによって得られたセラミックス積層体のキャビティ
底面に電子部品を実装する。
PROBLEM TO BE SOLVED: To provide a method of manufacturing a ceramic multilayer wiring board in which an electronic component is mounted on a bottom surface of a cavity recessed in a surface of a ceramic laminate, and a high flatness is provided on a bottom surface of the cavity of the ceramic laminate. Get. SOLUTION: In the method for manufacturing a ceramic multilayer wiring board according to the present invention, after forming a green sheet laminate 24 having a cavity 21, the green sheet laminate is formed.
An elastic sheet 7 having a rubber hardness of 30 degrees or less is covered on the surface of the cavity 24 and the green sheet laminate 24 is subjected to hot pressing by hydrostatic pressure through the elastic sheet 7. After that, the green sheet laminate 24 is fired and cut,
Electronic components are mounted on the bottom surfaces of the cavities of the ceramic laminate thus obtained.
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、携帯電話機等の電
子機器に装備される各種電子回路を構成するためのセラ
ミックス多層配線基板の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a ceramic multilayer wiring board for forming various electronic circuits mounted on electronic equipment such as a mobile phone.
【０００２】[0002]
【従来の技術】従来、携帯電話機等の小型の電子機器に
おいては、機器を構成する複数の回路素子を１チップの
セラミックス多層配線基板に集積化して、該セラミック
ス多層基板をメイン基板上に実装することが行なわれて
いる。図５は、セラミックス多層配線基板(１)の積層構
造を表わしており、複数のセラミックス層(２)が積層さ
れて、セラミックス積層体(20)を構成している。各セラ
ミックス層(２)の表面には、インダクタやコンデンサを
構成する複数の回路素子パターン(３)が形成されてい
る。これらの回路素子パターン(３)は、セラミックス層
(２)を貫通して形成された垂直導電路(以下、バイアホ
ールという)(31)によって互いに接続されている。又、
セラミックス積層体(20)の表面にはキャビティ(21)が凹
設され、該キャビティ(21)の底面に、弾性表面波フィル
ター等の電子部品(４)が搭載されており、該電子部品
(４)はボンディングワイヤ(32)を介して前記回路素子パ
ターン(３)と接続されている。セラミックス積層体(20)
の表面には、キャビティ(21)を覆って蓋体(５)が設置さ
れ、パッケージ化されたセラミックス多層配線基板(１)
を構成している。2. Description of the Related Art Conventionally, in a small electronic device such as a mobile phone, a plurality of circuit elements constituting the device are integrated on a one-chip ceramic multilayer wiring board and the ceramic multilayer board is mounted on a main board. Is being done. FIG. 5 shows a laminated structure of the ceramic multilayer wiring board (1), and a plurality of ceramic layers (2) are laminated to form a ceramic laminated body (20). On the surface of each ceramic layer (2), a plurality of circuit element patterns (3) forming an inductor and a capacitor are formed. These circuit element patterns (3) consist of ceramic layers
They are connected to each other by a vertical conductive path (hereinafter, referred to as a via hole) (31) formed through (2). or,
A cavity (21) is provided on the surface of the ceramic laminate (20), and an electronic component (4) such as a surface acoustic wave filter is mounted on the bottom surface of the cavity (21).
(4) is connected to the circuit element pattern (3) via a bonding wire (32). Ceramics laminated body (20)
A lid (5) is installed on the surface of the so as to cover the cavity (21), and the packaged ceramic multilayer wiring board (1)
Are configured.
【０００３】上記セラミックス多層配線基板(１)は、図
４に示す工程によって製造されている。先ず図４(ａ)の
如く、セラミックス混合材料からなるグリーンシート(2
5)を作製する。次に、同図(ｂ)の如くグリーンシート(2
5)の必要箇所にキャビティ用貫通孔(22)やバイアホール
用貫通孔(23)を開設した後、同図(ｃ)の如くグリーンシ
ート(25)の表面に導電材料を印刷して、回路素子パター
ンやバイアホールとなる導体層(30)を形成する。The above-mentioned ceramic multilayer wiring board (1) is manufactured by the process shown in FIG. First, as shown in Fig. 4 (a), a green sheet (2
5) is produced. Next, as shown in Fig. 2 (b), the green sheet (2
After opening the through hole (22) for the cavity and the through hole (23) for the via hole at the required locations of 5), the conductive material is printed on the surface of the green sheet (25) as shown in FIG. A conductor layer (30) which will be an element pattern and a via hole is formed.
【０００４】この様にして得られたグリーンシート(25)
を複数層に積層して、図４(ｄ)に示すグリーンシート積
層体(24)を構成する。そして、該グリーンシート積層体
(24)を平板状の治具(６)上に設置すると共に、該グリー
ンシート積層体(24)の表面にシリコンゴム製の弾性シー
ト(７)を被せ、これらを樹脂製袋に収納して真空パック
化した状態で、適当な温度の液体に浸漬し、静水圧をか
ける。これによって、グリーンシート積層体(24)は熱プ
レスされて、一体化される。その後、図４(ｅ)に示す如
く一体化されたグリーンシート積層体(24)をキャビティ
(21)毎に分断して、複数の積層体チップ(26)を得る。そ
して、同図(ｆ)に示す如く各積層体チップ(26)に焼成を
施して、セラミックス積層体(20)を得る。The green sheet (25) thus obtained
Are laminated in a plurality of layers to form a green sheet laminate (24) shown in FIG. And the green sheet laminate
(24) is placed on a flat jig (6), the surface of the green sheet laminate (24) is covered with an elastic sheet (7) made of silicon rubber, and these are stored in a resin bag. In a vacuum packed state, it is immersed in a liquid at an appropriate temperature and hydrostatic pressure is applied. As a result, the green sheet laminate (24) is hot pressed and integrated. Then, the green sheet laminated body (24) integrated as shown in FIG.
Dividing into each (21) to obtain a plurality of laminated chips (26). Then, as shown in FIG. 6F, each laminated body chip (26) is fired to obtain a ceramic laminated body (20).
【０００５】この様にして得られたセラミックス積層体
(20)のキャビティ(21)の底面に、図５の如く電子部品
(４)を実装し、ワイヤボンディングを施し、蓋体(５)を
設置することによって、セラミックス多層配線基板(１)
が完成する。Ceramic laminate obtained in this way
On the bottom of the cavity (21) of (20), as shown in FIG.
By mounting (4), wire bonding, and installing the lid (5), the ceramic multilayer wiring board (1)
Is completed.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、従来の
セラミックス多層配線基板(１)においては、セラミック
ス積層体(20)のキャビティ(21)の底面の平坦性が悪く、
電子部品(４)の実装やワイヤボンディングが困難となっ
て、製造歩留まりが低い問題があった。そこで本発明の
目的は、セラミックス積層体(20)のキャビティ(21)の底
面に高い平面度が得られるセラミックス多層配線基板の
製造方法を提供することである。However, in the conventional ceramic multilayer wiring board (1), the flatness of the bottom surface of the cavity (21) of the ceramic laminate (20) is poor,
It becomes difficult to mount the electronic component (4) and wire bonding, and there is a problem that the manufacturing yield is low. Therefore, an object of the present invention is to provide a method for manufacturing a ceramic multilayer wiring board in which a high flatness is obtained on the bottom surface of the cavity (21) of the ceramic laminate (20).
【０００７】[0007]
【課題を解決する為の手段】本発明者らは、上記目的を
達成するべく鋭意研究を行なった結果、従来のセラミッ
クス多層配線基板においてセラミックス積層体のキャビ
ティの底面の平坦性が悪かった原因を次の様に究明し、
本発明の完成に至った。即ち、図４(ｄ)に示す従来のグ
リーンシート積層体(24)の熱プレス工程においては、図
２(ａ)に示す如く治具(６)上にグリーンシート積層体(2
4)を設置すると共に、該グリーンシート積層体(24)の表
面にキャビティ(21)を覆って弾性シート(７)を設置した
後、同図(ｂ)の如く弾性シート(７)を介してグリーンシ
ート積層体(24)に静水圧をかけた場合、弾性シート(７)
は、その弾性変形によってグリーンシート積層体(24)の
キャビティ底面(21a)(21b)に沿って屈曲することになる
が、従来はゴム硬度が５０度程度の弾性シート(７)が用
いられていたために、段差を有するキャビティ底面(21
a)(21b)に十分に密着しない状態で、キャビティ底面(21
a)(21b)を不均一に加圧することになり、この結果、図
２(ｃ)に示す様に加圧後のキャビティ底面(21a″)(21
b″)が平坦性の悪いものとなっていたのである。As a result of intensive studies aimed at achieving the above object, the inventors of the present invention have found that the flatness of the bottom surface of the cavity of the ceramic laminate in the conventional ceramic multilayer wiring board was poor. Investigate as follows,
The present invention has been completed. That is, in the hot pressing process of the conventional green sheet laminate (24) shown in FIG. 4 (d), the green sheet laminate (2) is placed on the jig (6) as shown in FIG. 2 (a).
4) is installed, and the elastic sheet (7) is installed on the surface of the green sheet laminate (24) so as to cover the cavity (21), and then, the elastic sheet (7) is interposed as shown in FIG. Elastic sheet (7) when hydrostatic pressure is applied to the green sheet laminate (24)
Will bend along the cavity bottom surfaces (21a), (21b) of the green sheet laminate (24) due to its elastic deformation, but conventionally, the elastic sheet (7) having a rubber hardness of about 50 degrees is used. The bottom of the cavity (21
a) (21b) is not fully adhered to the bottom of the cavity (21
a) (21b) is non-uniformly pressed, and as a result, as shown in FIG. 2 (c), the bottom surface (21a ″) (21
b ″) had poor flatness.
【０００８】上述の知見から、本発明においては、図４
(ｄ)に示すグリーンシート積層体(24)の熱プレス工程に
て、従来よりもゴム硬度の低い弾性シート(７)を用いる
こととした。即ち、本発明に係るセラミックス多層配線
基板の製造方法は、セラミックス層(２)となるグリーン
シート(25)を複数枚作製し、この中の必要枚数のグリー
ンシート(25)にキャビティ用貫通孔(22)を開設すると共
に、回路素子パターン(３)となる導体層(30)を形成する
第１工程と、第１工程を経て得られる複数枚のグリーン
シート(25)を積層して、キャビティ(21)を有するグリー
ンシート積層体(24)を作製する第２工程と、グリーンシ
ート積層体(24)の表面に、キャビティ(21)を覆ってゴム
硬度が３０度以下の弾性シート(７)を被せ、該弾性シー
ト(７)を介してグリーンシート積層体(24)に静水圧によ
る熱プレスを施す第３工程と、第３工程を経て得られる
グリーンシート積層体(24)に、焼成の後に分断を施し、
或いは分断の後に焼成を施すことによって、キャビティ
(21)を有するセラミックス積層体(20)を得る第４工程
と、セラミックス積層体(20)のキャビティ(21)に電子部
品(４)を実装する第５工程とを有している。第３工程で
用いる弾性シート(７)は、例えばシリコンゴム製であっ
て、厚さが約０.６ｍｍである。From the above findings, in the present invention, as shown in FIG.
In the step of hot pressing the green sheet laminate (24) shown in (d), the elastic sheet (7) having a lower rubber hardness than the conventional one is used. That is, in the method for manufacturing a ceramic multilayer wiring board according to the present invention, a plurality of green sheets (25) to be the ceramic layers (2) are prepared, and the necessary number of green sheets (25) among them are provided with cavity through holes ( 22), the first step of forming the conductor layer (30) to be the circuit element pattern (3) and a plurality of green sheets (25) obtained through the first step are stacked to form a cavity ( The second step of producing a green sheet laminate (24) having 21), and an elastic sheet (7) having a rubber hardness of 30 degrees or less covering the cavity (21) on the surface of the green sheet laminate (24). After the firing, the third step of subjecting the green sheet laminate (24) to thermal pressing by hydrostatic pressure through the elastic sheet (7) and the green sheet laminate (24) obtained through the third step Divide it,
Alternatively, by firing after dividing, the cavity
The method has a fourth step of obtaining the ceramic laminate (20) having (21) and a fifth step of mounting the electronic component (4) in the cavity (21) of the ceramic laminate (20). The elastic sheet (7) used in the third step is made of, for example, silicone rubber and has a thickness of about 0.6 mm.
【０００９】上記本発明のセラミックス多層配線基板の
製造方法においては、弾性シート(７)を介してグリーン
シート積層体(24)に静水圧による熱プレスを施す第３工
程にて、従来よりもゴム硬度の低い弾性シート(７)が用
いられているので、静水圧によって弾性シート(７)が十
分に屈曲して、グリーンシート積層体(24)のキャビティ
底面に接触することになる。この結果、キャビティ底面
が均一に加圧されて、キャビティ底面の平面度を維持し
たままグリーンシート積層体(24)が圧縮され、一体化さ
れる。In the above-mentioned method for manufacturing a ceramic multilayer wiring board of the present invention, in the third step of hydrostatically pressing the green sheet laminate (24) through the elastic sheet (7), rubber is used more than before. Since the elastic sheet (7) having low hardness is used, the elastic sheet (7) is sufficiently bent by hydrostatic pressure and comes into contact with the bottom surface of the cavity of the green sheet laminate (24). As a result, the bottom surface of the cavity is uniformly pressed, and the green sheet laminate (24) is compressed and integrated while maintaining the flatness of the bottom surface of the cavity.
【００１０】[0010]
【発明の効果】本発明に係るセラミックス多層配線基板
の製造方法によれば、グリーンシート積層体(24)のキャ
ビティ底面に高い平面度が得られるので、該グリーンシ
ート積層体(24)に分断及び焼成を施して得られるセラミ
ックス積層体(20)においても、キャビティ(21)の底面に
高い平面度が得られ、この結果、セラミックス多層配線
基板の製造歩留まりが向上する。EFFECTS OF THE INVENTION According to the method for manufacturing a ceramic multilayer wiring board according to the present invention, a high flatness can be obtained at the bottom surface of the cavity of the green sheet laminate (24). Also in the ceramic laminate (20) obtained by firing, a high flatness is obtained on the bottom surface of the cavity (21), and as a result, the manufacturing yield of the ceramic multilayer wiring board is improved.
【００１１】[0011]
【発明の実施の形態】以下、本発明の実施の形態につ
き、図面に沿って具体的に説明する。本発明に係るセラ
ミックス多層配線基板(１)は、図５に示す如く、複数の
セラミックス層(２)が積層されて、セラミックス積層体
(20)を構成している。各セラミックス層(２)の表面に
は、インダクタやコンデンサを構成する複数の回路素子
パターン(３)が形成されている。これらの回路素子パタ
ーン(３)は、セラミックス層(２)を貫通して形成された
バイアホール(31)によって互いに接続されている。又、
セラミックス積層体(20)の表面にはキャビティ(21)が凹
設され、該キャビティ(21)の底面に、弾性表面波フィル
ター等の電子部品(４)が搭載されており、該電子部品
(４)はボンディングワイヤ(32)を介して前記回路素子パ
ターン(３)と接続されている。セラミックス積層体(20)
の表面には、キャビティ(21)を覆って蓋体(５)が設置さ
れ、パッケージ化されたセラミックス多層配線基板(１)
を構成している。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be specifically described below with reference to the drawings. As shown in FIG. 5, a ceramic multilayer wiring board (1) according to the present invention has a plurality of ceramic layers (2) laminated to form a ceramic laminate.
It constitutes (20). On the surface of each ceramic layer (2), a plurality of circuit element patterns (3) forming an inductor and a capacitor are formed. These circuit element patterns (3) are connected to each other by via holes (31) formed through the ceramic layer (2). or,
A cavity (21) is provided on the surface of the ceramic laminate (20), and an electronic component (4) such as a surface acoustic wave filter is mounted on the bottom surface of the cavity (21).
(4) is connected to the circuit element pattern (3) via a bonding wire (32). Ceramics laminated body (20)
A lid (5) is installed on the surface of the so as to cover the cavity (21), and the packaged ceramic multilayer wiring board (1)
Are configured.
【００１２】尚、電子部品(４)が実装されたキャビティ
底面の幅は３ｍｍ、深さは１.１ｍｍであり、ワイヤボ
ンディングが施された２段目のキャビティ底面の幅は４
ｍｍ、深さは０.５ｍｍである。The bottom surface of the cavity on which the electronic component (4) is mounted has a width of 3 mm and a depth of 1.1 mm.
mm, the depth is 0.5 mm.
【００１３】上記セラミックス多層配線基板(１)は、図
４に示す工程によって製造されている。先ず図４(ａ)の
如く、セラミックス混合材料からなるグリーンシート(2
5)を作製する。次に、同図(ｂ)の如くグリーンシート(2
5)の必要箇所にキャビティ用貫通孔(22)やバイアホール
用貫通孔(23)を開設した後、同図(ｃ)の如くグリーンシ
ート(25)の表面に導電材料を印刷して、回路素子パター
ンやバイアホールとなる導体層(30)を形成する。The ceramic multilayer wiring board (1) is manufactured by the process shown in FIG. First, as shown in Fig. 4 (a), a green sheet (2
5) is produced. Next, as shown in Fig. 2 (b), the green sheet (2
After opening the through hole (22) for the cavity and the through hole (23) for the via hole at the required locations of 5), the conductive material is printed on the surface of the green sheet (25) as shown in FIG. A conductor layer (30) which will be an element pattern and a via hole is formed.
【００１４】この様にして得られたグリーンシート(25)
を複数層に積層して、図４(ｄ)に示すグリーンシート積
層体(24)を構成する。そして、該グリーンシート積層体
(24)を平板状の治具(６)上に設置すると共に、該グリー
ンシート積層体(24)の表面に、ゴム硬度が３０度以下、
厚さが０.６ｍｍのシリコンゴム製の弾性シート(７)を
被せ、これらを樹脂製袋に収納して真空パック化した状
態で、適当な温度の液体に浸漬し、静水圧をかける。こ
れによって、グリーンシート積層体(24)は熱プレスされ
て、一体化される。その後、図４(ｅ)に示す如く一体化
されたグリーンシート積層体(24)をキャビティ(21)毎に
分断して、複数の積層体チップ(26)を得る。そして、同
図(ｆ)に示す如く各積層体チップ(26)に焼成を施して、
セラミックス積層体(20)を得る。The green sheet (25) thus obtained
Are laminated in a plurality of layers to form a green sheet laminate (24) shown in FIG. And the green sheet laminate
(24) is placed on a flat jig (6), and the surface of the green sheet laminate (24) has a rubber hardness of 30 degrees or less.
An elastic sheet (7) made of silicon rubber having a thickness of 0.6 mm is covered, and these are housed in a resin bag and vacuum packed, and then immersed in a liquid at an appropriate temperature and hydrostatic pressure is applied. As a result, the green sheet laminate (24) is hot pressed and integrated. Thereafter, as shown in FIG. 4 (e), the integrated green sheet laminate (24) is divided into cavities (21) to obtain a plurality of laminate chips (26). Then, as shown in FIG. 6F, each laminated body chip (26) is fired,
A ceramic laminate (20) is obtained.
【００１５】この様にして得られたセラミックス積層体
(20)のキャビティ(21)の底面に、図５の如く電子部品
(４)を実装した後、ワイヤボンディングを施し、蓋体
(５)を設置することによって、本発明のセラミックス多
層配線基板(１)が完成する。Ceramic laminate obtained in this way
On the bottom of the cavity (21) of (20), as shown in FIG.
After mounting (4), wire bonding is applied to the lid
By installing (5), the ceramic multilayer wiring board (1) of the present invention is completed.
【００１６】上記セラミックス多層配線基板(１)の製造
方法によれば、図４(ｄ)に示すグリーンシート積層体(2
4)の熱プレス工程において、図１(ａ)に示す如く治具
(６)上にグリーンシート積層体(24)を設置すると共に、
該グリーンシート積層体(24)の表面にキャビティ(21)を
覆って弾性シート(７)を設置した後、同図(ｂ)の如く弾
性シート(７)を介してグリーンシート積層体(24)に静水
圧をかけた場合、弾性シート(７)は、その弾性変形によ
ってグリーンシート積層体(24)のキャビティ底面(21a)
(21b)に沿って屈曲し、段差を有するキャビティ底面(21
a)(21b)に十分に密着して、グリーンシート積層体(24)
の表面を均一に加圧する。この結果、図１(ｃ)に示す様
にグリーンシート積層体(24)には、高い平面度のキャビ
ティ底面(21a′)(21b′)が得られる。According to the method for manufacturing the above-mentioned ceramic multilayer wiring board (1), the green sheet laminated body (2
In the hot pressing process of 4), the jig as shown in Fig. 1 (a)
Install the green sheet laminate (24) on (6),
After the elastic sheet (7) is installed on the surface of the green sheet laminated body (24) so as to cover the cavity (21), the green sheet laminated body (24) is inserted through the elastic sheet (7) as shown in FIG. When hydrostatic pressure is applied to the elastic sheet (7), the elastic sheet (7) is elastically deformed to cause the bottom surface (21a) of the cavity of the green sheet laminate (24).
The bottom of the cavity (21
Adhere sufficiently to a) (21b), green sheet laminate (24)
The surface of is uniformly pressed. As a result, as shown in FIG. 1 (c), the cavity bottom surfaces (21a ') (21b') having high flatness are obtained in the green sheet laminate (24).
【００１７】図３(ａ)(ｂ)は、弾性シート(７)のゴム硬
度を２０度〜８０度の範囲で変化させた場合のキャビテ
ィ底面の平坦性の変化を表わしている。ここで、キャビ
ティ底面の平坦性とは、図２(ｂ)に示す如く電子部品が
実装されるべきキャビティ底面(21a)の最大高低差Ａ
と、ワイヤボンディングが施されるべき２段目のキャビ
ティ底面(21b)の最大高低差Ｂを表わしている。図３
(ａ)(ｂ)に示す如く、何れのキャビティ底面において
も、ゴム硬度が３０度よりも大きい場合は、ゴム硬度が
高くなるにつれて平坦性が悪化しているが、ゴム硬度３
０度以下においては、ゴム硬度に拘わらず略一定の平坦
性が得られている。又、ゴム硬度３０度以下における平
坦性は何れも２０μｍ以下となっており、電子部品の実
装やワイヤボンディングに支障のない平坦性が得られて
いる。FIGS. 3A and 3B show changes in the flatness of the bottom surface of the cavity when the rubber hardness of the elastic sheet 7 is changed in the range of 20 to 80 degrees. Here, the flatness of the bottom surface of the cavity means the maximum height difference A of the bottom surface (21a) of the cavity on which electronic parts are to be mounted as shown in FIG. 2 (b).
And the maximum height difference B of the bottom surface (21b) of the second stage to be wire-bonded. Figure 3
As shown in (a) and (b), when the rubber hardness is larger than 30 degrees on both bottom surfaces of the cavities, the flatness deteriorates as the rubber hardness increases.
At 0 degrees or less, substantially constant flatness is obtained regardless of rubber hardness. In addition, the flatness at a rubber hardness of 30 degrees or less is 20 μm or less, and flatness that does not hinder mounting of electronic components and wire bonding is obtained.
【００１８】この結果から、セラミックス多層配線基板
の製造方法にゴム硬度が３０度以下の弾性シート(７)を
採用する優位性が実証される。尚、ゴム硬度が２０度以
下の弾性シート(７)においては、製造上並びに耐久性上
の問題があるため、ゴム硬度としては２０度〜３０度が
好ましい。From these results, the superiority of adopting the elastic sheet (7) having a rubber hardness of 30 degrees or less is demonstrated in the method for manufacturing a ceramic multilayer wiring board. Since the elastic sheet (7) having a rubber hardness of 20 degrees or less has problems in production and durability, the rubber hardness is preferably 20 degrees to 30 degrees.
【００１９】尚、本発明の各部構成は上記実施の形態に
限らず、特許請求の範囲に記載の技術的範囲内で種々の
変形が可能である。例えば、図４に示すセラミックス多
層配線基板の製造工程においては、同図(ｄ)に示す熱プ
レス工程の後、同図(ｆ)に示す焼成工程を施し、その後
に同図(ｅ)に示す分断工程を施して、セラミックス積層
体(20)を得ることも可能である。The constitution of each part of the present invention is not limited to the above-mentioned embodiment, and various modifications can be made within the technical scope described in the claims. For example, in the manufacturing process of the ceramic multi-layer wiring board shown in FIG. 4, after the hot pressing step shown in FIG. 4D, the firing step shown in FIG. It is possible to obtain a ceramics laminate (20) by performing a dividing step.
【図１】本発明に係るセラミックス多層配線基板の製造
工程において、熱プレス工程の作用を表わす一連の拡大
断面図である。FIG. 1 is a series of enlarged cross-sectional views showing an operation of a hot pressing step in a manufacturing process of a ceramics multilayer wiring board according to the present invention.
【図２】従来のセラミックス多層配線基板の製造工程に
おいて、熱プレス工程の作用を表わす一連の拡大断面図
である。FIG. 2 is a series of enlarged cross-sectional views showing the operation of the hot pressing step in the conventional manufacturing process of a ceramic multilayer wiring board.
【図３】弾性シートのゴム硬度を変えた場合におけるキ
ャビティ底面の平坦性の変化を表わすグラフである。FIG. 3 is a graph showing changes in flatness of the bottom surface of the cavity when the rubber hardness of the elastic sheet is changed.
【図４】セラミックス多層配線基板の製造工程を表わす
一連の断面図である。FIG. 4 is a series of cross-sectional views showing a manufacturing process of a ceramic multilayer wiring board.
【図５】セラミックス多層配線基板の積層構造を表わす
拡大断面図である。FIG. 5 is an enlarged cross-sectional view showing a laminated structure of a ceramic multilayer wiring board.
(１) セラミックス多層配線基板 (２) セラミックス層 (20) セラミックス積層体 (21) キャビティ (21a) キャビティ底面 (21b) キャビティ底面 (24) グリーンシート積層体 (25) グリーンシート (３) 回路素子パターン (４) 電子部品 (６) 治具 (７) 弾性シート (1) Ceramic multilayer wiring board (2) Ceramic layer (20) Ceramic laminate (21) Cavity (21a) Cavity bottom (21b) Bottom of cavity (24) Green sheet laminate (25) Green sheet (3) Circuit element pattern (4) Electronic components (6) Jig (7) Elastic sheet
───────────────────────────────────────────────────── フロントページの続き (72)発明者 小倉 隆 大阪府大東市三洋町１番１号 三洋電子部 品株式会社内 (72)発明者 本郷 政紀 大阪府大東市三洋町１番１号 三洋電子部 品株式会社内 (72)発明者 錦織 啓之 大阪府大東市三洋町１番１号 三洋電子部 品株式会社内 Ｆターム(参考） 5E346 AA02 AA12 AA15 AA22 CC17 EE24 EE25 EE27 EE28 FF45 GG05 GG08 GG09 HH11 HH31 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Takashi Ogura 1-1 Sanyo-cho, Daito-shi, Osaka Sanyo Electronics Department Product Co., Ltd. (72) Inventor Masaki Hongo 1-1 Sanyo-cho, Daito-shi, Osaka Sanyo Electronics Department Product Co., Ltd. (72) Inventor Hiroyuki Nishikori 1-1 Sanyo-cho, Daito-shi, Osaka Sanyo Electronics Department Product Co., Ltd. F term (reference) 5E346 AA02 AA12 AA15 AA22 CC17 EE24 EE25 EE27 EE28 FF45 GG05 GG08 GG09 HH11 HH31
Claims (2)
(３)が形成されたセラミックス層(２)を積層してセラミ
ックス積層体(20)が構成され、該セラミックス積層体(2
0)の表面にはキャビティ(21)が凹設され、該キャビティ
(21)の底面に１或いは複数の電子部品(４)が実装されて
いるセラミックス多層配線基板の製造方法において、 セラミックス層(２)となるグリーンシート(25)を複数枚
作製し、この中の必要枚数のグリーンシート(25)にキャ
ビティ用貫通孔(22)を開設すると共に、回路素子パター
ン(３)となる導体層(30)を形成する第１工程と、 第１工程を経て得られる複数枚のグリーンシート(25)を
積層して、キャビティ(21)を有するグリーンシート積層
体(24)を作製する第２工程と、 グリーンシート積層体(24)の表面に、キャビティ(21)を
覆ってゴム硬度が３０度以下の弾性シート(７)を被せ、
該弾性シート(７)を介してグリーンシート積層体(24)に
静水圧による熱プレスを施す第３工程と、 第３工程を経て得られるグリーンシート積層体(24)に、
焼成の後に分断を施し、或いは分断の後に焼成を施すこ
とによって、キャビティ(21)を有するセラミックス積層
体(20)を得る第４工程と、 セラミックス積層体(20)のキャビティ(21)に電子部品
(４)を実装する第５工程とを有していることを特徴とす
るセラミックス多層配線基板の製造方法。1. One or a plurality of circuit element patterns on the surface
The ceramic layer (2) on which (3) is formed is laminated to form a ceramic layered body (20).
A cavity (21) is provided on the surface of (0)
In the method for manufacturing a ceramic multilayer wiring board in which one or a plurality of electronic components (4) are mounted on the bottom surface of (21), a plurality of green sheets (25) to be the ceramic layers (2) are produced, and A first step of forming a through hole (22) for a cavity in a required number of green sheets (25) and forming a conductor layer (30) to be a circuit element pattern (3), and a plurality of steps obtained through the first step The second step of producing a green sheet laminate (24) having a cavity (21) by laminating a plurality of green sheets (25), and covering the cavity (21) on the surface of the green sheet laminate (24). Cover the elastic sheet (7) with a rubber hardness of 30 degrees or less,
A third step of hydrostatically pressing the green sheet laminate (24) through the elastic sheet (7), and a green sheet laminate (24) obtained through the third step,
A fourth step of obtaining a ceramics laminated body (20) having a cavity (21) by dividing after firing or by firing after dividing, and electronic parts in the cavity (21) of the ceramics laminate (20).
And a fifth step of mounting (4). A method for manufacturing a ceramic multilayer wiring board, comprising:
て、厚さが約０.６ｍｍである請求項１に記載のセラミ
ックス多層配線基板の製造方法。2. The method for manufacturing a ceramic multilayer wiring board according to claim 1, wherein the elastic sheet (7) is made of silicon rubber and has a thickness of about 0.6 mm.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002092344A JP2003289119A (en) | 2002-03-28 | 2002-03-28 | Manufacturing method of ceramic multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002092344A JP2003289119A (en) | 2002-03-28 | 2002-03-28 | Manufacturing method of ceramic multilayer wiring board |
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| Publication Number | Publication Date |
|---|---|
| JP2003289119A true JP2003289119A (en) | 2003-10-10 |
Family
ID=29237199
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7244331B1 (en) * | 2004-10-07 | 2007-07-17 | Northrop Grumman Corporation | Method of producing an LTCC substrate with cavities having improved bondability |
| JP2009117565A (en) * | 2007-11-06 | 2009-05-28 | Maruwa Co Ltd | CERAMIC MOLDED BODY FOR INSTALLING ELECTRONIC COMPONENTS, ITS MANUFACTURING METHOD, AND ELASTIC COVER SHEET USED FOR THE METHOD |
| JP2009182184A (en) * | 2008-01-31 | 2009-08-13 | Seiko Epson Corp | Manufacturing method of ceramic multilayer substrate |
| KR100986973B1 (en) | 2008-08-25 | 2010-10-11 | 주식회사 엠티 | Grip belt structure for transporting chip ceramic electronic parts with enhanced bearing capacity |
| JP2011228521A (en) * | 2010-04-21 | 2011-11-10 | Fujitsu Ltd | Manufacturing method of semiconductor device |
| WO2012108533A1 (en) * | 2011-02-10 | 2012-08-16 | 旭硝子株式会社 | Method for manufacturing substrate for light emitting element and substrate for light emitting element |
-
2002
- 2002-03-28 JP JP2002092344A patent/JP2003289119A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7244331B1 (en) * | 2004-10-07 | 2007-07-17 | Northrop Grumman Corporation | Method of producing an LTCC substrate with cavities having improved bondability |
| JP2009117565A (en) * | 2007-11-06 | 2009-05-28 | Maruwa Co Ltd | CERAMIC MOLDED BODY FOR INSTALLING ELECTRONIC COMPONENTS, ITS MANUFACTURING METHOD, AND ELASTIC COVER SHEET USED FOR THE METHOD |
| JP2009182184A (en) * | 2008-01-31 | 2009-08-13 | Seiko Epson Corp | Manufacturing method of ceramic multilayer substrate |
| KR100986973B1 (en) | 2008-08-25 | 2010-10-11 | 주식회사 엠티 | Grip belt structure for transporting chip ceramic electronic parts with enhanced bearing capacity |
| JP2011228521A (en) * | 2010-04-21 | 2011-11-10 | Fujitsu Ltd | Manufacturing method of semiconductor device |
| WO2012108533A1 (en) * | 2011-02-10 | 2012-08-16 | 旭硝子株式会社 | Method for manufacturing substrate for light emitting element and substrate for light emitting element |
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