JP2003115750A - Semiconductor device - Google Patents

Abstract

(57) [Problem] To provide a semiconductor device which is versatile, can minimize an increase in circuit scale, and can adjust delay characteristics flexibly and efficiently. A first ring oscillator 131 that can oscillate in response to a first enable signal S121 and a second ring that can oscillate in response to a second enable signal S122 and have an oscillation cycle different from that of the first ring oscillator 131. A delay oscillator 13 that includes a ring oscillator 132 and accumulates the oscillation cycle difference to generate a delay characteristic equivalent or similar to the critical path; and a delay amount generated by the accumulation in the delay characteristic synthesizer 13 And a detection signal S1 from the delay detection circuit 14.
4, a control circuit 15 for outputting a control signal S152 indicating a power supply voltage _VDD to be supplied to the delay characteristic synthesizing circuit 13 and the target circuit 11 to the power supply voltage supply circuit 16 is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a mechanism for grasping a critical path delay characteristic of a target circuit and adaptively controlling a power supply voltage supplied to an LSI to reduce power consumption. It is a thing.

[0002]

2. Description of the Related Art In recent years, in semiconductor circuits, a method of lowering a power supply voltage has been generally adopted in order to reduce power consumption. This is because the AC component of the power consumption of the semiconductor circuit (LSI) is proportional to the square of the power supply voltage, and the reduction of the power supply voltage is most effective for reducing the power consumption of the LSI. From such a viewpoint, in recent years, a method has been reported in which the power supply voltage is dynamically controlled with respect to the operating frequency of the LSI, process variations, and the like, and the minimum voltage is always supplied.

FIG. 16 is a diagram showing an example of the configuration of a replica circuit for monitoring the delay characteristic of a critical path which has been used conventionally. In the replica circuit 1, the gate delay elements 2-1 to 2-n are connected in multiple stages (cascade), the input pulse PI is propagated, and the number of stages of the connected delay elements 2 set by the delay setting signal DSET is set by the selector 3. A desired delay characteristic is obtained by changing the delay characteristic. By monitoring the operation of the replica circuit, the minimum operable voltage is supplied to the LSI.

[0004]

However, in the conventional replica circuit described above, since a plurality of gate elements are connected in order to obtain a characteristic equivalent to that of a critical path, it is possible to obtain a large delay. Then, there is a disadvantage that the circuit scale becomes large.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device which has versatility, minimizes an increase in circuit scale, and can flexibly and efficiently adjust delay characteristics. To provide.

[0006]

In order to achieve the above object, a first aspect of the present invention is a semiconductor device having a function of grasping the delay characteristic of a critical path of a target circuit and capable of oscillating. It includes a first delay unit and a second delay unit having an oscillation cycle different from that of the first delay unit, and is critical by accumulating an oscillation cycle difference between the first delay unit and the second delay unit. It has a delay characteristic synthesizing circuit that generates a delay characteristic equivalent to or similar to the path.

A second aspect of the present invention is a semiconductor device having a function of grasping the delay characteristic of a critical path of a target circuit, which is capable of oscillating a first delay unit and the first delay unit. And a second delay unit having a different oscillation cycle, and a delay characteristic for generating a delay characteristic equivalent to or similar to a critical path by accumulating an oscillation cycle difference between the first delay unit and the second delay unit. A combination circuit, a power supply voltage supply circuit for supplying a power supply voltage to the target circuit and the delay characteristic combination circuit, a delay detection circuit for detecting a delay amount generated by accumulation in the delay characteristic combination circuit, and a delay detection circuit A control circuit for instructing the power supply voltage supply circuit based on the detection signal of the power supply voltage value to be supplied to the delay characteristic combining circuit and the target circuit. With the door.

In the first or second aspect, the first and second delay units include a ring oscillator.

In the first or second aspect, the delay characteristic synthesizing circuit counts the oscillation output of the first delay unit and the oscillation output of the second delay unit. 2 counters, and a target delay amount is obtained by accumulating the delay difference generated by the first and second ring oscillators a desired number of times based on the outputs of the first and second counters. .

In the first or second aspect, in the delay characteristic synthesizing circuit, the number of times of accumulation can be arbitrarily set from outside, and the set value is compared with the outputs of the first and second counters. And a comparison circuit for detecting that the target number of accumulations has been reached.

According to the first or second aspect, there is provided a pulse generation circuit which generates two reference pulse signals having different phases indicating a target delay amount according to a clock frequency and which activates the delay characteristic synthesizing circuit. Have.

In the first or second aspect, the oscillation cycle difference between the first ring oscillator and the second ring oscillator is generated by a delay element having a desired delay characteristic.

In the first or second aspect, the delay generated by the first delay element included in the first ring oscillator and the delay generated by the second delay element included in the second ring oscillator. The first and second delay elements are configured such that the difference between the two becomes a delay having a desired delay characteristic.

Further, in a second aspect, the control circuit is
After the delay detecting circuit finishes detecting the delay amount output from the delay characteristic synthesizing circuit, the operation of the delay characteristic synthesizing circuit is stopped.

A third aspect of the present invention is a semiconductor device having a function of grasping the delay characteristic of a critical path of a target circuit, wherein the first delay unit capable of oscillating and the first delay unit. And a second delay unit having a different oscillation cycle, and a delay characteristic for generating a delay characteristic equivalent to or similar to a critical path by accumulating an oscillation cycle difference between the first delay unit and the second delay unit. A plurality of combining circuits, each of the delay characteristic combining circuits includes a first delay unit and a second delay unit that includes a delay element for generating a delay having a different delay characteristic;
The respective delay characteristic synthesizing circuits are connected in cascade to synthesize a plurality of delays having different delay characteristics at a desired ratio to obtain a delay characteristic equivalent to or similar to a critical path.

A fourth aspect of the present invention is a semiconductor device having a function for grasping the delay characteristic of a critical path of a target circuit, wherein the first delay unit capable of oscillating and the first delay unit. And a second delay unit having a different oscillation cycle, and a delay characteristic for generating a delay characteristic equivalent to or similar to a critical path by accumulating an oscillation cycle difference between the first delay unit and the second delay unit. Each of the delay characteristic combining circuits includes a delay element for generating a delay having a different delay characteristic;
The delay characteristic synthesizing circuits are cascaded to synthesize delays having a plurality of different delay characteristics at a desired ratio to obtain a delay characteristic equivalent to or similar to a critical path.
A power supply voltage supply circuit that supplies a power supply voltage to the target circuit and the delay characteristic synthesis circuit, a delay detection circuit that detects the delay amount generated by accumulation in the delay characteristic synthesis circuit at the final stage, and a detection of the delay detection circuit. And a control circuit for instructing the power supply voltage supply circuit based on the signal to instruct the power supply voltage value to be supplied to the delay characteristic combining circuit and the target circuit.

In the third or fourth aspect, the first and second delay units include a ring oscillator.

In the third or fourth aspect, each of the delay characteristic synthesizing circuits counts the oscillation output of the first delay unit and the oscillation output of the second delay unit. A second counter and based on the outputs of the first and second counters, the first counter
The target delay amount is obtained by accumulating the delay difference generated by the second ring oscillator a desired number of times.

In the third or fourth aspect, in each of the delay characteristic synthesizing circuits, the number of accumulations can be arbitrarily set from the outside, and the set value is compared with the first and second counter outputs. Then, it has a comparison circuit for detecting that the target number of times of accumulation is reached.

According to the third or fourth aspect, pulse generation for generating a reference signal for activating the delay characteristic synthesizing circuit of the first stage, which is two pulse signals having different phases indicating the target delay amount according to the clock frequency. It has a circuit.

In a third or a fourth aspect, in the plurality of cascaded delay characteristic synthesizing circuits, the output signal of the delay characteristic synthesizing circuit of the preceding stage becomes a signal for activating the delay characteristic synthesizing circuit of the next stage. ing.

According to a fourth aspect, the control circuit is
After the delay detection circuit finishes detecting the delay amount output from the delay characteristic combining circuit at the final stage, the operation of all the delay characteristic combining circuits connected in series is stopped.

A fifth aspect of the present invention is a semiconductor device having a function for grasping the delay characteristic of a critical path of a target circuit, which is capable of oscillating a first delay unit and the first delay unit. And a second delay unit having a different oscillation cycle, and a delay characteristic for generating a delay characteristic equivalent to or similar to a critical path by accumulating an oscillation cycle difference between the first delay unit and the second delay unit. The delay characteristic combining circuit includes a plurality of delay elements for generating delays having different delay characteristics, and the delay characteristic combining circuit includes different delay elements. A plurality of delay components are accumulated at the same time, and the delay elements that have reached the target number of accumulations are sequentially separated by the circuit to selectively separate the plurality of delay components to a desired ratio. In combined to obtain the critical path equivalent or similar delay characteristics.

A sixth aspect of the present invention is a semiconductor device having a function of grasping delay characteristics of a critical path of a target circuit, wherein the first delay unit capable of oscillating and the first delay unit. And a second delay unit having a different oscillation cycle, and a delay characteristic for generating a delay characteristic equivalent to or similar to a critical path by accumulating an oscillation cycle difference between the first delay unit and the second delay unit. The delay characteristic combining circuit includes a plurality of delay elements for generating delays having different delay characteristics, and the delay characteristic combining circuit includes different delay elements. A plurality of delay components are accumulated at the same time, and the delay elements that have reached the target number of accumulations are sequentially separated by the circuit to selectively separate the plurality of delay components to a desired ratio. Generated by accumulating in the power supply voltage supply circuit that supplies the power supply voltage to the target circuit and the delay characteristic synthesis circuit, and the delay characteristic synthesis circuit. It has a delay detection circuit for detecting the delay amount, and a control circuit for instructing the power supply voltage supply circuit based on the detection signal of the delay detection circuit to instruct the delay characteristic combining circuit and the power supply voltage value to be supplied to the target circuit.

In the fifth or sixth aspect, the delay characteristic synthesizing circuit counts the oscillating output of the first delay unit and the oscillating output of the second delay unit. 2 counters, and a target delay amount is obtained by accumulating a desired number of delay differences generated by the first and second ring oscillators based on the outputs of the first and second counters. .

In the fifth or sixth aspect, in the delay characteristic synthesizing circuit, the number of times of accumulation can be arbitrarily set from the outside, and the set value is compared with the outputs of the first and second counters. And a comparison circuit for detecting that the target number of accumulations has been reached.

According to a fifth or sixth aspect, there is provided a pulse generation circuit for generating a reference signal for activating the delay characteristic synthesizing circuit, which is two pulse signals having different phases indicating a target delay amount according to a clock frequency. Have.

Further, in a sixth aspect, the control circuit is
After the delay detection circuit finishes detecting the delay amount output from the delay characteristic synthesizing circuit, the operation of the delay characteristic synthesizing circuit is stopped.

According to the present invention, a start signal for starting the operation is sent from the control circuit to the pulse generating circuit. The pulse generation circuit receives the start signal, generates a reference signal which is two pulse signals having a delay difference of one cycle of the clock signal, and outputs the reference signal to the delay characteristic combining circuit. In the delay characteristic synthesizing circuit, the first and second ring oscillators included in the delay unit start oscillating in response to the reference signal, and the first and second counter counting operations start. Further, the comparison circuit starts the comparison between the output signals of the first and second counters and the cumulative number setting value. At this time, for example, the oscillation cycle τ1 of the first ring oscillator is
It oscillates in a cycle longer than the oscillation cycle τ2 of the second ring oscillator by the delay difference (τ1-τ2) generated by the delay element. As a result, the oscillation cycle difference (τ1−τ2) between the first and second ring oscillators is accumulated every cycle. Then, when the output values of the first and second counters match the cumulative number setting value, the comparison circuit outputs two signals to the delay detection circuit.

In the delay detection circuit which receives the two output signals of the comparison circuit, for example, the rising edges of both signals are compared with each other, and the delay difference between both edges is output to the control circuit as delay information. The control circuit generates a control signal for instructing the power supply voltage supply circuit to increase, decrease, or maintain the power supply voltage based on the obtained delay information, and outputs the control signal to the power supply voltage supply circuit. As a result, the power supply voltage V supplied from the power supply voltage supply circuit to the target circuit and the delay characteristic combining circuit changes. Further, in the control circuit, when the delay information from the delay detection circuit is acquired,
Output of the start signal is stopped. As a result, in the pulse generation circuit, the reference signal is set to inactive,
The operation of the delay characteristic combining circuit is stopped. The above processing is repeatedly executed, and the power supply voltage is controlled so as to finally reach a desired value.

Further, in the delay characteristic synthesizing circuit, the number of accumulations can be arbitrarily set from the outside, and the comparator circuit has a function of comparing the set value with the counter output and detecting that the target number of accumulations has been reached. Since it has, it becomes possible to adjust the generated delay characteristic after the LSI is manufactured.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION First Embodiment FIG. 1 is a circuit diagram showing a first embodiment of a semiconductor device according to the present invention.

FIG. 1 shows a first embodiment of the present invention. The semiconductor device 10 includes a target circuit 11, a pulse generation circuit 12, a delay characteristic synthesis circuit 13, a delay detection circuit 14, a control circuit 15, which has a transmission path and whose delay characteristics are monitored.
And a power supply voltage supply circuit 16.

Here, the pulse generating circuit 12, the delay characteristic synthesizing circuit 13, the delay detecting circuit 14, the control circuit 15, and the power supply voltage supply circuit 16 may be integrated on the same chip as the target circuit 11, or the power supply may be integrated. The voltage supply circuit 16 may be externally attached.

The pulse generation circuit 12 receives the start signal S151 from the control circuit 15 and receives the clock signal CLK.
First reference signal (enable signal) S121 and second reference signal (enable signal), which are two pulses having different phases indicating the target delay amount according to the clock frequency of
S122 is generated and output to the delay characteristic synthesizing circuit 13.
These two pulses having different phases are control signals for activating the delay characteristic synthesizing circuit 13.

The delay characteristic synthesizing circuit 13 is driven by the output signal S131 of the first ring oscillator 131, the second ring oscillator 132, which is the first delay unit, and the first ring oscillator 131, which is the second delay unit. First counter 133, a second counter 134 driven by the output signal S132 of the second ring oscillator 132, a cumulative count setting value ACV set by a register (not shown) or an external pin, and the first counter 13
3 output signal S133 and outputs the comparison result to the delay detection circuit 14 as the first coincidence detection signal S135, similarly the accumulation count set value set by the register or the external pin. ACV and second counter 1
It has a second comparison circuit 136 that compares the output signal S134 of the S.34 and the comparison result as a second coincidence detection signal S136 to the delay detection circuit 14.

As shown in FIG. 1, the first ring oscillator 131 has a two-input NAND gate NA131 whose one input terminal is connected to the supply line of the first enable signal S121 by the pulse generation circuit 12, and a NAND gate. Delay elements D131-1, D131-2, D131 connected in series between the output terminal of NA131 and the other input terminal
-3, D131-4, D131-5, D131-6 and D131-7 are configured to oscillate, and output the first oscillation signal S131 to the counter 133.

As shown in FIG. 1, the second ring oscillator 132 has a two-input NAND gate NA132 whose one input terminal is connected to the supply line of the second enable signal S122 by the pulse generation circuit 12, and a NAND gate. Delay elements D132-1, D132-2, and D132 connected in series between the output terminal of NA132 and the other input terminal
-3, D133-4, D132-5, D132-6 and D132-7 are configured to oscillate and output a second oscillation signal S132 to the counter 134.

NAND gate NA131 as a delay element included in first ring oscillator 131, NAND gate NA1 as a delay element included in delay elements D131-1 to D131-7 and second ring oscillator 132.
32, the delay element D13 included in the first ring oscillator 131 among the delay elements D132-1 to D132-7
1-5 is configured to have a delay larger by Δτ than the delay element D132-5 included in the second ring oscillator 132. Delay elements D131-5 and D1
All the delay elements other than 32-5 are configured to have the same delay characteristic. For example, NAND gate NA1
31, NAND gate NA132, delay element D131-
1 and delay element D132-1, delay element D131-2 and delay element D132-2, delay element D131-3 and delay element D132-3, delay element D131-4 and delay element D13
2-4, delay element D131-6 and delay element D132-
6. The delay element D131-7 and the delay element D132-7 are configured to have the same delay characteristic.

As a result, the first ring oscillator 13
1 oscillates in a cycle longer than the second ring oscillator 132 by 2Δτ, and the oscillation cycle difference 2Δτ between both ring oscillators is accumulated every cycle. Then, in the delay characteristic synthesizing circuit 13, a desired delay can be generated by counting the number of times of accumulation with a counter and performing accumulation until the target number of times of accumulation is reached.

FIGS. 2 and 3 show first and second configuration examples of the delay elements D131-5 and D132-5 for generating a delay difference in the oscillation cycle of the first and second ring oscillators 131 and 132. FIG.

In the first configuration example, as shown in FIG. 2A, the delay element D131-5 included in the first ring oscillator 131 includes the buffers 131-5-1 and 131-5.
-2 stage configuration, the delay element D132-5 included in the second ring oscillator 132 is the buffer 132-5-1.
It has a one-stage configuration. In this first configuration example, the first
Since the oscillation cycle of the ring oscillator 131 is longer than that of the second ring oscillator 132 by the delay of the buffer 131-5-2, it is possible to generate the gate delay component.

In the second configuration example, as shown in FIGS. 3A and 3B, the delay element D131-5 is connected to the wiring 13.
1-5-3, and the delay element D132-5 is formed by the wiring 132-5-3. Wiring 131-
The total wiring length of 5-3 and 132-5-3 is set to the same length (L1 + L2), and drivers 131-4 and 132-4 and a receiver 131- that drive the wiring.
6, 132-6 also have the same size. And the wiring 13
3-5A, a signal is output from the end of the wiring, as shown in FIG.
As shown in (B), a signal is output from a position having a length L1 from the left end in the figure. Therefore, the oscillation cycle of the first ring oscillator 131 is longer than the oscillation cycle of the second ring oscillator 132 by the delay of the wiring length L2, and the wiring delay component can be generated.

Although two types of delay elements are shown as an example here, the implementation method is not limited to this, and the necessary conditions are delay elements D131-5 and D132-.
5 is configured so that a delay difference having a desired delay characteristic is generated, and the delay difference is accumulated to generate a delay having a desired delay characteristic.

The delay detecting circuit 14 is the delay characteristic synthesizing circuit 1
The third output signal S135 of the first comparison circuit 135 and the output signal S136 of the second comparison circuit 136 are received to detect the delay amount generated by the accumulation and output to the control circuit 15 as a detection signal S14.

The control circuit 15 controls the power supply voltage supply circuit 16 based on the detection signal S14 of the delay detection circuit 14 to instruct the power supply voltage V _DD to be supplied to the delay characteristic synthesizing circuit 13 and the target circuit 11. Is output.

The power supply voltage supply circuit 16 adjusts the power supply voltage value to a value according to the control signal S15 from the control circuit 15 and supplies it to the delay characteristic synthesizing circuit 14 and the target circuit 11.

Next, the operation according to the first embodiment will be described with reference to FIG.
Will be described in association with the timing chart of FIG.

First, as shown in FIG. 4B, the start signal S151 for starting the operation is sent from the control circuit 15 to the pulse generation circuit 12. Pulse generation circuit 12
Then, in response to the start signal S151, as shown in FIG.
As shown in (C) and (G), the clock signal CLK
The first enable signal S121 and the second enable signal S122 having a delay difference of one cycle are generated and output to the delay characteristic synthesizing circuit 13.

In the delay characteristic synthesizing circuit 13, the first enable signal S121 is applied to the first ring oscillator 1
31, the counter 133, and the comparison circuit 135. On the other hand, the second enable signal S122 is input to the second ring oscillator 132, the counter 134, and the comparison circuit 136. Thereby, the first and second
The ring oscillators 131 and 132 start to oscillate, and the counters 133 and 134 are released from reset, and the counting operation is started. In addition, the comparison circuit 135,
At 136, the output signals S13 of the counters 133, 134, as shown in FIGS. 4 (E) and (I), respectively.
3, S134 is started to be compared with the cumulative number setting value ACV.

At this time, the first ring oscillator 131
Oscillation cycle τ1 of the second ring oscillator 132
Than the oscillation cycle τ2 of the delay elements 131-5 and 13-5.
It oscillates in a cycle longer by the delay difference (τ1-τ2) caused by 2-5. As a result, the oscillation cycle difference (τ1) between the first and second ring oscillators 131 and 132 is increased.
−τ2) is accumulated every cycle. And FIG.
As shown in (E), (I), (F), and (J),
When the output values of the first and second counters 133 and 134 match the cumulative number set value ACV, the first and second counters
The first and second coincidence detection signals S135 and S136 are output from the comparison circuits 135 and 136 to the delay detection circuit 14.

Here, as shown in FIGS. 4C and 4F, the time τd from the rising edge of the first enable signal S121 to the rising edge of the first match detection signal S135 and FIG. ) And (J), the difference (τd−τc) in the time τc from the rising edge of the enable signal S132 to the rising edge of the second coincidence detection signal S136 is the obtained delay amount, and between both rising edges. Is the target delay amount (clock 1
Delay difference (1cycle- (τd-τ
c)).

First and second comparison circuits 135 and 136
The first and second coincidence detection signals S135, S13
In the delay detection circuit 14 which has received 6, the rising edge of the first match detection signal S135 and the second match detection signal S1
The rising edge of 36 is compared, and the delay difference between both edges is output to the control circuit 15 as delay information S14. In the control circuit 15, the control signal S1 for instructing the power supply voltage supply circuit 16 to increase, decrease or maintain the power supply voltage based on the obtained delay information S14.
52 is generated and output to the power supply voltage supply circuit 16.
As a result, the power supply voltage V _DD supplied from the power supply voltage supply circuit 16 to the target circuit 11 and the delay characteristic synthesis circuit 13 changes. Further, in the control circuit 15, when the delay information from the delay detection circuit 14 is acquired, the start signal S151 is switched to the low level as shown in FIG. 4 (B). As a result, in the pulse generating circuit 12, the first and second enable signals S121 and S122 are switched to the low level, and the operation of the delay characteristic synthesizing circuit 13 is stopped.

The above processing is repeatedly executed, and the power supply voltage is controlled so that τd-τc = 1 cycle is finally obtained. First and second ring oscillators 131, 1
Since the oscillation cycle of 32 changes depending on the controlled power supply voltage, after the delay characteristic synthesizing circuit 13 is activated,
The time until the delay amount is detected by the delay detection circuit 14 also changes depending on the power supply voltage.

In this method, since the control circuit 15 carries out the timing for activating / stopping the delay characteristic synthesizing circuit 13,
Immediately after the delay information from the delay detection circuit 14 is acquired, the delay characteristic synthesizing circuit 13 is stopped, that is, the delay generation / detection is performed once in the minimum time according to the power supply voltage, or a fixed fixed operation is performed. It is possible to flexibly perform control such as performing delay generation / detection once in a cycle. This is very effective in controlling the latency of the delay generation and ensuring the stability of the power supply voltage control loop.

As described above, according to the first embodiment, the control circuit 15 receives the start signal S151 and the first phase having a different phase indicating the target delay amount according to the clock frequency of the clock signal CLK. Enable signal S1
21 and the pulse generation circuit 12 that generates the second enable signal S122, the first ring oscillator 131 that can oscillate by receiving the first enable signal S121, and the first ring oscillator 131 that can oscillate by receiving the second enable signal S122. A delay characteristic synthesizing circuit 13 that includes a first ring oscillator 131 and a second ring oscillator 132 having a different oscillation cycle, and accumulates the oscillation cycle difference to generate a delay characteristic equivalent to or similar to a critical path; The delay detection circuit 14 for detecting the delay amount generated by the accumulation in the characteristic combination circuit 13, and the delay characteristic combination circuit 13 and the target circuit 11 for the power supply voltage supply circuit 16 based on the detection signal S14 of the delay detection circuit 14. a control circuit 15 for outputting a control signal S152 to instruct the power supply voltage V _DD to be supplied to Since there is provided, while suppressing the increase in circuit scale, it is possible to finely adjust the delay characteristics. In addition, since a plurality of different basic delay elements (delay components) are prepared and combined, there is versatility and it is possible to match the delay characteristics of all target circuits. Further, since the delay generation / detection timing is controlled by the control circuit, there is an advantage that the stability of the power supply voltage control loop can be flexibly adjusted.

Second Embodiment FIG. 5 is a circuit diagram showing a second embodiment of the semiconductor device according to the present invention.

The second embodiment differs from the first embodiment described above in that the delay elements 131-5 and 132-5 according to the first embodiment of FIG. B) a first delay characteristic synthesizing circuit 13A composed of gate delay elements and a second delay characteristic synthesizing circuit 13B composed of wiring delay elements shown in FIGS. 4A and 4B.
And are connected in series between the pulse generation circuit 13 and the delay detection circuit 14.

The first delay characteristic synthesizing circuit 13A includes a first ring oscillator 131A and a second ring oscillator 1.
32A, the output signal S of the first ring oscillator 131A
A first counter 133A driven by 131A, a second counter 134A driven by an output signal S132A of the second ring oscillator 132A, a gate accumulation number set value ACV-A set by a register (not shown) or an external pin. And the output signal S1 of the first counter 133A
33A and compares the comparison result with the first match detection signal S1.
35A, the first comparison circuit 135A for outputting to the second delay characteristic synthesizing circuit 13B, the accumulation number setting value ACV-A similarly set by the register or the external pin, and the output signal S134A of the second counter 134A. The second comparison circuit 136A for comparing and outputting the comparison result as the second coincidence detection signal S136A to the second delay characteristic combining circuit 13B is included.

The first ring oscillator 131A is shown in FIG.
, A NAND gate NA131A having one input terminal connected to the supply line of the first enable signal S121 by the pulse generation circuit 12 and a NAND gate NA131A
Delay elements D131-1, D131-2, D connected in series between the output terminal of the gate NA131A and the other input terminal
131-3, D131-4, D131-5-1, D13
1-5-2, D131-6 and D131-7 are configured to oscillate and output a first oscillation signal S131A to a first counter 133A.

The second ring oscillator 132A is shown in FIG.
, A two-input NAND gate NA132A whose one input terminal is connected to the supply line of the second enable signal S122 by the pulse generation circuit 12 and a NAND
Delay elements D132-1, D132-2, and D connected in series between the output terminal of the gate NA132A and the other input terminal
132-3, D132-4, D132-5-1, D13
2-6 and D132-7 are configured to oscillate,
The second oscillation signal S132A is output to the second counter 134A.

The NAND gate NA131 as a delay element included in the first ring oscillator 131A, the delay elements D131-1 to D131-7 and the NAND gate N as a delay element included in the second ring oscillator 132.
Among A132 and delay elements D132-1 to D132-7, the delay element D131-5 (-1, -2) included in the first ring oscillator 131A is the delay element D132- included in the second ring oscillator 132A. The delay is larger than that of 5-1 by Δτ. As a result, the oscillation cycle of the first ring oscillator 131A is longer than that of the second ring oscillator 132A by the delay of the buffer 131-5-2, so that the gate delay component can be generated.

The second delay characteristic synthesizing circuit 13B includes a third ring oscillator 131B and a fourth ring oscillator 1.
32B, the output signal S of the third ring oscillator 131B
The third counter 133B driven by 131B, the fourth counter 134B driven by the output signal S132B of the fourth ring oscillator 132B, and the wiring accumulation number set value ACV-B set by a register (not shown) or an external pin. And the output signal S13 of the third counter 133B
3B and compares the comparison result with the third match detection signal S13.
The third comparison circuit 135B, which outputs 5B to the delay detection circuit 14, compares the accumulated number setting value ACV-B similarly set by the register or the external pin with the output signal S134B of the fourth counter 134B, and compares It has a fourth comparison circuit 136B which outputs the result to the delay detection circuit 14 as a fourth match detection signal S136B.

The third ring oscillator 131B is shown in FIG.
As shown in FIG. 2, one input terminal is connected to the supply line of the first coincidence detection signal S135A by the first comparison circuit 135A of the first delay characteristic synthesizing circuit 13A.
ND gate NA131B and NAND gate NA131
Delay elements D131-1, D131-2, D131-3, D1 connected in series between the output terminal of B and the other input terminal
31-4, D131-5-3, D131-6 and D1
31-7 makes it possible to oscillate, and the third oscillation signal S
131B is output to the third counter 133B.

The fourth ring oscillator 132B is shown in FIG.
As shown in FIG. 2, a two-input NA whose one input terminal is connected to the supply line of the second coincidence detection signal S136B by the second comparison circuit 136A of the first delay characteristic combination circuit 13A.
ND gate NA132B and NAND gate NA132
Delay elements D132-1, D132-2, D132-3, D1 connected in series between the B output terminal and the other input terminal
32-4, D132-5-1, D132-6 and D1
32-7 is configured to oscillate, and the fourth oscillation signal S
132B is output to the fourth counter 134B.

NAND gate NA131B as a delay element included in the third ring oscillator 131B, NAND elements NA131B and delay element D132 as delay elements included in the delay elements D131-1 to D131-7 and fourth ring oscillator 132B. -1 to D132-7
Among them, the wiring 131-5-3 as a delay element included in the third ring oscillator 131B outputs a signal from the end of the wiring, while the fourth ring oscillator 132.
Since the signal is output from the position of the length L1 to the wiring 132-5-3 included in B, the oscillation cycle of the third ring oscillator 131B is the same as that of the fourth ring oscillator 1B.
It becomes longer than the oscillation cycle of 32B by the delay of the wiring length L2, and the wiring delay component can be generated.

Next, the operation according to the second embodiment will be described with reference to FIG.
Will be described in association with the timing chart of FIG.

First, as shown in FIG. 6B, the control circuit 15 sends a start signal S 151 for starting the operation to the pulse generation circuit 12. Pulse generation circuit 12
Then, in response to the start signal S151, as shown in FIG.
As shown in (J), a first enable signal S121 and a second enable signal S122 having a delay difference of one cycle of the clock signal CLK are generated and output to the first delay characteristic synthesizing circuit 13A. .

In the first delay characteristic synthesizing circuit 13A, the first enable signal S121 is input to the first ring oscillator 131A, the first counter 133A, and the first comparing circuit 135A. On the other hand, the second enable signal S122 causes the second ring oscillator 132 to
A, the second counter 134A, and the second comparison circuit 1
36A is input. As a result, the oscillation of the first and second ring oscillators 131A and 132A is started, and the first and second counters 133A and 134A are also activated.
The reset operation is released and the counting operation starts. Further, in the first and second comparison circuits 135A and 136A, as shown in FIGS. 6E and 6L, respectively,
Output signals S133A, S of counters 133A, 134A
The comparison between 134A and the cumulative number setting value ACV-A is started.

Then, as shown in FIGS. 6 (E), (L), (F), and (M), the first and second counters 1
In 33A and 134A, the gate delay components are accumulated, and when the output values of the first and second counters 133A and 134A match the accumulation number set value ACV-A, the first and second comparisons are performed. The first and second coincidence detection signals S135A and S136A are output from the circuits 135A and 136A to the second delay characteristic synthesizing circuit 13B.

Here, as shown in FIGS. 6C and 6F, the time τgtd from the rising edge of the first enable signal S121 to the rising edge of the first match detection signal S135A and FIG. ) And (M), the gate delay is the difference in time τgtc from the rising edge of the second enable signal S122 to the rising edge of the second match detection signal S136A.

These first and second coincidence detection signals S1
35A and S136A are enable signals for the second delay characteristic synthesizing circuit 13B at the next stage. Then, the first coincidence detection signal S135A is output to the second delay characteristic combining circuit 1
It is input to the 3B third ring oscillator 131B, the third counter 133B, and the third comparison circuit 135B. Similarly, the second match detection signal 136A is the fourth ring oscillator 132 of the second delay characteristic synthesizing circuit 13B.
B, the fourth counter 134B, and the fourth comparison circuit 1
36B is input. As a result, the oscillations of the third and fourth ring oscillators 131B and 132B are started, and the third and fourth counters 133B and 134B are also activated.
The reset operation is released and the counting operation starts. Further, in the third and fourth comparison circuits 135B and 136B, as shown in FIGS. 6H and 6O, respectively,
Output signals S133B, S of counters 133B, 134B
The comparison between 134B and the cumulative number setting value ACV-B is started.

Then, as shown in FIGS. 6 (H), (O), (I), and (P), the third and fourth counters 1
In 33B and 134B, the gate delay components are accumulated, and when the output values of the third and fourth counters 133B and 134B match the accumulated number setting value ACV-B, the third and fourth comparisons are performed. Third and fourth coincidence detection signals S135B and S136B are output from the circuits 135B and 136B to the delay detection circuit 14.

Here, as shown in FIGS. 6F and 6I, the time τrcd from the rising edge of the first match detection signal S135A to the rising edge of the third match detection signal S135B and FIG. As shown in M) and (P), the wiring delay is the difference in the time τrcc from the rising edge of the second match detection signal S136A to the rising edge of the fourth match detection signal S136B, and the signals S135B and S136B The delay difference of the rising edge of is the final delay difference with respect to the target delay amount (1 clock cycle). The subsequent processing is performed in the same manner as in the first embodiment.

That is, the third and fourth comparison circuits 13
Third and fourth coincidence detection signals S by 5B and 136B
In the delay detection circuit 14 receiving 135B and S136B,
The rising edge of the third match detection signal S135B and the rising edge of the fourth match detection signal S136B are compared, and the delay difference between the both edges is output to the control circuit 15 as delay information S14. In the control circuit 15, a control signal S152 for instructing the power supply voltage supply circuit 16 to increase, decrease or maintain the power supply voltage is generated based on the obtained delay information S14, and the power supply voltage supply circuit 16 is generated. Is output. As a result, from the power supply voltage supply circuit 16 to the target circuit 11 and the delay characteristic synthesis circuit 1
The power supply voltage V _DD supplied to 3A and 13B changes. Further, in the control circuit 15, when the delay information from the delay detection circuit 14 is acquired, the start signal S151 is switched to the low level as shown in FIG. 6 (B). As a result, in the pulse generating circuit 12, the first and second enable signals S121 and S122 are switched to the low level, and the operation of the delay characteristic synthesizing circuit 13A is stopped.

According to the second embodiment, by independently setting the number of times the gate and wiring delay components are accumulated, the delay components can be combined at an arbitrary ratio to generate a desired delay. Therefore, it is possible to more flexibly match the critical path characteristics of the target circuit.

Further, in the second embodiment, an example in which the two delay components of the gate delay component and the wiring delay component are combined is shown, but the present invention is not limited to this. By introducing more delay elements having different delay characteristics with the same configuration, it becomes possible to combine more delay components. The necessary condition is that a plurality of delay characteristic synthesizing circuits each composed of delay elements having different delay characteristics are connected in series to synthesize a plurality of delay components at an arbitrary ratio to generate a desired delay characteristic. is there.

Third Embodiment FIG. 7 is a circuit diagram showing a third embodiment of the semiconductor device according to the present invention.

The third embodiment is different from the above-mentioned first embodiment in that the gates shown in FIGS. 2 and 3 are provided in the first and second ring oscillators constituting the delay characteristic synthesizing circuit. It is configured to have both delay elements and wiring delay elements and to be able to simultaneously accumulate both delay components of the gate delay component and the wiring delay component. Then, in the delay characteristic synthesizing circuit 20 according to the third exemplary embodiment, when the cumulative value of each delay component reaches the cumulative number set value, the selector selects a transmission path in which a delay difference does not occur between both ring oscillators. By providing a switching function, simultaneous accumulation of multiple delay components is realized.

Specifically, the delay characteristic synthesizing circuit 20 according to the third embodiment includes a first ring oscillator 201,
Second ring oscillator 202, first counter 203 driven by output signal S201 of first ring oscillator 201, second counter 204 driven by output signal S202 of second ring oscillator 202, register not shown Alternatively, the first comparison circuit 205 which compares the gate accumulation number setting value ACV-A set by the external pin with the output signal S203 of the first counter 203 and outputs the comparison result as the first match detection signal S205. Similarly, the gate accumulation number setting value ACV-A set by the register or the external pin and the output signal S of the second counter 204.
204 and compares the comparison result with the second match detection signal S2.
The second comparison circuit 206 which outputs as 06, the wiring accumulation number setting value ACV-B set by a register (not shown) or an external pin, and the output signal S20 of the first counter 203.
3 and the comparison result is the third match detection signal S207.
The third comparison circuit 207 which outputs as, similarly, the wiring number set value ACV-B set by the register or the external pin.
And the output signal S204 of the second counter 204 are compared, and the fourth comparison circuit 208 for outputting the comparison result as the fourth match detection signal S208, the first match detection signal S20.
5 and the third coincidence detection signal S207 are ANDed, and the result is output to the delay detection circuit 14 as the signal S209, and the second coincidence detection signal S206 and the fourth coincidence detection. The logical product of the delay detection circuit 14 and the signal S208 is obtained, and the result is used as a signal S210.
It has a second AND gate 210 for outputting to.

As shown in FIG. 7, the first ring oscillator 201 has a two-input NAND gate NA201 whose one input terminal is connected to the supply line of the first enable signal S121 by the pulse generation circuit 12, and a NAND gate NA201. Delay elements D201-1, D201-2, D201 connected in series between the output terminal of NA201 and the other input terminal
-3, D201-4, D201-5, D201-6, D
201-7, D201-8, D201-9, transmission path P
201-1 and P201-2, selector SL201-
1, the transmission paths P201-3 and P201-4, the selector SL201-2, and the delay element D201-10 are configured to oscillate, and the first oscillation signal S201
To the counter 203.

The transmission path P201-1 is, for example, shown in FIG.
The wiring delay element D131-5-3 shown in FIG. Further, the transmission path P201-2 is composed of, for example, the gate delay element 132-5-1 shown in FIG. The transmission path P201-3 is, for example, the gate delay elements 131-5-1 and 131-131 shown in FIG.
-5-2. In addition, the transmission path P20
1-4 are gate delay elements 1 shown in FIG. 2B, for example.
32-5-1.

Transmission paths P201-1 and P201-2
Is connected in parallel to the output of the delay element D201-9, and the other end of the transmission path P201-1 is connected to the selector S.
It is connected to the select terminal A of L201-1, and the transmission path P
The other end of 201-2 is connected to the select terminal B of the selector SL201-1. One ends of the transmission paths P201-3 and P201-4 are connected in parallel to the output of the selector SL201-1, and the other ends of the transmission paths P201-3 are connected to the select terminal A of the selector SL201-2. The other end of P201-4 is the selector SL201
-2 select terminal B is connected.

The selector SL201-1 responds to the third coincidence detection signal S207 from the third comparison circuit 207.
Connect terminal A or B to the output terminal. For example, the selector SL201-1 has the third comparison circuit 207
When the coincidence detection signal S207 is low level, the terminal A is connected to the output terminal, and when the third coincidence detection signal S207 is high level, the terminal B is connected to the output terminal.
The selector SL201-2 connects the terminal A or B to the output terminal according to the first match detection signal S205 from the first comparison circuit 205. For example, selector SL201
-2 connects terminal A to the output terminal when the first match detection signal S205 by the first comparison circuit 205 is at low level, and when the first match detection signal S205 is at high level, Connect terminal B to the output terminal.

As shown in FIG. 7, the second ring oscillator 202 has a two-input NAND gate NA202 whose one input terminal is connected to the supply line of the first enable signal S121 by the pulse generation circuit 12, and a NAND gate NA202. Delay elements D202-1, D202-2, D202 connected in series between the output terminal of the NA202 and the other input terminal
-3, D202-4, D202-5, D202-6, D
202-7, D202-8, D202-9, transmission path P
202-1 and P202-2, selector SL202-
1, the transmission paths P202-3 and P202-4, the selector SL202-2, and the delay element D202-10 so that they can oscillate, and the second oscillation signal S202
To the counter 204.

The transmission path P202-1 is, for example, as shown in FIG.
It is composed of a wiring delay element D132-5-3 shown in FIG. Further, the transmission path P202-2 is composed of, for example, the gate delay element 132-5-1 shown in FIG. The transmission path P202-3 is composed of, for example, the gate delay element 132-5-1 shown in FIG. Similarly, the transmission path P202-4 is composed of, for example, the gate delay element 132-5-1 shown in FIG.

Transmission paths P202-1 and P202-2
Of the transmission path P202-1 is connected in parallel to the output of the delay element D202-9, and the other end of the transmission path P202-1 is connected to the selector S.
The transmission path P is connected to the select terminal A of L202-1.
The other end of 202-2 is connected to the select terminal B of the selector SL202-1. One ends of the transmission paths P202-3 and P202-4 are connected in parallel to the output of the selector SL202-1 and the other ends of the transmission paths P202-3 are connected to the select terminal A of the selector SL202-2. The other end of P202-4 is the selector SL202
-2 select terminal B is connected.

The selector SL202-1 responds to the fourth coincidence detection signal S208 from the fourth comparison circuit 208.
Connect terminal A or B to the output terminal. For example, the selector SL202-1 has a fourth comparison circuit 208
When the coincidence detection signal S208 is low level, the terminal A is connected to the output terminal, and when the fourth coincidence detection signal S208 is high level, the terminal B is connected to the output terminal.
The selector SL202-2 connects the terminal A or B to the output terminal according to the second match detection signal S206 from the second comparison circuit 206. For example, selector SL202
-2 connects terminal A to the output terminal when the second match detection signal S206 by the second comparison circuit 206 is at low level, and when the second match detection signal S206 is at high level, Connect terminal B to the output terminal.

Next, the operation according to the third embodiment will be described with reference to FIG.
Will be described in association with the timing chart of FIG. Here, the gate delay accumulation number ACV-A is shown as M times, and the wiring delay accumulation number ACV-B is shown as N times (M <N).

First, the start signal S 151 for starting the operation is sent from the control circuit 15 to the pulse generation circuit 12. In the pulse generation circuit 12, the start signal S15
In response to 1, the first enable signal S121 and the second enable signal S122 having a delay difference of one cycle of the clock signal CLK are received as shown in FIGS. It is generated and output to the delay characteristic synthesizing circuit 20.

In the delay characteristic synthesizing circuit 20, the first enable signal S121 is applied to the first ring oscillator 20.
1, the first counter 203, the first comparison circuit 205, the third comparison circuit 207, and the first AND gate 209.
Entered in. On the other hand, the second enable signal S122 indicates that the second ring oscillator 202 and the second counter 20
4, the second comparison circuit 206, the fourth comparison circuit 208, and the second AND gate 210. Thereby, the first and second ring oscillators 201, 202
Is started, the reset of the first and second counters 203 and 204 is released, and the counting operation is started. In addition, the first and second comparison circuits 205,
At 206, FIG. 8 (E), (F),
As shown in (K) and (L), counters 205 and 206
The comparison between the output signals S205, S206 and the gate delay accumulation number setting value ACV-A is started. Similarly, in the third and fourth comparison circuits 207 and 208, as shown in FIGS. The comparison with the wiring delay accumulation number setting value ACV-B is started.

At this time, the output signal S205 of the first comparison circuit 205 and the output signal S of the second comparison circuit 206
Since 206 is at a low level as shown in FIGS. 8F and 8L, the selectors SL201-1 and SL20 in the first and second ring oscillators 201 and 202, respectively.
1-2 and SL202-1, SL202-2,
All the transmission paths P201-1, P201-3 and P202-1, P202-3 on the A side are selected and connected to the output terminal. In the first and second ring oscillators 201 and 202, the gate delay elements 131-5-1 and 132-5-1 and the wiring delay elements 131-5-3 and 1 are included.
Oscillation occurs with a delay difference caused by the wiring length difference L2 of 32-5-3. That is, τ1−τ2 = gate delay component + wiring delay component, and the gate delay and the wiring delay are accumulated at the same time.

First and second ring oscillators 20
At the time when the number of accumulations at 1,202 reaches M times,
As shown in (F) and (L), the output signal S205 of the first comparison circuit 205 and the output signal S206 of the second comparison circuit 206 switch from low level to high level.
As a result, the connection with the output terminals of the selector SL201-2 of the first ring oscillator 201 and the selector SL202-2 of the second ring oscillator 202 is switched to the B-side transmission paths P201-4 and P202-4.
Since the transmission paths P201-4 and P202-4 on the B side have the same configuration, no delay difference occurs between both transmission paths.
Therefore, after that, the gate delay is not accumulated,
Only wire delays are accumulated. That is, τ3−τ4 = wiring delay component.

When the number of times of accumulation reaches N times, as shown in FIGS. 8G and 8M, the output signal S207 of the third comparison circuit 207 and the fourth comparison circuit 208 are output.
The output signal S208 of is switched from the low level to the high level. As a result, the connection with the output terminals of the selector SL201-1 of the first ring oscillator 201 and the selector SL202-1 of the second ring oscillator 202 is switched to the B-side transmission paths P201-2 and P202-2, and the wiring delay Also ends the accumulation of.

In addition, the output signal S of the first comparison circuit 205
205 and the output signal S207 of the third comparison circuit 207
Is input to the first AND gate 209 and is input to FIG.
As shown in, the final high level is output to the delay detection circuit 14 as the final delay signal S209.
Similarly, the output signal S206 of the second comparison circuit 206 and the output signal S208 of the fourth comparison circuit 208 are input to the second AND gate 210 and finally set to the high level as shown in FIG. And the final delayed signal S2
It is output as 10 to the delay detection circuit 14. Delay signal S
The delay difference between the rising edges of 209 and S210 is the final delay difference with respect to the target delay amount (1 clock cycle). The subsequent processing is performed in the same manner as in the first embodiment.

That is, in the delay detection circuit 14 which receives the delay signals S209 and S210 by the first and second AND gates 209 and 210, the rising edge of the delay signal S209 and the rising edge of the delay signal S210 are compared, and both The delay difference between the edges is output to the control circuit 15 as delay information S14. In the control circuit 15, a control signal S152 for instructing the power supply voltage supply circuit 16 to increase, decrease or maintain the power supply voltage is generated based on the obtained delay information S14, and the power supply voltage supply circuit 16 is generated. Is output. As a result, the power supply voltage V _DD supplied from the power supply voltage supply circuit 16 to the target circuit 11 and the delay characteristic combining circuit 20 changes. Further, in the control circuit 15, at the time when the delay information from the delay detection circuit 14 is acquired, as shown in FIG.
151 is switched to the low level. As a result, in the pulse generation circuit 12, the first and second enable signals S121 and S122 are switched to the low level,
The operation of the delay characteristic synthesizing circuit 20 is stopped.

According to the third embodiment, since all delay components are accumulated at the same time, compared with the second embodiment in which each delay component is sequentially accumulated, from the start of operation to the final operation. There is an advantage that the time (latency) until the delay value is obtained can be greatly shortened.

Further, in the third embodiment, an example in which the two delay components of the gate delay component and the wiring delay component are combined has been shown, but the present invention is not limited to this. By introducing more delay elements having different delay characteristics with the same configuration, it becomes possible to combine more delay components. The necessary condition is to configure a ring oscillator with a plurality of delay elements having different delay characteristics, and sequentially delete the delay elements that have reached the target number of accumulations to synthesize a plurality of delay components at an arbitrary ratio, A desired delay characteristic can be generated.

In the first to third embodiments described above, the delay elements for generating the delay difference between the oscillation cycles of the first and second ring oscillators are the gate delays shown in FIGS. 2 and 3. Although the element and the wiring delay element have been described as an example, the present invention is not limited to this, and various aspects are possible, and it is possible to generate a delay having various delay components. There is no end.

The third to ninth configuration examples of the delay element for producing the delay difference in the oscillation cycles of the first and second ring oscillators will be described below with reference to FIGS. 9 to 15. Note that here, FIG. 1 according to the first embodiment is used.
The first ring oscillator 131 and the second ring oscillator 132 will be described as examples.

FIG. 9 is a circuit diagram showing a third structural example of the delay element for generating the delay difference in the oscillation cycle of the first and second ring oscillators as the delay unit according to the present invention.

In the third configuration example, as shown in FIG. 9A, the delay element 131-5 included in the first ring oscillator 131 is the first inverter BF131-5 using the NMOS delay element. 1 and a second inverter BF131-5-2 composed of a CMOS inverter are cascade-connected, and as shown in FIG. 9B, the delay element 132-5 included in the second ring oscillator 132 is NMO
First inverter BF132-5-using S delay element
Second inverter BF consisting of 1 and CMOS inverter
It has the structure which connected 132-5-2 in cascade.

The first ring oscillator 131 has a first
The inverter BF131-5-1 is as shown in FIG.
And PMOS transistors PT131-1, PT131
-2, and NMOS transistors NT131-1, N
It is composed of T131-2. PMOS transistor
The sources of the converters PT131-1 and PT131-2 are power sources.
Pressure V _DDConnected to the supply line of the PMOS transistor
The drains of PT131-1 and PT131-2 are connected to each other
Both gates are commonly connected to the signal input line IN.
ing. NMOS transistors NT131-1, NT1
The source of 31-2 is connected to the ground line GND, and NM
OS transistors NT131-1, NT131-2
The rains are connected to each other, and the NMOS transistor NT13
The gate of 1-1 is connected to the signal input line IN, and NM
The gate of the OS transistor NT131-2 is NMOS
Sources of Transistor NT131-1, NT131-2,
That is, is connected to the ground line GND. That
The PMOS transistors PT131-1, PT131
-2 drain connection point and NMOS transistor
The connection between the drains of the NT131-1 and NT131-2
The connection point is connected, and this connection node ND131-1 is the next stage.
Inverter BF131-5-2 input node ND13
It is connected to 1-2. In addition, the second inverter BF
131-5-2 is the power supply voltage V_DDSupply line and ground
PMOS transistor PT131-
3 and NMOS transistor NT131-3 are connected in series
The gates of both transistors are connected to the input node ND131.
-2, and the PMOS transistor PT131-3
And the drains of the NMOS transistor NT131-3
The output node ND131-3 is configured by the connection point of
There is.

As shown in FIG. 9B, the first inverter BF132-5-1 of the second ring oscillator 132 has the PMOS transistors PT132-1 and PT132.
-2, and NMOS transistors NT132-1, N
It is composed of T132-2. The drains of the PMOS transistors PT132-1 and PT132-2 are connected to the supply line of the power supply voltage V _DD , the drains of the PMOS transistors PT132-1 and PT132-2 are connected to each other, and both gates are commonly connected to the signal input line IN. Has been done. NMOS transistors NT132-1, NT
The drain of 132-2 is connected to the ground line GND,
NMOS transistors NT132-1, NT132-2
Drains are connected to each other, and both gates are commonly connected to the signal input line IN. The connection point between the drains of the PMOS transistors PT132-1, PT132-2 and the NMOS transistor NT132-1,
The connection points between the drains of the NT132-2 are connected, and this connection node ND132-1 is the inverter BF1 of the next stage.
It is connected to the input node ND132-2 of 32-5-2. In addition, the second inverter BF132-5-2,
A PMOS transistor PT132-3 and an NMOS transistor NT132-3 are connected in series between the supply line of the power supply voltage V _DD and the ground line GND, the gates of both transistors are connected to the input node ND132-2, and P
An output node ND132-3 is configured by the connection point between the drains of the MOS transistor PT132-3 and the NMOS transistor NT132-3.

Considering the signal delay here,
In the ring oscillator 131 of the NMOS transistor NT131-1 when the input signal is at the high level.
Is turned on, and the nodes ND131-1 and ND131
-2 potential is pulled down to ground level. At this time, NM
Since the gate of the OS transistor NT131-2 is connected to the ground line GND, the OS transistor NT131-2 is not turned on, and the charges of the nodes ND131-1 and ND131-2 are slowly released only by the NMOS transistor NT131-1. Be seen. On the other hand, in the second ring oscillator 132, when the input signal is at the high level, the NMOS transistors NT132-1 and NT1
Both transistors 32-2 are turned on, and the node N
The potentials of D132-1 and ND132-2 are pulled down to the ground level. Therefore, the first ring oscillator 131
Nodes ND132-1, ND132-2 compared to
The discharge of the electric charge of is performed promptly. That is, the oscillation cycle of the first ring oscillator 131 is longer than the oscillation cycle of the second ring oscillator 132 by the signal propagation delay related to the NMOS transistor NT131-2.

FIG. 10 is a circuit diagram showing a fourth configuration example of the delay element for generating the delay difference in the oscillation cycle of the first and second ring oscillators as the delay unit according to the present invention.

In the fourth configuration example, as shown in FIG. 10A, the delay element 131-5 included in the first ring oscillator 131 is the first inverter BF131-5 using the PMOS delay element. 3 and a second inverter BF131-5-4 composed of a CMOS inverter are cascade-connected, and as shown in FIG. 10B, the delay element 132-5 included in the second ring oscillator 132 is P
First inverter BF132-using MOS delay element
5-3 and a second inverter BF132-5-5 composed of a CMOS inverter are connected in cascade.

The first ring oscillator 131 has a first
The inverter BF131-5-3 is shown in FIG.
As described above, the PMOS transistors PT131-4 and PT13
1-5, and NMOS transistor NT131-4,
It is composed of NT131-5. PMOS transistor
The sources of transistors PT131-4 and PT131-5 are power supplies
Voltage V _DDConnected to the supply line of the PMOS transistor
The drains of the PT131-4 and PT131-5 contact each other.
And the gate of the PMOS transistor PT131-4
Is connected to the signal input line IN,
The gate of the PT131-5 is a PMOS transistor PT
131-4 source and own source, ie power supply
Voltage V_DDConnected to the supply line. NMOS Tiger
Sources of transistors NT131-4 and NT131-5 are connected.
An NMOS transistor NT connected to the ground line GND
The drains of 131-4 and NT131-5 are connected to each other.
NMOS transistors NT131-4 and NT131
The gate of -5 is commonly connected to the signal input line IN
There is. Then, the PMOS transistors PT131-4,
Connection point between drains of PT131-5 and NMOS
Drain of transistors NT131-4 and NT131-5
Connection points are connected to each other, and this connection node ND131
-4 is the input node of the inverter BF131-5-4 at the next stage
ND131-5. Also, the second in
The barter BF131-5-4 has a power supply voltage V_DDSupply of
PMOS transistor P between the ground line and the ground line GND.
T131-6 and NMOS transistor NT131-6
Connected in series, the gates of both transistors are input nodes
Connected to ND131-5, PMOS transistor PT
131-6 and NMOS transistor NT131-6
The output node ND131-6 becomes
It is configured.

The first ring oscillator 132 has a first
The inverter BF132-5-4 is shown in FIG. 10 (B).
As described above, the PMOS transistors PT132-4 and PT13
2-5, and NMOS transistor NT132-4,
It is composed of NT132-5. PMOS transistor
The sources of transistors PT132-4 and PT132-5 are power supplies
Voltage V _DDConnected to the supply line of the PMOS transistor
The drains of the PT132-4 and PT132-5 are in contact with each other.
And both gates are commonly connected to the signal input line IN.
Has been. NMOS transistors NT132-4, NT
The source of 132-5 is connected to the ground line GND, and N
Of the MOS transistors NT132-4 and NT132-5
The drains are connected to each other and both gates are connected to the signal input line I.
Commonly connected to N. And the PMOS transistor
Between the drains of the star PT132-4, PT132-5
Connection point and NMOS transistors NT132-4, N
The connection point between the drains of T132-5 is connected.
The connection node ND132-4 is the next-stage inverter BF13.
2-5-4 is connected to the input node ND132-5
It In addition, the second inverter BF132-5-4 is a
Source voltage V_DDBetween the supply line and the ground line GND of
MOS transistor PT132-6 and NMOS transistor
Both transistors are connected in series.
Of the PM is connected to the input node ND132-5 and PM
OS transistor PT132-6 and NMOS transistor
Output from the connection point between the drains of the
ND132-6 is configured.

Considering the signal delay here,
In the ring oscillator 131 of, when the input signal is at the low level, the PMOS transistor PT131-4
Is turned on, and the nodes ND131-4, ND131
The potential of -5 is raised to the power supply voltage _VDD level. At this time, since the gate of the PMOS transistor PT131-5 is connected to the power supply voltage V _DD , the PMOS transistor PT131-5 is not turned on, and the charges are supplied to the nodes ND131-4 and ND131-5. Only done loosely. On the other hand, in the second ring oscillator 132, when the input signal is low level, the PMOS transistors PT132-4 and PT132
Both transistors 132-5 are turned on, and the potentials of the nodes ND132-4 and ND132-5 are set to the power supply voltage V _DD.
Raise to a level. Therefore, as compared with the case of the first ring oscillator 131, the nodes ND132-4, ND
The charge is supplied to 132-5 promptly. That is, the oscillation cycle of the first ring oscillator 131 is longer than the oscillation cycle of the second ring oscillator 132 by the signal propagation delay of the PMOS transistor PT131-5.

FIG. 11 is a circuit diagram showing a fifth configuration example of the delay element for generating the delay difference in the oscillation cycle of the first and second ring oscillators as the delay unit according to the present invention.

In the fifth configuration example, as shown in FIG. 11A, the delay element 131-5 included in the first ring oscillator 131 is the first inverter BF131-5 using the stacked NMOS delay element. -5 and a second inverter BF131-5-6 composed of a CMOS inverter are cascade-connected, and as shown in FIG.
Delay element 132- included in the ring oscillator 132 of
5 is a first inverter B composed of a CMOS inverter
It has a configuration in which the F132-5-5 and a second inverter BF132-5-6 composed of a CMOS inverter are connected in cascade.

As shown in FIG. 11A, the first inverter BF131-5-5 of the first ring oscillator 131 has PMOS transistors PT131-7 and N.
MOS transistors NT131-7 to NT131-10
It is composed by. PMOS transistor PT13
The source of 1-7 is connected to the supply line of the power supply voltage V _DD , the drain of the PMOS transistor PT131-1 is connected to the node ND131-7, and the gate is connected to the signal input line IN. NMOS transistor NT
131-7 to NT131-10 are nodes ND131-7
Is connected in series between the ground line and the ground line GND, and an NMOS
The gate of the transistor NT131-7 is connected to the signal input line IN, and the NMOS transistor NT131-8
~ The gate of NT131-10 is connected to the supply line of power supply voltage V _DD . Then, the PMOS transistor P
The connection node ND131-7 between the drains of T131-7 and the NMOS transistor NT131-7 is the input node ND131-8 of the inverter BF131-5-6 at the next stage.
It is connected to the. In addition, the second inverter BF131
-5-6 is a supply line of the power supply voltage V _DD and a ground line G
PMOS transistor PT131-8 and N between ND and
MOS transistors NT131-11 are connected in series, and the gates of both transistors are input node ND131-.
8 and the output node ND131-9 is formed by the connection point between the drains of the PMOS transistor PT131-8 and the NMOS transistor NT131-11.

As shown in FIG. 11B, the first inverter BF132-5-5 of the second ring oscillator 132 has the PMOS transistors PT132-7 and NM.
It is composed of an OS transistor NT132-7. A PMOS transistor PT132-7 and an NMOS transistor NT132-7 are connected in series between the supply line of the power supply voltage V _DD and the ground line GND, the gates of both transistors are connected to the signal input line IN, and P
A node ND132-7 is configured by the connection point between the drains of the MOS transistor PT132-7 and the NMOS transistor NT132-7, and the node ND132-7 is the input node ND of the inverter BF132-5-6 at the next stage.
132-8. In addition, the second inverter BF132-5-6 has the PMOS transistor PT13 between the supply line of the power supply voltage V _DD and the ground line GND.
2-8 and the NMOS transistor NT132-8 are connected in series, and the gates of both transistors are input node ND1.
32-8 connected to the PMOS transistor PT132
An output node ND132-9 is formed by the connection point between the drains of −8 and the NMOS transistor NT132-8.

Considering the signal delay here,
In the ring oscillator 131 of, when the input signal is at the high level, the NMOS transistor NT131-7
Is turned on and the NMOS transistors NT131-8 to NT13 are biased by the power supply voltage V _DD.
1-10 through nodes ND131-7, ND131-
The potential of 8 is pulled down to the ground level. At this time, NMO
Since not only the S-transistor NT131-7 but also the NMOS transistors NT131-8 to NT131-10 are passed through, the charges of the nodes ND131-7 and ND131-8 are released gently. On the other hand, in the second ring oscillator 132, when the input signal is at the high level, the NMOS transistor NT132-7 is turned on and the nodes ND132-7 and ND132-8 are turned on.
Pull the potential of to the ground level. Therefore, as compared with the case of the first ring oscillator 131, the node ND13
2-7 and ND132-8 are quickly discharged. That is, the oscillation cycle of the first ring oscillator 131 is longer than that of the second ring oscillator 132, that is, the NMOS transistors NT131-8 to N.
It becomes longer by the signal propagation delay related to T131-10.

FIG. 12 is a circuit diagram showing a sixth structural example of the delay element for generating the delay difference in the oscillation cycle of the first and second ring oscillators as the delay unit according to the present invention.

In the sixth configuration example, as shown in FIG. 12A, the delay element 131-5 included in the first ring oscillator 131 is a first inverter BF131-5 using a stacked PMOS delay element. -7 and a second inverter BF131-5-8 composed of a CMOS inverter are cascade-connected, and as shown in FIG.
Delay element 132- included in the ring oscillator 132 of
5 is a first inverter B composed of a CMOS inverter
It has a configuration in which F132-5-7 and a second inverter BF132-5-8 composed of a CMOS inverter are connected in cascade.

As shown in FIG. 12A, the first inverter BF131-5-7 of the first ring oscillator 131 has PMOS transistors PT131-9 to PT1.
2 and an NMOS transistor NT131-12. The PMOS transistor PT1 is provided between the supply line of the power supply voltage V _DD and the node ND131-10.
31-9 to PT131-12 are connected in series, and PMO
The gate of the S transistor PT131-12 is connected to the signal input line IN, and the PMOS transistor PT131-
The gates of 9 to PT131-11 have the reference potential Vss (GN
D). NMOS transistor NT13
1-12 is the node ND131-10 and the ground line GND
And NMOS transistor NT1 connected in series between
The gate of 31-12 is connected to the signal input line IN. Then, the PMOS transistor PT131-12
And the connection node ND131-10 between the drains of the NMOS transistor NT131-12 and the drain of the NMOS transistor NT131-12 is the inverter B of the next stage.
It is connected to the input node ND131-11 of the F131-5-8. In addition, the second inverter BF131-5-
Reference numeral 8 denotes a PMOS transistor PT131-13 and NMO between the supply line of the power supply voltage _VDD and the ground line GND.
The S transistor NT131-13 is connected in series, the gates of both transistors are connected to the input node ND131-11, and the PMOS transistors PT131-13 and N are connected.
The output node ND131-12 is configured by the connection point between the drains of the MOS transistors NT131-13.

As shown in FIG. 12B, the first inverter BF132-5-7 of the second ring oscillator 132 has the PMOS transistors PT132-9 and NM.
It is composed of an OS transistor NT132-9. The PMOS transistor PT132-9 and the NMOS transistor NT132-9 are connected in series between the supply line of the power supply voltage V _DD and the ground line GND, the gates of both transistors are connected to the signal input line IN, and PM
A node ND132-10 is configured by a connection point between the drains of the OS transistor PT132-9 and the NMOS transistor NT132-9, and the node ND132-10 is an input node ND of the inverter BF132-5-8 of the next stage.
132-11. In addition, the second inverter BF132-5-8 has the PMOS transistor PT1 between the supply line of the power supply voltage V _DD and the ground line GND.
32-10 and the NMOS transistor NT132-10 are connected in series, the gates of both transistors are connected to the input node ND132-11, and the PMOS transistor P
T132-10 and NMOS transistor NT132-1
Output node ND132 depending on the connection point between the drains of 0
-12 is configured.

Considering the signal delay here,
In the ring oscillator 131 of, when the input signal is low level, the PMOS transistor PT131-1
2 is turned on, and the PMOS transistors PT131-9 to PT are biased by the reference potential Vss.
Nodes ND131-10 and ND1 through 131-11
The potential of 31-11 is raised to the power supply voltage _VDD level.
At this time, not only the PMOS transistors PT131-12 but also the PMOS transistors PT131-9 to PT13.
1-11, the nodes ND131-10,
The electric charge is slowly supplied to the ND131-11. On the other hand, in the second ring oscillator 132, when the input signal is at the low level, the PMOS transistor PT132-9 is turned on and the node ND
132-10, ND132-11 potential is the power supply voltage V _DD
Raise to a level. Therefore, compared to the case of the first ring oscillator 131, the nodes ND132-10, N
The electric charge is quickly supplied to D132-11.
That is, the oscillation cycle of the first ring oscillator 131 is longer than that of the second ring oscillator 132, that is, the PMOS transistors PT131-9 to PT13.
It becomes longer by the signal propagation delay related to 1-11.

FIG. 13 is a circuit diagram showing a seventh configuration example of the delay element for generating the delay difference in the oscillation cycle of the first and second ring oscillators as the delay unit according to the present invention.

In the seventh configuration example, as shown in FIG. 13A, the delay element 131-5 included in the first ring oscillator 131 is a gate CMOS with a large gate length L.
First Inverter BF131-5-9 Using Delay Element
And a second inverter BF1 including a CMOS inverter
31-5-10 has a configuration in which cascade connection of 31-5-10 is performed.
As shown in (B), the delay element 132-5 included in the second ring oscillator 132 includes the delay element 132-5.
131-5-9, a first inverter BF132-5-9 composed of a CMOS inverter having a gate length L shorter than CM and CM
Second inverter BF132- which is an OS inverter
It has a configuration in which 5-10 are connected in cascade.

The first inverter BF131-5-9 of the first ring oscillator 131 is composed of a PMOS transistor PT131-14 and an NMOS transistor NT131-14, as shown in FIG. 13 (A). Supply line of power supply voltage V _DD and ground line GND
Between the PMOS transistor PT131-14 and NM
OS transistors NT131-14 are connected in series,
The gates of both transistors are connected to the signal input line IN, and the PMOS transistors PT131-14 and NMO are connected.
A node ND131-13 is configured by a connection point between drains of the S transistor NT131-14, and a node ND131
131-13 is the next stage inverter BF131-5-10
Of the input node ND131-14. In addition, the second inverter BF131-5-10 has a PMO between the supply line of the power supply voltage V _DD and the ground line GND.
The S transistor PT131-15 and the NMOS transistor NT131-15 are connected in series, the gates of both transistors are connected to the input node ND131-14, and P
An output node ND131-15 is configured by the connection point between the drains of the MOS transistor PT131-15 and the NMOS transistor NT131-15.

As shown in FIG. 13B, the first inverter BF132-5-9 of the second ring oscillator 132 has the PMOS transistors PT132-11 and N.
It is composed of a MOS transistor NT132-11. Between the supply line of the power supply voltage V _DD and the ground line GND, the PMOS transistors PT132-11 and NMO are connected.
The S transistor NT132-11 is connected in series, the gates of both transistors are connected to the signal input line IN, and the PMOS transistor PT132-11 and NMOS are connected.
A node ND132-13 is configured by a connection point between drains of the transistor NT132-11, and a node ND1
32-13 is connected to the input node ND132-14 of the inverter BF132-5-10 at the next stage. Also,
The second inverter BF132-5-10 has a power supply voltage V
_A PMOS transistor PT132-12 and an NMOS transistor N are provided between the _DD supply line and the ground line GND.
T132-12 are connected in series, the gates of both transistors are connected to the input node ND132-14, and the PMO
An output node ND132-15 is configured by a connection point between drains of the S transistor PT132-12 and the NMOS transistor NT132-12.

Considering the signal delay here,
First inverter BF13 of the ring oscillator 131 of
1-5-9 PMOS transistor PT131
The gate length of −14 constitutes the first inverter BF132-5-9 of the second ring oscillator 132.
It is set to be longer (longer) than the gate length of the S transistor PT132-11. Similarly, the gate length of the NMOS transistor NT131-14 forming the first inverter BF131-5-9 of the first ring oscillator 131 forms the first inverter BF132-5-9 of the second ring oscillator 132. The gate length of the NMOS transistor PT132-11 is set to be longer (longer). Therefore, the first ring oscillator 131
In the first inverter BF131-5-9, the charges and discharges of the nodes ND131-13 and ND131-14 are performed more slowly than the first inverter BF132-5-9 of the second ring oscillator 132. Be seen. That is, the oscillation cycle of the first ring oscillator 131 is longer than that of the second ring oscillator 132.
It becomes longer by the signal propagation delay related to the transistor NT131-14.

FIG. 14 is a diagram showing an eighth configuration example of the delay element for generating the delay difference in the oscillation cycle of the first and second ring oscillators as the delay unit according to the present invention.

In the eighth configuration example, as shown in FIG. 14A, the delay element D131-5 included in the first ring oscillator 131 is the buffer 131-5-4, 131-.
In addition to the two-stage configuration of 5-5, a configuration in which a large load capacitance C131 is connected between the connection point of the two and the ground line is adopted, and as shown in FIG.
The delay element D132-5 included in 2-5 is the buffer 1
It has a two-stage configuration of 32-5-4 and 132-5-5. In the eighth configuration example, the first ring oscillator 1
The oscillation cycle of 31 is the second ring oscillator 132.
Since it becomes longer than the delay related to the large load capacitance C131, the gate delay component can be generated.

FIG. 15 is a diagram showing a ninth configuration example of the delay element for generating a delay difference in the oscillation cycle of the first and second ring oscillators as the delay unit according to the present invention.

In the ninth configuration example, as shown in FIGS. 15A and 15B, the delay element D131-5 is connected to the wiring 13.
1-5-6, the delay element D132-5 includes the wiring 132-5-6, but is biased to connect the output of the delay element 132-4 in the previous stage to the delay element 132-6 in the next stage. Has become. Therefore, the oscillation cycle of the first ring oscillator 131 is longer than the oscillation cycle of the second ring oscillator 132 by the delay of the wiring length, and the wiring delay component can be generated.

[0130]

As described above, according to the present invention,
While suppressing the increase in circuit scale by accumulating the difference in oscillation cycle between ring oscillators with different oscillation cycles,
The delay characteristics can be finely adjusted. In addition, since a plurality of different basic delay elements (delay components) are prepared and combined, there is versatility and it is possible to match the delay characteristics of all target circuits. Further, since the delay generation / detection timing is controlled by the control circuit, the stability of the power supply voltage control loop can be flexibly adjusted.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a semiconductor device according to the present invention.

FIG. 2 is a diagram showing a first configuration example of a delay element for generating a delay difference in the oscillation cycle of the first and second ring oscillators of FIG. 1 according to the present invention.

FIG. 3 is a diagram showing a second configuration example of a delay element for generating a delay difference in the oscillation cycle of the first and second ring oscillators of FIG. 1 according to the present invention.

FIG. 4 is a timing chart for explaining the operation of the semiconductor device according to the first embodiment.

FIG. 5 is a circuit diagram showing a second embodiment of a semiconductor device according to the present invention.

FIG. 6 is a timing chart for explaining the operation of the semiconductor device according to the second embodiment.

FIG. 7 is a circuit diagram showing a third embodiment of the semiconductor device according to the present invention.

FIG. 8 is a timing chart for explaining the operation of the semiconductor device according to the third embodiment.

FIG. 9 is a diagram showing a third configuration example of the delay element for generating the delay difference in the oscillation cycle of the first and second ring oscillators according to the present invention.

FIG. 10 is a diagram showing a fourth configuration example of the delay element for generating the delay difference in the oscillation cycle of the first and second ring oscillators according to the present invention.

FIG. 11 is a diagram showing a fifth configuration example of the delay element for generating the delay difference in the oscillation cycles of the first and second ring oscillators according to the present invention.

FIG. 12 is a diagram showing a sixth configuration example of the delay element for generating the delay difference in the oscillation cycle of the first and second ring oscillators according to the present invention.

FIG. 13 is a diagram showing a seventh configuration example of the delay element for generating the delay difference in the oscillation cycles of the first and second ring oscillators according to the present invention.

FIG. 14 is a diagram showing an eighth configuration example of the delay element for generating the delay difference in the oscillation cycle of the first and second ring oscillators according to the present invention.

FIG. 15 is a diagram showing a ninth configuration example of the delay element for generating the delay difference in the oscillation cycles of the first and second ring oscillators according to the present invention.

FIG. 16 is a diagram showing a configuration example of a replica circuit for monitoring the delay characteristic of a critical path which has been used conventionally.

[Explanation of symbols]

10, 10A, 10B ... Semiconductor device, 11 ... Target circuit, 12 ... Pulse generation circuit, 13, 13A, 13B,
20 ... Delay characteristic combining circuit, 131 ... First ring oscillator, NA131 ... NAND gate, D131-1 to D131-1.
131-7 ... Delay element (delay element), 131-5-1,
131-5-1 ... buffer, D131-5-3 ... wiring,
BF131-5-1 to BF131-5-10 ... Buffer, 132 ... Second ring oscillator, NA132 ... N
AND gate, D132-1 to D132-7 ... Delay element (delay element), D132-5-1 ... Buffer, D132
-5-3 ... Wiring, BF132-5-1 to BF132-5
-10 ... buffer, 133 ... first counter, 134 ...
2nd counter, 135 ... 1st comparison circuit, 136 ... 2nd comparison circuit, 14 ... Delay detection circuit, 15 ... Control circuit,
16 ... Power supply voltage supply circuit, 201 ... First ring oscillator, 202 ... Second ring oscillator, 203 ... First
, 204 ... Second counter, 205 ... First comparison circuit, 206 ... Second comparison circuit, 207 ... Third comparison circuit, 208 ... Fourth comparison circuit, 209 ... First AN
D gate, 210 ... Second AND gate.

Claims (37)

[Claims] 1. A semiconductor device having a function for grasping delay characteristics of a critical path of a target circuit, the first delay unit capable of oscillating, and the second delay unit having an oscillation cycle different from that of the first delay unit. And a delay characteristic synthesizing circuit for generating a delay characteristic equivalent to or similar to a critical path by accumulating an oscillation cycle difference between the first delay unit and the second delay unit. 2. The first and second delay units include:
The semiconductor device according to claim 1, further comprising a ring oscillator. 3. The delay characteristic synthesizing circuit counts the oscillation output of the first delay unit, and the second counter counts the oscillation output of the second delay unit.
A counter, and obtains a target delay amount by accumulating the delay difference generated by the first and second ring oscillators a desired number of times based on the outputs of the first and second counters. Item 2. The semiconductor device according to item 1. 4. The delay characteristic synthesizing circuit is capable of arbitrarily setting the number of accumulations from the outside, and the set value and the first
4. The semiconductor device according to claim 3, further comprising a comparison circuit that compares the output of the second counter with the output of the second counter to detect that the target number of accumulations has been reached. 5. The pulse generation circuit according to claim 1, further comprising a pulse generation circuit for generating a reference signal for activating the delay characteristic synthesizing circuit, which is two pulse signals having different phases indicating a target delay amount according to a clock frequency. Semiconductor device. 6. The semiconductor device according to claim 2, wherein an oscillation cycle difference between the first ring oscillator and the second ring oscillator is generated by a delay element having a desired delay characteristic. 7. A difference between a delay generated by a first delay element included in the first ring oscillator and a delay generated by a second delay element included in the second ring oscillator is a desired delay. The semiconductor device according to claim 2, wherein the first and second delay elements are configured so as to have a delay having characteristics. 8. A semiconductor device having a function for grasping delay characteristics of a critical path of a target circuit, the first delay unit capable of oscillating, and the second delay unit having an oscillation cycle different from that of the first delay unit. Delay unit combining circuit for generating delay characteristics equivalent to or similar to a critical path by accumulating oscillation cycle differences between the first delay unit and the second delay unit, and the target circuit And a power supply voltage supply circuit that supplies a power supply voltage to the delay characteristic synthesis circuit, a delay detection circuit that detects the delay amount generated by the accumulation in the delay characteristic synthesis circuit, and a power supply voltage based on the detection signal of the delay detection circuit. Semiconductor having delay circuit synthesizing circuit for supply circuit and control circuit for instructing power supply voltage value to be supplied to target circuit Location. 9. The first and second delay units include:
The semiconductor device according to claim 8, further comprising a ring oscillator. 10. The delay characteristic synthesizing circuit counts the oscillation output of the first delay unit, and the second counter counts the oscillation output of the second delay unit.
A counter, and obtains a target delay amount by accumulating the delay difference generated by the first and second ring oscillators a desired number of times based on the outputs of the first and second counters. Item 9. The semiconductor device according to item 8. 11. The delay characteristic synthesizing circuit can arbitrarily set the number of accumulations from outside, and compares the set value with the outputs of the first and second counters to reach a target number of accumulations. 11. A comparison circuit for detecting the fact that
The semiconductor device described. 12. A semiconductor device according to claim 8, further comprising a pulse generation circuit for generating a reference signal for activating the delay characteristic synthesizing circuit, which is two pulse signals having different phases indicating a target delay amount according to a clock frequency. apparatus. 13. The semiconductor device according to claim 9, wherein an oscillation cycle difference between the first ring oscillator and the second ring oscillator is generated by a delay element having a desired delay characteristic. 14. A difference between a delay generated by a first delay element included in the first ring oscillator and a delay generated by a second delay element included in the second ring oscillator is a desired delay. 10. The first and second delay elements are configured to provide a characteristic delay.
The semiconductor device described. 15. The semiconductor device according to claim 8, wherein the control circuit stops the operation of the delay characteristic synthesizing circuit after the delay detection circuit finishes detecting the delay amount output from the delay characteristic synthesizing circuit. . 16. A semiconductor device having a function for grasping delay characteristics of a critical path of a target circuit, the first delay unit capable of oscillating, and the second delay unit having an oscillation cycle different from that of the first delay unit. And a plurality of delay characteristic synthesizing circuits that generate delay characteristics equivalent to or similar to a critical path by accumulating the oscillation cycle difference between the first delay unit and the second delay unit. The first and second delay units included in each of the delay characteristic combining circuits include delay elements for generating delays having different delay characteristics, and the delay characteristic combining circuits are cascaded to form a plurality of different delays. A semiconductor device in which delays having characteristics are combined at a desired ratio to obtain delay characteristics equivalent to or similar to a critical path. 17. The semiconductor device according to claim 16, wherein the first and second delay units include a ring oscillator. 18. The delay characteristic synthesizing circuit comprises:
A first counter that counts the oscillation output of the second delay unit, and a second counter that counts the oscillation output of the second delay unit.
A counter, and obtains a target delay amount by accumulating the delay difference generated by the first and second ring oscillators a desired number of times based on the outputs of the first and second counters. Item 17. The semiconductor device according to item 16. 19. The delay characteristic synthesizing circuit can arbitrarily set the number of accumulations from the outside, and compares the set value with the outputs of the first and second counters to obtain a target number of accumulations. 2. A comparison circuit for detecting arrival of the signal.
8. The semiconductor device according to item 8. 20. A pulse generating circuit for generating a reference signal for activating the delay characteristic synthesizing circuit in the first stage, which is two pulse signals having different phases indicating a target delay amount according to a clock frequency. The semiconductor device described. 21. In the plurality of cascaded delay characteristic synthesizing circuits, the output signal of the delay characteristic synthesizing circuit of the preceding stage is a signal for activating the delay characteristic synthesizing circuit of the next stage. Semiconductor device. 22. A semiconductor device having a function for grasping delay characteristics of a critical path of a target circuit, the first delay unit capable of oscillating, and the second delay unit having an oscillation cycle different from that of the first delay unit. And a plurality of delay characteristic synthesizing circuits that generate delay characteristics equivalent to or similar to a critical path by accumulating the oscillation cycle difference between the first delay unit and the second delay unit. The first and second delay units included in each of the delay characteristic combining circuits include delay elements for generating delays having different delay characteristics, and the delay characteristic combining circuits are cascaded to form a plurality of different delays. A delay having characteristics is synthesized at a desired ratio to obtain a delay characteristic equivalent to or similar to a critical path, and the target circuit and the delay characteristic described above are further added. A power supply voltage supply circuit that supplies a power supply voltage to the synthesis circuit, a delay detection circuit that detects the amount of delay generated by accumulation in the delay characteristic combining circuit at the final stage, and a power supply voltage based on the detection signal of the delay detection circuit A semiconductor device comprising: a supply circuit; a delay characteristic synthesizing circuit; 23. The semiconductor device according to claim 22, wherein the first and second delay units include a ring oscillator. 24. Each of the delay characteristic synthesizing circuits comprises:
A first counter that counts the oscillation output of the second delay unit, and a second counter that counts the oscillation output of the second delay unit.
A counter, and obtains a target delay amount by accumulating the delay difference generated by the first and second ring oscillators a desired number of times based on the outputs of the first and second counters. Item 23. The semiconductor device according to Item 22. 25. In each of the delay characteristic synthesizing circuits, the number of accumulations can be arbitrarily set from the outside, and the set value is compared with outputs of the first and second counters to obtain a target number of accumulations. 3. A comparison circuit for detecting the arrival of the signal.
4. The semiconductor device according to 4. 26. A pulse generating circuit for generating a reference signal for activating the delay characteristic synthesizing circuit in the first stage, which is two pulse signals having different phases indicating a target delay amount according to a clock frequency. The semiconductor device described. 27. In the plurality of cascaded delay characteristic synthesizing circuits, the output signal of the delay characteristic synthesizing circuit of the preceding stage is a signal for activating the delay characteristic synthesizing circuit of the next stage. Semiconductor device. 28. The control circuit stops the operation of all the delay characteristic combining circuits connected in series after the delay detecting circuit finishes detecting the delay amount output from the delay characteristic combining circuit at the final stage. 23. The semiconductor device according to claim 22, wherein 29. A semiconductor device having a function of grasping delay characteristics of a critical path of a target circuit, the first delay unit capable of oscillating, and the second delay unit having an oscillation cycle different from that of the first delay unit. And a plurality of delay characteristic synthesizing circuits that generate delay characteristics equivalent to or similar to a critical path by accumulating the oscillation cycle difference between the first delay unit and the second delay unit. The first and second delay units included in the delay characteristic combining circuit include a plurality of delay elements for generating delays having different delay characteristics, and the delay characteristic combining circuit simultaneously accumulates a plurality of different delay components. In addition to the calculation, the delay elements that have reached the target number of accumulations are sequentially separated by the circuit to combine multiple delay components at the desired ratio and A semiconductor device that obtains delay characteristics equivalent to or similar to the optical path. 30. The delay characteristic synthesizing circuit counts the oscillation output of the first delay unit, and the second counter counts the oscillation output of the second delay unit.
A counter, and obtains a target delay amount by accumulating the delay difference generated by the first and second ring oscillators a desired number of times based on the outputs of the first and second counters. Item 32. The semiconductor device according to item 29. 31. In the delay characteristic synthesizing circuit, the number of accumulations can be arbitrarily set from the outside, and the set value is compared with the outputs of the first and second counters to reach a target number of accumulations. 31. A comparison circuit for detecting that the operation has been performed
The semiconductor device described. 32. The pulse generation circuit according to claim 29, further comprising a pulse generation circuit for generating a reference signal for activating the delay characteristic synthesizing circuit, which is two pulse signals having different phases indicating a target delay amount according to a clock frequency. Semiconductor device. 33. A semiconductor device having a function for grasping a delay characteristic of a critical path of a target circuit, the first delay unit capable of oscillating, and the second delay unit having an oscillation cycle different from that of the first delay unit. And a plurality of delay characteristic synthesizing circuits that generate delay characteristics equivalent to or similar to a critical path by accumulating the oscillation cycle difference between the first delay unit and the second delay unit. The first and second delay units included in the delay characteristic combining circuit include a plurality of delay elements for generating delays having different delay characteristics, and the delay characteristic combining circuit simultaneously accumulates a plurality of different delay components. In addition to the calculation, the delay elements that have reached the target number of accumulations are sequentially separated by the circuit to combine multiple delay components at the desired ratio and A delay characteristic equivalent to or similar to that of the optical path, and further, a power supply voltage supply circuit for supplying a power supply voltage to the target circuit and the delay characteristic combining circuit, and a delay amount generated by accumulation in the delay characteristic combining circuit are detected. A semiconductor device having a delay detection circuit and a control circuit for instructing a power supply voltage supply circuit based on a detection signal of the delay detection circuit to instruct a power supply voltage value to be supplied to a delay characteristic combining circuit and a target circuit. 34. The delay characteristic synthesizing circuit counts the oscillation output of the first delay unit, and the second counter counts the oscillation output of the second delay unit.
A counter, and obtains a target delay amount by accumulating the delay difference generated by the first and second ring oscillators a desired number of times based on the outputs of the first and second counters. Item 34. The semiconductor device according to Item 33. 35. In the delay characteristic synthesizing circuit, the number of accumulations can be arbitrarily set from the outside, and the target accumulation number is reached by comparing the set value with the outputs of the first and second counters. 35. A comparison circuit for detecting that the operation has been performed
The semiconductor device described. 36. The pulse generation circuit according to claim 33, further comprising a pulse generation circuit for generating a reference signal for activating the delay characteristic synthesizing circuit, which is two pulse signals having different phases indicating a target delay amount according to a clock frequency. Semiconductor device. 37. The control circuit stops the operation of the delay characteristic synthesizing circuit after the delay detecting circuit finishes detecting the amount of delay output from the delay characteristic synthesizing circuit. Semiconductor device.