JP2003100752A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the planarization of an interlayer insulating film without depending on the density of an underlying pattern, to suppress the occurrence of global steps, and to obtain high flatness of the surface of the interlayer insulating film. A main object is to provide a method for manufacturing a semiconductor device. SOLUTION: A polishing liquid to which a polishing-suppressing component which is easily adsorbed by a predetermined substance and has a property of suppressing polishing is added is prepared. An interlayer insulating film 3 is formed on the semiconductor substrate 1 on which the element 2a or the wiring 2b is formed so as to cover the element 2a or the wiring 2b. At the bottom of the concave portion formed on the surface of the interlayer insulating film 3, a modified layer 7 containing a predetermined substance that adsorbs a polishing-suppressing component is formed. The surface of the interlayer insulating film 3 is mechanically and chemically polished using a polishing liquid.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a method for manufacturing a semiconductor device, and more particularly to a method for flattening an interlayer insulating film formed on an element or wiring on a semiconductor substrate.

[0002]

2. Description of the Related Art Large scale integrated circuits
ed circuit (LSI) with higher integration, finer structure,
With the increase in the number of wiring layers, the depth of focus of the stepper used in the manufacturing process is decreasing year by year, and the exposure margin is becoming severe. Therefore, after forming an interlayer insulating film on an element or wiring on a semiconductor substrate, a step formed on the surface of the interlayer insulating film is subjected to chemical mechanical polishing (Chemical Mechanical Polishing).
g: hereinafter referred to as CMP), it is important to completely flatten.

FIG. 3 shows a method of flattening a step on the surface of an interlayer insulating film by conventional CMP. First, as shown in FIG. 3A, a pattern of the element 2a or the wiring 2b is formed on the semiconductor substrate 1. Next, as shown in FIG. 3B, the interlayer insulating film 3 is deposited on the element 2a or the wiring 2b. Finally, as shown in FIG. 3C, the step on the interlayer insulating film 3 is C
Polish by MP and flatten.

In conventional CMP, the local step on the interlayer insulating film 3 can be eliminated relatively easily. However, due to the density of the pattern of the underlying element 2a or the wiring 2b, the region 4a in which the pattern of the underlying element 2a or the wiring 2b exists in a large area has a low polishing rate, while the depopulated region 4b has a high polishing rate. Further, in CMP, since a wafer is pressed against a polishing pad which is an elastic body to perform polishing, in a region 4c having a large area where the underlying element 2a or the wiring 2b pattern does not exist, the polishing pad surface elastically contacts the interlayer film surface. , Polishing progresses (dishing).

As a result, as shown in FIG. 3C, a difference in film thickness of the interlayer insulating film 3, that is, a so-called global step difference occurs.

In order to improve this problem, a large area of the underlying element 2 is constrained by a design rule at the pattern design stage.
The pattern of the a or the wiring 2b is divided, or a dummy pattern is arranged in a region where the pattern of the underlying element 2a or the wiring 2b does not exist to eliminate the density of the pattern of the underlying element 2a or the wiring 2b. There is.

However, it is not perfect because the design rule is incomplete or the design rule cannot be satisfied in terms of circuit design. Further, new problems such as complication of pattern design and increase of wiring capacity due to arrangement of dummy patterns are occurring.

[0008]

As described above, in the flattening of the step on the interlayer insulating film by the conventional CMP, the difference in the polishing rate due to the density of the underlying pattern or the dishing of a large area without the pattern is performed. Therefore, there is a problem that a global step is generated.

In order to solve this problem, the design rule is restricted at the pattern designing stage to divide a large-area base pattern, or a dummy pattern is arranged in a region where the pattern does not exist. I am trying to

However, the design rule is not perfect, and the circuit cannot satisfy the design rule in terms of circuit. In addition, new problems such as complicated pattern design and increased wiring capacity due to the placement of dummy patterns have arisen.

Therefore, the present invention has been made in order to solve the above-mentioned problems, and by selectively suppressing the polishing of a portion other than the step portion, the global step difference can be achieved without depending on the density of the underlying pattern. It is an object of the present invention to provide an improved method for manufacturing a semiconductor device so that the occurrence of the semiconductor device can be suppressed.

[0012]

In the method for manufacturing a semiconductor device according to claim 1, first, a polishing liquid to which a polishing-suppressing component which is easily adsorbed by a predetermined substance and has a property of suppressing polishing is added. To prepare. An interlayer insulating film is formed on the semiconductor substrate on which the element or wiring is formed so as to cover the element or wiring. A modified layer containing the predetermined substance that adsorbs the polishing-suppressing component is formed on the bottom of the recess formed on the surface of the interlayer insulating film. The surface of the interlayer insulating film is mechanically polished by using the polishing liquid.

According to the present invention, the stepped portion on the surface of the interlayer insulating film is normally polished. On the other hand, polishing of recesses having no step is selectively suppressed. Therefore, the occurrence of a global step is suppressed without depending on the density of the underlying pattern, and as a result, high flatness of the interlayer insulating film surface can be obtained.

The method of manufacturing a semiconductor device according to a second aspect is the method according to the first aspect, wherein a water-soluble binder resin is used as the polishing suppressing component.

The method of manufacturing a semiconductor device according to a third aspect is the method of manufacturing a semiconductor device according to the second aspect, wherein the modified layer containing a substance that adsorbs the water-soluble binder resin is shallowly formed at the bottom of the recess. .

According to a fourth aspect of the present invention, in the method of manufacturing the semiconductor device according to the third aspect, the step of shallowly forming the modified layer includes a step of applying a photoresist on the surface of the interlayer insulating film, The method includes the steps of forming a resist pattern from the photoresist so that the resist is left only in the portions other than the recesses, and ion-implanting the bottom of the recesses with low energy using the resist pattern as a mask.

A method of manufacturing a semiconductor device according to a fifth aspect is the method according to the fourth aspect, wherein the interlayer insulating film is made of SiO ₂ , PSG (phosphosilicate glass), or BS.
G (borosilicate glass) or BPSG (borophosphosi)
Duplicate glass).

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

In the present invention, when a step on the interlayer insulating film is flattened by CMP, a water-soluble binder resin is added to the conventional polishing liquid so as to have a property of selectively polishing only the step. To do. In this case, the polishing rate changes sharply with respect to changes in the impurity concentration in the interlayer insulating film. The present invention has been made paying attention to this characteristic.

FIG. 1 shows a specific example of this characteristic. Figure 1
In order to give step selectivity to ordinary ceria (CeO ₂ ) slurry, a water-soluble binder resin is added,
It is a figure which shows the relationship between the B (boron) density | concentration in BPSG, and the polishing rate at the time of polishing PSG. Polyacrylic acid ammonium salt was used as the water-soluble binder resin. Other than this, trehalose, hydroxyethyl cellulose, chitosan, and various surfactants can be used as the water-soluble binder resin.

It can be seen from FIG. 1 that the polishing rate of BPSG sharply decreases when the B concentration is 2.7 to 2.9 wt%.

FIG. 2 shows an embodiment of flattening a step on an interlayer insulating film according to a method of manufacturing a semiconductor device according to the present invention which utilizes this characteristic.

Referring to FIG. 2A, on the pattern of the element 2a or the wiring 2b formed on the semiconductor substrate 1,
Interlayer insulating film 3 made of SiO ₂ , PSG, BSG, BPSG, etc.
Deposit.

As the interlayer insulating film 3, PSG, BSG, B
When PSG is used, data of B and P concentrations and polishing rates as shown in FIG. 1 are obtained using a polishing liquid to which a water-soluble binder resin used for polishing is added in advance. Moreover,
The B and P (phosphorus) concentrations are set to have a sufficient margin with respect to the region 5a where the normal polishing rate is obtained and the region 5b where the polishing rate sharply decreases.

The thickness of the interlayer insulating film to be deposited is set to a predetermined interlayer film thickness + α (50 to 200 nm) on a predetermined CMP5, underlying element 2a or wiring 2b pattern.

Next, as shown in FIG. 2B, a photoresist is applied on the interlayer insulating film (not shown), and a resist pattern is formed by a photolithography process so that the photoresist is left only on the stepped portion and the inclined portion. 6 is formed.

With reference to FIGS. 2B and 2C, impurities such as B or P are ion-implanted at low energy using the resist pattern 6 as a mask. As a result, the modified layer 7 is formed on the interlayer insulating film 3 in a very shallow region on the bottom surface of the recess.

The impurity concentration to be implanted is S when the interlayer insulating film 3 is S.
In the case of iO ₂ , referring to FIG. 1, the concentration is set to have a sufficient margin with respect to the region 5b where the polishing rate is extremely small and the region 5b where the chemical polishing rate sharply decreases. To do.

Finally, as shown in FIG. 2 (d), the steps on the interlayer insulating film 3 are polished and flattened by CMP using a predetermined polishing liquid containing a water-soluble binder resin for imparting step selectivity. Turn into.

At this time, the step portion is selectively polished by the step selectivity of the polishing liquid to which the water-soluble binder resin is added, so that the step disappears. When the step is eliminated, polishing is suppressed.
On the other hand, since the polishing rate of the bottom of the concave portion whose surface is covered with the modified layer 7 containing a large amount of impurities such as B and P is extremely low, it is hardly polished.

Therefore, it is possible to suppress the occurrence of global steps without depending on the density of the underlying pattern and to obtain high flatness of the surface of the interlayer insulating film.

Further, in order to eliminate the unevenness of the underlying pattern, the design rule is applied at the pattern designing stage,
It is not necessary to divide a large-area base pattern, or to arrange a dummy pattern in a region where the pattern does not exist, and it is possible to suppress the complexity of pattern design or an increase in wiring capacity due to the arrangement of the dummy pattern.

Furthermore, the thickness of the modified layer 7 containing impurities at the bottom of the recess is α of the film thickness of the above-mentioned pre-polishing interlayer insulating film 3.
The energy at the time of ion-implanting impurities is set so as to be about (50 to 200 nm), and CMP is performed.
If the overpolish amount or time is set appropriately, the interlayer insulation film thickness on the underlying element 2a or the wiring 2b pattern is the predetermined film after CMP when high flatness is obtained on the interlayer insulation film. This means that the modified layer 7 is thick and the modified layer 7 at the bottom of the recess is also removed.

As a result, the deposition amount of the interlayer insulating film deposited before CMP can be reduced as compared with the conventional technique, and the polishing amount by CMP can also be reduced. Therefore, the processing time can be shortened to improve the processing capability and reduce the process cost. It will be possible.

The embodiments disclosed this time are to be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description but by the claims, and is intended to include meanings equivalent to the claims and all modifications within the scope.

[0036]

As described above, according to the present invention,
When the interlayer insulating film is flattened, the occurrence of a global step is suppressed without depending on the density of the underlying pattern. By the way,
A semiconductor device having a highly flat interlayer insulating film surface can be obtained.

[Brief description of drawings]

FIG. 1 is a diagram specifically showing a characteristic that, when an interlayer insulating film is polished with a polishing liquid containing a water-soluble binder resin, a polishing rate changes sharply with respect to a change in impurity concentration in the insulating film. is there.

FIG. 2 is a cross-sectional view of a semiconductor device showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view of a semiconductor device showing a method of planarizing a step on the surface of an interlayer insulating film by conventional CMP.

[Explanation of symbols]

1 semiconductor substrate, 2a element pattern, 2b wiring pattern, 3 interlayer insulating film, 4a large area pattern region, 4
b lower layer pattern region, 4c large-area unpatterned region, 5a normal polishing rate region, 5b region where polishing rate sharply decreases, 5c region where polishing rate is extremely low, 6 photoresist, 7 modified layer.

Claims (5)

[Claims] 1. A step of preparing a polishing liquid to which a polishing-suppressing component having a property of easily adsorbing to a predetermined substance and suppressing polishing is added; and a step of preparing a polishing liquid on a semiconductor substrate having an element or wiring formed thereon, A step of forming an interlayer insulating film so as to cover the element or the wiring, and a modified layer containing the predetermined substance that adsorbs the polishing inhibiting component is formed on the bottom of the recess formed in the surface of the interlayer insulating film. A method of manufacturing a semiconductor device, comprising: a step; and a step of mechanochemically polishing the surface of the interlayer insulating film with the polishing liquid. 2. The method for manufacturing a semiconductor device according to claim 1, wherein a water-soluble binder resin is used as the polishing suppressing component. 3. The modified layer containing a substance that adsorbs the water-soluble binder resin is shallowly formed on the bottom of the recess.
The method for manufacturing a semiconductor device according to claim 2. 4. The step of shallowly forming the modified layer includes a step of applying a photoresist to the surface of the interlayer insulating film, and a resist pattern so that the photoresist is left only in a portion other than the concave portion. 4. A step of forming, and a step of ion-implanting into the bottom of the recess with low energy using the resist pattern as a mask.
A method of manufacturing a semiconductor device according to item 1. 5. The interlayer insulating film is made of SiO ₂ , PSG,
The method for manufacturing a semiconductor device according to claim 4, wherein the semiconductor device is formed of BSG or BPSG.