JP2003179034A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

[PROBLEMS] To improve the reliability of a semiconductor integrated circuit device having a conductor film pattern containing aluminum as a main component. SOLUTION: Conductive film 16 mainly composed of aluminum
After patterning the first layer wiring L1 having the thickness d by dry etching, the sidewall protection film 18 on the processed side wall is formed.
Then, the photoresist pattern 17a used as the etching mask is removed by plasma ashing. Subsequently, the chlorine component adhering to the surface of the insulating film 15b and the first layer wiring L1 is removed by plasma ashing using a mixed gas of oxygen gas and methanol gas. At this time, the main surface temperature of the wafer is set to be relatively low during the ashing removal process of the photoresist pattern 17a and the like, and the main surface temperature of the wafer is set to be relatively high during the removal process of the chlorine component. I do. Further, these plasma ashing processes are performed in different processing chambers.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for manufacturing a semiconductor integrated circuit device, and more particularly, to the aluminum (A) etching process using a resist film as an etching mask.
The present invention relates to a technique effectively applied to a technique for removing a resist film after patterning a conductor film mainly containing 1).

[0002]

2. Description of the Related Art Usually, a resist film after etching a conductor film containing aluminum as a main component is ashed by plasma treatment using a mixed gas of oxygen gas (O ₂ ) and fluorine (F) gas. It is removed by ashing. But in this way,
Since chlorine (Cl) adhering to the surface of the conductor film cannot be sufficiently removed during the etching process, after the etching process, when the wafer is carried into the atmosphere or when the wafer is cleaned, the chlorine and the atmosphere There is a problem of so-called corrosion, in which hydrochloric acid is formed due to the reaction between water and water in the cleaning liquid to corrode the conductor film. Therefore, when plasma treatment using a mixed gas of an oxygen gas and a gas containing hydrogen (H) is performed, the chlorine attached to the surface of the conductor film can be satisfactorily removed together with the removal of the resist film. The above corrosion can be suppressed.

A technique for removing the resist after etching the conductor film containing aluminum as a main component is described in, for example, Japanese Patent Laid-Open No. 5-109673, and the side wall protective film formed during dry etching is cured. In order to prevent this, first, the resist film is removed at a low temperature of 100 ° C. or lower by plasma treatment using a mixed gas of oxygen gas and CHF ₃ gas, and then oxygen gas and methanol gas (CH ₃ A technique of volatilizing residual chlorine by plasma treatment using a mixed gas with (OH) is disclosed.

Further, for example, in Japanese Unexamined Patent Publication No. 7-254589, oxygen gas and hydrogen (H) such as methanol gas are contained in a state where the temperature of the sample stage is set to a high temperature of about 200 ° C. to 300 ° C. A technique of removing the resist film by plasma treatment using a mixed gas with a gas is disclosed.

[0005]

However, the present inventor has found that the above resist film removing technique has the following problems.

That is, when the plasma treatment using the mixed gas of the oxygen gas and the gas containing hydrogen (H) is performed, the occurrence of corrosion can be suppressed, but in this case, the stage temperature during the treatment is not raised to some extent. However, the chlorine component cannot be removed efficiently, which is a problem in terms of productivity. Therefore, it is necessary to perform the treatment with the stage temperature raised. However, if the resist film is removed while the stage temperature is raised, a new problem arises that the side wall protection film formed on the side wall of the conductor film is hardened and becomes difficult to remove. The side wall protective film, which is deposited on the side wall of the conductor film when the conductor film is etched and left as it is, causes a problem of corrosion of the conductor film because it contains chlorine, and also contains aluminum and has a conductive property. Since it has such a property, it causes a short circuit failure, which causes a decrease in the reliability and yield of the semiconductor integrated circuit device.

An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor integrated circuit device having a conductor film pattern containing aluminum as a main component.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, according to the present invention, after the plasma treatment using a gas containing oxygen is carried out at a relatively low temperature, the main purpose is to remove the resist film and the sidewall film,
It has a step of performing a plasma treatment using a mixed gas of oxygen gas and a gas containing hydrogen under a relatively high temperature condition mainly for removing chlorine.

[0011]

DETAILED DESCRIPTION OF THE INVENTION Before describing the present invention in detail,
The meanings of the terms in the present application are as follows.

1. A wafer is a silicon single crystal substrate (semiconductor wafer; generally a substantially circular surface) used for manufacturing integrated circuits, a sapphire substrate, a glass substrate, and other insulating materials.
It refers to semi-insulating or semiconductor substrates, etc., and composite substrates thereof. In the present application, a semiconductor integrated circuit device is not limited to a device formed on a semiconductor or an insulating substrate such as a silicon wafer or a sapphire substrate, and unless otherwise specified, a TFT (Thin
-Film-Transistor) and STN (Super-Twisted-Nema)
tic) shall include those made on other insulating substrates such as glass such as liquid crystal.

2. The device surface is a main surface of a wafer on which a device pattern corresponding to a plurality of chip regions is formed by lithography.

In the following embodiments, when there is a need for convenience, the description will be divided into a plurality of sections or embodiments, but unless otherwise specified, they are not unrelated to each other, One is in the relation of some or all of modifications of the other, details, supplementary explanations, and the like.

In the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.) of elements, the number is explicitly specified and, in principle, is limited to a specific number. The number is not limited to the specific number except the case, and may be a specific number or more or less.

Furthermore, in the following embodiments, the constituent elements (including element steps, etc.) are not necessarily essential unless otherwise specified or in principle considered to be essential. Needless to say

Similarly, in the following embodiments, when referring to shapes, positional relationships, etc. of constituent elements, etc., except when explicitly stated or when it is considered that the principle is not clear, it is substantially the same. In addition, the shape and the like are included or similar. This also applies to the above numerical values and ranges.

Further, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

Further, in this embodiment, a MIS • FET (Metal Insula) representing a field effect transistor is used.
tor Semiconductor Field Effect Transistor) MI
Abbreviated as S, p-channel type MIS • FET is abbreviated as pMIS, and n-channel type MIS • FET is abbreviated as nMIS.

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is an explanatory view of a corrosion generation model of a wiring containing aluminum (Al) as a main component. The wiring 51 formed on the insulating film 50 includes, for example, the conductive barrier film 5 on the conductive barrier film 51a via the main conductive film 51b.
It has a dissimilar metal laminated structure in which 1c is laminated. The relatively thin conductive barrier films 51a and 51c are, for example, a refractory metal film such as titanium (Ti) or titanium tungsten (TiW), a refractory metal nitride film such as titanium nitride (TiN), or the like. It is formed of a laminated film. The relatively thick main conductor film 51b is formed of a conductor film containing aluminum as a main component, such as an aluminum-silicon (Si) -copper (Cu) alloy or an aluminum-copper alloy. By the way, since such a wiring 51 is usually formed by a dry etching process using a gas containing chlorine (Cl),
A large amount of chlorine component adheres to the surface of the insulating film 50 and the wiring 51 after the pattern formation. When the wiring 51 is exposed to the atmosphere or the cleaning liquid while a large amount of chlorine component is adhered as described above, the water in the atmosphere or the water in the cleaning liquid adheres to the surface of the wiring 51 to form a hydrochloric acid (HCl) aqueous solution. The aluminum in the wiring 51 reacts with hydrochloric acid to generate a foreign substance 52 due to aluminum corrosion. Foreign object 52
Contains aluminum hydroxide (Al (OH) ₃ ) and has conductivity. In particular, when the wiring 51 has a laminated structure of the conductor film 51b containing aluminum as the main component and the refractory metal-based conductive barrier films 51a and 51c as described above, the battery due to the contact potential difference between different metals is used. The effect accelerates corrosion.

Next, FIG. 2 is an explanatory view of a defect caused by corrosion of a wiring containing aluminum as a main component.
The conductive foreign matter 52 flowing out of the wiring 51 comes into contact with the adjacent wiring 51 and a short circuit defect occurs. Further, since aluminum in the wiring 51 is precipitated in the aqueous solution and corrodes, the aluminum in the wiring 51 disappears. That is,
Since a current flows where the wiring 51 is thin, electromigration and stress migration are caused, and disconnection failure of the wiring 51 occurs.

Next, FIGS. 3 and 4 are explanatory views of a model of corrosion generation of wiring due to a cell action. FIG. 3 shows the battery action by aluminum-copper, and FIG. 4 shows the battery action by aluminum-titanium nitride. Code 5
3 has shown the hydrochloric acid aqueous solution.

The cathodic reaction with copper or titanium nitride is represented by the following equation.

[0025] In other _{words, O 2 + 4e + 2H 2} O → 4OH - 2H + + 2e → is the H ₂ ↑. On the other hand, the anodic reaction with aluminum is represented by the following equation.

That is, Al → Al ³⁺ + 3e Al ³⁺ + 3OH ⁻ → Al (OH) ₃ The OH ⁻ ions thus produced at the cathode are combined with the aluminum ions (Al ³⁺ ) produced at the anode. As a result, foreign substances containing aluminum hydroxide (Al (OH) ₃ ) and the like are generated.

Therefore, when plasma treatment is performed using a mixed gas of oxygen gas and a gas containing hydrogen (H), the chlorine deposited on the surface of the conductor film can be satisfactorily removed together with the removal of the resist film. Therefore, the above corrosion can be suppressed. However, in this case, considering the removal efficiency of chlorine and the like, it is necessary to perform the treatment at a stage temperature of about 150 ° C. or higher, but the treatment of removing the resist film at a high stage temperature is performed. Then, a new problem arises that the side wall protective film formed on the side wall of the conductor film is hardened and becomes difficult to remove.

Therefore, in the present embodiment, after the plasma treatment using the gas containing oxygen is performed on the wafer in the relatively low temperature condition, mainly for the purpose of removing the resist film and the sidewall film (first Processing step), a plasma processing using a mixed gas of oxygen gas and hydrogen-containing gas is performed under a relatively high temperature condition mainly for removing chlorine (second processing step). Accordingly, the chlorine component adhering to the surface of the conductor film during the etching process of the conductor film can be satisfactorily removed before being exposed to the atmosphere or the cleaning liquid, so that the corrosion of the conductor film can be suppressed or prevented. In addition, since the chlorine component is removed after the sidewall film formed on the sidewall of the conductor film is removed during the etching process of the conductor film, the sidewall film cannot be removed after the resist film removal process. Can be avoided. Therefore, the yield and reliability of the semiconductor integrated circuit device can be improved.

Particularly, the first processing step and the second processing step are performed in different processing chambers. As a result, the first and second
Since the wafer processing temperature (stage temperature or wafer surface temperature) in the processing step can be set in a short time, the throughput can be significantly improved. Further, since the accuracy of setting the wafer processing temperature in the first and second processing steps can be improved, it is possible to perform processing as intended, and it is possible to improve the yield and reliability of the semiconductor integrated circuit device. .

Next, FIG. 5 shows an example of the semiconductor manufacturing apparatus 1 used in the manufacturing process of the semiconductor integrated circuit device of this embodiment.

The semiconductor manufacturing apparatus 1 has processing units 2 and 3. The processing unit 2 is a single-wafer processing unit that consistently performs the etching process of the conductor film and the removing process of the resist film used as a mask during the etching process.
Here, a processing unit 2 having a radial multi-chamber structure having a central transfer chamber 2a, a plurality of processing chambers 2b to 2d installed around the transfer chamber 2a, and a plurality of load lock chambers 2e is illustrated. Has been done.

In the transfer chamber 2a, a wafer 4 is loaded into each chamber by a transfer means such as a transfer arm,
It is a vacuum chamber in which the wafer 4 is unloaded from each chamber and moved to another desired place. The processing chambers 2b are vacuum processing chambers for performing an etching process on a conductor film using a resist film as an etching mask, and for example, two process chambers are installed. By providing two processing chambers 2b,
The etching processing ability can be improved. The processing chamber 2c is a vacuum processing chamber for performing the processing of the first processing step for removing the resist film and the like after the etching processing, and for example, one processing chamber is installed. The processing chamber 2d is a vacuum processing chamber for performing the processing of the second processing step for removing the chlorine component after the etching processing, and for example, two processing chambers are installed. The two processing chambers 2d are provided because the processing chamber 2d
This is because the processing time is longer than that in the processing chamber 2c, and the difference in the processing time is shortened or eliminated. These processing chambers 2
As the device structure of c and 2d, for example, a parallel plate type plasma ashing device, a barrel type ashing device, a microwave ashing device, an inductively coupled plasma ashing device or a helicon wave plasma ashing device can be used. The load lock chamber 2e is a vacuum chamber for loading and unloading the wafer 4 without exposing the processing chamber to the atmosphere. One wafer cassette that accommodates a plurality of wafers 4 is set in each load lock chamber 2e.

The processing unit 3 is a processing unit that consistently performs the cleaning process, the drying process, the baking process, and the like after the resist film removing process, and has process chambers 3a to 3c. The processing chamber 3a is a single-wafer processing cup for performing a cleaning process using an alkaline cleaning liquid or an acid cleaning liquid. The processing chamber 3b is a single-wafer processing cup for washing and drying processing for performing washing with water and drying after washing with water.
The processing chamber 3c is a single-wafer processing chamber for bake processing. The processing in the processing unit 3 is performed in the atmosphere.

Next, an example of a method of manufacturing the semiconductor integrated circuit device of this embodiment will be described with reference to FIGS. Here, a case will be described in which the technical idea of the present invention is applied to a method of manufacturing a semiconductor integrated circuit device having, for example, a CMIS (Complementary MIS) circuit.

FIG. 6 is a sectional view of the essential part of the wafer 4 during the manufacturing process of the semiconductor integrated circuit device, and FIG. 7 is an enlarged sectional view of the essential part of FIG. The semiconductor substrate (hereinafter, simply referred to as a substrate) 4S forming the wafer 4 is, for example, 1 to
P-type silicon (Si) having a specific resistance of about 10 Ωcm
The isolation portion 5 is made of a single crystal and is selectively formed on its main surface (device surface). Here, for example, LOC
Although the separation portion 5 formed of a silicon oxide (SiO ₂ or the like) film formed by an OS (Local Oxidization of Silicon) method or the like is illustrated, the groove-shaped separation portion (SGI (Shallo
w Groove Isolation) or STI (Shallow Trench I
solation)). In the case of the groove type separation portion, for example, a silicon oxide film is embedded in the groove formed in the main surface of the substrate 4S.

Further, the substrate 4S has a main surface from the main surface thereof.
A p-type well PWL and an n-type well NWL are selectively formed over a predetermined depth of S. p-type well PW
For example, boron is introduced into L, and phosphorus is introduced into the n-type well NWL. Then, nMISQn and pMISQp are formed in the active region surrounded by the isolation portion 5 in the regions of the p-type well PWL and the n-type well NWL.

The gate insulating film 6 of nMISQn and pMISQp is made of, for example, a silicon oxide film having a thickness of about 6 nm. The film thickness of the gate insulating film 6 referred to here is a film thickness equivalent to silicon dioxide, and may not match the actual film thickness. The gate insulating film 6 may be made of a silicon oxynitride film instead of the silicon oxide film. That is, the structure may be such that nitrogen is segregated at the interface between the gate insulating film 6 and the substrate 4S. The silicon oxynitride film is more effective than the silicon oxide film in suppressing the generation of interface states in the film and reducing electron traps.
The hot carrier resistance can be improved and the insulation resistance can be improved. Further, the silicon oxynitride film is less likely to be penetrated by impurities than the silicon oxide film. Therefore, the use of the silicon oxynitride film results in diffusion of impurities in the gate electrode material toward the substrate 4S side. It is possible to suppress variation in the value voltage. To form the silicon oxynitride film, for example, the substrate 4S may be heat-treated in a nitrogen-containing gas atmosphere such as NO, NO ₂ or NH ₃ .

The gate electrodes 7 of the nMISQn and the pMISQp are made of, for example, a low resistance polycrystalline silicon film, and a metal film such as a tungsten (W) film via a barrier metal film such as a tungsten nitride (WN) film. It is a so-called polymetal gate structure having a laminated structure of. However, the gate electrode structure is not limited to this, and may be, for example, a single film structure of a low-resistance polycrystalline silicon film, for example, a titanium silicide (TiSi _x ) film or a low-resistance polycrystalline silicon film. having a cobalt silicide (CoSi _x) film is laminated structure may be a so-called polycide structure. A side wall 8 made of, for example, a silicon oxide film is formed on the side surface of such a gate electrode 7. A cap film CP made of, for example, a silicon oxide film or a silicon nitride (Si ₃ N ₄ etc.) film is formed on the upper surface of the gate electrode 7. The channels of nMISQn and pMISQp are formed in the portion of the substrate 1S immediately below the gate electrode 7.

The semiconductor region 9 for the source and drain of the nMISQn has a so-called LDD (Lightly Dod) having an n ⁻ type semiconductor region 9a and an n ⁺ type semiconductor region 9b.
pedDrain) structure. n ^- type semiconductor region 9a
Is formed at a position adjacent to the channel. Further, the n ⁺ type semiconductor region 9b is the n ⁻ type semiconductor region 9a.
N ⁻ type semiconductor region 9 at a position separated from the channel by an amount
It is formed in a state of being electrically connected to a. For example, phosphorus (P) or arsenic (As) is introduced into both the n ⁻ type semiconductor region and the n ⁺ type semiconductor region, but the n ⁻ type has a lower impurity concentration than the n ⁺ type. Has been done. Below each of the n ⁻ type semiconductor regions 9a, p
A semiconductor region 10 of the mold is formed. The semiconductor region 10 is also called a punch-through stopper region or a halo region and is a region for suppressing or preventing the short channel effect, and is formed by introducing boron, for example.

On the other hand, the semiconductor region 11 for the source and drain of the pMISQp has a so-called LD having ap ⁻ type semiconductor region 11a and ap ⁺ type semiconductor region 11b.
It has a D structure. p ^- type semiconductor region 11a is formed at a position adjacent to the channel, p ⁺ -type semiconductor region 11b, the p ^- type semiconductor region ^- p a position away from type semiconductor region 11a amount corresponding channel It is formed in a state of being electrically connected to 11a. Boron, for example, is introduced into both the p ⁻ type semiconductor region 11a and the p ⁺ type semiconductor region 11b, but the p ⁻ type is p ⁺ type.
The impurity concentration is lower than that of the mold. Below each of the p ⁻ type semiconductor regions 11a, an n type semiconductor region 1 is formed.
2 is formed. The semiconductor region 12 is also called a punch-through stopper region or a halo region and is a region for suppressing or preventing the short channel effect, and is formed by introducing phosphorus or arsenic, for example.

On the main surface of such a substrate 1S, insulating films 15a and 15b are sequentially deposited from the bottom. The relatively thin insulating film 15a is made of, for example, a silicon nitride film or the like, and the relatively thick insulating film 15b is made of, for example, a silicon oxide film or the like. The insulating film 15a is the insulating films 15a and 15b.
When the contact hole CNT is bored in the hole, it functions as an etching stopper under the condition that the etching selection ratio between the silicon oxide film and the silicon nitride film becomes large. That is, at the time of forming the contact hole CNT, the insulating film 1 made of the silicon nitride film is first subjected to the etching treatment under the condition that the silicon oxide film is easily etched.
Etching is performed under the condition that the silicon nitride film is easily etched when 5a is exposed. This allows
It is possible to suppress or prevent the problem that the substrate 1S and the separation portion 5 are excessively etched.

The upper surface of the insulating film 15b is flattened. As a material for the insulating film 15b, B having a high reflow property is used.
A PSG (Boron-doped Phospho Silicate Glass) film or an SOG (Spin On Glass) film formed by a spin coating method may be adopted. This makes it possible to fill the narrow space between the gate electrodes 7, 7 adjacent to each other. A part of the main surface of the substrate 1S and a part of the gate electrode 7 are exposed from the bottom of the contact hole CNT. Then, a thin conductor film 16a is formed on the upper surface of the insulating film 15b and in the contact hole CNT (bottom surface and side surface), and the conductor film 1 is formed in the contact hole CNT.
A plug 16b is embedded via 6a.

The conductor film (second conductor film) 16a has a structure in which a refractory metal nitride film such as titanium nitride (TiN) is laminated on a refractory metal film such as titanium (Ti). The thickness is, for example, about 100 nm. As a material of the conductor film 16a, a refractory metal such as titanium tungsten (TiW) or a refractory metal silicide such as molybdenum silicide (MoSix) may be used. The plug 16b is made of a refractory metal film such as tungsten (W). The conductor film 16a has a barrier function for suppressing or blocking movement of various metal atoms and semiconductor atoms, a function for improving the adhesiveness between the plug 16b and the like and the insulating films 15a and 15b and the substrate 1S, and CVD for the plug 16b. (Chemical Vapor D
eposition) It has various functions such as a function as a base film at the time of film formation and a function of improving resistance to electromigration and stress migration. In such a configuration, after the conductor film 16a is deposited by the sputtering method, the conductor film for forming the plug 16b is deposited thereon by the CVD method, and the conductor film for forming the plug 16b is anisotropically dry-etched. It is formed by etching back by the method.

Conductor films 16c to 16f are sequentially deposited on the conductor films 16a and 16b from the lower layer by, for example, a sputtering method or the like. The thinnest conductor films (second conductor films) 16c and 16e are made of a refractory metal film such as titanium having a thickness of about 1 to 3 nm.
It has a function of improving the adhesiveness between a, 16b, 16f and the conductor film 16d. The thickest conductor film (first conductor film)
16d is, for example, a single film of aluminum (Al) having a thickness of about 500 nm, aluminum-silicon (Si)-
It is made of a conductor film containing aluminum as a main component, such as a copper (Cu) alloy film, an aluminum-silicon alloy film, or an aluminum-copper alloy film, and is a main conductor material for wiring. The second thinnest conductor film (second conductor film) 16f is made of, for example, a refractory metal nitride film having a thickness of about 100 nm such as titanium nitride, and has a function of improving resistance to electromigration and stress migration, and an exposure process. It has an antireflection function to reduce or prevent light scattering. As the material of the conductor film 16f, a refractory metal such as titanium tungsten (TiW) or a refractory metal silicide such as molybdenum silicide (MoSix) may be used.

On this conductor film 16f, a photoresist pattern (hereinafter, simply referred to as a resist pattern) 17a used as an etching mask at the time of forming a wiring is formed by a photolithography technique (that is, an exposure process, a development process, a bake process, etc.). A series of processes). Although the case where the resist pattern 17a is a negative type resist film is illustrated here, the present embodiment can be applied to the case where a positive type resist film is used. Further, in the present embodiment, when the resist pattern 17a is composed of a novolac-based resist material for exposure to visible light or ultraviolet rays (i-line having a wavelength of 365 nm, etc.) or excimer laser exposure (KrF having a wavelength of 248 nm, wavelength 193 nm). ArF,
Any of the cases where it is composed of a chemically amplified resist material for F _{2 having a} wavelength of 157 nm) can be applied. The thickness of the resist pattern 17a varies depending on the thickness of the conductor film to be processed, etc., and therefore cannot be generally stated, but is 1.3 μm, for example.
It is about 1.5 μm.

In the present embodiment, a plurality of wafers 4 having such a structure are loaded in the wafer cassette into the load lock chamber 2e of the semiconductor manufacturing apparatus 1 shown in FIG. In the semiconductor manufacturing apparatus 1, wafers 4 are taken out one by one from the wafer cassette in the load lock chamber 2e by the transfer arm in the transfer chamber 2a maintained in a vacuum state and loaded into the processing chamber 2b for etching processing. In the processing chamber 2b for etching processing, for example, BCl
Anisotropic dry etching using chlorine-based gas such as ₃ , Cl ₂ or SiCl ₄ (eg RIE; Re
Conductive Ion Etching) is applied to the wafer 4 to expose the conductor film 1 from the resist pattern 17a.
6a, 16c to 16f are removed by etching. In this etching process, the conductor films 16a, 16c to 16f
(And a sidewall protection film is formed on the sidewall of the resist pattern 17a). Here, mainly the resist pattern 17
The etching products of a are conductor films 16a, 16c to 16f.
Is polymerized and adsorbed on the processed side wall to form a side wall protective film.
Accordingly, during the etching process, the conductor film 16
Since the processed sidewalls of a and 16c to 16f can be protected from neutral etching species and slight ion bombardment, undercut can be suppressed or prevented, and vertical etching can be achieved. , Conductor film 1
It is possible to improve the processing accuracy of 6a, 16c to 16f.

FIG. 8 is a cross-sectional view of the essential part of the wafer 4 after the above etching treatment, and FIG. 9 is the conductor films 16a, 16c to 16 of FIG.
Each of the enlarged sectional views of the main part of f is shown. By the above etching process, the first layer wiring L1 formed of the conductor films 16a and 16c to 16f is formed. At this stage,
As shown in FIG. 9, the side wall protective film (side wall film) 18 is formed on the side walls of the conductor films 16a, 16c to 16f and the resist pattern 17a. The sidewall protection film 18 causes abnormal growth in the subsequent insulating film forming process, and halogen such as chlorine remaining in the sidewall protection film 18 causes corrosion of the conductor film 16d mainly composed of aluminum or the like. It causes the deterioration of the reliability and the yield of the semiconductor integrated circuit device, such as the occurrence of a short circuit failure due to its conductivity including aluminum, and it is preferably removed after the etching process. Further, at this stage, a large amount of chlorine (Cl) contributing to etching adheres to the surfaces of the sidewall protection film 18, the insulating film 15b and the resist pattern 17a.

Next, in the semiconductor manufacturing apparatus 1 shown in FIG. 5, the wafer 4 is taken out from the processing chamber 2b for etching processing by the transfer arm in the transfer chamber 2a maintained in the vacuum state, and the wafer 4 is processed. Bring to. In the processing chamber 2c, for example, a plasma ashing process using a mixed gas of oxygen gas (O ₂ ) and a gas containing fluorine is performed on one wafer 4 to form the resist pattern 1
7a and the sidewall protection film 18 are removed by ashing (first
Processing step). The mechanism for removing the resist film in this case will be described later.

In the present embodiment, the temperature of the main surface of the wafer 4 is set to be lower than the temperature of the main surface of the wafer 4 during the subsequent plasma processing for removing chlorine, during the processing in the processing chamber 2c. Specifically, the temperature of the main surface of the wafer 4 is higher than, for example, normal temperature (about 20 ° C.) and is 120 ° C. or lower, 100 ° C. or lower, 80 ° C. or lower, or around 80 ° C. When the temperature of the main surface of the wafer 4 is set to 120 ° C. or higher, the resist pattern 17a and the sidewall protection film 18 are hardened and it becomes difficult to remove them. Further, if the temperature is raised too much, the conductor film 16f may be removed by the attack of atoms in the gas containing fluorine. The temperature of the main surface of the wafer 4 is set by the temperature of the stage on which the wafer 4 is mounted and the heat supplied from the plasma. Generally, the stage temperature of about −5 ° C. to −10 ° C. The temperature of the main surface of the.

Examples of the above-mentioned fluorine-containing gas include CF ₄ , CHF ₃ , C ₂ F ₆ , C ₃ F ₈ , C ₄ F ₈ or S.
There is F ₆ . When this gas containing fluorine is introduced, the fluorine atom draws hydrogen (H) from the resist film, thereby destabilizing the skeleton of the polymer and making it highly reactive. The fluorine atom serves to lower the activation energy of the reaction between the oxygen atom and the resist film. Fluorine also increases the proportion of atomic oxygen in the oxygen plasma.
By these, the resist pattern 17a and the sidewall protection film 1
Since the ashing rate of 8 etc. can be improved, the processing efficiency can be improved. Therefore, the throughput can be improved, and the productivity of the semiconductor integrated circuit device can be improved. Further, since the introduction of fluorine atoms can reduce sodium (Na) contamination, the yield and reliability of the semiconductor integrated circuit device can be improved. further,
By using the gas containing fluorine, the upper surface of the insulating film 15b is also slightly removed, so that foreign matters such as organic polymer residues on the insulating film 15b can also be removed.

Further, the processing time in the processing chamber 2c cannot be generally stated because it varies depending on the film thickness of the resist pattern 17a and the like, but is, for example, about 30 seconds.

FIG. 10 is an enlarged sectional view of an essential part of the first layer wiring L1 after the removal processing (first processing step) of the resist pattern 17a and the sidewall protection film 18 in the processing chamber 2c. The resist pattern and the sidewall protection film have been removed. At this stage, chlorine components are attached to the surfaces of the wiring L1 and the insulating film 15b.

Next, in the semiconductor manufacturing apparatus 1 shown in FIG. 5, the wafer 4 which has been processed in the processing chamber 2c is taken out from the processing chamber 2c by the transfer arm in the transfer chamber 2a maintained in a vacuum state. Carry on to 2d. Processing room 2d
Then, for example, by subjecting one wafer 4 to plasma ashing treatment using a mixed gas of oxygen gas (O ₂ ) and H ⁺ or OH ⁻ or a gas generated by dissociation of both of them, chlorine components are removed. Remove (second processing step).
The chlorine component removing mechanism in this case will be described later.

In the present embodiment, this processing chamber 2d
In order to efficiently remove the chlorine component during the process (1), the temperature of the main surface of the wafer 4 is set higher than the temperature of the main surface of the wafer 4 in the first processing step. Specifically, the temperature of the main surface of the wafer 4 is set to, for example, about 150 ° C. to 350 ° C.
The temperature is preferably about 180 ° C to 250 ° C, for example about 200 ° C. The above-mentioned 350 ° C. is the processing chamber 2d of this embodiment.
Is the maximum temperature that can be supplied. The temperature of the main surface of the wafer 4 in this case is also set by the temperature of the stage on which the wafer 4 is placed and the heat supplied from the plasma, and is generally set to about -5 ° C to -10 ° C of the stage temperature. It By increasing the temperature of the main surface of the wafer 4 in this way, chlorine components on the surface of the wafer 4 can be efficiently removed, so that the throughput can be improved and the productivity of the semiconductor integrated circuit device can be improved. Is possible.

Further, temporarily, in one processing chamber, the above first and second
If the processing of the processing steps is performed, the stage temperature must be changed for each step, and therefore continuous processing takes time. Since the wafers 4 are processed one by one, it takes a huge amount of time to process a plurality of wafers 4,
The productivity (mass productivity) of the semiconductor integrated circuit device is significantly reduced. On the other hand, in the present embodiment, the processing chamber 2
Since c and 2d are divided, the time for setting the temperature of the main surface of the wafer 4 during each processing can be shortened, so that the throughput can be greatly improved and the productivity (mass productivity) of the semiconductor integrated circuit device can be improved. It is possible to improve.

In addition, it is assumed that one processing chamber has the above first and second processing chambers.
When the processing of the processing step is performed, the stage temperature has to be changed for each step, so that the main surface temperature of the wafer 4 at each step changes for each wafer 4 to be processed (the variation becomes large). The processing result may differ for each case. On the other hand, in the present embodiment, since the processing chambers 2c and 2d are separated, it is possible to improve the accuracy of setting the temperature of the main surface of the wafer 4 during each processing, so that the intended processing can be performed. As a result, the reproducibility of processing can be improved, and as a result, the yield and reliability of the semiconductor integrated circuit device can be improved.

As the gas generated by dissociating the above H ⁺ or OH ⁻ or both, for example, hydrogen gas (H ₂ ), steam (H ₂ O), methanol (CH ₃ O)
H), ethanol (C ₂ H ₅ OH), propanol (C _{3
H 7 OH, IPA; Isopropylalcohol)} , there is a butanol (C ₄ H ₉ OH) or acetone (CH ₃ COCH) and the like. In the present embodiment, for example, methanol (CH ₃ O
Although H) gas was used, steam (H ₂ O) is preferable in terms of safety, easy handling, and environmental aspects. Further, propanol is also used in the manufacturing process (for example, the steam drying process) of the semiconductor integrated circuit device and is easy to handle because it is used well. By introducing such a gas, residual chlorine components are removed by H ⁺ and OH ⁻ generated by dissociation. The processing in the processing chamber 2d also has the ability to remove the residual resist pattern, the residual sidewall protective film, or the residual organic polymer film on the surface of the insulating film 15b. Therefore, the residual resist pattern on the surface of the wafer 4, the residual sidewall protective film, or the residual organic polymer film on the surface of the insulating film 15b may be removed in the processing chamber 2.

Although the processing time in the processing chamber 2d is regulated by the stage temperature in the processing chamber 2d, it cannot be said unconditionally.
Considering good removal of the chlorine component, the processing time is longer than the processing time in the processing chamber 2c for the purpose of removing the resist pattern and the sidewall protection film, and is, for example, about 90 seconds to 120 seconds. As described above, in the present embodiment, since the processing time in the processing chamber 2d is longer than the processing time in the processing chamber 2c, the number of processing chambers 2d is set larger than that in the processing chambers 2c. For example, the processing chamber 2c has one
Two d are provided. As a result, the processing time difference between the processing chambers 2c and 2d can be shortened or eliminated, so that the processing from the processing chamber 2c to the processing chamber 2d can proceed smoothly and the overall processing efficiency can be improved. Is possible. Therefore, it is possible to maintain or improve the productivity (mass productivity) of the semiconductor integrated circuit device.

FIG. 11 is an enlarged cross-sectional view of an essential part of the first layer wiring L1 after the chlorine component removal treatment (second treatment step; anticorrosion treatment) in the treatment chamber 2d. The chlorine (Cl) component on the surfaces of the wafer 4 and the first layer wiring L1 is significantly reduced. Therefore, the first layer wiring L1 is corroded.
Can be suppressed or prevented. Further, since the side wall protective film 18 has already been removed, there is no problem that the side wall protective film 18 and the like are hardened even if the main surface of the wafer 4 is heated to a high temperature.

Next, in the semiconductor manufacturing apparatus 1 shown in FIG. 5, the wafer 4 which has been processed in the processing chamber 2d is taken out from the processing chamber 2c by the transfer arm in the transfer chamber 2a which is maintained in a vacuum state. Load lock chamber 2 for wafer 4
It is accommodated in the wafer cassette of e. Load lock chamber 2e
The wafer cassette of 1 is taken out into the atmosphere and transferred from the processing section 2 to the adjacent processing section 3. In this processing unit 3, the wafer 4 is
Wash one by one. First, the wafer 4 is loaded into the processing chamber 3a, and the surface of the wafer 4 is cleaned with, for example, an alkaline cleaning liquid (Mitsubishi Gas Chemical (ELMC20, etc.). In the case of using an acidic cleaning liquid instead of the alkaline cleaning liquid, Then, the wafer 4 is transferred to the processing chamber 3b, and the surface of the wafer 4 is cleaned with, for example, pure water.The cleaning effect can be improved by using ultrasonic cleaning during the cleaning process. After that, the wafer 4 is subjected to, for example, a spin drying process in the processing chamber 3b, and the wafer 4 after the drying process is transferred to the processing chamber 3c and subjected to a baking process.

FIG. 12 is a sectional view of the essential part of the wafer 4 after the above wet cleaning treatment, and FIG. 13 is an enlarged sectional view of the essential part of FIG. At this stage, chlorine components on the surfaces of the first-layer wiring L1 and the insulating film 15b are removed.

FIG. 14 is a cross-sectional view of essential parts of the wafer 4 during the manufacturing process of the semiconductor integrated circuit device, which is subsequent to FIGS. 12 and 13. Here, the second layer wiring L2 and the third layer wiring L3 formed by the same etching process as the first layer wiring L1 and the subsequent processes (including the first and second processing steps) are formed. There is. Therefore, the wiring corrosion can be suppressed or prevented also in the second and third layer wirings L2 and L3. The problem of the side wall protective film can be avoided. The etching process and the subsequent processes can be efficiently advanced. The conductor film 16a of the second and third layer wirings L2 and L3 is formed of, for example, a single film of titanium nitride. The conductor film 16d of the second-layer wiring L2 is thicker than the conductor film 16d of the first-layer wiring L1, and the conductor film 16d of the third-layer wiring L3 is thicker than the conductor film 16d of the second-layer wiring L2. It is formed thicker than. The other configurations of the second and third layer wirings L2 and L3 are the same as those of the first layer wiring L1.

Insulating films 15c, 15e between the wiring layers,
15 f, 15 h, and 15 i are, for example, TEOS (Tetraeth
It is composed of a silicon oxide film deposited by a plasma CVD method using oxysilane) gas. The insulating films 15d and 15g between the adjacent wirings are made of, for example, a silicon oxide film formed by the CVD method, and are formed for flattening. The insulating film 15j forming the surface protective film is made of, for example, a silicon nitride film, and the insulating film 15k forming the surface protective film thereon is made of, for example, a polyimide resin.

The second layer wiring L2 is made of insulating films 15c and 15e.
Is electrically connected to the first-layer wiring L1 through the conductor film 16a and the plug 16b in the through hole TH formed in. The third layer wiring L3 is electrically connected to the second layer wiring L2 through the conductor film 16a and the plug 16b in the through holes TH formed in the insulating films 15f and 15h. An opening 19 is formed in a part of the insulating films 15k and 15j so that a part of the third layer wiring L3 is exposed. A part of the third-layer wiring L3 exposed from the opening 19 forms a bonding pad (external terminal) portion BP. The conductor film 16f is removed from the upper surface of the bonding pad portion BP of the third layer wiring L3, and the conductor film 16d of the third layer wiring L3 is exposed from the opening 19.

Next, FIGS. 15 and 16 show models of resist film removal and chlorine component removal (anticorrosion treatment). Note that in FIGS. 15 and 16, the first,
The action in the second processing step is also shown.

[0066] Figure 15 as the process gas in the first treatment step, for example using a mixed gas of oxygen (O ₂₎ gas and CF _4, as the process gas in the second process step, for example, oxygen gas (O ₂ ) And a mixed gas of methanol (CH ₃ OH) gas are used.

First, in the first treatment step, an oxygen radical (O ^* ) generated by dissociation of oxygen gas (O ₂ ) and a fluorine radical (F ^* ) generated by dissociation of CF ₄ are generated. Attack on the resist film, CO _x , H ₂ O and HF are generated, and the resist pattern 17a and the sidewall protection film 18 are removed. This is represented by a chemical formula, for example, as follows.

O ₂ → 2O ^* CF ₄ → CF _x ^* + (4-X) F ^* C, H, O (resist) + O ^* + F ^* → CO _x + H ₂ O
↑ + HF ↑ In the subsequent second treatment step, H ⁺ generated by dissociation of methanol (CH ₃ OH) and residual chlorine component (C
l ^-) and hydrochloric acid by reacting (HCl) is generated. Hydrochloric acid (HCl) produced in vacuum is immediately volatilized.
Thereby, the chlorine component is removed. This is represented by a chemical formula, for example, as follows.

[0069] ^{_{CH 3 OH → CH x * +}} (3-X) H + + OH - CH x * + (3-X) H + + Cl - → CH x Cl y ↑ + H
Cl ↑ Next, FIG. 16 shows the processing gas of the first processing step
For example, oxygen gas (O ₂ ) is used, and as the processing gas in the second processing step, for example, oxygen gas (O ₂ ) and water vapor (H _2
The case where a mixed gas with ₂ O) gas is used is shown.

First, in the first treatment step, oxygen radicals (O ^* ) generated by the dissociation of oxygen gas (O ₂ ) attack the resist film to produce CO _x.
And H ₂ O are generated, and the resist pattern 17a and the sidewall protection film 18 are removed. This is represented by a chemical formula, for example, as follows.

O ₂ → 2O ^* C, H, O (resist) + O ^* → CO _x + H ₂ O ↑ In the subsequent second processing step, H ⁺ generated by dissociation of water vapor (H ₂ O) The residual chlorine component (Cl ⁻ ) reacts with each other to generate hydrochloric acid (HCl). This hydrochloric acid is immediately volatilized in the same manner as above, and the chlorine component can be removed. This is represented by a chemical formula, for example, as follows.

[0072] ^{_{H 2 O → H + + OH}} - H + + Cl - → HCl ↑ above, the invention made by the inventors has been concretely described based on the embodiments, the present invention is limited to these embodiments It goes without saying that various modifications can be made without departing from the scope of the invention.

For example, although the case where the radial type multi-chamber apparatus is used has been described in the above-mentioned embodiment, the present invention is not limited to this, and for example, a linear type chamber in which a central transfer chamber and processing chambers on both sides of the transfer chamber are arranged. A multi-chamber device may be used.

Further, in the above-mentioned embodiment, the ashing technique of the resist pattern used at the time of patterning the conductor film having the laminated structure has been described, but the conductor film is formed of a single conductor film containing aluminum as a main component. The present invention can also be applied in such cases.

In the above description, the invention made by the present inventor is the field of application which is the background of the invention.
The case where the method is applied to the method for manufacturing a semiconductor integrated circuit device having an S circuit has been described, but the present invention is not limited to this, and for example, a DRAM (Dynamic Random Access Memor) is used.
y), SRAM (Static Random Access Memory) or flash memory (EEPROM; Electric Erasable)
Method for manufacturing a semiconductor integrated circuit device having a memory circuit such as Programmable Read Only Memory), a method for manufacturing a semiconductor integrated circuit device having a logic circuit such as a microprocessor, or the memory circuit and the logic circuit on the same substrate It can also be applied to the manufacturing method of the embedded semiconductor integrated circuit device. It can also be applied to a method for manufacturing a flat panel display or a micromachine. INDUSTRIAL APPLICABILITY The present invention can be applied to a technique including a step of patterning a conductor film containing aluminum as a main component using a resist film as an etching mask and then ashing and removing the resist film used as the etching mask.

[0076]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

That is, with the main purpose of removing the resist film and the side wall film, after performing a plasma treatment using a gas containing oxygen under a relatively low temperature condition, the main purpose is to remove chlorine. The reliability of the semiconductor integrated circuit device can be improved by including a step of performing plasma treatment using a mixed gas of oxygen gas and a gas containing hydrogen under high temperature conditions.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a corrosion generation model of a wiring containing aluminum as a main component.

FIG. 2 is an explanatory diagram of a defect caused by corrosion of a wiring containing aluminum as a main component.

FIG. 3 is an explanatory diagram of a model of corrosion generation of wiring due to a battery action.

FIG. 4 is an explanatory diagram of a corrosion generation model of wiring due to a battery action.

FIG. 5 is an explanatory diagram of an example of a semiconductor manufacturing apparatus used in a manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 6 is a fragmentary cross-sectional view of a wafer during a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 7 is an enlarged cross-sectional view of the main parts of FIG.

FIG. 8 is a cross-sectional view of the essential part of the wafer during the manufacturing process of the semiconductor integrated circuit device, following FIGS. 6 and 7;

9 is an enlarged cross-sectional view of the main parts of FIG.

FIG. 10 is an enlarged cross-sectional view of an essential part of a wiring on a wafer during the manufacturing process of the semiconductor integrated circuit device, following FIGS. 8 and 9;

FIG. 11 is an enlarged cross-sectional view of an essential part of a wiring on a wafer during the manufacturing process of the semiconductor integrated circuit device, following FIG. 10;

12 is a fragmentary cross-sectional view of the wafer during the manufacturing process of the semiconductor integrated circuit device, following FIG. 11;

13 is an enlarged cross-sectional view of a main part of FIG.

FIG. 14 is a fragmentary cross-sectional view of the wafer during the manufacturing process of the semiconductor integrated circuit device, following FIGS. 12 and 13;

FIG. 15 is an explanatory diagram of a model of resist film removal and chlorine component removal by plasma ashing treatment using a gas generated by dissociation of H ⁺ or OH ⁻ or both.

FIG. 16 is an explanatory diagram of a model of resist film removal and chlorine component removal by plasma ashing treatment using a gas generated by dissociation of H ^+, OH ^−, or both.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor manufacturing apparatus 2 Processing part 2a Transfer chamber 2b Processing chamber 2c Processing chamber 2d Processing chamber 2e Load lock chamber 3 Processing parts 3a to 3c Processing chamber 4 Wafer 4S Semiconductor substrate 5 Separation part 6 Gate insulating film 7 Gate electrode 8 Sidewall 9 Semiconductor region 9a Semiconductor region 9b Semiconductor region 10 Semiconductor region 11 Semiconductor region 11a Semiconductor region 11b Semiconductor region 12 Semiconductor regions 15a to 15k Insulating films 16a, 16c, 16e, 16f Conductor film (second conductor film) 16b Plug 16d Conductor film (first) 1 conductor film 17a Photoresist pattern 18 Side wall protective film (side wall film) 19 Opening 50 Insulating film 51 Wiring 52 Foreign matter 53 Hydrochloric acid aqueous solution PWL p-type well NWL n-type well Qp p-channel type MIS • FET Qn n-channel type MIS • FET CP Cap film CNT Contact hole L The first layer wiring L2 second layer wiring L3 third layer wiring BP bonding pad portion

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Nobuhito Yamaguchi             Hitachi, 145 Nakajima, Nanae-cho, Kameda-gun, Hokkaido             Inside North Sea Semiconductor Co., Ltd. F term (reference) 5F004 AA14 BA04 BB18 BC06 BD01                       CA04 DA01 DA02 DA03 DA04                       DA11 DA13 DA16 DA18 DA24                       DA26 DB09 DB26 EB02                 5F033 HH08 HH09 HH18 HH23 HH29                       HH33 JJ18 JJ19 JJ23 JJ29                       JJ33 KK08 KK09 KK18 KK23                       KK29 KK33 MM08 NN06 NN07                       PP06 PP15 QQ03 QQ08 QQ09                       QQ11 QQ12 QQ13 QQ15 QQ16                       QQ25 QQ31 QQ37 QQ93 QQ98                       RR04 RR06 RR09 RR15 RR22                       SS11 SS15 TT02 TT04 WW03                       XX05 XX06 XX18

Claims (31)

[Claims] 1. A method for manufacturing a semiconductor integrated circuit device comprising the following steps: (a) a step of depositing a conductor film containing aluminum as a main component on a wafer, and (b) the conductor film. Forming a photoresist pattern on the substrate, (c) etching away the conductor film exposed from the photoresist pattern by an etching method using a gas containing chlorine,
(D) With respect to the wafer after the etching treatment, the main purpose is to remove the side wall film and the photoresist pattern formed on the side wall of the conductor film, with the temperature of the main surface of the wafer being the first temperature. As the first processing step of performing a plasma processing using a gas containing oxygen, and (e) the second surface of the wafer after the step (d), in which the temperature of the main surface of the wafer is higher than the first temperature. A second processing step of performing plasma processing using a mixed gas of oxygen gas and hydrogen-containing gas mainly for the purpose of removing chlorine adhering to the main surface of the wafer and the surface of the conductor film at a temperature. 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first processing step and the second processing step have separate processing chambers. Method. 3. The method for manufacturing a semiconductor integrated circuit device according to claim 2, wherein the number of processing chambers in the second processing step is larger than the number of processing chambers in the first processing step. Manufacturing method of semiconductor integrated circuit device. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first temperature is 120 ° C. or lower. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first temperature is 100 ° C. or lower. 6. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first temperature is 80 ° C. or lower. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the second temperature is 150 ° C. to 350 ° C. or lower. 8. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the second temperature is 180 ° C. to 250 ° C. or lower. 9. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the second temperature is 200 ° C. 10. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first temperature is 120 ° C. or lower and the second temperature is 150 ° C. to 350 ° C. Device manufacturing method. 11. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein a gas containing fluorine is added to the gas containing oxygen in the first processing step. 12. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the gas containing hydrogen in the second processing step is methanol gas. 13. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the gas containing hydrogen in the second processing step is propanol gas. 14. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the gas containing hydrogen in the second processing step is water vapor. 15. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the conductor film is an aluminum film,
A method of manufacturing a semiconductor integrated circuit device, comprising an alloy film containing one or both of silicon and copper. 16. A method of manufacturing a semiconductor integrated circuit device comprising the following steps: (a) A first conductor film containing aluminum as a main component and a different type of the first conductor film from each other on a wafer. Depositing a conductor film having a laminated structure of a second conductor film, (b) forming a photoresist pattern on the conductor film having the laminated structure, and (c) forming the laminated structure exposed from the photoresist pattern. A step of etching the conductive film having an etching method using a gas containing chlorine,
(D) With respect to the wafer after the etching process, the sidewall film formed on the sidewall of the conductor film having the laminated structure and the photoresist pattern are formed with the temperature of the main surface of the wafer set to the first temperature. A first treatment step in which a plasma treatment using a gas containing oxygen is performed mainly for removal.
(E) With respect to the wafer after the step (d), a conductor film having a main surface of the wafer and a laminated structure with the temperature of the main surface of the wafer set to a second temperature higher than the first temperature. Second treatment step of performing plasma treatment using a mixed gas of oxygen gas and hydrogen-containing gas, mainly for removing chlorine attached to the surface of the. 17. The method for manufacturing a semiconductor integrated circuit device according to claim 16, wherein the first processing step and the second processing step have separate processing chambers. Method. 18. The method of manufacturing a semiconductor integrated circuit device according to claim 17, wherein the number of processing chambers in the second processing step is larger than the number of processing chambers in the first processing step. Manufacturing method of semiconductor integrated circuit device. 19. The method of manufacturing a semiconductor integrated circuit device according to claim 16, wherein the first temperature is 120 ° C. or lower. 20. The method of manufacturing a semiconductor integrated circuit device according to claim 16, wherein the first temperature is 100 ° C. or lower. 21. The method of manufacturing a semiconductor integrated circuit device according to claim 16, wherein the first temperature is 80 ° C. or lower. 22. The method of manufacturing a semiconductor integrated circuit device according to claim 16, wherein the second temperature is 150 ° C. to 350 ° C.
A method of manufacturing a semiconductor integrated circuit device, wherein the temperature is equal to or lower than ° C. 23. The method of manufacturing a semiconductor integrated circuit device according to claim 16, wherein the second temperature is 180 ° C. to 250 ° C.
A method of manufacturing a semiconductor integrated circuit device, wherein the temperature is equal to or lower than ° C. 24. The method of manufacturing a semiconductor integrated circuit device according to claim 16, wherein the second temperature is 200 ° C. 25. The method for manufacturing a semiconductor integrated circuit device according to claim 16, wherein the first temperature is 120 ° C. or lower and the second temperature is 150 ° C. to 350 ° C. Device manufacturing method. 26. The method of manufacturing a semiconductor integrated circuit device according to claim 16, wherein a gas containing fluorine is added to the gas containing oxygen in the first processing step. 27. The method of manufacturing a semiconductor integrated circuit device according to claim 16, wherein the gas containing hydrogen in the second processing step is methanol gas. 28. The method of manufacturing a semiconductor integrated circuit device according to claim 16, wherein the gas containing hydrogen in the second processing step is a propanol gas. 29. The method of manufacturing a semiconductor integrated circuit device according to claim 16, wherein the gas containing hydrogen in the second processing step is water vapor. 30. The method of manufacturing a semiconductor integrated circuit device according to claim 16, wherein the first conductor film is an alloy film in which one or both of silicon and copper are added to an aluminum film. Manufacturing method of integrated circuit device. 31. The method of manufacturing a semiconductor integrated circuit device according to claim 16, wherein the second conductor film is a refractory metal film,
A method of manufacturing a semiconductor integrated circuit device, comprising a high melting point nitride film or a high melting point metal silicide film.