JP2003031680A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve electrical characteristics of a field effect transistor. SOLUTION: The method for manufacturing a semiconductor device comprises the steps of forming a gate insulating film 3 and a gate electrode 4a on a semiconductor substrate 1S, and then implanting an impurity to form a channel region 6 of the field effect transistor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technique, and more particularly to a technique effectively applied to a semiconductor device manufacturing technique having a field effect transistor.

[0002]

2. Description of the Related Art In the method of forming a field effect transistor studied by the present inventors, a gate insulating film and a gate electrode are sequentially formed after introducing impurity ions for forming a well and a channel into a semiconductor substrate, and a source is further formed. And a semiconductor region for drain is formed on the semiconductor substrate.

Incidentally, for example, Japanese Patent Laid-Open No. 7-254645 discloses a CMOS (Complementary Metal Oxide Semicon).
In a manufacturing process of a ductor, after forming a field insulating film and a gate electrode, a predetermined impurity is ion-implanted into a semiconductor substrate with energy that passes through the n-channel type MIS • FET (Metal InsulatorSemic).
A technique for forming a p-well in an on-ductor field effect transistor forming region and an n-well in a p-channel type MIS • FET forming region is disclosed.

[0004]

However, the inventors of the present invention have found that the field effect transistor formation technique studied by the above inventors has the following problems.

That is, first, it is necessary to separately form a photoresist mask pattern in the process of implanting impurity ions for forming a well and a channel. In particular, in the process of manufacturing a semiconductor device having a CMIS circuit, it is necessary to implant impurities for forming wells and channels for each of n-channel type and p-channel type field effect transistor forming regions. Will increase. Therefore, there is a problem that the number of manufacturing steps of the semiconductor device and the manufacturing cost increase.

Second, due to the heat treatment after the impurity ion implantation process for forming the well and channel, redistribution occurs in the impurity profile of the well and channel, and it is difficult to form a desired impurity profile.
In particular, in a p-channel field effect transistor in a semiconductor device having a CMIS circuit, an n-type gate electrode is used. However, with the miniaturization of the gate length, a short channel caused by the redistribution of the above-mentioned impurity profile and the like. There is a problem in that the effect problem becomes apparent and desired electrical characteristics cannot be obtained. Therefore, in order to suppress or prevent the short channel effect, a so-called dual gate electrode structure is used in which the gate electrode of an n-channel field effect transistor is n-type and the gate electrode of a p-channel field-effect transistor is p-type. May have been adopted. However, in this technique, the conductivity type of the gate electrode has to be different for the n-channel field effect transistor and the p-channel field effect transistor, and therefore the photoresist mask pattern forming step and the impurity introducing step for that purpose are performed. As a result, the number of semiconductor device manufacturing steps and the manufacturing cost increase.

An object of the present invention is to provide a technique capable of improving the electric characteristics of a field effect transistor.

Another object of the present invention is to provide a technique capable of reducing the cost of a semiconductor device.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the present invention comprises a step of forming a gate electrode on a gate insulating film and then introducing an impurity for forming a channel into a semiconductor substrate below the gate electrode.

Further, according to the present invention, the well forming impurities are introduced into the semiconductor substrate using the masking layer used as a mask in the impurity introducing step for forming the channel as a mask.

Further, according to the present invention, a semiconductor region for a source and a drain of a field effect transistor is formed on a semiconductor substrate by using a masking layer used as a mask in an impurity introducing step for forming the channel as a mask. It introduces impurities.

[0014]

DETAILED DESCRIPTION OF THE INVENTION Before describing the present invention in detail,
The meanings of the terms in the present application are as follows.

1. In the present application, the term “semiconductor device” means not only a device formed on a single crystal silicon substrate but also an SOI device unless otherwise specified.
(Silicon On Insulator) substrate and TFT (Thin Film Trans
istor) shall include those made on other substrates such as substrates for liquid crystal manufacturing.

2. Wafers are thin plates of silicon or other semiconductor single crystals (also called semiconductor wafers, generally in the shape of a disk), sapphire substrates, glass substrates, other insulating, anti-insulating or semiconductor substrates, etc. used in the manufacture of semiconductor integrated circuits. We refer to those composite substrates.

3. A semiconductor integrated circuit chip or a semiconductor chip (hereinafter, simply referred to as a chip) refers to a wafer in which a wafer process (wafer process or previous process) is completed is divided into unit circuit groups.

4. A surface channel refers to a structure in which a channel current flows on the surface of a semiconductor substrate when a gate voltage is applied to a transistor under circuit operating conditions. n
In the channel type MIS • FET, the polysilicon of the gate electrode has the n type polarity and the p channel type MIS
In the FET, the Fermi level of the Si substrate is adjusted by making the polysilicon of the gate electrode have the p-type polarity, and the channel region is formed at the interface between the gate oxide film and the Si substrate.

5. A buried channel refers to a structure in which a channel current flows on the surface of a semiconductor substrate and inside deeper than that when a gate voltage is applied to a transistor under circuit operating conditions. For example, p-channel type M
By making the gate electrode of the IS-FET n-type, a channel region is formed near the np junction inside the Si substrate.

In the following embodiments, when there is a need for convenience, they will be described by dividing them into a plurality of sections or embodiments, but unless otherwise specified, they are not unrelated to each other, One is in the relation of some or all of modifications of the other, details, supplementary explanations, and the like.

Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.) of elements, it is clearly limited to a specific number when explicitly stated and in principle. The number is not limited to the specific number except the case, and may be a specific number or more or less.

Further, in the following embodiments, the constituent elements (including element steps, etc.) are not always essential unless otherwise specified or in principle considered to be essential in principle. Needless to say

Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the constituent elements, etc., except when explicitly indicated or when it is considered that the principle is not clear, it is substantially the same. In addition, the shape and the like are included or similar. This also applies to the above numerical values and ranges.

Further, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

In the drawings used in the present embodiment, hatching may be used even in a plan view so as to make the drawings easy to see.

Further, in this embodiment, a MIS • FET (Metal Insula) representing a field effect transistor is used.
tor Semiconductor Field Effect Transistor) MI
Abbreviated as S, p-channel type MIS • FET is abbreviated as pMIS, and n-channel type MIS • FET is abbreviated as nMIS.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1) First, a basic example of a method of manufacturing a semiconductor device according to the present embodiment will be described with reference to FIGS.

FIG. 1 is a sectional view of the essential part of a wafer during the manufacturing process of the semiconductor device. A semiconductor substrate (hereinafter, simply referred to as a substrate) 1S forming the wafer 1 is made of a flat circular thin plate made of, for example, p-type single crystal silicon, and has a groove-shaped separation portion on its main surface (device formation surface). (STI: Shallow Trench Isolation) 2 is formed. The groove-shaped separating portion 2 is formed by embedding, for example, a silicon oxide film in the groove formed on the main surface of the substrate 1S. A region of the substrate 1S surrounded by the isolation portion 2 is an active region (or device formation region). In the present embodiment, a case will be described in which a pMIS is formed in the active region. The separation part 2 is not limited to SGI, but can be variously modified, and may have a structure formed by, for example, a selective oxidation (LOCOS; Local Oxidation of Silicon) method.

A gate insulating film 3 made of, for example, silicon oxide (SiO _x ) is formed on the main surface of the substrate 1S by a thermal oxidation method or the like. The gate insulating film 3 may be made of silicon oxynitride (SiON) instead of silicon oxide. That is, the structure may be such that nitrogen is segregated at the interface between the gate insulating film 3 and the substrate 1S. Since the silicon oxynitride film has a higher effect of suppressing the generation of interface states in the film and reducing electron traps than the silicon oxide film, the hot carrier resistance of the gate insulating film 3 can be improved, and the insulating property can be improved. The resistance can be improved.

Further, the gate insulating film 3 may be formed of, for example, a silicon nitride film or a composite insulating film of a silicon oxide film and a silicon nitride film. If the gate insulating film 3 made of a silicon oxide film is thinned to a silicon dioxide equivalent film thickness of less than 5 nm, particularly less than 3 nm, the breakdown voltage breakdown becomes obvious due to generation of direct tunnel current or hot carriers caused by stress. Since the silicon nitride film has a higher dielectric constant than the silicon oxide film, its silicon dioxide equivalent film thickness becomes thinner than the actual film thickness. That is, in the case of having a silicon nitride film, a capacitance equivalent to that of a relatively thin silicon dioxide film can be obtained even if it is physically thick. Therefore, by forming the gate insulating film 3 with a single silicon nitride film or a composite film of the same and a silicon oxide film, its effective film thickness can be made larger than that of the gate insulating film formed with a silicon oxide film. Therefore, the occurrence of tunnel leakage current and the reduction of breakdown voltage due to hot carriers can be improved.

A gate electrode 4aa made of, for example, low resistance polycrystalline silicon is patterned on the gate insulating film 3. The gate electrode 4a contains, for example, phosphorus (P) and is set to be n-type. Examples of a method of making the gate electrode 4a n-type include, for example, a method of simultaneously doping phosphorus and the like when depositing a polycrystalline silicon film for forming the gate electrode 4a by a CVD method, and a non-doped method of forming a gate electrode. After depositing the polycrystalline silicon film by the CVD method, a method of introducing phosphorus or arsenic (As) into the polycrystalline silicon film by, for example, an ion implantation method, or containing phosphorus or the like on the non-doped polycrystalline silicon film. A method of depositing an insulating film or the like and then thermally diffusing phosphorus in the insulating film into a non-doped polycrystalline silicon film may be used.

FIG. 2 is a sectional view of the essential part of the wafer during the manufacturing process of the semiconductor device, following FIG. Here, for example, by introducing an impurity such as boron (B) from the main surface side of the substrate 1S by an ion implantation method,
P ⁻ type semiconductor regions 5a for source and drain are formed on the main surface of the substrate 1S. This p ⁻ type semiconductor region 5a
Has the function of suppressing or preventing hot carriers,
This is a region for forming a so-called LDD (Lightly Doped Drain) structure. That is, the p ⁻ type semiconductor region 5a is a low impurity concentration region that suppresses or prevents hot carriers.

FIG. 3 is a cross-sectional view of essential parts of the wafer during the manufacturing process of the semiconductor device, following FIG. Here, impurities such as phosphorus or arsenic are added to the substrate 1S.
The n-well NWL is formed by penetrating the gate electrode 4a from the main surface side of the substrate 1S and introducing it into the substrate 1S by an ion implantation method so as to spread over a predetermined depth from the main surface of the substrate 1S. In the impurity introduction process at this time, since the gate electrode 4a is already formed, the gate electrode 4a
The arrival depth of the impurities under the region where the gate electrode 4a exists is shallower than the arrival depth of the impurity under the region where the gate electrode 4a does not exist.

FIG. 4 is a sectional view of the essential part of the wafer during the manufacturing process of the semiconductor device, following FIG. Here, for example, impurities such as boron are introduced into the substrate 1S from the main surface side of the substrate 1S through the gate electrode 4a by an ion implantation method, so that the p ⁻ -type impurity is directly formed on the substrate 1S just below the gate electrode 4a. A buried channel region 6 is formed. The buried channel region 6 is formed to have a peak of impurity concentration at a predetermined depth from the main surface of the substrate 1S. In the present embodiment, the process of forming the buried channel region 6 is performed after the process involving the heat treatment such as the process of forming the gate insulating film 3 so that the impurities in the buried channel region 6 are re-diffused. Can be suppressed. Therefore, the buried channel region 6
Can be formed with a desired impurity profile. Therefore, the electrical characteristics of pMIS can be improved. However, the processing order of FIGS. 2 to 4 is not limited to the above, and any order may be performed. The first concept is that the buried channel region 6
That is, the impurity introducing step for forming the is performed after the patterning step of the gate electrode 4a. The second concept is
As will be described later, the impurity introduction process of FIGS. 2 to 4 is continuously performed by using a common masking layer, for example, a photoresist pattern as a mask. By using a common photoresist pattern for use in the impurity introduction process, a series of photolithography processes including coating, exposure, development, baking and cleaning of the photoresist film can be completed in one step. That is, the photolithography process can be reduced by two processes as compared with the case where the impurity introduction processes are performed separately. Also, the number of photomasks can be reduced. Therefore, the development time and manufacturing time of the semiconductor device can be shortened. Further, the material cost, the fuel cost, and the work amount can be reduced, and the cost of the semiconductor device can be reduced.

FIG. 5 is a sectional view of the essential part of the wafer during the manufacturing process of the semiconductor device, following FIG. Here, an insulating film made of a silicon oxide film is deposited on the main surface of the substrate 1 by a CVD (Chemical Vapor Deposition) method or the like, and then etched back by an anisotropic dry etching method or the like, thereby forming a gate. A sidewall 7 made of, for example, silicon oxide is formed on the side surface of the electrode 4a.

FIG. 6 is a sectional view of the essential part of the wafer during the manufacturing process of the semiconductor device, following FIG. Here, the substrate 1S is introduced by introducing an impurity such as boron from the main surface side of the substrate 1S by an ion implantation method.
A p ⁺ type semiconductor region 5b for source and drain is formed on the main surface of S. Since this step is performed after forming the sidewall 7 as described above, the p ⁺ type semiconductor region 5b is formed in the substrate 1S at a position separated from the gate electrode 4a by the plane width dimension of the sidewall 7. To be done. Therefore, the p ⁺ type semiconductor region 5b is provided at a position separated from the end of the buried channel region 6 by the p ⁻ type semiconductor region 5a. In this way pMI
SQp is formed. That is, the p ⁺ type semiconductor region 5b
Is a high impurity concentration region having a higher impurity concentration than the p ⁻ type semiconductor region 5a.

FIG. 7 shows the impurity profile in the substrate 1 immediately below the gate electrode of the semiconductor device manufactured in this way. FIG. 7A shows the impurity profile by ion type, and FIG. 7B shows it by conductivity type. The solid line in FIG. 7A shows the boron profile, and the broken line shows the phosphorus profile. Also, FIG.
The solid line in (b) shows the impurity profile of the p-type semiconductor region, and the broken line shows the impurity profile of the n-type semiconductor region. In the present embodiment, FIG.
As shown in (a) and (b), the peak of the impurity profile for forming the p ⁻ type buried channel region 6 is clear so that a sharp peak is drawn from the main surface of the substrate 1 to a predetermined depth position. It can be seen that it is formed in such a state. That is, according to the present embodiment, the depth position of the p ⁻ type buried channel 6 can be formed as designed or in a state very close to the designed value. Therefore, since the electrical characteristics of the pMISQp can be improved as described above, it is possible to improve the operation reliability and the operation performance of the semiconductor device.

On the other hand, FIG. 8 is a technique studied by the inventors of the present invention, in which cross-sectional views of main parts of a semiconductor device manufactured by using a technique of introducing impurities for forming a channel before forming a gate electrode are compared. Show for. Further, FIG. 9 shows an impurity profile in the substrate immediately below the gate electrode of the semiconductor device of FIG. 9A shows the impurity profile by ion type, and FIG. 9B shows it by conductivity type. The solid line and the broken line in FIG. 9A indicate the boron profile and the phosphorus profile, respectively. The solid line in FIG. 9B shows the impurity profile of the p-type semiconductor region, and the broken line shows the impurity profile of the n-type semiconductor region.

In FIG. 8, reference numeral 50 is a substrate and 51 is n.
Wells, 52a are p ⁻ type semiconductor regions, 52b are p ⁺ type semiconductor regions, 53 is a p type buried channel region, 54 is a gate insulating film, and 55 is a gate electrode. In this technique, since the impurities for forming the n-well 51 are introduced before the formation of the gate electrode 55, the depth thereof is almost the same either directly under the gate electrode 4a or in the region where the gate electrode 4a is desired to exist. There is. And in FIG.
As shown in (a) and (b), it seems that the peak of the impurity profile for forming the p-type buried channel region 53 extends from the predetermined depth position of the substrate 50 to the main surface side of the substrate 1. It can be seen that it is formed in such a state.

That is, in the present embodiment, the pMISQp of the n-type gate electrode can be easily formed by introducing the impurity for forming the channel through the gate electrode 4a. pMI of n-type gate electrode
In S, since the work function difference between the gate electrode 4a and the substrate 1S is small, a voltage slightly lower than the bandgap voltage (for example, about -1V) must be applied to turn on the MIS. Therefore, impurity ions for forming a channel such as boron or boron difluoride are ion-implanted into the main surface portion of the substrate 1S immediately below the gate electrode 4a, and the main surface portion of the substrate 1S is ap ⁻ type semiconductor region. By forming the (buried channel region 6), the threshold voltage is lowered and the operation speed is promoted. Board 1
Although the p ⁻ type semiconductor region is formed on the main surface portion of S, the gate electrode 4a does not turn on between the source and the drain due to the zero bias, because the n type gate electrode 4a and the p ⁻ type semiconductor region are not turned on.
This is because the p ⁻ type semiconductor region is depleted due to the work function difference from the type semiconductor region. This structure is generally called a buried channel type because a channel is formed near the np junction inside the substrate 1S when the gate electrode 4a is negatively biased.

However, in this method, the threshold voltage is
In order to make it even lower, injection of impurity ions such as boron
The substrate 1S is zero-biased when the amount is increased.
P inside S^-Type semiconductor region is not depleted, so
A leak occurs between the drain and the drain. There
So, as another structure, to lower the threshold voltage
Makes the gate electrode p-type and has a channel shape like phosphorus.
Ion implantation of impurity ions for production. In this case,
Since the channel is formed on the main surface of the substrate 1S, it is generally exposed.
It is called a surface channel type. However, the gate voltage of pMIS
When the pole 4a is of p type, as described above, the resist pattern is
The number of process steps (and the number of photomasks) to increase
A problem arises. In the above explanation, the threshold voltage is lowered.
For this reason, it was explained that the surface channel type was used.^-Type
Of the semiconductor region is diffused by heat treatment after ion implantation,
Even if the n-junction is deepened from the main surface of the substrate 1S,
P ^-Type semiconductor region is not depleted, the source and
A leak will occur between the drains. That is, n-type
PMIS of the gate electrode of^-Mold semiconductor region
Gate insulating film formation process after ion implantation for formation
By performing heat treatment such as
Deepening from the main surface, p^-Type semiconductor region is depleted
Without increasing the leakage current between the source and drain.
It In particular, the leakage between the source and drain as described above
The problem of noise becomes more remarkable as the gate length is reduced. this
In the present embodiment, p.^-
Of impurity ions for forming a semiconductor region of the mold
After the step of forming the gate insulating film 3 and the gate electrode 4a,
Since it does not go through the heat history, p^-Mold semiconductor region
Impurities do not spread inside the substrate 1S,
Sufficient cut-off characteristics are obtained even if the pole 4a is not p-type
be able to.

Next, a case where the technical idea of the present invention is applied to a method of manufacturing a semiconductor device having a flash memory will be described with reference to FIGS.

FIG. 10 is a cross-sectional view of essential parts in the process of manufacturing the semiconductor device. In FIG. 10, a memory cell region (flash memory formation region) M of the flash memory and a high breakdown voltage nMIS formation region (second region) H are shown.
N, a high breakdown voltage pMIS formation region (second region) HP, an nMIS formation region (first region) LN for logic, and a pMIS formation region (first region) LP for logic are shown. An insulating film 8a made of, for example, silicon oxide is formed on the main surface of the substrate 1S.

FIG. 11 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device, following FIG. Here, the substrate 1S
A photoresist pattern (that covers the high breakdown voltage nMIS formation region HN and the high breakdown voltage pMIS formation region HP and exposes the memory cell region M, the logic nMIS formation region LN and the pMIS formation region LP on the main surface of PR1 (hereinafter simply referred to as a resist pattern) is formed by a photolithography technique. Then, using this resist pattern PR1 as a mask, for example, phosphorus is introduced into the substrate 1S by an ion implantation method. As a result, the substrate 1
A deep n well NBL is formed at a deep position of S. Then, the resist pattern PR1 is removed.

FIG. 12 shows a cross-sectional view of essential parts in the manufacturing process of a semiconductor device, following FIG. Here, first, on the main surface of the substrate 1S, the high breakdown voltage pMIS formation region HP, the logic nMIS formation region LN and the pMIS formation region LP are covered, and the memory cell region M and the high breakdown voltage nMIS are formed.
A resist pattern PR that exposes the formation region HN
2 is formed by a photolithography technique. Then, using this resist pattern PR2 as a mask, for example, boron is introduced into the substrate 1S by an ion implantation method.
As a result, the p well 9P is formed in the memory cell region M and the high breakdown voltage nMIS formation region HN of the substrate 1S. The p-well 9P in the memory cell region M is surrounded by the deep n-well NBL on the outer periphery (side surface and bottom surface) and is electrically isolated from the substrate 1S. Then, using the same resist pattern PR2 as a mask, for example, boron difluoride (B
F ₂ ) is introduced into the substrate 1S by the ion implantation method. This impurity introduction step is performed in the memory cell and the high breakdown voltage nMIS.
Is an impurity introducing step for adjusting the threshold voltage, that is, an impurity introducing step for forming a channel region. The channel region in this case is a surface channel. The condition at this time is that the dose amount is, for example, 2.5 × 10 5.
^The ion implantation energy is about ¹² / cm ² , and the ion implantation energy is, for example, about 100 keV. Impurity introduction step for forming the p well 9N, memory cell and high breakdown voltage nMIS
The order may be reversed in the impurity introduction step for forming the channel. Then, the resist pattern PR2 is removed.

FIG. 13 shows the fabrication of the semiconductor device following FIG.
The principal part sectional drawing in the process is shown. Here, first,
The memory cell region M and the high breakdown voltage nMIS are formed on the main surface of the plate 1S.
The formation region HN, the nMIS formation region LN for logic, and
And the pMIS formation region LP are covered to form a high breakdown voltage pMIS.
A resist pattern PR3 that exposes the region HP is formed.
It is formed by a photolithography technique. This register
Using the pattern PR3 as a mask, for example, phosphorus ions
It is introduced into the substrate 1S by the injection method. This allows the substrate
An n well 10N is formed in the 1S high breakdown voltage pMIS formation region HP.
Form. Then, the same resist pattern PR3 is masked.
For example, boron difluoride (BF) ₂) Ion injection
It is introduced into the substrate 1S by an injection method. This impurity introduction process
Is the introduction of impurities for adjusting the threshold voltage of the high breakdown voltage pMIS.
Process, that is, impurities for forming a channel region
This is an introduction process. In this case, the channel region is
It is said to be a flannel. The conditions at this time are the dose amount
Is, for example, 1.6 × 10¹²/ Cm²Degree, ion implantation
The apparent energy is, for example, about 100 keV. the above
Impurity introduction process for forming n-well 10N and high breakdown voltage
This is followed by the impurity introduction process for forming the pMIS channel.
You may reverse the order. After that, the resist pattern PR3
Then, the insulating film 8a is removed.

FIG. 14 is a cross-sectional view of essential parts in the manufacturing process of a semiconductor device, following FIG. Here, first, the substrate 1S is subjected to a thermal oxidation process at, for example, 800 ° C. for about 23 minutes to form a film having a thickness of, for example, 11
A gate insulating film (third gate insulating film) 3a made of silicon oxide having a thickness of about nm is formed. This gate insulating film 3
a functions as a tunnel insulating film of the memory cell. Then, a conductor film 11 having, for example, a low resistance polycrystalline silicon structure is deposited on the main surface of the substrate 1S on which the gate insulating film 3a has been formed, by the CVD method or the like, and then, thereon.
For example, an interlayer film 12 formed by sequentially depositing a silicon oxide film, a silicon nitride film, and a silicon oxide film from the lower layer in FIG.
Are deposited by the CVD method or the like.

FIG. 15 is a cross-sectional view of essential parts in the manufacturing process of a semiconductor device, following FIG. Here, first, the memory cell region M is covered on the interlayer film 12, and the high breakdown voltage nM is applied.
A resist pattern PR4 that exposes the IS formation region HN, the high breakdown voltage pMIS formation region HP, the logic nMIS formation region LN, and the pMIS formation region LP is formed by a photolithography technique. Then, using the resist pattern PR4 as an etching mask, the interlayer film 12 and the conductor film 11 exposed therefrom are removed by etching by a dry etching method. Then, the resist pattern PR4 is removed.

FIG. 16 is a cross-sectional view of essential parts in the manufacturing process of a semiconductor device, following FIG. Here, the substrate 1S
On the other hand, the gate insulating film 3a in the region exposed from the conductor film 11 is grown by performing a thermal oxidation process at 800 ° C. for about 8 minutes, and the high breakdown voltage nMIS formation region HN,
A relatively thick gate insulating film 3b having a thickness of, for example, about 16 nm is formed in the high breakdown voltage pMIS formation region HP, the logic nMIS formation region LN, and the pMIS formation region LP. The gate insulating film 3b is a gate insulating film (second gate insulating film) 3b having a high breakdown voltage nMIS and a high breakdown voltage pMIS.
Is.

FIG. 17 is a cross-sectional view of essential parts in the manufacturing process of a semiconductor device, following FIG. Here, first, on the main surface of the substrate 1S, the memory cell region M and the high breakdown voltage nMIS are formed.
The formation region HN and the high breakdown voltage pMIS formation region HP are covered, and the logic nMIS formation regions LN and pMIS are formed.
Resist pattern PR such that the formation region LP is exposed
5 is formed. Subsequently, the resist pattern PR5 is used as an etching mask to expose the insulating film 3b.
Are removed by etching. After that, the resist pattern PR
Remove 5.

FIG. 18 shows a cross-sectional view of essential parts in the process of manufacturing a semiconductor device, following FIG. Here, the substrate 1S
In contrast, for example, 750 ° C, about 7 minutes or 900 ° C,
By performing thermal oxidation treatment for about 30 minutes, the nMIS formation region LN and the pMIS formation region LP for logic are formed.
Then, a gate insulating film (first gate insulating film) 3c made of, for example, silicon oxide is formed. At this time, the insulating film 3b also grows, and the high breakdown voltage nMIS formation region HN and the high breakdown voltage pMIS are formed.
In the formation region HP, the gate insulating film 3d having a heat about the sum of the film thicknesses of the insulating films 3a and 3b is formed. The gate insulating film 3c has a thickness of, for example, about 4 nm.
It is thinner than a and thinner than the insulating film 3b.
The thickness of the gate insulating film 3d is, for example, about 20 nm. Then, a conductor film 13 for forming a gate electrode is deposited on the main surface of the substrate 1S by a CVD method or the like. The conductor film 13 is made of, for example, n-type low resistance polycrystalline silicon containing phosphorus. As a method of making the conductor film 13 n-type, for example, a method of simultaneously doping phosphorus when the conductor film 13 is deposited by the CVD method, or a method of depositing a non-doped polycrystalline silicon film by the CVD method and then forming the polycrystalline silicon For example, a method in which phosphorus or arsenic (As) is introduced into the film by an ion implantation method or an insulating film containing phosphorus or the like is deposited on the non-doped polycrystalline silicon film, and then phosphorus in the insulating film is non-doped. A method such as thermal diffusion to a polycrystalline silicon film may be used. As described above, in the present embodiment, the gate electrodes of the nMIS and the pMIS can be made to have the common conductivity type, so that the impurity implantation process can be omitted. That is, n
The step of forming a resist pattern required when the conductivity types of the gate electrode are different between MIS and pMIS can be reduced by one step. Therefore, a series of lithographic steps such as application of resist film, exposure, development, baking and cleaning can be omitted. Also, the number of photomasks can be reduced by one. Therefore, the development time and the manufacturing time of the semiconductor device can be shortened. Further, since the material cost, the fuel cost and the work amount can be reduced, the cost of the semiconductor device can be reduced.

FIG. 19 is a cross-sectional view of essential parts in the manufacturing process of a semiconductor device, following FIG. Here, the conductor film 1
3 is patterned by a photolithography technique and a dry etching technique, so that a high breakdown voltage nMI can be obtained.
An n-type gate electrode 13a of S, a high breakdown voltage pMIS, a logic nMIS, and a logic pMIS is formed. The gate electrode 13a in the pMIS formation region for logic corresponds to the gate electrode 4a.

FIG. 20 is a cross-sectional view of essential parts in the manufacturing process of a semiconductor device, following FIG. Here, the conductor film 13, the interlayer film 12 and the conductor film 11 remaining in the memory cell region M are patterned by the photolithography technique and the dry etching technique, so that the floating gate electrode 11a of the memory cell and the interlayer film 12 are patterned.
And the control gate electrode 13b is formed.

FIG. 21 shows a cross-sectional view of essential parts in the process of manufacturing a semiconductor device, following FIG. Here, first, a resist pattern PR6 is formed on the main surface of the substrate 1S by a photolithography technique. Resist pattern P
R6 is a high breakdown voltage nMIS formation region HN, a high breakdown voltage pMIS
The memory cell region M is formed so as to cover the formation region HP, the logic nMIS formation region LN, and the pMIS formation region LP. Subsequently, using the resist pattern PR6 as a mask, for example, phosphorus or arsenic is introduced into the substrate 1S by an ion implantation method to form the n ⁻ type semiconductor regions 14a for the source and drain of the memory cell. After that, using the resist pattern PR6 as a mask, for example, boron or boron difluoride is introduced into the substrate 1S by an ion implantation method or the like to p-type punch-through stopper region (pocket region or halo) for suppressing or preventing punch-through. (Also called an area) may be formed. The order of the impurity introducing step for forming the punch-through stopper region and the impurity introducing step for forming the semiconductor region 14a may be reversed. Then, the resist pattern PR6 is removed.

FIG. 22 shows a cross-sectional view of essential parts in the manufacturing process of a semiconductor device, following FIG. Here, first, a resist pattern PR7 is formed on the main surface of the substrate 1S by a photolithography technique. Resist pattern P
R7 is a memory cell region M, a high breakdown voltage pMIS formation region H
P, logic nMIS formation region LN and pMIS
It is formed so as to cover the formation region LP and expose the high breakdown voltage nMIS formation region HN. Then, using the resist pattern PR7 as a mask, for example, phosphorus or arsenic is introduced into the substrate 1S by an ion implantation method to form n ⁻ type semiconductor regions 15a for the source and drain of the high breakdown voltage nMIS. Then, using the resist pattern PR7 as a mask, boron or boron difluoride is introduced into the substrate 1S by an ion implantation method or the like to suppress or prevent punch through p
A punch through stopper region (pocket region) of the mold may be formed. The order of the impurity introducing step for forming the punch-through stopper region and the impurity introducing step for forming the semiconductor region 15a may be reversed. Then, the resist pattern PR7 is removed.

FIG. 23 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device, following FIG. Here, first, a resist pattern PR8 is formed on the main surface of the substrate 1S by a photolithography technique. Resist pattern P
R8 is a memory cell region M, a high breakdown voltage nMIS formation region H
N, nMIS formation region LN and pMIS for logic
It is formed so as to cover the formation region LP and expose the high breakdown voltage pMIS formation region HP. Subsequently, using the resist pattern PR8 as a mask, boron difluoride or boron is introduced into the substrate 1S by an ion implantation method to form p ⁻ type semiconductor regions 16a for the source and drain of the high breakdown voltage pMIS. . Thereafter, using the resist pattern PR8 as a mask, for example, phosphorus may be introduced into the substrate 1S by an ion implantation method or the like to form an n-type punch-through stopper region (pocket region) for suppressing or preventing punch-through. .
The order of the impurity introducing step for forming the punch through stopper region and the impurity introducing step for forming the semiconductor region 16a may be reversed. Then, the resist pattern PR8 is removed.

24 and 25 are sectional views of the essential part in the manufacturing process of the semiconductor device, following FIG. Here, first, the resist pattern PR is formed on the main surface of the substrate 1S.
9 is formed by a photolithography technique. The resist pattern (masking layer) PR9 covers the memory cell region M, the high breakdown voltage nMIS formation region HN, the high breakdown voltage pMIS formation region HP and the logic pMIS formation region LP, and exposes the logic nMIS formation region LN. Has been formed. Then, as shown in FIG. 24, using the resist pattern PR9 as a mask, for example, boron is introduced into the substrate 1S by penetrating the gate electrode 13a by an ion implantation method.
A p well PWL is formed in the S formation region LN. The condition at this time is that the dose amount is, for example, 1.5 × 10 ¹³ / c
m ² and ion implantation energy is, for example, 300
It is about keV. After that, the resist pattern PR
Using p. 9 as a mask, for example, boron is introduced into the substrate 1S through the gate electrode 13a by an ion implantation method or the like to form a p ⁻ type surface channel region. The conditions at this time are, for example, 1.3 × 10
^The ion implantation energy is about ¹³ / cm ² , and the ion implantation energy is about 100 keV, for example.

Then, as shown in FIG.
Using the pattern PR9 as a mask, for example, phosphorus or diamond
To introduce the element into the substrate 1S by the ion implantation method or the like.
For nMIS source and drain for logic
N^-The semiconductor region 17a of the mold is formed. Then, that
Using the resist pattern PR9 as a mask, for example, boron
Alternatively, boron difluoride is ion-implanted into the substrate 1
Introduction into S suppresses or prevents punch through
P-type punch-through stopper area (pocket area)
Area) may be formed. These p-well PWL and p-type
Surface channel, n ^-Type semiconductor region 17a and p type
Impurity introduction for forming punch-through stopper region
The steps may be performed in any order. afterwards,
The resist pattern PR9 is removed.

In this embodiment, the p well PW is used.
A common resist pattern PR is used in the impurity introduction process for forming the L and p type surface channels, the n ⁻ type semiconductor region 17a and the p type punch through stopper region.
9 can be used as a mask. Therefore, similar to the above, it is possible to reduce a series of photolithography steps involving application, exposure, development, baking and cleaning of the photoresist film. Also, the number of photomasks can be reduced. Therefore, the development time and manufacturing time of the semiconductor device can be shortened. Further, the material cost, the fuel cost, and the work amount can be reduced, and the cost of the semiconductor device can be reduced.

[0061] Also, p in the nMIS ^- the impurity introducing step for forming the mold surface channel region of, by proceeding after the step of forming the gate electrode 13a, the p ^- due to diffusion of impurity in the surface channel region of the The redistribution can be suppressed or prevented, and the p ⁻ -type surface channel region can be formed at the depth position as designed (or in a state very close to it) and the impurity distribution state, so that the leakage current between the source and the drain can be prevented. It is possible to improve the electrical characteristics of the nMIS for logic such that the occurrence can be suppressed or prevented.

26 and 27 are the same as FIGS. 24 and 2.
5 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device following step 5. Here, first, a resist pattern (masking layer) PR10 is formed on the main surface of the substrate 1S by a photolithography technique. Resist pattern PR10
Is a memory cell region M, a high breakdown voltage nMIS formation region HN,
High breakdown voltage pMIS formation region HP and logic nMI
It is formed so as to cover the S formation region LN and expose the pMIS formation region LP for logic. Then, FIG.
6, using the resist pattern PR10 as a mask, for example, phosphorus is introduced into the substrate 1S through the gate electrode 13a by an ion implantation method.
An n well NWL is formed in the pMIS formation region LP for logic. As the conditions at this time, the dose amount is, for example, about 1.2 × 10 ¹³ / cm ² , and the ion implantation energy is, for example, about 480 keV. Then, using the resist pattern PR10 as a mask, for example, boron is introduced into the substrate 1S through the gate electrode 13a by an ion implantation method or the like to form a p ⁻ -type buried channel region. The conditions at this time are, for example, a dose amount of about 5 × 10 ¹² / cm ² and an ion implantation energy of about 80 keV.

Then, as shown in FIG. 27, by using the resist pattern PR10 as a mask, for example, boron or boron difluoride is introduced into the substrate 1S by an ion implantation method or the like, so that for the source and drain of the pMIS for logic. Forming a p ⁻ type semiconductor region 18a. Then, using the resist pattern PR10 as a mask, for example, phosphorus is introduced into the substrate 1S by an ion implantation method or the like to form an n-type punch-through stopper region (pocket region) for suppressing or preventing punch-through. good. The impurity introducing steps for forming the n well NWL, the p type buried channel, the p ⁻ type semiconductor region 18a and the n type punch through stopper region may be performed in any order. Then, the resist pattern PR10 is removed.

In this embodiment, the n-well NW is used.
L, p type buried channel, p ⁻ type semiconductor region 18a
And a common resist pattern P in the impurity introducing step for forming the n-type punch through stopper region.
R10 can be used as a mask. For this reason,
Similar to the above, the photolithography process can be reduced.
Also, the number of photomasks can be reduced. Therefore, the development time and manufacturing time of the semiconductor device can be shortened. Further, the material cost, the fuel cost, and the work amount can be reduced, and the cost of the semiconductor device can be reduced.

[0065] Also, p in the pMIS ^- the impurity introducing step for forming the type buried channel region of, by proceeding after the step of forming the gate electrode 13a, the p ^- by diffusion of impurities in the buried channel region of the Redistribution can be suppressed or prevented, and the p ⁻ -type buried channel region can be formed at the depth position as designed (or in a state very close to it) and the impurity distribution state, so that the leakage current between the source and the drain can be prevented. It is possible to improve the electrical characteristics of the pMIS for logic such that the generation can be suppressed or prevented.

FIG. 28 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device, following FIG. 26 and FIG. Here, an insulating film made of, for example, silicon oxide is deposited on the main surface of the substrate 1S by a CVD method or the like, and then the insulating film is etched back by an anisotropic dry etching method to form side surfaces of the gate electrode 13a. Then, a sidewall 7a is formed on the side surface of the pattern formed by the floating gate electrode 11a, the interlayer film 12 and the control gate electrode 13b of the memory cell.

FIG. 29 is a cross-sectional view of essential parts in the manufacturing process of a semiconductor device, following FIG. 28. Here, first, a resist pattern PR11 is formed on the main surface of the substrate 1S by a photolithography technique. The resist pattern PR11 covers the high breakdown voltage pMIS formation region HP and the logic pMIS formation region LP, and exposes the nMIS formation region, that is, the memory cell region M, the high breakdown voltage nMIS formation region HN, and the logic nMIS formation region LN. Is formed. Then, by using the resist pattern PR11 as a mask, for example, arsenic or phosphorus is introduced into the substrate 1S by an ion implantation method, and n for source and drain of the memory cell MC, the high breakdown voltage nMISQhn, and the logic nMISQln is introduced.
^{The +} type semiconductor regions 14b, 15b and 17b are formed.
Then, the resist pattern PR11 is removed.

FIG. 30 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device, following FIG. 29. Here, first, a resist pattern PR12 is formed on the main surface of the substrate 1S by a photolithography technique. The resist pattern PR12 covers the memory cell region M, the high breakdown voltage nMIS formation region HN and the logic nMIS formation region LN, and the high breakdown voltage pMIS formation region HP and the logic pMIS formation region LN.
It is formed so as to expose the MIS formation region LP, that is, the pMIS formation region. Then, using the resist pattern PR12 as a mask, for example, boron difluoride or boron is introduced into the substrate 1S by an ion implantation method to form a p ⁺ type semiconductor for the source and drain of the high breakdown voltage pMISQhp and the logic pMISQlp. Regions 16b and 18b are formed. Then, the resist pattern PR12 is removed.

The gate lengths of the high breakdown voltage nMISQhn and the high breakdown voltage pMISQhp are, for example, about 0.9 μm. Further, the threshold voltage (V of the high breakdown voltage nMISQhn
th) is, for example, about 0.45 V and has a high breakdown voltage pMISQh.
The threshold voltage (Vth) of p is, for example, about −0.45V. In addition, high breakdown voltage nMISQhn and high breakdown voltage p
The drive power supply voltage of MISQhp is, for example, about 3.3V.

The gate lengths of the logic nMISQln and pMISQlp are, for example, about 0.25 μm or 0.32 μm. In addition, nMI for logic
The threshold voltage (Vth) of SQln is, for example, 0.15.
About V, the threshold voltage (Vth) of the pMISQlp for logic is about -0.15V, for example. Also,
The driving power supply voltage of the logic nMISQln and pMISQlp is, for example, about 1.8V.

FIG. 31 is a plan view schematically showing the circuit configuration of the chip 1C which constitutes the semiconductor device manufactured in this manner. On the main surface of the chip 1C, a memory cell region M of the flash memory, a high breakdown voltage MIS formation region (the high breakdown voltage nMIS formation region HN and the high breakdown voltage pMIS formation region HP) HM, and a low threshold voltage (Vth) MIS.
A formation region (nMIS formation region LN and pMIS formation region LP for logic) LM is arranged.

(Embodiment 2) In the present embodiment, a modification of the step of introducing a channel region forming impurity will be described with reference to FIGS.

FIG. 32 shows a cross-sectional view of the essential parts in the manufacturing process of the semiconductor device of the second embodiment. A conductor film 4 is deposited on the main surface of the substrate 1S via a gate insulating film 3. The conductor film 4 is made of, for example, n-type low resistance polycrystalline silicon containing phosphorus. The method of making the conductor film 4 n-type is the same as that described in the first embodiment, and thus the description thereof is omitted. A resist pattern PR is formed on the conductor film 4.
13 is formed by the photolithography technique. The resist pattern PR13 is a masking layer for forming a gate electrode and is formed so as to cover the gate electrode forming region and expose the other portions. Note that N is
The nMIS formation region (first region) and P indicate the pMIS formation region (first region), respectively.

FIG. 33 is a cross-sectional view of essential parts in the manufacturing process of a semiconductor device, following FIG. 32. Here, using the resist pattern PR13 shown in FIG. 32 as an etching mask, the conductor film 4 exposed therefrom is removed by etching by a dry etching method or the like. As a result, nMI
Both the S and pMIS n-type gate electrodes 4a are simultaneously patterned. Then, the resist pattern PR1
3 has been removed.

FIG. 34 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device, following FIG. 33. Here, first, a resist pattern PR14 is formed on the main surface of the substrate 1S by a photolithography technique. The resist pattern PR14 covers the pMIS formation region P and
It is formed so that the S formation region N is exposed. Then, using the resist pattern PR14 as a mask, for example, phosphorus or arsenic is ion-implanted or the like to form the substrate 1S.
To form an n ⁻ type semiconductor region 17a for the source and drain of the nMIS. In this step, the impurity introducing step for forming the punch-through stopper region may be performed as in the first embodiment. Then, the resist pattern PR14 is removed.

FIG. 35 is a cross-sectional view of essential parts in the manufacturing process of a semiconductor device, following FIG. 34. Here, first, a resist pattern PR15 is formed on the main surface of the substrate 1S by a photolithography technique. The resist pattern PR15 covers the nMIS formation region N, and the pMI
It is formed so that the S formation region P is exposed. Then, using the resist pattern PR15 as a mask, for example, boron or boron difluoride is introduced into the substrate 1S by an ion implantation method or the like to form p ⁻ type semiconductor regions 18a for pMIS source and drain. In this step, the impurity introducing step for forming the punch-through stopper region may be performed as in the first embodiment. Then, the resist pattern PR15 is removed.

FIG. 36 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device, following FIG. 35. Here, the sidewalls 7a are formed on the side surfaces of the gate electrode 4a in the same manner as in the first embodiment.

37 and 38 are sectional views of the essential part in the manufacturing process of the semiconductor device, following FIG. 36. Here, first, a resist pattern (masking layer) PR16 is formed on the main surface of the substrate 1S by a photolithography technique. The resist pattern PR16 is formed so as to cover the pMIS formation region P and expose the nMIS formation region N. Then, as shown in FIG. 37, using the resist pattern PR16 as a mask, for example, arsenic or phosphorus is introduced into the substrate 1S by an ion implantation method to form the n ⁺ type semiconductor regions 17b for the source and drain of the nMISQln. Form.

Then, as shown by the solid line arrow in FIG. 38, using the resist pattern PR16 as a mask, for example, boron is introduced into the substrate 1S through the gate electrode 4a by an ion implantation method to form an nMIS formation region. P well PWL is formed in N. The conditions at this time are
This is the same as the first embodiment. After that, as shown by the wavy line arrow in FIG. 38, using the resist pattern PR16 as a mask, for example, boron is introduced into the substrate 1S through the gate electrode 4a by an ion implantation method or the like, whereby a p ⁻ -type surface channel is formed. The region 6a is formed. Then, the resist pattern PR16 is removed. Note that n ⁺
The impurity introduction steps for forming the p-type semiconductor region 17b, the p well PWL, and the surface channel region 6a may be performed in any order.

39 and 40 are sectional views of the essential part in the manufacturing process of the semiconductor device, following FIG. 38. Here, first, a resist pattern (masking layer) PR17 is formed on the main surface of the substrate 1S by a photolithography technique. The resist pattern PR17 is formed so as to cover the nMIS formation region N and expose the pMIS formation region P. Subsequently, as shown in FIG. 39, using the resist pattern PR17 as a mask, for example, boron or boron difluoride is ion-implanted into the substrate 1
By introducing into S, ap ⁺ type semiconductor region 18b for the source and drain of pMISQlp is formed.

Then, as shown by the solid arrow in FIG. 40, using the resist pattern PR17 as a mask, phosphorus or arsenic is introduced into the substrate 1S through the gate electrode 4a by the ion implantation method, and pM is introduced.
An n well NWL is formed in the IS formation region P. The conditions at this time are the same as those in the first embodiment. After that, FIG.
As indicated by the wavy line arrow 0, the resist pattern P
Using R17 as a mask, for example, boron is introduced into the substrate 1S through the gate electrode 4a by an ion implantation method or the like to form the p ⁻ type buried channel region 6b. Then, the resist pattern PR17 is removed.
Note that the impurity introduction steps for forming the p ⁺ type semiconductor region 18b, the n well NWL, and the buried channel region 6b may be performed in any order.

FIG. 41 is a cross-sectional view of essential parts in the manufacturing process of a semiconductor device, following FIG. 40. Here, first, part of the main surface of the substrate 1S (n ⁺ type semiconductor region 17b and p ⁺ type semiconductor region 18b) and the upper surface of the gate electrode 4a are exposed, and then, on the main surface of the substrate 1S, A refractory metal film such as tungsten or cobalt is deposited by a sputtering method, a CVD method or the like. Subsequently, the substrate 1S is subjected to heat treatment to cause a silicide reaction at the contact portion between the metal film and silicon. Then, by removing the unreacted metal film, the silicide layer 19 made of, for example, tungsten silicide or cobalt silicide is formed into the n ⁺ -type semiconductor region 17.
It is formed in a self-aligned manner on the upper surface of the b, p ⁺ type semiconductor region 18b and the gate electrode 4a (salicide process).

FIG. 42 shows the impurity profile in the substrate 1 immediately below the gate electrode of the semiconductor device manufactured in this way. 42A shows the impurity profile by ion type, and FIG. 42B shows it by conductivity type. The solid line in FIG. 42A is the profile of boron,
The dashed lines indicate the phosphorus profiles, respectively. The solid line in FIG. 42B shows the impurity profile of the p-type semiconductor region, and the broken line shows the impurity profile of the n-type semiconductor region. In the present embodiment,
As in the first embodiment, the peak of the impurity profile for forming the p ⁻ -type buried channel region 6b is clearly defined so that a sharp peak is drawn from the main surface of the substrate 1S to a predetermined depth position. You can see that it is formed. That is, according to this embodiment, the depth position of the p ⁻ type buried channel 6b can be formed as designed or in a state very close to the designed value. Therefore, the electrical characteristics of the pMISQlp can be improved as described above, and the operation reliability and the operation performance of the semiconductor device can be improved. Similar effects can be obtained with nMISQln.

As described above, also in the second embodiment, the same effect as in the first embodiment can be obtained.

(Third Embodiment) In the third embodiment, a pMIS structure having the punch-through stopper region will be described. FIG. 43 shows a sectional view of the main part of the pMISQp. The punch-through stopper region 20 is set to be n-type by introducing, for example, phosphorus or arsenic, and is formed with an impurity distribution surrounding the side portion and the lower portion of the p ⁻ -type semiconductor region 5a. By providing such a punch through stopper region 20, pMI
The short channel effect in SQp can be suppressed or prevented. That is, it is possible to suppress or prevent the generation of the leak current between the source and the drain of the pMISQp. This structure is nM
When applied to IS, punch through stopper area 20
Is p, for example, when boron or boron difluoride is introduced.
Set to type.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, the case where the substrate is made of silicon has been described, but the present invention is not limited to this and various modifications can be made. For example, a semiconductor layer S provided on an insulating film is used.
An OI substrate or an epitaxial substrate in which an epitaxial layer is provided on the surface of a semiconductor substrate may be used.

In the above description, the case where the invention made by the present inventor is mainly applied to the method of manufacturing a semiconductor device having a flash memory which is the field of application of the invention has been described, but the invention is not limited thereto. , Other memory such as DRAM (Dynamic Random Acc
ess Memory) or SRAM (Static Random Access M)
method of manufacturing a semiconductor device having another memory circuit such as an emory), a method of manufacturing a semiconductor device having a logic circuit such as a microprocessor, or a mixed mounting type in which the memory circuit and the logic circuit are provided on the same substrate. It is also applicable to the method of manufacturing a semiconductor device.

[0089]

The effects obtained by the typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows. (1) .After forming the gate electrode on the gate insulating film, by introducing the impurities for forming the channel into the semiconductor substrate under the gate electrode, the redistribution of the impurities for forming the channel due to thermal diffusion is suppressed. Alternatively, it can be prevented, and the formation state of the channel can be improved, so that the electrical characteristics of the field effect transistor can be improved. (2). A photolithography step for forming a masking layer by introducing impurities for forming a well into a semiconductor substrate using the masking layer used as a mask in the step of introducing impurities for forming the channel as a mask. Can be reduced and the number of photomasks can be reduced,
It is possible to reduce the cost of the semiconductor device.

[Brief description of drawings]

FIG. 1 is a fragmentary cross-sectional view of a wafer during a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of the essential part of the wafer during the manufacturing process of the semiconductor device, following FIG. 1;

FIG. 3 is a cross-sectional view of the essential part of the wafer during the manufacturing process of the semiconductor device, following FIG. 2;

FIG. 4 is a sectional view of the essential part of the wafer during the manufacturing process of the semiconductor device, following FIG. 3;

FIG. 5 is a cross-sectional view of the essential part of the wafer during the manufacturing process of the semiconductor device, following FIG. 4;

FIG. 6 is a cross-sectional view of the essential part of the wafer during the manufacturing process of the semiconductor device, following FIG. 5;

7A and 7B are explanatory views of impurity profiles in a semiconductor substrate directly below a gate electrode of a semiconductor device manufactured by the method described in FIGS.

FIG. 8 is a cross-sectional view of essential parts of a semiconductor device manufactured using a technique studied by the present inventors, which is a technique of introducing an impurity for forming a channel before forming a gate electrode.

9A and 9B are explanatory views of an impurity profile in a semiconductor substrate immediately below a gate electrode of the semiconductor device in FIG.

FIG. 10 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device being an embodiment of the present invention.

FIG. 11 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 10;

12 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG.

FIG. 13 is a main-portion cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 12;

FIG. 14 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 13;

FIG. 15 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 14;

16 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG.

FIG. 17 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 16;

FIG. 18 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 17;

FIG. 19 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 18;

FIG. 20 is a main-portion cross-sectional view of the semiconductor device during the manufacturing process thereof, which is subsequent to FIG. 19;

FIG. 21 is a main-portion cross-sectional view of the semiconductor device during the manufacturing process thereof, which is subsequent to FIG. 20;

22 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG.

23 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG.

24 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG.

25 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG. 23.

FIG. 26 is a main-portion cross-sectional view of the semiconductor device during a manufacturing step, which is subsequent to FIGS. 24 and 25;

27 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device, following FIG. 24 and FIG. 25.

28 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device, following FIG. 26 and FIG. 27.

29 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG. 28. FIG.

30 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG. 29. FIG.

FIG. 31 is a plan view schematically showing a circuit configuration of a semiconductor chip that constitutes a semiconductor device.

FIG. 32 is a main-portion cross-sectional view of a semiconductor device which is another embodiment of the present invention during a manufacturing step.

33 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG. 32.

34 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG. 33. FIG.

FIG. 35 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG. 34.

36 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG. 35.

FIG. 37 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG. 36.

38 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG. 36. FIG.

FIG. 39 is a main-portion cross-sectional view of the semiconductor device during the manufacturing process thereof, which is subsequent to FIG. 38;

FIG. 40 is a main-portion cross-sectional view of the semiconductor device during the manufacturing process thereof, which is subsequent to FIG. 38;

41 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG. 40. FIG.

42 (a) and 42 (b) are explanatory views of an impurity profile in a semiconductor substrate immediately below a gate electrode of a semiconductor device manufactured by the method described in FIGS. 32 to 42.

FIG. 43 is a cross-sectional view of essential parts of a semiconductor device according to still another embodiment of the present invention.

[Explanation of symbols]

1 Wafer 1S Semiconductor Substrate 1C Semiconductor Chip 2 Separation Part 3 Gate Insulating Film 3a Gate Insulating Film (Third Gate Insulating Film) 3b Gate Insulating Film (Second Gate Insulating Film) 3c Gate Insulating Film (First Gate Insulating Film) 3d Gate Insulating film 4a Gate electrode 5a Semiconductor region 5b Semiconductor region 6 Buried channel region 6a Surface channel region 6b Buried channel region 7 Sidewall 7a Sidewall 8a Insulating film 9P p well 10N n well 11 Conductive film 11a Floating gate electrode 12 Interlayer film 13 Conductor Film 13b Control gate electrode 13a Gate electrode 14a Semiconductor region 14b Semiconductor region 15a Semiconductor region 15b Semiconductor region 16a Semiconductor region 16b Semiconductor region 17a Semiconductor region 17b Semiconductor region 18a Semiconductor region 18b Semiconductor region 19 Silicide layer 2 0 punch through stopper region 50 semiconductor substrate 51 n well 52a p ⁻ type semiconductor region 52b p ⁺ type semiconductor region 53 buried channel region 54 gate insulating film 55 gate electrode NWL n well PWL p well M memory cell region of flash memory ( Flash memory formation region) HN High breakdown voltage n-channel type MIS • FET formation region (second region) HP High breakdown voltage p-channel type MIS • FET formation region (second region) HM High breakdown voltage MIS formation region LM Low threshold Value voltage MIS formation region LN n-channel type MIS • FET formation region for logic (first region) LP p-channel type MIS • FET formation region (first region) N n-channel MIS • FET Formation region (first region) P p-channel type MIS • FET formation region (first region) PR PR15 photoresist pattern Qp p-channel type MIS • FET Qhn high breakdown voltage n-channel type MIS • FET Qln n channel type MIS • FET Qhp high breakdown voltage p-channel type MIS • FET Qlp p-channel type MIS • FET MC Memory cell

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/792 (72) Inventor Shiro Kambara 5-20-1 Kamimizumoto-cho, Kodaira-shi, Tokyo Stock company Hitachi, Ltd. Semiconductor Group (72) Inventor Nobue Nakajima 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Hitachi Ltd. Semiconductor Group (72) Inventor Kenichi Kuroda 5-chome, Mizumizumoto-cho, Kodaira-shi, Tokyo No. 1 F-term in semiconductor group, Hitachi, Ltd. (reference) 5F048 AA09 AB03 AC01 AC03 BA01 BB05 BB11 BB16 BE02 BE03 BG14 5F083 EP18 EP23 EP63 EP64 EP68 EP69 GA28 JA04 JA32 PR12 PR36 PR42 PR52 ZA12 5F101 BA45 BB05 B07 BD07 BD27 BD27 BD09

Claims (25)

[Claims] 1. A method of manufacturing a semiconductor device, comprising the steps of: (a) a step of forming a gate insulating film on a semiconductor substrate;
(B) a step of forming an n-type gate electrode on the gate insulating film, (c) a step of forming a p-channel type field effect transistor and an n-type gate electrode on the semiconductor substrate after the step (b). A step of forming a masking layer having openings formed therein, and (d) after the step (c), a channel is formed in the semiconductor substrate using the masking layer as a mask so that a buried channel is formed under the n-type gate electrode. Introducing impurities for use. 2. The method for manufacturing a semiconductor device according to claim 1, wherein an impurity for forming an n-type well is formed in a formation region of a p-channel type field effect transistor on the semiconductor substrate by using the masking layer as a mask. And a step of introducing impurities for forming p ⁻ type semiconductor regions for source and drain. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the masking layer is used as a mask to form an n-type well in a p-channel field-effect transistor formation region of the semiconductor substrate. And a step of introducing impurities for forming p ⁺ -type semiconductor regions for the source and drain. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity for channel formation is
A method of manufacturing a semiconductor device, comprising an impurity capable of forming a p-type semiconductor region on the semiconductor substrate. 5. A method of manufacturing a semiconductor device, comprising: (a) forming a masking layer on a semiconductor substrate, the masking layer covering the first region and opening the second region; (B) introducing an impurity for forming a well into the semiconductor substrate of the second region, (c) introducing an impurity for forming a channel into the semiconductor substrate of the second region, (d) above (a) )
After the steps (c) to (c), a step of forming a first gate insulating film on the semiconductor substrate in the first region; (e) After the steps (a) to (c), the first gate insulating film is formed on the semiconductor substrate in the second region. Forming a second gate insulating film thicker than one gate insulating film, (f)
A step of forming an n-type gate electrode on the first and second gate insulating films, (g) after the step (f), the second region is covered on the semiconductor substrate, and the first region is After forming a masking layer to be opened, using the masking layer as a mask, introducing an impurity for forming a channel of the field effect transistor in the first region into the semiconductor substrate. 6. The method for manufacturing a semiconductor device according to claim 5, wherein in the step (g), an impurity for forming a well is formed in the field effect transistor formation region of the semiconductor substrate using the masking layer as a mask. And a step of introducing an impurity for forming a low-impurity-concentration semiconductor region for a source and a drain. 7. The method for manufacturing a semiconductor device according to claim 5, wherein in the step (g), the masking layer is used as a mask to form an impurity for forming a well in a field effect transistor formation region of the semiconductor substrate. And a step of introducing an impurity for forming a high impurity concentration semiconductor region for a source and a drain, the method for manufacturing a semiconductor device. 8. The method of manufacturing a semiconductor device according to claim 5, 6 or 7, wherein the first region is a region for forming a field effect transistor for logic, and the second region is a field effect transistor for high breakdown voltage. A method of manufacturing a semiconductor device, comprising: 9. The method for manufacturing a semiconductor device according to claim 5, wherein the step (g) includes the following steps: the method for manufacturing a semiconductor device; After forming a masking layer covering the formation region of the n-channel type field effect transistor and opening the formation region of the p-channel type field effect transistor in one region, the masking layer is used as a mask to form the mask on the semiconductor substrate. A step of introducing an impurity for forming a channel in a p-channel field effect transistor. 10. The method for manufacturing a semiconductor device according to claim 5, wherein the step (g) includes the following steps: the method for manufacturing a semiconductor device; After forming a masking layer in which the formation region of the p-channel type field effect transistor is covered in one region and the formation region of the n-channel type field effect transistor is opened, the masking layer is used as a mask to form the mask on the semiconductor substrate. A step of introducing an impurity for forming a channel in the n-channel field effect transistor. 11. The method for manufacturing a semiconductor device according to claim 5, wherein the step (g) includes the following steps: the method for manufacturing a semiconductor device; After forming a masking layer covering the formation region of the n-channel type field effect transistor and opening the formation region of the p-channel type field effect transistor in one region, the masking layer is used as a mask to form the mask on the semiconductor substrate. a step of introducing an impurity for forming a channel in a p-channel type field effect transistor, the formation region of the p-channel type field effect transistor is covered with the first region, and the formation region of the n-channel type field effect transistor is opened. After forming a masking layer, the masking layer is used as a mask and the n-channel type electrode is applied to the semiconductor substrate. Introducing an impurity for forming the channel in effect transistors. 12. A method of manufacturing a semiconductor device, comprising the steps of: (a) forming a masking layer on a semiconductor substrate, the masking layer covering the first region and opening a formation region of a flash memory. (B) introducing impurities for forming wells into the semiconductor substrate in the flash memory forming region, (c) introducing impurities for forming channels into the semiconductor substrate in the flash memory forming region, (D) a step of forming a first gate insulating film on the semiconductor substrate in the first region after the steps (a) to (c),
(E) After the steps (a) to (c), a step of forming a third gate insulating film on the semiconductor substrate in the formation region of the flash memory, and (f) an n-type gate on the first gate insulating film. After the step (g) and the step (f) of forming an electrode, a masking layer is formed on the semiconductor substrate, the masking layer covering the formation region of the flash memory and opening the first region, and then forming the masking layer. Using the mask as a mask, introducing an impurity for forming a channel of the field effect transistor in the first region into the semiconductor substrate. 13. The method for manufacturing a semiconductor device according to claim 12, wherein in the step (g), an impurity for forming a well is formed in the field effect transistor formation region of the semiconductor substrate using the masking layer as a mask. And a step of introducing an impurity for forming a low-impurity-concentration semiconductor region for a source and a drain. 14. The method for manufacturing a semiconductor device according to claim 12, wherein in the step (g), an impurity for forming a well is formed in the field effect transistor formation region of the semiconductor substrate using the masking layer as a mask. And a step of introducing an impurity for forming a high impurity concentration semiconductor region for a source and a drain, the method for manufacturing a semiconductor device. 15. The method of manufacturing a semiconductor device according to claim 12, 13 or 14, wherein the first region is a formation region of a field effect transistor for logic. 16. The method of manufacturing a semiconductor device according to claim 12, wherein the step (g) includes the following steps: the method for manufacturing a semiconductor device; After forming a masking layer covering the formation region of the n-channel type field effect transistor and opening the formation region of the p-channel type field effect transistor in one region, the masking layer is used as a mask to form the mask on the semiconductor substrate. A step of introducing an impurity for forming a channel in a p-channel field effect transistor. 17. The method for manufacturing a semiconductor device according to claim 12, wherein the step (g) includes the following steps: the method for manufacturing a semiconductor device; After forming a masking layer in which the formation region of the p-channel type field effect transistor is covered in one region and the formation region of the n-channel type field effect transistor is opened, the masking layer is used as a mask to form the mask on the semiconductor substrate. A step of introducing an impurity for forming a channel in the n-channel field effect transistor. 18. The method of manufacturing a semiconductor device according to claim 12, wherein the step (g) includes the following steps: After forming a masking layer covering the formation region of the n-channel type field effect transistor and opening the formation region of the p-channel type field effect transistor in one region, the masking layer is used as a mask to form the mask on the semiconductor substrate. a step of introducing an impurity for forming a channel in a p-channel type field effect transistor, the formation region of the p-channel type field effect transistor is covered with the first region, and the formation region of the n-channel type field effect transistor is opened. And forming an n-channel type mask on the semiconductor substrate using the masking layer as a mask. Introducing an impurity for forming the channel in field effect transistors. 19. A method of manufacturing a semiconductor device, comprising: (a) a step of forming a gate insulating film on a semiconductor substrate;
(B) a step of forming an n-type gate electrode on the gate insulating film, (c) a masking layer in which a formation region of a p-channel type field effect transistor is opened on the semiconductor substrate after the step (b). And then, using the masking layer as a mask, introducing an impurity for forming a channel of a p-channel field effect transistor into the semiconductor substrate, (d) after the step (b), n is formed on the semiconductor substrate. A step of forming a masking layer in which a formation region of the channel type field effect transistor is opened, and then introducing an impurity for forming a channel of the n channel type field effect transistor into the semiconductor substrate using the masking layer as a mask. 20. The method of manufacturing a semiconductor device according to claim 19, wherein in the step (c), the n-type is formed in the formation region of the p-channel type field effect transistor on the semiconductor substrate using the masking layer as a mask. A method of manufacturing a semiconductor device, comprising at least one of a step of introducing an impurity for forming a well and a step of introducing an impurity for forming a p ⁻ type semiconductor region for a source and a drain. . 21. The method of manufacturing a semiconductor device according to claim 19, wherein in the step (c), an n-type field effect transistor is formed in the semiconductor substrate using the masking layer as a mask. A method of manufacturing a semiconductor device, comprising at least one of a step of introducing an impurity for forming a well and a step of introducing an impurity for forming a p ⁺ type semiconductor region for a source and a drain. . 22. The method of manufacturing a semiconductor device according to claim 19, wherein in the step (d), the masking layer is used as a mask, and a p-type field effect transistor is formed in a region where the n-channel field-effect transistor is formed on the semiconductor substrate. A method of manufacturing a semiconductor device, comprising at least one of a step of introducing an impurity for forming a well and a step of introducing an impurity for forming an n ⁻ type semiconductor region for a source and a drain. . 23. The method of manufacturing a semiconductor device according to claim 19, wherein in the step (d), the masking layer is used as a mask, and a p-type field effect transistor is formed in a region of the semiconductor substrate. A method of manufacturing a semiconductor device, comprising at least one of a step of introducing an impurity for forming a well and a step of introducing an impurity for forming an n ⁺ type semiconductor region for a source and a drain. . 24. The method for manufacturing a semiconductor device according to claim 19, wherein the channel forming impurities of the p-channel field effect transistor and the n-channel field effect transistor are the impurities. A method of manufacturing a semiconductor device, comprising an impurity capable of forming a p-type semiconductor region on a semiconductor substrate. 25. A method of manufacturing a semiconductor device, comprising the steps of: (a) forming a gate insulating film on a semiconductor substrate;
(B) a step of forming an n-type gate electrode on the gate insulating film, (c) after the step (b), a field effect transistor formation region and an n-type gate electrode are opened on the semiconductor substrate. Forming a masking layer, (d) introducing impurities for forming a channel into the semiconductor substrate using the masking layer as a mask so that a channel is formed under the n-type gate electrode after the step (c). The process of doing.