JP2003017701A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2003017701A JP2003017701A JP2001203590A JP2001203590A JP2003017701A JP 2003017701 A JP2003017701 A JP 2003017701A JP 2001203590 A JP2001203590 A JP 2001203590A JP 2001203590 A JP2001203590 A JP 2001203590A JP 2003017701 A JP2003017701 A JP 2003017701A
- Authority
- JP
- Japan
- Prior art keywords
- region
- source
- drift layer
- type base
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
- H10D12/411—Insulated-gate bipolar transistors [IGBT]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
- H10D12/411—Insulated-gate bipolar transistors [IGBT]
- H10D12/441—Vertical IGBTs
- H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
- H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
- H10D84/141—VDMOS having built-in components
- H10D84/146—VDMOS having built-in components the built-in components being Schottky barrier diodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/663—Vertical DMOS [VDMOS] FETs having both source contacts and drain contacts on the same surface, i.e. up-drain VDMOS
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
- H10D64/251—Source or drain electrodes for field-effect devices
- H10D64/256—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies
Landscapes
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
(57)【要約】
【課題】小型化と低コスト化を実現することができる半
導体装置を提供する。
【解決手段】半導体基板１におけるＮ-ドリフト層３の
表層部にセル毎のＰ型ベース領域５が形成されるととも
に、Ｐ型ベース領域５での表層部にＮ+ソース領域１０
が形成され、さらに、Ｐ型ベース領域５の一部領域およ
びソース領域１０の一部領域に対しゲート絶縁膜６を介
してゲート電極７ａ，７ｂが配置されるとともに、Ｐ型
ベース領域５の一部領域およびソース領域１０の一部領
域と接するソース電極８が設けられている。セル毎のＰ
型ベース領域５の間において半導体基板１の上面にドリ
フト層３が露出しており、ソース電極８とショットキー
接触してボディダイオード１３を形成している。
(57) [Problem] To provide a semiconductor device capable of realizing size reduction and cost reduction. A P-type base region for each cell is formed in a surface portion of an N − drift layer in a semiconductor substrate, and an N + source region is formed in a surface portion of the P-type base region.
Are formed. Further, gate electrodes 7a and 7b are arranged via a gate insulating film 6 with respect to a partial region of P-type base region 5 and a partial region of source region 10, and one region of P-type base region 5 is formed. A source electrode 8 in contact with the partial region and a part of the source region 10 is provided. P per cell
The drift layer 3 is exposed on the upper surface of the semiconductor substrate 1 between the mold base regions 5 and forms a body diode 13 in Schottky contact with the source electrode 8.
Description
【０００１】[0001]
【発明の属する技術分野】この発明は半導体装置に係
り、詳しくはパワーＭＯＳトランジスタに関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a power MOS transistor.
【０００２】[0002]
【従来の技術】従来、図７に示すように、縦型パワーＭ
ＯＳＦＥＴを形成したチップ１００とは別に、当該ＭＯ
ＳＦＥＴの電流容量に適したショットキーバリアダイオ
ードを形成したチップ２００を用意し、図８に示すよう
に、基板の上にパワーＭＯＳＦＥＴを形成したチップ１
００とショットキーバリアダイオードを形成したチップ
２００を配置し、パワーＭＯＳＦＥＴに対し配線３０
１，３０２によりショットキーバリアダイオードを外付
けにて接続していた。2. Description of the Related Art Conventionally, as shown in FIG.
In addition to the chip 100 on which the OSFET is formed, the MO
A chip 200 having a Schottky barrier diode suitable for the current capacity of an SFET is prepared, and as shown in FIG. 8, a chip 1 having a power MOSFET formed on a substrate.
00 and a chip 200 formed with a Schottky barrier diode are arranged, and wiring 30 is provided for the power MOSFET.
The Schottky barrier diode was externally connected with 1,302.
【０００３】しかし、この場合には２チップであるので
基板の占有面積が大きくなり、部品コスト及び組み付け
コストを含めたトータルコストが高くなる。特に、１０
０アンペア以上の大電流システムでは、チップサイズが
特に大きくなるために、この問題が顕在化する。However, in this case, since the number of chips is two, the area occupied by the substrate becomes large, and the total cost including the component cost and the assembly cost becomes high. Especially 10
In a high current system of 0 ampere or more, this problem becomes apparent because the chip size becomes particularly large.
【０００４】[0004]
【発明が解決しようとする課題】本発明はこのような背
景の下になされたものであり、その目的は、小型化と低
コスト化を実現することができる半導体装置を提供する
ことにある。SUMMARY OF THE INVENTION The present invention has been made under such a background, and an object thereof is to provide a semiconductor device capable of realizing miniaturization and cost reduction.
【０００５】[0005]
【課題を解決するための手段】請求項１に記載の発明
は、セル毎のベース領域の間において半導体基板の上面
にドリフト層を露出させ、露出させたドリフト層とソー
スまたはエミッタ電極をショットキー接触させてボディ
ダイオードを形成したことを特徴としている。よって、
ワンチップ内に、パワーＭＯＳＦＥＴに加えてショット
キーバリアダイオードがボディダイオードとして形成さ
れ、小型化と低コスト化を実現することができる。According to a first aspect of the present invention, a drift layer is exposed on an upper surface of a semiconductor substrate between base regions of cells, and the exposed drift layer and the source or emitter electrode are Schottky. The feature is that the body diode is formed by contacting with each other. Therefore,
In addition to the power MOSFET, a Schottky barrier diode is formed as a body diode in one chip, and it is possible to realize miniaturization and cost reduction.
【０００６】また、請求項２に記載のように、セル間に
おいてトランジスタ・オフ時に形成される空乏層が重な
る部位でドリフト層とソースまたはエミッタ電極をショ
ットキー接触させることにより、逆バイアス印加時には
ＰＮ接合の空乏層が広がり、電界緩和効果によりダイオ
ードには高電圧が印加されないようにすることができ
る。According to a second aspect of the present invention, the drift layer and the source or emitter electrode are in Schottky contact at a portion where depletion layers formed when the transistor is turned off overlaps between cells, so that PN is applied when a reverse bias is applied. The depletion layer of the junction expands, and a high voltage can be prevented from being applied to the diode due to the electric field relaxation effect.
【０００７】さらに、請求項３に記載のように、半導体
基板の上面に凹部を形成し、この凹部の底面においてド
リフト層とソースまたはエミッタ電極をショットキー接
触させると、セルサイズ拡大と寄生バイポーラトランジ
スタ動作を抑制することができる。Further, when a recess is formed in the upper surface of the semiconductor substrate and the drift layer and the source or emitter electrode are in Schottky contact with the bottom surface of the recess, the cell size is expanded and the parasitic bipolar transistor is formed. The operation can be suppressed.
【０００８】[0008]
【発明の実施の形態】（第１の実施の形態）以下、この
発明を具体化した第１の実施の形態を図面に従って説明
する。BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings.
【０００９】図１には、本実施の形態における半導体装
置の縦断面を示す。本例ではトレンチゲートタイプの縦
型パワーＭＯＳＦＥＴに適用している。Ｎ+シリコン基
板２の上にＮ-ドリフト層（Ｎ-シリコン層）３が形成さ
れ、半導体基板１を構成している。Ｎ-ドリフト層３
（半導体基板１）の上面表層部にはセル毎のＰ型ベース
領域５が離間して形成されている。換言すると、Ｎ-ド
リフト層３の表層部においてセル間にＰ型ベース領域５
を形成しない領域を設けている。FIG. 1 shows a vertical cross section of the semiconductor device according to the present embodiment. This example is applied to a trench gate type vertical power MOSFET. An N − drift layer (N − silicon layer) 3 is formed on the N + silicon substrate 2 to form the semiconductor substrate 1. N - drift layer 3
P-type base regions 5 for each cell are formed separately on the upper surface layer of the (semiconductor substrate 1). In other words, the P-type base region 5 is formed between the cells in the surface layer portion of the N − drift layer 3.
A region is formed in which no
【００１０】各セルでのＰ型ベース領域５の表層部には
Ｎ+ソース領域１０がＰ型ベース領域５よりも浅く形成
されている。また、半導体基板１の上面にはトレンチ４
が形成され、トレンチ４はＮ+ソース領域１０およびＰ
型ベース領域５を貫通してＮ-ドリフト層３に達してい
る。An N + source region 10 is formed shallower than the P type base region 5 in the surface layer portion of the P type base region 5 in each cell. In addition, the trench 4 is formed on the upper surface of the semiconductor substrate 1.
Is formed, the trench 4 is formed into the N + source region 10 and P
It penetrates through the mold base region 5 and reaches the N − drift layer 3.
【００１１】トレンチ４の内壁面にはゲート酸化膜（ゲ
ート絶縁膜）６が形成され、その内部にはゲート電極７
ａが埋め込まれている。さらに、トレンチ４の開口部に
おいてゲート電極７ａの上にはゲート電極７ｂが形成さ
れている。このようにして、Ｐ型ベース領域５の一部領
域およびＮ+ソース領域１０の一部領域に対しゲート絶
縁膜６を介してゲート電極７ａ，７ｂが配置されてい
る。A gate oxide film (gate insulating film) 6 is formed on the inner wall surface of the trench 4, and a gate electrode 7 is formed inside thereof.
a is embedded. Further, a gate electrode 7b is formed on the gate electrode 7a in the opening of the trench 4. In this way, the gate electrodes 7a and 7b are arranged in the partial region of the P-type base region 5 and the partial region of the N + source region 10 with the gate insulating film 6 interposed therebetween.
【００１２】半導体基板１の上面にはソース電極８が設
けられ、ソース電極８はＰ型ベース領域５の一部領域お
よびＮ+ソース領域１０の一部領域と接している。同時
に、半導体基板１の上面におけるセル間のＮ-ドリフト
層３が露出する部位において、ソース電極８をショット
キー接触させている。これにより、ショットキーバリア
ダイオード１３が形成されている。このように縦型パワ
ーＭＯＳＦＥＴのセル間にＰ型ベース領域５を拡散しな
い部分を形成し、この部分（Ｎ-ドリフト層３が露出す
る部分）にショットキーバリアダイオード１３を形成し
ている。A source electrode 8 is provided on the upper surface of the semiconductor substrate 1, and the source electrode 8 is in contact with a partial region of the P type base region 5 and a partial region of the N + source region 10. At the same time, the source electrode 8 is in Schottky contact with the portion of the upper surface of the semiconductor substrate 1 where the N − drift layer 3 between cells is exposed. Thereby, the Schottky barrier diode 13 is formed. In this way, the portion where the P-type base region 5 is not diffused is formed between the cells of the vertical power MOSFET, and the Schottky barrier diode 13 is formed in this portion (the portion where the N − drift layer 3 is exposed).
【００１３】また、基板１の下面において全面にドレイ
ン電極９が形成されている。この素子の等価回路は、図
２に示すように、ワンチップ内において縦型パワーＭＯ
ＳＦＥＴ１２に対しショットキーバリアダイオード（内
蔵ショットキーバリアダイオード）１３が並列に接続さ
れた構成となる。A drain electrode 9 is formed on the entire lower surface of the substrate 1. As shown in FIG. 2, the equivalent circuit of this element has a vertical power MO in one chip.
A Schottky barrier diode (built-in Schottky barrier diode) 13 is connected in parallel to the SFET 12.
【００１４】以上のように本実施形態においては、セル
毎のＰ型ベース領域５の間において半導体基板１の上面
にＮ-ドリフト層３を露出させ、露出させたＮ-ドリフト
層３とソース電極８をショットキー接触させてボディダ
イオード１３を形成した。よって、ワンチップ内に、縦
型パワーＭＯＳＦＥＴ１２に加えてショットキーバリア
ダイオード１３がボディダイオードとして形成され、小
型化と低コスト化を実現することができる。また、ショ
ットキーバリアダイオード１３は高速フライホイールダ
イオードとして優れた性能を持ち、Ｌ負荷スイッチング
性能に優れた縦型パワーＭＯＳＦＥＴとなる。さらに、
図１のセル間においてトランジスタ・オフ時に形成され
る空乏層が重なる部位でＮ-ドリフト層３とソース電極
８をショットキー接触させている。よって、ショットキ
ーバリアダイオードは、逆バイアス印加時に電流が漏れ
やすいが、本実施形態の構造ではショットキーバリアダ
イオード１３は狭い間隔Ｗ１でＰ型ベース領域（Ｐ型拡
散層）５，５間で囲まれ、逆バイアス印加時に広がった
空乏層が左右に重なることになり、電界緩和効果により
印加電圧が低減され、漏れ電流が抑えられる。つまり、
逆バイアス印加時にはＰＮ接合の空乏層が広がり、電界
緩和効果によりダイオードには高電圧が印加されない。
（第２の実施の形態）次に、第２の実施の形態を、第１
の実施の形態との相違点を中心に説明する。As described above, in the present embodiment, the N − drift layer 3 is exposed on the upper surface of the semiconductor substrate 1 between the P type base regions 5 of each cell, and the exposed N − drift layer 3 and the source electrode are exposed. 8 was brought into Schottky contact to form a body diode 13. Therefore, in addition to the vertical power MOSFET 12, the Schottky barrier diode 13 is formed as a body diode in one chip, and downsizing and cost reduction can be realized. Further, the Schottky barrier diode 13 has excellent performance as a high-speed flywheel diode, and becomes a vertical power MOSFET excellent in L load switching performance. further,
The N − drift layer 3 and the source electrode 8 are in Schottky contact at the portion where the depletion layer formed when the transistor is turned off overlaps between the cells in FIG. Therefore, in the Schottky barrier diode, a current easily leaks when a reverse bias is applied, but in the structure of the present embodiment, the Schottky barrier diode 13 is surrounded by the P-type base regions (P-type diffusion layers) 5 and 5 at a narrow interval W1. As a result, the depletion layers that spread when a reverse bias is applied overlap left and right, the applied voltage is reduced due to the electric field relaxation effect, and the leakage current is suppressed. That is,
When a reverse bias is applied, the depletion layer of the PN junction expands, and a high voltage is not applied to the diode due to the electric field relaxation effect. (Second Embodiment) Next, the second embodiment will be described with reference to the first embodiment.
The difference from the above embodiment will be mainly described.
【００１５】図３には、図１に代わる本実施の形態での
構造を示す。図１に示した第１の実施形態のように基板
１の表面にＰ型ベース領域５を形成しない領域を作る
と、このためのＰ型ベース領域（拡散領域）５の抵抗成
分（Ｒ分）が余分に必要となり、セルサイズが大きくな
り、ＤＭＯＳのオン抵抗が大きくなってしまう。セルサ
イズがどの程度拡大するか見積もってみると、例えば、
Ｐ型ベース領域５の拡散深さを１．５μｍとすると、こ
れによるセルサイズの増加は１．５μｍ×０．９（横広
がり係数）×２＝２．７μｍとなる。従来構造で４μｍ
の場合、この構造では６．７μｍとなり、計算の結果、
オン抵抗は約２０％増加する。また、ショットキーバリ
アダイオード接続部近傍でのＮＰＮ寄生トランジスタの
ベース長さが短いため、寄生動作し易い構造となってい
る。FIG. 3 shows the structure of the present embodiment, which is an alternative to FIG. When a region in which the P-type base region 5 is not formed is formed on the surface of the substrate 1 as in the first embodiment shown in FIG. 1, the resistance component (R component) of the P-type base region (diffusion region) 5 for this is formed. Are additionally required, the cell size becomes large, and the ON resistance of the DMOS becomes large. When estimating how much the cell size will increase, for example,
When the diffusion depth of the P-type base region 5 is 1.5 μm, the increase in cell size due to this is 1.5 μm × 0.9 (lateral spread coefficient) × 2 = 2.7 μm. 4 μm with conventional structure
In this case, this structure has a size of 6.7 μm.
The on-resistance increases by about 20%. In addition, since the base length of the NPN parasitic transistor near the Schottky barrier diode connection portion is short, the structure facilitates parasitic operation.
【００１６】そこで、図３に示す本実施の形態の構造で
は、半導体基板１の上面でのショットキーバリアダイオ
ード形成箇所に凹部２０を形成し、この凹部２０の底面
においてＮ-ドリフト層３とソース電極８をショットキ
ー接触させている。これにより、Ｐ型ベース領域５は深
さ方向において深くなるほど隣接するＰ型ベース領域５
との距離が大きくなり、上記のセルサイズ拡大を抑制す
ることができるとともに、Ｎ+ソース領域１０とＮ-ドリ
フト層３を離間させてＮＰＮ寄生トランジスタのベース
長さを長くしてＮＰＮ寄生トランジスタ動作を抑制する
ことができる。Therefore, in the structure of the present embodiment shown in FIG. 3, a recess 20 is formed in the Schottky barrier diode formation position on the upper surface of the semiconductor substrate 1, and the N − drift layer 3 and the source are formed on the bottom of the recess 20. The electrode 8 is in Schottky contact. As a result, the P-type base regions 5 are adjacent to each other as they become deeper in the depth direction.
And the N + source region 10 and the N − drift layer 3 are separated from each other to increase the base length of the NPN parasitic transistor to operate the NPN parasitic transistor. Can be suppressed.
【００１７】なお、凹部２０の深さについては、トラン
ジスタ・オフ時に形成される空乏層が重なる部分（高さ
Ｈ１）よりも深くすると前述の電界緩和効果が得られに
くいので、空乏層が重なる部分（Ｈ１）よりも浅くする
のが望ましい。If the depth of the recess 20 is deeper than the portion (height H1) where the depletion layer formed when the transistor is turned off overlaps, it is difficult to obtain the above-mentioned electric field relaxation effect, so that the portion where the depletion layer overlaps is difficult to obtain. It is desirable to make it shallower than (H1).
【００１８】第１，２の実施形態以外にも、図４に示す
ようにアップドレイン型のＤＭＯＳトランジスタに適用
してもよい。図４のアップドレイン型のＤＭＯＳトラン
ジスタの場合、セル群の外周部にディープＮ+領域（ド
レイン領域）１４が形成されている。Besides the first and second embodiments, it may be applied to an up-drain type DMOS transistor as shown in FIG. In the case of the up-drain type DMOS transistor of FIG. 4, a deep N + region (drain region) 14 is formed in the outer peripheral portion of the cell group.
【００１９】あるいは、図５に示すようにＬＤＭＯＳト
ランジスタや図６に示すようにＩＧＢＴに適用してもよ
い。図５のＬＤＭＯＳトランジスタの場合、半導体基板
２９のＮ-ドリフト層３０の上面表層部にはＰ型ベース
領域３１が形成されている。Ｐ型ベース領域３１の表層
部にはＮ+ソース領域３３がＰ型ベース領域３１よりも
浅く形成されている。半導体基板２９の上面においてＰ
型ベース領域３１の一部領域およびＮ+ソース領域３３
の一部領域に対しゲート絶縁膜３５を介してゲート電極
３６が配置されている。また、基板２９の上面において
Ｐ型ベース領域３１の一部領域およびＮ+ソース領域３
３の一部領域と接するソース電極３７が設けられてい
る。一方、半導体基板２９の上面の表層部にＰ領域３２
が形成されるとともにＰ領域３２の表層部にＮ+領域３
４が形成され、半導体基板２９の上面においてＮ+領域
３４に接触するようにドレイン電極３８が形成されてい
る。半導体基板２９の上面におけるセル間（Ｐ型ベース
領域３１，３１の間）においてトレンチ３９が形成さ
れ、トレンチ３９の内部にはソース電極３７が配置され
ている。よって、トレンチ３９の底面においてソース電
極３７がＮ-ドリフト層３０とショットキーバリア接触
している。このようにして、セル毎のＰ型ベース領域３
１の間において半導体基板２９の上面にドリフト層３０
が露出してソース電極３７とＮ-ドリフト層３０をショ
ットキー接触させている。Alternatively, it may be applied to an LDMOS transistor as shown in FIG. 5 or an IGBT as shown in FIG. In the case of the LDMOS transistor of FIG. 5, a P-type base region 31 is formed on the upper surface layer of the N − drift layer 30 of the semiconductor substrate 29. An N + source region 33 is formed shallower than the P type base region 31 in the surface layer portion of the P type base region 31. P on the upper surface of the semiconductor substrate 29
Partial region of the mold base region 31 and N + source region 33
A gate electrode 36 is disposed on a partial region of the gate insulating film 35. Further, on the upper surface of the substrate 29, a partial region of the P-type base region 31 and the N + source region 3 are formed.
A source electrode 37 is provided that is in contact with a partial region of No. 3. On the other hand, the P region 32 is formed on the surface layer of the upper surface of the semiconductor substrate 29.
And the N + region 3 is formed on the surface of the P region 32.
4 is formed, and the drain electrode 38 is formed so as to contact the N + region 34 on the upper surface of the semiconductor substrate 29. A trench 39 is formed between cells (between the P-type base regions 31, 31) on the upper surface of the semiconductor substrate 29, and a source electrode 37 is arranged inside the trench 39. Therefore, the source electrode 37 is in Schottky barrier contact with the N − drift layer 30 on the bottom surface of the trench 39. In this way, the P-type base region 3 for each cell is
Drift layer 30 on the upper surface of the semiconductor substrate 29 between
Is exposed and the source electrode 37 and the N − drift layer 30 are in Schottky contact.
【００２０】このようにＬＤＭＯＳトランジスタのセル
間にＰ型ベース領域３１を拡散しない部分を形成し、こ
の部分にショットキーバリアダイオード４０を形成す
る。また、図６のＩＧＢＴの場合、セルの間（Ｐ型ベー
ス領域５，５間）にショットキーバリアダイオード１３
が形成されている。図６のようにＩＧＢＴに適用する場
合においては、図１でのソース電極（ソース領域）がエ
ミッタ電極（エミッタ領域）となり、ドレイン電極がコ
レクタ電極となる。また、図６において、チップ外周縁
（セル群の外周部）には等電位リング（ＥＱＲ）４１が
配置され、等電位リング（ＥＱＲ）４１はその下のＮ+
領域４２を介して基板側と電気的に接続されるとともに
コレクタ電極９とワイヤを介して接続されている。In this way, a portion where the P-type base region 31 is not diffused is formed between the cells of the LDMOS transistor, and the Schottky barrier diode 40 is formed in this portion. In the case of the IGBT shown in FIG. 6, the Schottky barrier diode 13 is provided between the cells (between the P-type base regions 5 and 5).
Are formed. In the case of applying to the IGBT as shown in FIG. 6, the source electrode (source region) in FIG. 1 becomes the emitter electrode (emitter region) and the drain electrode becomes the collector electrode. Further, in FIG. 6, an equipotential ring (EQR) 41 is arranged on the outer peripheral edge of the chip (outer peripheral portion of the cell group), and the equipotential ring (EQR) 41 is under N +.
It is electrically connected to the substrate side via the region 42 and is also connected to the collector electrode 9 via a wire.
【図１】第１の実施の形態における半導体装置の縦断面
図。FIG. 1 is a vertical sectional view of a semiconductor device according to a first embodiment.
【図２】第１の実施の形態における半導体装置の等価回
路図。FIG. 2 is an equivalent circuit diagram of the semiconductor device according to the first embodiment.
【図３】第２の実施の形態における半導体装置の縦断面
図。FIG. 3 is a vertical sectional view of a semiconductor device according to a second embodiment.
【図４】別例における半導体装置の縦断面図。FIG. 4 is a vertical cross-sectional view of a semiconductor device according to another example.
【図５】別例における半導体装置の縦断面図。FIG. 5 is a vertical cross-sectional view of a semiconductor device according to another example.
【図６】別例における半導体装置の縦断面図。FIG. 6 is a vertical cross-sectional view of a semiconductor device according to another example.
【図７】従来技術を説明するための半導体装置の縦断面
図。FIG. 7 is a vertical cross-sectional view of a semiconductor device for explaining a conventional technique.
【図８】従来技術を説明するための半導体装置の等価回
路図。FIG. 8 is an equivalent circuit diagram of a semiconductor device for explaining a conventional technique.
１…半導体基板、３…ドリフト層、５…Ｐ型ベース領
域、６…ゲート絶縁膜、７ａ，７ｂ…ゲート電極、８…
ソース電極、１０…ソース領域、２０…凹部、２９…半
導体基板、３０…ドリフト層、３１…Ｐ型ベース領域、
３３…ソース領域、３５…ゲート絶縁膜、３６…ゲート
電極、３７…ソース電極1 ... Semiconductor substrate, 3 ... Drift layer, 5 ... P-type base region, 6 ... Gate insulating film, 7a, 7b ... Gate electrode, 8 ...
Source electrode, 10 ... Source region, 20 ... Recessed portion, 29 ... Semiconductor substrate, 30 ... Drift layer, 31 ... P-type base region,
33 ... Source region, 35 ... Gate insulating film, 36 ... Gate electrode, 37 ... Source electrode
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 29/872 Ｈ０１Ｌ 29/78 ３０１Ｄ 29/48 Ｐ Ｆターム(参考） 4M104 AA01 CC03 GG09 GG10 GG14 GG18 HH14 HH20 5F140 AA00 AA17 AA25 AB05 AB06 AC21 AC23 AC24 BD19 BF43 BF44 BH30 BJ25 BJ26 BJ30 CB07 ─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 7 Identification code FI theme code (reference) H01L 29/872 H01L 29/78 301D 29/48 PF term (reference) 4M104 AA01 CC03 GG09 GG10 GG14 GG18 HH14 HH20 5F140 AA00 AA17 AA25 AB05 AB06 AC21 AC23 AC24 BD19 BF43 BF44 BH30 BJ25 BJ26 BJ30 CB07
Claims (3)
電型のドリフト層（３，３０）の表層部にセル毎の第２
導電型のベース領域（５，３１）が形成されるととも
に、当該ベース領域（５，３１）での表層部に第１導電
型のソースまたはエミッタ領域（１０，３３）が形成さ
れ、さらに、ベース領域（５，３１）の一部領域および
ソースまたはエミッタ領域（１０，３３）の一部領域に
対しゲート絶縁膜（６，３５）を介してゲート電極（７
ａ，７ｂ，３６）が配置されるとともに、ベース領域
（５，３１）の一部領域およびソースまたはエミッタ領
域（１０，３３）の一部領域と接するソースまたはエミ
ッタ電極（８，３７）が設けられたパワーＭＯＳトラン
ジスタであって、 セル毎のベース領域（５，３１）の間において半導体基
板（１，２９）の上面にドリフト層（３，３０）を露出
させ、露出させたドリフト層（３，３０）とソースまた
はエミッタ電極（８，３７）をショットキー接触させて
ボディダイオード（１３，４０）を形成したことを特徴
とする半導体装置。1. A second layer for each cell is provided on a surface layer portion of a drift layer (3, 30) of a first conductivity type in a semiconductor substrate (1, 29).
A conductive type base region (5, 31) is formed, and a first conductive type source or emitter region (10, 33) is formed in a surface layer portion of the base region (5, 31). A gate electrode (7) is provided to a partial region of the region (5, 31) and a partial region of the source or emitter region (10, 33) via a gate insulating film (6, 35).
a, 7b, 36) and a source or emitter electrode (8, 37) in contact with a partial region of the base region (5, 31) and a partial region of the source or emitter region (10, 33). And a drift layer (3, 30) exposed on the upper surface of the semiconductor substrate (1, 29) between the base regions (5, 31) of each cell. , 30) and the source or emitter electrode (8, 37) are in Schottky contact to form a body diode (13, 40).
形成される空乏層が重なる部位でドリフト層（３）とソ
ースまたはエミッタ電極（８）をショットキー接触させ
たことを特徴とする請求項１に記載の半導体装置。2. The drift layer (3) is in Schottky contact with the source or emitter electrode (8) at a portion where depletion layers formed when the transistor is turned off overlaps between cells. Semiconductor device.
０）を形成し、この凹部（２０）の底面においてドリフ
ト層（３）とソースまたはエミッタ電極（８）をショッ
トキー接触させたことを特徴とする請求項１または２に
記載の半導体装置。3. A recess (2) is formed on the upper surface of the semiconductor substrate (1).
0) is formed, and the drift layer (3) is in Schottky contact with the source or emitter electrode (8) on the bottom surface of the recess (20).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001203590A JP2003017701A (en) | 2001-07-04 | 2001-07-04 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001203590A JP2003017701A (en) | 2001-07-04 | 2001-07-04 | Semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| JP2003017701A true JP2003017701A (en) | 2003-01-17 |
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ID=19040199
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001203590A Pending JP2003017701A (en) | 2001-07-04 | 2001-07-04 | Semiconductor device |
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| Country | Link |
|---|---|
| JP (1) | JP2003017701A (en) |
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