JP2003016049A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of evaluating and pre- producing without developing a microprocessor with a built-in flash memory and capable of modifying a program in an early stage of mass production. SOLUTION: A microprocessor 1 with a built-in mask ROM(read only memory) and a flash memory 4 are composed of individual chips and both of the microprocessor 1 and the memory 4 are connected oppositely via bumped electrodes 5. The microprocessor 1 has a recognition circuit 6 to recognize a connection of a flash memory 4. A CPU(central processing unit) of the microprocessor 1 determines presence of the connection by a recognizing signal from the circuit 6, if the presence is determined, the microprocessor 1 interrupts data access to the mask ROM to enable data access to the memory 4 and operates according to the program in the memory 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more specifically, to a semiconductor in which an electrically rewritable nonvolatile memory such as a flash memory is mounted on a microcomputer (hereinafter referred to as a microcomputer). It relates to the device.

[0002]

2. Description of the Related Art A microcomputer incorporated in an electronic device product requires an operation program stored in a ROM (read only memory) when controlling the operation of the microcomputer and the operation of the entire electronic device. A mass-produced microcomputer product usually has a built-in mask ROM suitable for mass production in terms of price and configuration (hereinafter referred to as a mask ROM built-in microcomputer).
FIG. 7A is a plan view of a mask ROM built-in microcomputer 101 including a central processing unit (hereinafter, referred to as CPU (central processing unit)) 102 and a mask ROM 103 mounted on the same semiconductor chip. It is shown. An operation program is written in the mask ROM 103 at the manufacturing stage of a semiconductor wafer. This mask R
The OM 103 is a read-only memory and cannot rewrite the program written at the manufacturing stage.

However, in the evaluation / trial production of electronic equipment products in which a microcomputer is incorporated and in the initial stage of mass production, it is necessary to frequently change programs. Conventionally, at the stage where such a program change occurs, the program is changed by using a microcomputer having an electrically rewritable flash memory (hereinafter referred to as a flash memory built-in microcomputer) without using a mask ROM built-in microcomputer. Was possible. FIG. 7B shows a plan view of a flash memory built-in microcomputer 111 configured by mounting a CPU 112 and a flash memory 113 on the same semiconductor chip.
Since the program in the memory can be changed by using the flash memory built-in microcomputer 111, it is very effective in the evaluation / trial production of electronic equipment products and in the initial stage of mass production.

For these reasons, conventionally, a microcomputer with a built-in flash memory is used at the stage when the program needs to be corrected, and mass production is carried out with a microcomputer with a built-in mask ROM after the program is fixed.

[0005]

However, when using a microcomputer with a built-in flash memory at the stage where the program needs to be modified, the microcomputer developer must use a microcomputer with a built-in flash memory according to the product type of the mask ROM built-in microcomputer to be mass-produced. Had to develop. Therefore, two microcomputers, a mask ROM built-in microcomputer and a flash memory built-in microcomputer, are to be developed, and there is a problem that the development cost becomes high.

Further, the flash memory is a mask ROM
Compared with, the manufacturing process is complicated and the technical barrier is high, so the development and manufacturing costs tend to be high. For example, in forming a memory cell of a flash memory,
Compared to the microcomputer manufacturing process, there are many heat treatments, and it is necessary to form high-voltage transistors. Therefore, it is difficult to combine these steps with the manufacturing process of the microcomputer to form the flash memory on the same semiconductor chip as the microcomputer. In addition, flash memory microcomputers are used in small quantities because they are mainly used in the evaluation / trial production and early stages of mass production. Therefore, it is not easy to reduce the cost of the chip itself.

The present invention is directed to solving these problems.
An object of the present invention is to provide a semiconductor device capable of performing evaluation / trial manufacture and program modification at an early stage of mass production without developing a microcomputer with a built-in flash memory, and realizing a significant reduction in development cost.

[0008]

In order to achieve the above object, the semiconductor device of the present invention comprises at least a CPU and an R.
A microcomputer having an OM and having external electrodes used for connection to an electrically rewritable non-volatile memory formed by another chip, and whether or not the non-volatile memory is connected to the microcomputer. And a recognition circuit for generating a recognition signal indicating

According to this structure, an electrically rewritable nonvolatile memory composed of a chip different from the microcomputer can be connected to the microcomputer via the external electrodes of the microcomputer, so that evaluation / trial manufacture or It is possible to change the electrical program in the initial stage of mass production. Moreover, since this nonvolatile memory is externally connected to the microcomputer, it can be removed from the microcomputer. Therefore, evaluation /
The nonvolatile memory is removed after the trial production and the initial stage of mass production, and the confirmed program is rewritten in the ROM in the microcomputer.
If it is stored in, the configuration similar to the mass-produced product can be obtained. Therefore, the product manufactured as a prototype can be treated as a mass-produced product after the evaluation / trial production and the initial stage of mass production.

The semiconductor device of the present invention is composed of a microcomputer having at least a CPU and a ROM therein, and a chip different from the microcomputer, and is electrically rewritable nonvolatile memory connected to the microcomputer by an external electrode. Sex memory,
It may be configured to include a recognition circuit that generates a recognition signal indicating whether the nonvolatile memory is connected to the microcomputer.

According to this structure, since the electrically rewritable nonvolatile memory is provided, it is possible to electrically change the program in the evaluation / trial production or the initial stage of mass production. Furthermore, since the nonvolatile memory is composed of a chip separate from the microcomputer and is connected to the microcomputer by external electrodes, it can be removed after the evaluation / trial production or the initial stage of mass production. Therefore, the nonvolatile memory is removed after the evaluation / trial production or the initial stage of mass production, and the determined program is stored again in the ROM in the microcomputer, so that the same configuration as the mass-produced product can be obtained. Therefore, after the evaluation / trial production and the initial stage of mass production, the nonvolatile memory can be removed and the product can be handled as a mass-produced product.

As described above, according to the semiconductor device of the present invention, even if a microcomputer with a built-in flash memory is not developed,
It is possible to change the electrical program at the initial stage of evaluation / trial production and mass production, and the development cost can be significantly reduced.

Further, in the case of the configuration of the present invention, if the nonvolatile memory is developed as a single chip, it can be combined with a plurality of types of microcomputers, so that the development cost can be reduced. Further, if a single chip of a non-volatile memory having a different storage capacity is easily prepared, it is possible to easily realize a microcomputer product having a storage capacity required by the user for one type of microcomputer.

Further, in the semiconductor device of the present invention, when the recognition signal indicates a connection between the nonvolatile memory and the microcomputer, data access between the CPU and the ROM is cut off, and the CPU and the nonvolatile memory. It is preferable to be configured so that the data access to and can be performed.

According to this structure, it is possible to read data from the non-volatile memory to the CPU and rewrite data in the non-volatile memory by the CPU while the non-volatile memory is connected to the microcomputer.

Further, the semiconductor device of the present invention is the RO
A configuration in which M stores a switching program for controlling an operation of switching the data access destination of the CPU according to the recognition signal, and the CPU performs an operation of switching the data access destination by the switching program. Alternatively, by further comprising a control circuit that controls switching of the data access destination of the CPU according to the recognition signal, the CP when the nonvolatile memory is connected to the microcomputer.
It is possible to realize an operation of interrupting data access between U and the ROM and enabling data access between the CPU and the nonvolatile memory.

Further, in the semiconductor device of the present invention, the RO
M stores a write program for controlling a write operation to the non-volatile memory, the CPU and the ROM can access data when rewriting data in the non-volatile memory, and the CPU writes the write program. Therefore, it is preferable to rewrite the data in the nonvolatile memory.

It is preferable that the semiconductor device of the present invention further comprises an identification circuit for generating an identification signal for identifying the type of the non-volatile memory. According to this configuration,
It is also possible to change the control of the write operation to the nonvolatile memory according to the type of the connected nonvolatile memory. For example, the ROM stores a plurality of write programs for controlling a write operation to the non-volatile memory, the CPU and the ROM can access data when rewriting the data in the non-volatile memory, and the CPU By selecting a write program corresponding to the type of the non-volatile memory from the ROM according to the identification signal and rewriting the data of the non-volatile memory by the selected write program,
Since the write operation can be executed by the operation program according to the type of the nonvolatile memory, it is possible to use a plurality of types of nonvolatile memories without being limited to the type.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1A is a sectional view showing a schematic structure of the semiconductor device according to the present embodiment. As shown in FIG. 1A, in the semiconductor device of this embodiment, a mask ROM built-in microcomputer 1 and a flash memory (non-volatile memory) 4 are formed by different chips, and the mask ROM built-in microcomputer 1 is provided on the semiconductor device. The flash memory 4 is mounted. On the mask ROM microcomputer 1, an aluminum pad electrode 2 connected to an external lead terminal (not shown) by a conductive wire (not shown) and an aluminum pad electrode used for connection to the flash memory 4 (External electrode) 3 is formed. Further, solder bump electrodes (external electrodes) 5 are provided on the surface of the flash memory 4, and the bump electrodes 5 and the aluminum pad electrodes 3 of the mask ROM built-in microcomputer 1 are connected to each other. That is, the flash memory 4 is arranged so as to face the mask ROM built-in microcomputer 1 through the bump electrodes 5.

The basic structure of the mask ROM built-in microcomputer 1 of the present embodiment is almost the same as that of the mask ROM built-in microcomputer 101 used for mass production as shown in FIG. 7A. Also, the program stored in the mask ROM may be the minimum necessary program, and the evaluation program is stored in the flash memory 4.

Next, the configuration and operation of the entire semiconductor device will be described in detail with reference to FIG. 2 is shown in FIG.
The main wiring relation between the mask ROM built-in microcomputer 1 and the flash memory 4 in FIG. Here, in order to show the wiring relationship, the mask ROM built-in microcomputer 1 and the flash memory 4 are shown in a planar positional relationship.

The mask ROM built-in microcomputer 1 is a CPU 1
4. RAM (random acces) that can temporarily store data
s memory) 15, a mask RO in which data cannot be rewritten
The recognition circuit 6 for recognizing whether or not the M16 and the flash memory 4 are connected is provided. The RAM 15 and the mask ROM 16 are connected to the CPU 14 via address buses 17 and 19 and data buses 18 and 20, respectively. The recognition circuit 6 uses the wiring 23 for the flash memory 4
Connected with. The recognition signal output from the recognition circuit 6 is transmitted to the CPU 14 via the wiring 11. In addition,
In addition, peripheral functions and control lines of the mask ROM built-in microcomputer 1 are omitted.

On the other hand, the flash memory 4 is connected to the CPU 14 in the microcomputer 1 with built-in ROM by the address bus 21 and the data bus 22 via the bump electrodes 5.

In this configuration, the CPU 14 causes the flash memory 4 to operate in response to the recognition signal output from the recognition circuit 6.
The connection state of the flash memory 4 is judged, and when the flash memory 4 is connected, the access to the mask ROM 16 is blocked,
The data access destination is electrically switched so that the flash memory 4 can be accessed. With such an operation, the CPU 14 can read the program written in the flash memory 4 and can rewrite the program.

Further, in this configuration, the mask ROM 1
In addition to a program for writing data in the flash memory 4 (hereinafter, referred to as a write operation) (hereinafter, referred to as a write program), a data access of the CPU 14 is performed in response to a recognition signal from the recognition circuit 6. Mask R ahead
A program (hereinafter referred to as a switching program) for switching from the OM 16 to the flash memory 4 is stored. By reading this switching program, the CPU 14 blocks the data access to the mask ROM 16 and enables the data access to the flash memory 4. As another means for switching the data access destination, a hardware mechanism such as disposing a control circuit for switching according to the recognition signal from the recognition circuit 6 may be used. The flash memory 4
Is connected, the CPU 14 and the mask ROM 16 can be accessed when writing data to the flash memory 4.

Next, the recognition circuit 6 for recognizing whether or not the mask ROM built-in microcomputer 1 and the flash memory 4 are connected will be described with reference to FIGS. 1 (b) and 1 (c). Figure 1
(B) is an enlarged view of a recognition bump electrode portion to which the recognition circuit 6 is connected. FIG. 1C is a circuit configuration diagram of the recognition circuit 6.

As shown in FIG. 1B, the wiring 7 to which a constant voltage (Vh) is applied to the mask ROM built-in microcomputer 1.
Are arranged. The wiring 7 branches in the middle, and one of them is connected to the recognition circuit 6 via the wiring 8. The other is electrically connected to the wiring 9 arranged in the flash memory 4 via the recognition pad electrode 3a and the recognition bump electrode 5a. The wiring 9 is electrically connected to the wiring 10 arranged in the mask ROM built-in microcomputer 1 through the recognition bump electrode 5b and the recognition pad electrode 3b. Thus, the other of the branched wirings 7 is the wiring 9 and the wiring 1.
It is connected to the recognition circuit 6 via 0. Therefore, FIG.
23 corresponds to the other side of the branched wiring 7, the recognition electrode pads 3a and 3b, the recognition bump electrodes 5a and 5b, the wiring 9, and the wiring 10. The recognition signal output from the recognition circuit 6 is transmitted to the CPU 14 via the wiring 11.

The recognition circuit 6, as shown in FIG.
It is configured by a 2-input AND circuit 61. Pull-down resistors 64 are connected to the input terminals 62 and 63, respectively. The input terminal 62 is connected to the wiring 8, the input terminal 63 is connected to the wiring 10, and the output terminal 65 is connected to the wiring 11.

By configuring the identification circuit 6 with such a configuration, the following operation becomes possible. First, the constant voltage Vh
Is set to the high level of the 2-input AND circuit 61, and when the flash memory 4 is connected to the mask ROM built-in microcomputer 1, the 2-input AND circuit 6 from the input terminals 62 and 63 is input.
Both inputs to 1 are high level. Therefore, the output from the output terminal 65 of the 2-input AND circuit 61 becomes high level. On the other hand, when the flash memory 4 is not connected to the mask ROM built-in microcomputer 1, the input from the input terminal 62 connected to the wiring 8 is at a high level, and the input from the input terminal 63 connected to the wiring 10 is at a low level. Therefore, the output from the output terminal 65 becomes low level. That is, when the output from the output terminal 65 is at the high level, the flash memory 4 is connected, and when the output is at the low level, the flash memory 4 is not connected. The output from the output terminal 65 is input to the CPU 14 as a recognition signal, and the data access destination of the CPU 14 is switched as described above.

As described above, since the flash memory 4 is provided in the semiconductor device of this embodiment, it is possible to electrically change the program in the evaluation / trial production or the initial stage of mass production. Furthermore, the flash memory 4 is a mask ROM
Since the built-in microcomputer 1 is composed of a separate chip and is connected by the bump electrodes 5, the flash memory 4 is removed and the finalized program is rewritten to the mask ROM 1
By storing the data in No. 6, the semiconductor device of this embodiment used as a prototype has the same configuration as that of the mass-produced product. In other words, after the evaluation / trial production or the initial stage of mass production, the product manufactured as a prototype can be handled in the same manner as the mass-produced product.
Further, when the recognition circuit 6 recognizes that the flash memory 4 is connected, data access between the CPU 14 and the flash memory 4 is enabled, so that data reading from the flash memory 4 and data in the flash memory 4 are performed. Rewriting is also possible.

As described above, according to the semiconductor device of the present embodiment, it is possible to electrically change the program in the evaluation / trial production or the initial stage of mass production without developing the microcomputer with the built-in flash memory, which significantly reduces the development cost of the microcomputer. The effect that it can be reduced to

Further, in the case of the semiconductor device of this embodiment, if the flash memory 4 is developed as a single chip, it can be easily used for different microcomputers with a built-in mask ROM. That is, even if a microcomputer with a built-in flash memory is not developed for each microcomputer product, it is possible to configure a device having the same function as the microcomputer with a built-in flash memory by combining one type of flash memory with a plurality of built-in mask ROM microcomputers. can get. Furthermore, by preparing a single chip of a flash memory having a different storage capacity, it is possible to easily realize a microcomputer product having a storage capacity required by the user for one type of mask ROM microcomputer.

In the case of the semiconductor device of this embodiment, the bump ROM 5 connects the two chips of the mask ROM built-in microcomputer 1 and the flash memory 4. When the bump electrodes 5 are connected in this manner, the distance between chips is short, so that the resistance component can be reduced and the access speed is not delayed. The flash memory 4 has a high-speed operation C
Since the operation program of the PU 14 is described, the access speed between the flash memory 4 and the mask ROM built-in microcomputer 1 must be as high as possible. The connection between the two chips is, for example, as shown in FIG. 3, provided by laminating and bonding the two chips of the mask ROM built-in microcomputer 1 and the flash memory 4 to the aluminum pad electrode 2 and the flash memory 4 of the mask ROM built-in microcomputer 1. When the method of connecting the pad electrode 12 to the pad electrode 12 is performed by the wire 13, the distance between the two chips becomes long and the access speed becomes slower than that of the method using the bump electrode 5. Therefore, it is desirable to connect the two chips by the bump electrode 5 as in the present embodiment.

(Second Embodiment) A second embodiment according to the present invention will be described with reference to the drawings.

Unlike the semiconductor device according to the first embodiment, the semiconductor device according to the present embodiment uses a mask ROM in which a plurality of write programs describing the operation when writing data to the flash memory are stored. Further, the semiconductor device of this embodiment is provided with a flash memory specification identification circuit (hereinafter referred to as an identification circuit) for identifying the specifications of the flash memory. The semiconductor device of this embodiment will be specifically described below.

FIG. 4A is a sectional view showing a schematic structure of the semiconductor device according to the present embodiment. As shown in FIG. 4A, in the semiconductor device of the present embodiment, the mask ROM built-in microcomputer 31 and the flash memory 34 are configured by different chips, and the flash ROM (nonvolatile The memory) 34 is mounted. On the mask ROM microcomputer 31, an aluminum pad electrode 32 connected to an external lead terminal (not shown) by a conductive wire (not shown) and an aluminum pad electrode used for connection to the flash memory 34. (External electrode) 33 is formed. Further, solder bump electrodes (external electrodes) are provided on the surface of the flash memory 34.
35, the bump electrode 35 and the mask R
The aluminum pad electrode 33 of the OM built-in microcomputer 31 is connected. That is, the flash memory 34 is arranged so as to face the mask ROM built-in microcomputer 31 via the bump electrodes 35.

FIG. 5 shows the mask ROM shown in FIG.
The main wiring relationship between the built-in microcomputer 31 and the flash memory 34 is shown. In this embodiment, the CPU
Since the configuration other than 41, the mask ROM 42, and the identification circuit 36 is the same as that of the semiconductor device of the first embodiment,
The description is omitted here.

The CPU 41 is the CPU in the first embodiment.
In addition to the function of 14, the flash memory 34 further has a function of determining the specifications of the flash memory 34 by an identification signal output from the identification circuit 36, reading a write program according to the specifications, and performing a write operation.

The mask ROM 42 stores a plurality of write programs. When connecting flash memories of different specifications, the write programs are different. Therefore, as shown in FIG.
In addition to the switching program 451 for switching the data access destination of the CPU 41, a plurality of writing programs 452a for the flash memory of each specification
~ 452c is also stored. Mask RO of this embodiment
In the memory space 45 of M42, three programs, a write program a, a write program b, and a write program c, are stored so as to be compatible with flash memories of three different specifications.

The identification circuit 36 is provided as means for identifying the specifications of the flash memory 34 to be connected.
The identification circuit 36 will be described in detail below with reference to FIGS. FIG. 4B is an enlarged view of the bump electrode portion to which the recognition circuit 36 is connected. Figure 4 (c)
FIG. 6 is a circuit configuration diagram of a recognition circuit 36.

As shown in FIG. 4 (b), the flash memory 34 is provided with identification bump electrodes 35a to 35d used for identifying the specifications thereof. on the other hand,
The mask ROM built-in microcomputer 31 includes identification pad electrodes 33a to 33d connected to the identification bump electrodes 35a to 35d.
33d is arranged. Mask ROM built-in microcomputer 3
1, a wiring 37 to which a constant voltage (Vsel) is applied
Are arranged. The wiring 37 is the identification pad electrode 33.
The wiring 38 arranged in the flash memory 34 is electrically connected via the d and the bump electrode 35d for identification. The wiring 38 is connected to any of the identification bump electrodes 35a to 35c, and the identification pad electrodes 33a to 33c.
Is electrically connected to any of the wirings 39a to 39c in the mask ROM built-in microcomputer 31 via any of the above. The wirings 39a to 39c are connected to the identification circuit 36, respectively. The identification signal output from the identification circuit 36 is transmitted to the CPU 41 via the wirings 40a to 40c.
Which of the identification bump electrodes 35a to 35c the wiring 38 is connected to is determined by the specifications of the flash memory 34. The wirings 40a to 40c are wirings provided for each specification of the flash memory 34 (flash memory a, b, c type).

FIG. 4C shows the circuit configuration of the identification circuit 36. In the identification circuit 36, the voltage input to the wirings 361a to 361c provided for each flash memory specification is output terminal 362 for each flash memory specification.
It is a circuit configured to be output as an identification signal via a to 362c. In addition, the wirings 361a to 361
Pull-down resistors 363 are connected to the respective c.

Next, the operation of the identification circuit 36 will be described. For example, when the specification of the flash memory 34 is the “flash memory a” type, the flash memory 3
Since the wiring 38 in 4 is connected to the identification bump electrode 35a, the voltage Vsel (high level) is output to the output terminal 362a. The output to the other output terminals 362b and 362c becomes low level. Since the output terminal 362a is a terminal corresponding to the "flash memory a" type, since the power level output from the output terminal 362a is high, the connected flash memory 34 is
Can be identified as a "flash memory a" type. Even if the flash memory 34 has other specifications, that is, "flash memory b" or "flash memory c",
By connecting the wiring 38 to the identification bump electrode 35b or 35c, the corresponding output terminal 362b, 362c
Since the voltage level output to is changed, it can be identified in the same manner.

In this way, the output terminals 362a-362c
The specifications of the connected flash memory 4 can be identified by the voltage level output to the flash memory 4. In addition,
In the present embodiment, the mask ROM built-in microcomputer 31
Although the specifications of the three types of flash memory can be identified, the number of specifications of the flash memory that can be identified can be arbitrarily set by increasing or decreasing the number of identification bump electrodes.

Output terminals 362a-362 of the identification circuit 36
The output from c passes through the wirings 40a to 40c and is used as an identification signal by the CPU 41 in the mask ROM built-in microcomputer 31.
Be transmitted to. The CPU 41 responds to this identification signal by
A write program corresponding to the specifications of the connected flash memory 34 is selected from the mask ROM 42 and read out, and the write operation to the flash memory 34 is executed. For example, if the specification of the flash memory 34 is the “flash memory a” type, write program a is
A write program b is selected for the "flash memory b" type, and a write program c is selected for the "flash memory c" type to perform the write operation.

As described above, a plurality of write programs are stored in the memory space 45 of the mask ROM 42,
Moreover, by providing the identification circuit 36, it is possible to obtain the effect that the write operation can be performed with respect to a plurality of types of flash memories without limiting the type of the flash memory 34 to be connected.

[0048]

As described above, according to the semiconductor device of the present invention, it is not necessary to develop a microcomputer with a built-in flash memory in order to enable program change at the initial stage of evaluation / trial production or mass production. A significant reduction in development costs can be realized. Furthermore, by providing a circuit for identifying the specifications of the flash memory, it is possible to connect flash memories having a plurality of specifications without limiting the type of the flash memory.

[Brief description of drawings]

1A is a cross-sectional view showing a schematic configuration of a semiconductor device according to a first embodiment of the present invention, FIG. 1B is an enlarged view of a bump electrode portion to which a recognition circuit is connected, and FIG. c)
FIG. 3 is a circuit configuration diagram of the recognition circuit.

FIG. 2 is a block diagram showing a configuration of a semiconductor device according to a first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing an example of a connection method between a mask ROM built-in microcomputer and a flash memory.

4A is a sectional view showing a schematic configuration of a semiconductor device according to a second embodiment of the present invention, FIG. 4B is an enlarged view of a bump electrode portion to which a recognition circuit is connected, and FIG. c)
FIG. 3 is a circuit configuration diagram of the recognition circuit.

FIG. 5 is a block diagram showing a configuration of a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a mask RO according to a second embodiment of the present invention.
It is explanatory drawing which shows the memory space of M.

FIG. 7A is a plan view of a conventional mask ROM built-in microcomputer, and FIG. 7B is a plan view of a conventional flash memory built-in microcomputer.

[Explanation of symbols]

1 Mask ROM built-in microcomputer 2 Aluminum pad electrode 3 Aluminum pad electrode (external electrode) 3a, 3b Recognition pad electrode 4 Flash memory (nonvolatile memory) 5 Bump electrode (external electrode) 5a, 5b bump electrodes for recognition 6 recognition circuit 7,8,9,10,11 Wiring 17, 19, 21 address bus 18, 20, 22 data bus 23 wiring 31 Mask ROM built-in microcomputer 32 Aluminum pad electrode 33 Aluminum pad electrode (external electrode) 33a to 33d Identification pad electrodes 34 Flash memory (non-volatile memory) 35 Bump electrode (external electrode) 35a-35d Bump electrodes for identification 36 Flash memory specification identification circuit 37, 38, 39a to 39c, 40a to 40c Wiring 45 memory space 61 2-input AND circuit 62, 63 input terminals 64 pull-down resistor 65 output terminals 361a to 361c wiring 362a to 362c output terminals 363 pull-down resistor 451 switching program 452a to 452c write program

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Claims (8)

[Claims] 1. At least a CPU and a ROM are built-in,
Furthermore, a microcomputer having external electrodes used for connection with an electrically rewritable nonvolatile memory composed of another chip, and a recognition signal indicating whether or not the nonvolatile memory is connected to the microcomputer. A semiconductor device having a recognition circuit for generating the semiconductor device. 2. A microcomputer including at least a CPU and a ROM, an electrically rewritable nonvolatile memory, which is composed of a chip different from the microcomputer and is connected to the microcomputer by an external electrode, and the nonvolatile memory. A semiconductor device comprising a recognition circuit for generating a recognition signal indicating whether or not a memory is connected to the microcomputer. 3. When the recognition signal indicates a connection between the nonvolatile memory and the microcomputer, the data access between the CPU and the ROM is cut off, and the data access between the CPU and the nonvolatile memory is enabled. The semiconductor device according to claim 1 or 2, wherein 4. The ROM stores a switching program for controlling an operation of switching the data access destination of the CPU according to the recognition signal, and the CPU determines the data access destination by the switching program. The semiconductor device according to claim 3, wherein a switching operation is performed. 5. The semiconductor device according to claim 3, further comprising a control circuit that controls switching of a data access destination of the CPU according to the recognition signal. 6. The ROM stores a write program for controlling a write operation to the non-volatile memory, and the CPU and the ROM can access data when rewriting data in the non-volatile memory. The semiconductor device according to claim 1, wherein the CPU rewrites data in the non-volatile memory according to the write program. 7. The semiconductor device according to claim 1, further comprising an identification circuit that generates an identification signal for identifying the type of the nonvolatile memory. 8. The ROM stores a plurality of write programs for controlling a write operation to the non-volatile memory, and the CPU and the ROM access data when rewriting data in the non-volatile memory. It is possible that the CPU selects a write program corresponding to the type of the non-volatile memory from the ROM according to the identification signal, and rewrites the data in the non-volatile memory according to the selected write program. The semiconductor device according to claim 7.