JP2003008018A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a semiconductor device to obtain high gate reliability and operate with a low ON voltage by preventing an electric field form being converged on a gate insulating film at a trench terminal part. SOLUTION: The semiconductor device has the gate insulating film 7, having a laminated film of a silicon oxide film 7a, a silicon nitride film 7b, and a silicon oxide film 7c, formed on the flank of a trench 5 and a gate electrode 8 formed on the surface of the gate insulating film in the trench 5 and has a heavily doped area 6 formed at the terminal part of the trench 5; when the silicon oxide film 7a is formed through heat oxidation, speed-up oxidation is carried out on the heavily doped area 6. Consequently, the film thickness of the silicon oxide film 7a formed on the surface of the heavily doped area 6 becomes larger than that of the trench 5 except the terminal part, so that the gate reliability can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which an insulating film is formed on the inner wall of a trench formed on one surface of a semiconductor substrate, and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, as an apparatus of this type, Japanese Patent Laid-Open No.
There is one disclosed in Japanese Patent No. 132539. FIG. 10 shows a cross-sectional structure of this conventional semiconductor device. As shown in this figure, a trench 5 is formed on one surface of a semiconductor substrate, and a gate insulating film 7 including a silicon oxide film 7a, a silicon nitride film 7b, and a silicon oxide film 7c is formed on an inner wall of the trench 5. As a result, a transistor having a so-called trench gate structure is formed.

Since the gate insulating film 7 is composed of a composite film of the silicon oxide film 7a, the silicon nitride film 7b, and the silicon oxide film 7c, the gate insulating film 7 has a higher gate than that formed by only the silicon oxide film. The breakdown voltage is obtained so that the semiconductor device operates at a low ON voltage.

However, when the present inventors diligently studied a semiconductor device having such a structure, an electric field is concentrated at the upper and lower corners of the trench 5,
Therefore, it has been found that there is a problem that the gate breakdown voltage and reliability are lowered.

Therefore, the present inventors have filed a patent application No. 2000-1.
No. 0154, a semiconductor in which a stacked film including a silicon oxide film, a silicon nitride film, and a silicon oxide film is formed on a sidewall surface of a trench, and a silicon oxide film having a film thickness larger than that of the stacked film is formed on a trench upper portion and a bottom portion. Proposing a device. With such a structure, it is possible to alleviate the electric field concentration at the top and bottom of the trench and prevent the breakdown voltage from lowering, and at the same time, allow the semiconductor device to operate at a low ON voltage.

[0006]

However, the semiconductor device previously proposed by the present inventors has the following problems. FIG. 11 shows a plane pattern of the trench gate in the semiconductor device previously proposed by the present inventors, and description will be given based on this figure.

As shown in FIG. 11, an end portion of the trench 5 (for example, when the planar pattern of the trench 5 is a straight line, both ends thereof become the end portions. Hereinafter, referred to as a trench end portion. ) Exists, and the curvature increases at this portion. The gate insulating film 7 formed in such a portion has a film thickness distribution, and there are locally thin film portions. Since the side wall portion of the trench 5 has a smaller film thickness than the upper and bottom portions of the trench 5, a thinnest portion occurs at a position corresponding to the trench end portion of the side wall portion, and an electric field applied to this portion is generated. Becomes large, and the reliability of the gate insulating film 7 is lowered.

On the other hand, conventionally, in the trench gate type transistor, in order to improve the reliability of the gate insulating film, the accelerated oxidation in the high concentration source region arranged in the opening of the trench is utilized, The thickness of the gate oxide film is increased in the opening of the trench. However, such accelerated oxidation in the source region forms a thick portion and a non-thick portion in the gate oxide film. If the portion where the film thickness of the gate oxide film changes is applied to the channel region, there is a problem that the threshold voltage fluctuates and the variation in element characteristics increases.

On the other hand, it is conceivable to reduce the amount of change in the film thickness by reducing the film thickness of the gate oxide film, but on the other hand, there is concern that the life of the gate oxide film may be reduced.
It is also conceivable to form the source region deeply so that the gate oxide film thickness change point is located at the location of the trench sidewall surface that is the source region, but the source region is deeply formed. Therefore, strong thermal diffusion is required, and the lateral diffusion that occurs at that time becomes large, which makes it impossible to miniaturize the device and causes an increase in on-resistance.

In view of the above points, the present invention provides a semiconductor device capable of obtaining high gate reliability by preventing electric field concentration on the gate insulating film at the trench termination portion and operating at a low ON voltage. It is an object to provide a manufacturing method thereof.

Another object of the present invention is to provide a semiconductor device having a highly reliable gate insulating film and capable of obtaining a stable threshold voltage, and a method of manufacturing the same.

[0012]

In order to achieve the above object, in the invention described in claim 1, the semiconductor substrate (1 to 4)
A gate insulating film (7a to 7c) having a stacked film (7a to 7c) including a silicon oxide film (7a), a silicon nitride film (7b) and a silicon oxide film (7c) on the side surface of the trench (5) formed on one surface of 7) is formed, and the gate electrode (8) is formed on the surface of the gate insulating film (7) in the trench, the end portion of the trench (5) has at least the trench (5) of the semiconductor substrate. The high-concentration impurity region (6) is formed in the portion located on the side wall, and the film of the silicon oxide film (7a) formed on the surface of the high-concentration impurity region (6) of the stacked films (7a to 7b). It is characterized in that the thickness thereof is larger than that of the portion other than the end portion of the trench (5).

With such a structure, it is possible to prevent electric field concentration on the gate insulating film (7) at the end of the trench (5), obtain high gate reliability, and reduce it. The semiconductor device can be operated with an on-voltage.

According to the second aspect of the invention, the silicon nitride film (7b) is removed at the end of the trench (5), and the side wall of the trench (5) at the end of the trench (5) is removed. Is characterized in that a silicon oxide film (7f) having a larger film thickness than the laminated films (7a to 7c) is formed. Even in such a configuration, it is possible to prevent electric field concentration on the gate insulating film (7) at the end of the trench (5) and obtain high gate reliability. Thereby, the same effect as that of the first aspect can be obtained.

According to the third aspect of the present invention, in the central portion of the trench (5) corresponding to a portion other than the end portion, the gate insulating film (7) has the laminated film (7a ... 7c), and at least one of the upper portion and the bottom portion of the trench is made of a silicon oxide film (7d, 7e) thicker than the laminated film.

With such a structure, in the central portion of the trench (5), a high breakdown voltage can be obtained by the laminated film (7) formed on the side wall portion of the trench (5), and at the upper portion of the trench (5) and It is possible to alleviate the electric field concentration at the bottom and prevent the gate breakdown voltage (reliability) from decreasing at that portion.

According to a fourth aspect of the invention, the semiconductor substrate has a first region from the one surface side in the formation region of the trench (5).
A trench region (5) has a source region (4) of conductivity type, a base region (3) of second conductivity type, and a drift region (2) of first conductivity type, and the trench (5) includes the source region (4) and the base region (3). ) Is formed so as to reach the drift region (2) and the base region (3) located on the side wall of the trench (5) is used as the channel region in the central portion of the trench (5). Is configured. The invention described in claims 1 to 3 can be applied to such a semiconductor device.

According to the fifth or sixth aspect of the present invention, the high concentration first region (4a) having a predetermined depth from the one surface side and the second region (4b) formed at a concentration lower than that of the first region. To form the source region (4) and to penetrate the first and second regions (4a, 4b) and the base region (3) to reach the drift region (2). To form a second trench on the sidewall of the trench (5).
It is characterized in that the region is deeper than the first region.

In this way, the film thickness change point of the gate insulating film (7) is located in the side wall portion of the trench (5) from the first region (4a) to the second region (4b). You can This makes it possible to obtain a semiconductor device in which the gate insulating film (7) has high reliability and a stable threshold voltage can be obtained.

The invention described in claims 7 to 11 relates to the manufacturing method of the invention described in claims 1 to 6. The semiconductor device according to any one of claims 1 to 6 can be manufactured by these manufacturing methods.

The reference numerals in parentheses of the above-mentioned means indicate the correspondence with the concrete means described in the embodiments described later.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 (a),
FIG. 1B shows a cross sectional structure of a semiconductor device according to an embodiment of the present invention. This semiconductor device has a power MOSFE
1A has a transistor having a trench gate structure such as T and IGBT, and FIG. 1A shows a cross section including a channel region of the transistor, and FIG.
FIG. 4 shows a cross section including the terminal end of the trench of the transistor.

In FIGS. 1A and 1B, an n ⁻ type drift layer 2 is formed on an n ⁺ type or p ⁺ type silicon substrate 1, and a p type base region 3 is formed thereon. .
As shown in FIG. 1A, an n ⁺ type source region 4 is formed in the surface layer portion of the p type base region 3, and the silicon substrate 1, the n ⁻ type drift layer 2, the p type base region 3 and the n type source region 3 are formed. ^{The +} type source region 4 constitutes a semiconductor substrate. In this semiconductor substrate, a trench 5 is formed so as to penetrate the n ⁺ type source region 4 and the p type base region 3 and reach the n ⁻ type drift layer 2. Then, a high-concentration impurity region 6 as shown in FIG. 1B is provided at the end of the trench 5. The high-concentration impurity region 6 is formed in the end portion of the trench 5 from the upper portion of the trench 5 to the side surface and further to the bottom portion.

A gate insulating film 7 is formed on the inner wall of the trench 5. The gate insulating film 7 is a stack of a silicon oxide film (first silicon oxide film) 7a, a silicon nitride film 7b, and a silicon oxide film (second silicon oxide film) 7c formed on the sidewall of the trench 5. Membrane 7a-
7c and silicon oxide films 7d and 7e formed on the top and bottom of the trench 5, respectively.

The silicon nitride film 7b has its upper end located above the boundary between the p type base region 3 and the n ⁺ type source region 4, and its lower end located below the boundary between the p type base region 3 and the n ⁻ type drift layer 2. Is formed so as to be located at. Trench 5
Oxide films 7d, 7 formed on the top and bottom of the
The film e is a film having a larger film thickness than the laminated film formed on the sidewall of the trench 5. Then, as shown in FIG. 1B, the high-concentration impurity region 6 of the silicon oxide film 7a is formed.
The film thickness of the portion located on the surface of is larger than that of other portions. That is, at the trench end,
The film thickness of the laminated film is made larger than the portion other than the trench end portion (hereinafter referred to as the trench central portion), and not only the silicon oxide films 7d and 7e at the top and bottom of the trench 5 but also the film thickness of the laminated film. Is also configured to be large.

A gate electrode 8 made of doped polysilicon is formed on the surface of the gate insulating film 7 in the trench 5. An interlayer insulating film 9 made of BPSG or the like is formed on the p-type base region 3 and the n ⁺ -type source region 4 including the gate electrode 8. A source electrode 10 electrically connected to the p-type base region 3 and the n ⁺ -type source region 4 through the contact holes formed in the interlayer insulating film 9 and electrodes (not shown) connected to the gate and drain. No.) is formed, and the semiconductor device shown in FIG. 1 is configured.

With this structure, the p-type base region 3 is formed.
A trench gate structure in which a portion located on the side surface of the trench 5, that is, a portion adjacent to a laminated film formed of the silicon oxide film 7a, the silicon nitride film 7b, and the silicon oxide film 7c formed on the inner wall of the trench 5 is a channel region A transistor having

In such a structure, the portion of the gate insulating film 7 located on the side wall of the trench 5 is formed of a laminated film including the silicon oxide film 7a, the silicon nitride film 7b, and the silicon oxide film 7c. It becomes possible to obtain a high gate breakdown voltage (reliability). Moreover, since the silicon oxide films 7d and 7e formed on the upper and bottom portions of the trench 5 are made thicker than the laminated film formed on the side surfaces of the trench 5, the electric fields at the upper and lower corner portions of the trench 5 are increased. Concentration is alleviated, and it becomes possible to prevent a decrease in gate breakdown voltage (reliability) at that portion.

The film thickness of the laminated film at the end of the trench is made larger than that at the center of the trench,
Silicon oxide films 7d, 7 on the top and bottom of the trench 5
Not only e, but also the film thickness of the laminated film is increased. Therefore, it is possible to prevent the electric field concentration on the gate insulating film 7 at the trench termination portion, obtain high gate reliability, and obtain a semiconductor device that can be operated at a low ON voltage.

Next, a method of manufacturing the above-mentioned semiconductor device will be described with reference to the process charts shown in FIGS. However, in each of FIGS. 2 and 3, the left side of FIG.
It is assumed that the cross section corresponding to (a) and the right side of the drawing show the cross section corresponding to FIG.

First, in the step shown in FIG. 2A, a p ⁺ type or n ⁺ type silicon substrate 1 is prepared, and an n ⁻ type drift layer 2 is formed on the silicon substrate 1. Then, the p-type base region 3 and the n ⁺ -type source region 4 are sequentially formed by ion implantation and thermal diffusion. At this time, the depth of the p-type base region 3 is 2 to 3 μm, and the depth of the n ⁺ -type source region 4 is 0.5 μm.

Next, in the step shown in FIG. 2B, after depositing the silicon oxide film 11 serving as the first mask material, the silicon oxide film 11 is patterned by photolithography to form the silicon oxide film 11. Form an opening. Subsequently, in a step shown in FIG. 2C, anisotropic dry etching using the patterned silicon oxide film 11 as a mask is performed to perform n ⁺ type source regions 4 and p
A trench 5 penetrating the type base region 3 and reaching the n ⁻ type drift layer 2 is formed. At this time, for example, the trench depth is set to 4 to 6 μm.

Next, in the step shown in FIG. 2 (c), after removing the damage caused at the time of forming the trench, a mask material 12 such as a resist is deposited on the upper surface of the substrate. And
After opening the portion of the mask material 12 located at the trench end portion by photolithography, the mask material 1 is opened.
High-concentration impurity regions 6 are formed by performing oblique ion implantation using 2 as a mask.

Next, in the step shown in FIG. 3 (a), CF ₄
The silicon in the trench 5 is isotropically removed by about 0.1 μm by chemical dry etching using and O ₂ gas. Then, a sacrificial oxide film of about 100 nm is formed by thermal oxidation in H ₂ O or O ₂ atmosphere. After that, by wet etching with diluted hydrofluoric acid,
The sacrificial oxide film is removed. At this time, the etching time may be set to the time when only the sacrificial oxide film is removed, but if it is set to the time when both the sacrificial oxide film and the silicon oxide film 11 for the trench mask are removed, the trench The masking silicon oxide film 11 can also be etched at the same time.

After that, a silicon oxide film 7a of about 100 nm is formed by thermal oxidation in H ₂ O or O ₂ atmosphere. At this time, since the high-concentration impurity region 6 is formed at the end of the trench, the film thickness of the silicon oxide film 7a on the surface of the high-concentration impurity region 6 can be increased by the accelerated oxidation action.

Next, in the step shown in FIG.
A silicon nitride film 7b having a thickness of 10 to 30 nm is formed by the VD method.

Next, in the step shown in FIG. 3C, CHF
By anisotropic dry etching using ₄ and O ₂ gas system, a portion of the silicon nitride film 7b located on the side wall portion of the trench 5 is left, and a portion located on the upper and bottom portions of the trench 5 is removed. The silicon oxide film 7a is partially exposed.

Next, in the step shown in FIG. 4A, a silicon oxide film 7c of 50 Å or more is formed on the silicon nitride film 7b by, for example, thermal oxidation in H ₂ O or O ₂ atmosphere at 950 ° C. Form. At this time, the silicon oxide film 7 having a thickness of about 200 nm thickened by thermal oxidation is formed on the top and bottom of the trench 5 where the silicon nitride film 7b is removed.
d and 7e are formed.

Next, in the step shown in FIG.
After forming a doped polysilicon film 13 for forming the gate electrode 7 by the VD method, the doped polysilicon film 13 is etched back to a desired thickness. Then, the doped polysilicon film 13 is patterned,
The gate electrode 8 is formed.

Although not shown in the subsequent manufacturing process, the interlayer insulating film 9 is formed by plasma CVD, contact holes are formed in the interlayer insulating film 9 by photolithography and anisotropic etching, and the source electrode 10 is formed by sputtering. The semiconductor device shown in FIG. 1 is completed by forming electrodes such as.

By manufacturing as described above, the film thickness of the gate insulating film 7 is large not only in the upper and lower portions of the trench 5 but also in the side wall portions at the trench termination portion, and at the trench central portion, the upper portion of the trench 5 and the gate insulating film 7 are thick. It is possible to realize a structure in which the thickness of the gate insulating film 7 is large at the bottom and the thickness of the gate insulating film 7 is small at the side wall of the trench 5. As a result, it is possible to obtain a semiconductor device which can obtain high gate reliability and can be operated at a low ON voltage.

Further, since the oxide film thickness in the gate insulating film 7 is thick, it is possible to reduce the input capacitance. Further, since the oxide film thickness is thick even at the bottom of the trench 5, it is possible to improve the drain breakdown voltage and reduce the on-resistance.

The high concentration impurity region 6 at the end of the trench shown in this embodiment may be formed at any time after the trench etching and before the gate oxidation. Further, if the high concentration impurity region 6 can be made sufficiently high, the high concentration layer 6 may be formed before the trench formation.

(Second Embodiment) FIG. 5 shows a sectional structure of a semiconductor device according to a second embodiment of the present invention. Figure 5
FIG. 5A shows a cross section including a channel region of a transistor, and FIG. 5B shows a cross section including an end portion of a trench of a transistor. Below, FIG.
The configuration of the semiconductor device according to the present embodiment will be described based on the above. However, since the basic configuration of the semiconductor device is similar to that of the first embodiment, only portions different from the first embodiment will be described.

As shown in FIG. 5A, the semiconductor device of this embodiment has the same sectional structure as that of the first embodiment in the central portion of the trench, but as shown in FIG. The high-concentration impurity regions 6 formed in the embodiment (see FIG.
Of the silicon oxide film 7f which is thicker than the laminated films 7a to 7c.
It is different from the first embodiment in that it is composed of only (7a, 7c).

The method of manufacturing the semiconductor device according to the present embodiment will be described with reference to the process charts shown in FIGS.

First, in the steps shown in FIGS. 6A and 6B, the same steps as those in FIGS. 2A and 2B shown in the first embodiment are performed. Next, in the step shown in FIG. 6C, a silicon oxide film 7a of about 100 nm is formed by performing the same step as that of FIG. 3A in the first embodiment.
In the step shown in FIG. 3A, a silicon nitride film 7b having a thickness of 10 to 30 nm is formed by performing the same step as that shown in FIG. Then, in the step shown in FIG. 7B, the silicon nitride film 7b is left only on the side wall surface of the trench 5 by performing the same step as that in FIG. 3C shown in the first embodiment.

Next, in a step shown in FIG. 7C, a mask material 20 such as a resist is deposited on the upper surface of the substrate. And
After opening the portion of the mask material 20 located at the end of the trench by photolithography, the mask material 2
Isotropic dry etching or wet etching is performed using 0 as a mask to remove the silicon nitride film 7b remaining at the trench end portion.

Next, in the step shown in FIG. 8A, after the mask material 20 is removed, thermal oxidation is performed under the same conditions as in FIG. 4A shown in the first embodiment to form the silicon nitride film 7b. A silicon oxide film 7c is formed on top. At this time, the silicon oxide films 7d, 7e, and 7f having a thickness of about 200 nm, which are thickened by thermal oxidation, are formed on the upper and bottom portions of the trench 5 where the silicon nitride film 7b is removed, and further on the trench end portion.
Is formed.

Then, in the step shown in FIG.
After the gate electrode 8 is formed in the same manner as in FIG. 4B shown in the first embodiment, the interlayer insulating film 9 is further formed, and the contact hole is formed in the interlayer insulating film 9 by photolithography and anisotropic etching. By forming electrodes such as the source electrode 10 by the sputtering method, the semiconductor device shown in FIG. 5 is completed.

As described above, by removing the silicon nitride film 7b in the trench end portion, the thick silicon oxide film 7f is formed in the trench end portion during the subsequent thermal oxidation.
Can be formed. Even in this case, the same effect as that of the first embodiment can be obtained.

(Third Embodiment) FIG. 9 shows a sectional structure of a semiconductor device to which a third embodiment of the present invention is applied. In this embodiment, the configuration of the transistor in the first and second embodiments is changed. Hereinafter, based on FIG.
The structure of the semiconductor device according to the present embodiment will be described. Since the basic structure of the semiconductor device is the same as that of the first embodiment, only the parts different from the first embodiment will be described.

As shown in FIG. 9, the n ⁺ type source region 4
Is composed of a first region 4a and a second region 4b,
The trench 5 is formed so as to penetrate the first region 4a and the second region 4b. The second region 4b is configured to terminate within the first region 4a, is deeper than the first region 4a, and has a lower concentration than the first region 4a, specifically, the second region 4b during thermal oxidation. The concentration is so high that accelerated oxidation is not achieved. Therefore, of the gate insulating film 7 formed on the side wall surface of the trench 5, the portion in contact with the first region 4a is formed thick by the accelerated oxidation, and
The portion in contact with the region 4b is configured to be thin, with almost no accelerated oxidation.

Further, the distance from the second region 4b to the side wall surface of the trench 4 is shorter than the distance from the end of the first region 4a to the side wall surface of the trench 5.

In such a structure, the film thickness change point of the gate insulating film 7 is located at the location from the first region 4a to the second region 4b on the side wall surface of the trench. Therefore, the reliability of the gate insulating film 7 is high and the gate insulating film 7 does not have to be thinned or the high concentration first region 4a of the n ⁺ type source region 4 is not formed deep. The semiconductor device can have a stable threshold voltage.

The semiconductor device of this embodiment is
For example, in the first embodiment and the second embodiment, the step of forming the n ⁺ type source region 4 (FIG. 2A, FIG. 6A)
The second conductive type impurity is ion-implanted at a high concentration to form the first region 4a, and
It is manufactured by performing a step of forming second region 4b by ion-implanting conductivity type impurities at a low concentration.

(Other Embodiments) In the first embodiment,
The high concentration impurity region 6 is provided at the trench termination portion, and in the second embodiment, the silicon nitride film 7b at the trench termination portion is provided.
Although the gate insulating film 7 is made thicker at the trench end portions by removing the above, it is possible to combine both of them.

In each of the above-mentioned embodiments, the semiconductor device having the n-channel type transistor has been described as an example, but it goes without saying that the present invention is applied to the semiconductor device having the p-channel type transistor in which the conductivity types of the respective constituents are reversed. The invention may be applied.

[Brief description of drawings]

FIG. 1 is a diagram showing a cross-sectional structure of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a manufacturing process of the semiconductor device shown in FIG.

FIG. 3 is a diagram showing the manufacturing process of the semiconductor device, following FIG. 2;

FIG. 4 is a diagram showing the manufacturing process of the semiconductor device, following FIG. 3;

FIG. 5 is a diagram showing a cross-sectional structure of a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a manufacturing process of the semiconductor device shown in FIG. 5;

FIG. 7 is a diagram showing the manufacturing process of the semiconductor device, following FIG. 6;

FIG. 8 is a diagram showing the manufacturing process of the semiconductor device, following FIG. 7;

FIG. 9 is a diagram showing a cross-sectional structure of a semiconductor device according to a third embodiment of the present invention.

FIG. 10 is a diagram showing a cross-sectional structure of a conventional semiconductor device.

FIG. 11 is a diagram showing a plane pattern in the vicinity of a trench end portion.

[Explanation of symbols]

1 ... Silicon substrate, 2 ... N ^- type drift layer, 3 ... P-type base region, 4 ... N ⁺ type source region, 5 ... Trench, 6 ...
High concentration impurity region, 7 ... Gate insulating film, 7a, 7c to 7
f ... Silicon oxide film, 8 ... Gate electrode, 9 ... Interlayer insulating film, 10 ... Source electrode.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Akira Kuroyanagi             1-1, Showa-cho, Kariya city, Aichi stock market             Inside the company DENSO (72) Inventor Takashi Arakawa             1-1, Showa-cho, Kariya city, Aichi stock market             Inside the company DENSO (72) Inventor Yukio Tsuzuki             1-1, Showa-cho, Kariya city, Aichi stock market             Inside the company DENSO

Claims (11)

[Claims] 1. A laminated film composed of a silicon oxide film (7a), a silicon nitride film (7b) and a silicon oxide film (7c) on a side surface of a trench (5) formed on one surface of a semiconductor substrate (1-4). Gate insulating film having (7a to 7c) (7)
And the gate electrode (8) is formed on the surface of the gate insulating film (7) in the trench, the terminal portion of the trench (5) includes at least the trench () of the semiconductor substrate. A high-concentration impurity region (6) is formed in a portion located on the side wall of (5), and the high-concentration impurity region (6) of the laminated film (7a-7b) is formed.
A semiconductor device in which the film thickness of the silicon oxide film (7a) formed on the surface of the trench is larger than that of the portion other than the terminal end of the trench (5). 2. A laminated film composed of a silicon oxide film (7a), a silicon nitride film (7b) and a silicon oxide film (7c) on a side surface of a trench (5) formed on one surface of a semiconductor substrate (1-4). Gate insulating film having (7a to 7c) (7)
And the gate electrode (8) is formed on the surface of the gate insulating film (7) in the trench, the silicon nitride film (7b) is removed at the terminal end of the trench (5). The sidewall of the trench (5) at the end of the trench (5) has the laminated film (7a).
7c), a silicon oxide film (7f) having a larger film thickness is formed. 3. The gate insulating film (7) is formed in a central portion of the trench (5) corresponding to a portion other than the end portion, and the gate insulating film (7) is formed in the sidewall portion of the trench (5). 3. The semiconductor device according to claim 1 or 2, wherein at least one of an upper portion and a bottom portion of the trench is formed of a silicon oxide film (7d, 7e) thicker than the laminated film. 4. The semiconductor substrate comprises the trench (5).
The source region (4) of the first conductivity type, the base region (3) of the second conductivity type, and the drift region (2) of the first conductivity type from the one surface side in the formation region of the trench (5), , The drift region (2) penetrating the source region (4) and the base region (3)
And a transistor having the base region (3) located on the side wall of the trench (5) as a channel region is formed in the central portion of the trench (5). The semiconductor device according to claim 3, wherein the semiconductor device is a semiconductor device. 5. The source region includes a high-concentration first region (4a) having a predetermined depth from the one surface side, and a second region (4b) formed with a lower concentration than the first region. The trench has the first and second regions (4a, 4).
b) penetrating the base region (3) and reaching the drift region (2), and the second region is deeper than the first region in the sidewall portion of the trench. The semiconductor device according to claim 4, wherein: 6. A substrate (1) made of a first conductivity type or a second conductivity type semiconductor, a first conductivity type drift layer (2) formed on the substrate (1), and the drift layer ( 2) a second conductivity type base region (3) formed on or in the surface layer part, and a source region (4) formed in the surface layer part of the base region.
A trench (5) formed so as to penetrate the source region (4) and the base region (3) to reach the drift region (2); and a trench (5) formed at an upper portion, a sidewall portion and a bottom portion of the trench. The gate insulating film (7a to 7e) and the gate insulating film (7a) in the trench (5).
7e), the source region has a high-concentration first region (4a) having a predetermined depth from the one surface side, and the high-concentration region has the source region. A second region (4b) formed at a concentration lower than that of the region, the trench penetrating the first and second regions (4a, 4b) and the base region (3), and the drift layer. A semiconductor device, which is formed so as to reach (2), wherein the second region is deeper than the first region in a sidewall portion of the trench. 7. A gate insulating film (7) is formed on a side surface of a trench (5) formed on one surface of a semiconductor substrate (1-4), and a gate is formed on a surface of the gate insulating film (7) in the trench. In the method of manufacturing a semiconductor device in which an electrode (8) is formed, the step of forming the gate insulating film includes, at a terminal portion of the trench (5), at least a sidewall portion of the trench (5) in the semiconductor substrate. A step of forming a high concentration impurity region (6) at a position where it is located, and then performing thermal oxidation so that the thickness of the surface of the high concentration impurity region (6) of the trench (5) becomes thick. Forming a first silicon oxide film (7a) on the first silicon oxide film (7a), forming a silicon nitride film (7b) on the first silicon oxide film (7a), and forming a silicon nitride film (7b) on the silicon nitride film (7b). The method of manufacturing a semiconductor device, characterized by comprising a step of forming a second silicon oxide film (7c). 8. A gate insulating film (7) is formed on a side surface of a trench (5) formed on one surface of a semiconductor substrate (1-4), and a gate is formed on a surface of the gate insulating film (7) in the trench. In the method of manufacturing a semiconductor device in which an electrode (8) is formed, the step of forming the gate insulating film includes a step of forming a first silicon oxide film (7) on an inner wall of the trench (5).
a), forming a silicon nitride film (7b) on the first silicon oxide film (7a), and forming a silicon nitride film (7b) at the end of the trench (5). Then, the second silicon oxide film (7c) is formed on the silicon nitride film (7b) by thermal oxidation, and the silicon oxide film formed at the end of the trench (5) is removed. And a step of increasing the film thickness of the film (7a). 9. As the semiconductor substrate, a source region (1) of the first conductivity type, a base region (2) of the second conductivity type, a first conductivity type of the source region (4) from the one surface side in the formation region of the trench (5). Using the one having a drift region (2), forming the trench so as to penetrate the source region (4) and the base region (3) to reach the drift region (2), Is constituted by a high-concentration first region (4a) having a predetermined depth from the one surface side and a second region (4b) having a lower concentration and a deeper depth than the high-concentration region, and a sidewall of the trench (5). 9. The method of manufacturing a semiconductor device according to claim 7, wherein the second region (4b) is deeper than the first region (4a) in the portion. 10. In the step of forming the gate insulating film (7), after forming the silicon nitride film (7b), the silicon nitride film (7b) is formed on at least one of an upper portion and a bottom portion of the trench (5). ) Is removed, and then thermal oxidation is performed to form a silicon oxide film (7c) on the silicon nitride film (7b), and at the same time, to form a silicon oxide film (7c) on the silicon nitride film (7b). 10. The method for manufacturing a semiconductor device according to claim 7, wherein the film thickness of the silicon oxide film (7a) is increased in at least one side. 11. A step of preparing a substrate (1) made of a first conductivity type or a second conductivity type semiconductor, and a step of forming a drift layer (2) of the first conductivity type on the substrate (1). Forming a second conductivity type base region (3) on the drift layer (2) or on the surface layer portion; forming a source region (4) on the surface layer portion of the base region; (4) and a step of forming a trench (5) so as to penetrate the base region (3) and reach the drift region (2), and a gate insulating film (7a ... 7e), and the gate insulating film (7a) in the trench (5).
~ 7e) forming a gate electrode (8) on the surface of the semiconductor device, the step of forming the source region (4), the high-concentration A step of forming one region (4a), and a second step of lowering the concentration and deeper than the high concentration region
A step of forming a region (4b), and the step of forming the trench (5) includes the first and second steps.
The trench (5) is formed so as to penetrate the regions (4a, 4b), and the second region (4b) is deeper in the sidewall portion of the trench (5) than the first region (4a). A method of manufacturing a semiconductor device having the above-mentioned configuration.