JP2003052052A - Signal processing apparatus and method therefor, program and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To effectively use a cache memory mounted in a CPU. SOLUTION: A selector 31 outputs signals to a Y-distributor 32 for inputted digital video Y-signals and the distributor 32 distributes the Y-signals of 8 bits to a Y-FIFO 35. When the Y-FIFO 35 stores Y-outputs, the selector 38 selects outputs to be transferred among the Y-outputs putted out from the Y-FIFO 35 and transfer the selected outputs to a DMAC 40, and the DMAC 40, if accessible to a main bus 20, outputs addresses for designating areas on a DRAM 14 to the main bus 20, thus writing the Y-outputs transferred from the selector 38 into the DRAM 14 according to their addresses.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device and method, and a program and a recording medium, and more specifically, to an input luminance signal, a first color difference signal and a second color difference signal each having a predetermined word length. The present invention relates to a signal processing device and method for writing in different areas, a program, and a recording medium.

[0002]

2. Description of the Related Art Currently, a video signal for broadcasting station is, for example,
TU Rec656 (International Telecommunication
s Union Recommendation 656) Digitalized according to the standard. The digitized video signal (hereinafter, referred to as a digital video signal) includes a luminance signal (hereinafter, simply referred to as Y signal) represented by 8 bits and two color difference signals (hereinafter, simply referred to as U signal and V signal). Will be output in parallel. Further, in the digital video signal, the Y signal and the U signal or the V signal are alternately mixed, and for example,
U ₀ / Y ₀ / V ₀ / Y ₁ / U ₁ / Y ₂ / V ₁ / Y ₃ / ・
.. format is used.

Generally, an encoder writes a digital video signal in a main memory in a format in which the Y signal and the U signal or the V signal are alternately mixed as described above, and activates an encoding program by a CPU (Central Processing Unit). By doing so, the encoding process is performed. At this time, the CPU copies the digital video signal written in the main memory to the cache memory incorporated therein to speed up the processing.

Further, since the capacity of the cache memory is generally smaller than the capacity of the main memory, the CPU
Flushes or purges the cache memory and again copies the digital video signal from the main memory for subsequent processing.

[0005]

By the way, when the above-mentioned encoder encodes the digital video signal written in the main memory, any one of the target Y signal, U signal and V signal is actually used. One series of signals, for example a series of Y signals (Y ₀ / Y ₁ / Y ₃ / ...)
Only need. However, in the cache memory, the image on the main memory, that is, the digital video signal (U ₀ / Y ₀ / V ₀ / Y ₁ / U ₁ / Y ₂ / V ₁ /
A part of Y ₃ / ...) is copied. In this way, even though the capacity of the cache memory is smaller than that of the main memory, even unused U and V signals are copied, so that there is a problem in that the use efficiency of the cache memory decreases. .

Further, the CPU, in a state where the digital video signal of the above-mentioned format is copied to the cache memory, causes a process of cutting out only a series of Y signals required by the program, resulting in a heavy load. There is.

Therefore, the present invention has been proposed in view of the above circumstances, and provides a signal processing device and method, a program, and a recording medium capable of effectively using a cache memory mounted on a CPU. The purpose is to do.

[0008]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, a signal processing apparatus according to the present invention has a luminance signal, a first
In a signal processing device for processing a digital video signal in which the color difference signal and the second color difference signal are time-divided and arrayed, the input digital video signal is converted into a luminance signal, a first color difference signal, and a second color difference signal. A selecting unit for selecting, a brightness region in which the brightness signal, the first color difference signal, and the second color difference signal selected by the selecting unit are respectively stored;
And a writing control means for writing the luminance signal, the first color difference signal, and the second color difference signal to the luminance area, the first color difference area, and the second color difference area, respectively. With.

According to this signal processing device, the input digital video signal is sorted into the luminance signal, the first color difference signal and the second color difference signal, and the sorted luminance signal, the first color difference signal and the second color difference signal are selected. By writing the signals in the luminance area, the first color difference area, and the second color difference area of the storage unit, the luminance signal, the first color difference signal, and the second color difference signal are stored in independent areas.

In order to solve the above-mentioned problems, a signal processing method according to the present invention processes a digital video signal in which a luminance signal, a first color difference signal and a second color difference signal are time-divided and arranged. In the signal processing method, the input digital video signal is converted into a luminance signal, a first color difference signal and a second
And the luminance signal, the first color difference signal, and the second color difference signal selected in the selection step in the luminance area, the first color difference area, and the second color difference area of the storage unit. And a writing control step of writing.

According to this signal processing method, the input digital video signal is sorted into the luminance signal, the first color difference signal and the second color difference signal, and the sorted luminance signal, the first color difference signal and the second color difference signal are selected. By writing the signals in the luminance area, the first color difference area, and the second color difference area of the storage unit, the luminance signal, the first color difference signal, and the second color difference signal are stored in independent areas.

In order to solve the above-mentioned problems, the program according to the present invention has a luminance signal, a first color difference signal and a second color difference signal.
A signal processing device for processing a digital video signal in which the color difference signals are time-divided and arranged, and a selecting step of selecting the input digital video signal into a luminance signal, a first color difference signal and a second color difference signal, A process including a writing control process for writing the luminance signal, the first color difference signal, and the second color difference signal selected in the selecting step into the brightness region, the first color difference region, and the second color difference region of the storage unit is executed. Let

According to this program, the input digital video signal is sorted into the luminance signal, the first color difference signal and the second color difference signal, and the sorted luminance signal, the first color difference signal and the second color difference signal are selected. Luminance area of storage means, first
By writing in the color difference area and the second color difference area of
The luminance signal, the first color difference signal, and the second color difference signal are stored in independent areas.

In order to solve the above problems, the recording medium according to the present invention processes a digital video signal in which a luminance signal, a first color difference signal and a second color difference signal are time-divided and arranged. A sorting step of sorting the input digital video signal into a luminance signal, a first color difference signal and a second color difference signal, and a luminance signal, a first color difference signal and a second A program for executing a process including a writing control step of writing the color difference signal of (1) into the luminance region, the first color difference region, and the second color difference region of the storage means is recorded.

According to the program recorded on this recording medium, the inputted digital video signal is selected into a luminance signal, a first color difference signal and a second color difference signal, and the selected luminance signal, first color difference signal and By writing the second color difference signal in the brightness area, the first color difference area, and the second color difference area of the storage means, the brightness signal, the first color difference signal, and the second color difference signal are stored in independent areas. To be done.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the embodiment of the present invention, the present invention is applied to a PDA (Pers
onal DigitalAssistants).

This PDA is a signal processing device for processing a digital video signal in which a luminance signal, a first color difference signal and a second color difference signal are time-divided and arrayed, and the input digital video signal is a luminance signal, A selection unit as a selection unit that selects the first color difference signal and the second color difference signal, and a brightness region in which the brightness signal selected by the selection unit, the first color difference signal, and the second color difference signal are stored, DRAM (Dynamic Random Access Memory) as a storage means having a first color difference region and a second color difference region
And a luminance signal, a first color difference signal, and a second color difference signal in the luminance area, the first color difference area, and the second color difference area, respectively, as a write control means for DMAC (Direct M
emory Access Controller).

First, regarding the general external appearance of the PDA 1,
This will be described with reference to FIG. Here, a front view of the PDA 1 is shown in FIG. 1A, and a left side view of the PDA 1 is shown in FIG.

As shown in FIG. 1A, the PDA 1 is covered with a housing 7, and a display unit 2, a touch pad 3, an operation unit 4 and a camera 5 are provided on the front surface thereof. Further, as shown in FIG. 1B, the left side surface of the PDA 1
A rotary dial 6 is provided.

The display unit 2 is a liquid crystal display capable of monochrome display or color display, and displays various data. An input operation is performed on the touch pad 3 using an operation pen or the like (not shown). The operation unit 4 includes an operator that gives an instruction or the like to start an application program installed in the PDA 1. The camera 5 has a lens unit 5.
A digitized video (image) signal (hereinafter, digital video signal) is generated from the image of the subject captured in a. The camera 5 is attached, for example, on the display unit 2 and is rotatable by a predetermined angle based on the attached shaft. The rotary dial 6 gives an instruction or the like for causing the PDA 1 to execute various processes by a rotating operation or a pressing operation.

Next, the schematic structure of the PDA 1 is shown in FIG.
Will be explained. The PDA 1 includes a display unit 2, a touch pad 3, an operation unit 4, a camera 5, a rotary dial 6, and a CP.
U (Central Processing Unit) 11, camera interface 12, flash memory 13, DRAM 14,
External memory interface 15, USB interface 16, audio data reproducing unit 17, battery 18
And a power supply circuit section 19.

The CPU 11 is connected via the main bus 20 to
It is connected to the flash memory 13, the DRAM 14, the external memory interface 15, and the USB interface 16. Further, the CPU 11 is connected to the display unit 2, the touch pad 3, the operation unit 4, the rotary dial 6, and the audio data reproducing unit 17. The camera interface 12 is connected to the camera 5 and the main bus 20.

Next, each part of the PDA 1 will be described. The display unit 2 is a flash memory 13 or a DRAM.
The data written in 14 and the data written in an external memory (not shown) connected to the external memory interface 15 are displayed. The touch pad 3 outputs to the CPU 11 a signal designating a position and a locus touched by the tip of the operation pen when an input operation is performed using an operation pen (not shown). The operation unit 4
A signal that gives an instruction to the PDA 1 to execute various processes is output to the CPU 11 by operating the operator.
The rotary dial 6 is used for PD by rotating and pressing.
CPU sends a signal that gives A1 an instruction to execute various processes.
Output to 11. The audio data reproducing unit 17 reproduces audio data written in an external memory (not shown) connected to the external memory interface 15, and outputs the audio data to headphones or the like (not shown).

The flash memory 13 is a memory in which data is electrically written and erased, and the CPU 1
The program etc. which 1 runs are stored. DRAM14
Stores a program executed by the CPU 11 and data such as a digital video signal output from the camera interface 12. Here, as will be described in detail with reference to FIG. 5, the DRAM 14 is provided with independent areas for storing the Y output, U output, and V output of the digital video signal.

The external memory interface 15 is connected to a removable thin plate-shaped external memory (not shown). A personal computer or the like is connected to the USB interface 16 via a USB connector (not shown).

The power supply circuit section 19 converts the power supply voltage supplied from the battery 18 into internal power of a predetermined voltage, and C
By supplying to each unit such as the PU 11 and the display unit 2, P
Drive the entire DA1. The power supply circuit unit 19 may be supplied with power supply voltage from an AC adapter (not shown).

The camera 5 generates a digital video signal from the image of the subject captured by the lens section 5a and outputs it to the camera interface 12. The camera interface 12 will be described in detail with reference to FIG.
Input digital video signal via 0
Write to AM14.

The CPU 11 is a flash memory 13 or D
The program stored in the RAM 14 is read and the operation of each unit is controlled. For example, the CPU 11 reads the encode program from the flash memory 13 or the DRAM 14 and uses the MPEG (Moving Picture Experts) to read the digital video signal already written in the DRAM 14.
In the case of encoding by Group) or the like, the digital video signal is copied to the cache memory 11a to speed up the process.

The digital video signal output by the camera 5 will be described with reference to FIG. This digital video signal is, for example, ITU Rec656 (Internat
ional Telecommunications Union Recommendation656)
The luminance signal (hereinafter, simply referred to as Y signal) and the two color difference signals (hereinafter, simply referred to as U signal and V signal) which are based on the standard and are expressed by 8 bits are output in parallel. Further, the digital video signal has a format in which the Y signal and the U signal or the V signal are alternately mixed. Thereby, the camera 5 outputs the 8-bit pixel data unit digital video signal to the camera interface 12 in the above-mentioned format.

Next, the schematic structure of the camera interface 12 will be described in detail with reference to FIG. The camera interface 12 outputs the digital video signal output from the camera 5 in the above-mentioned format to the main bus 20.
It plays a role of writing to the DRAM 14 via the memory.

The camera interface 12 includes the selection unit 3
1, Y-distribution unit 32, U-distribution unit 33, V-distribution unit 3
4, Y-FIFO (First-In First-Out) 35, U-F
An IFO 36, a V-FIFO 37, a selection unit 38, a timing generator 39 and a DMAC 40 are provided.

The timing generator 39 is used by the camera 5
A synchronizing signal is extracted from the digital video signal output from the selection unit 31, the Y-distribution unit 32, the U-distribution unit 33, V
-Distributor 34, Y-FIFO 35, U-FIFO 36,
The V-FIFO 37, the selection unit 38, and the DMAC 40 generate timing signals required.

The selecting unit 31 outputs the digital video signal input by 8 bits to the Y-distribution unit 32 when it is a Y signal, outputs it to the U-distribution unit 33 when it is a U signal, and outputs V
If it is a signal, it is selected so as to be output to the V-distribution unit 34.

The Y-distribution unit 32 receives the input 8-bit Y
Y-FI is used so that the signal is packed into a 32-bit width that matches the word length handled by the CPU 11 as a basic unit.
The Y signal is distributed to the FO 35. The U-distribution unit 33 distributes the U signal to the U-FIFO 36 so that the input 8-bit U signal is packed into a 32-bit width that matches the word length handled by the CPU 11 as a basic unit.
The V-distribution unit 34 packs the input 8-bit V signal into a 32-bit width that matches the word length that the CPU 11 similarly treats as a basic unit, and the V-FIFO 3
Distribute V signal to 7.

In the Y-FIFO 35, the 8-bit Y signal distributed from the Y-distribution unit 32 is temporarily accumulated and 4
They are collectively packed into a 32-bit width, and the packed 32-bit wide Y signals are collectively pushed out as a Y output for a plurality of words. In the U-FIFO 36, the 8-bit U signal distributed from the U-distribution unit 33 is temporarily accumulated and packed into a 32-bit width by grouping four, and the packed 32-bit width U signal is converted into a plurality of words. It pushes out in order as a U output collectively.
In the V-FIFO 37, the 8-bit V signal distributed from the V-distribution unit 34 is temporarily accumulated, and four V signals are combined into three.
Packed to 2 bits wide and packed 3
A 2-bit width V signal is collectively pushed out as a V output for a plurality of words.

Here, the Y-FIFO 35 and U-FIFO
FIG. 5 shows an example of the Y output 51, the U output 52, and the V output 53 pushed out by the 36 and the V-FIFO 37. Y output 51
, The Y signal having a width of 32 bits is collected for 4 words. In the U output 52, U signals having a width of 32 bits are collected for 2 words. In the V output 53, V signals having a width of 32 bits are collected for 2 words.

The selection unit 38 includes a Y-FIFO 35 and a U-F.
The output to be transferred from the Y output 51, the U output 52, and the V output 53 pushed out from the IFO 36 and the V-FIFO 37 is selected and output to the DMAC 40.

The DMAC 40 transfers the output from the selector 38 to the main bus 20 and writes it in the DRAM 14. At this time, the DMAC 40 outputs to the main bus 20 an address designating an area on the DRAM 14 to which the output from the selection unit 38 is written. The DRAM 14 is provided with independent areas for storing the Y output 51, the U output 52, and the V output 53.

Next, the processing operation of the camera interface 12 having the above configuration will be described with reference to the flowchart shown in FIG.

First, when the digital video signal output from the camera 5 is input to the selection unit 31, step S1
At, the selection unit 31 selects whether or not the input digital video signal is a Y signal. If it is a Y signal,
The process proceeds to step S2 and is performed. On the other hand, if it is not the Y signal, the process proceeds to step S5 and is performed.

In step S2, the selection unit 31 determines that Y
The signal is output to the Y-distribution unit 32. In step S3, the Y-distribution unit 32 outputs the 8-bit Y signal to the Y-FIF.
Distribute to O35. In step S4, the timing generator 39 determines whether the Y output 51 is accumulated in the Y-FIFO 35. When the Y output 51 is accumulated in the Y-FIFO 35, the process proceeds to step S12 and is processed. On the other hand, when the Y output 51 is not stored in the Y-FIFO 35, the process returns to step S1 and the process is repeated.

Further, in step S5, the selection unit 31
Selects whether the input digital video signal is a U signal. If it is a U signal, the process proceeds to step S6 and is processed. On the other hand, if it is not a U signal, that is, V
If it is a signal, the processing proceeds to step S9.

In step S6, the selection unit 31 makes U
The signal is output to the U-distribution unit 33. In step S7, the U-distribution unit 33 outputs the 8-bit U signal to the U-FIF.
Distribute to O36. In step S8, the timing generator 39 determines whether the U output 52 is accumulated in the U-FIFO 36. When the U output 52 is stored in the U-FIFO 36, the process proceeds to step S12 and the process is performed. On the other hand, when the U output 52 is not accumulated in the U-FIFO 36, the process returns to step S1 and the process is repeated.

In step S9, the selection unit 31
Outputs the V signal to the V-distribution unit 34. Step S1
At 0, the V-distribution unit 34 converts the 8-bit V signal to V
-Distribute to the FIFO 37. In step S11,
The timing generator 39 applies V to the V-FIFO 37.
It is determined whether the output 53 is accumulated. V-FIFO3
If the V output 53 is accumulated in step 7, step S12
Proceed to and processing will be performed. On the other hand, V-FIFO 37
If the output 53 is not accumulated, the above step S1
The process is repeated by returning to.

In step S12, the selection unit 38
Y-FIFO 35, U-FIFO 36 and V-FIFO
Out of the Y output 51, U output 52, and V output 53 extruded from 37, the output to be transferred is selected and DMA
Transfer to C40.

In step S13, the DMAC 40
Inquires whether or not the main bus 20 can be accessed. When the access is possible, the process proceeds to step S14 and is performed. On the other hand, if you cannot access
The DMAC 40 is in a standby state until it can be accessed.

In step S14, the DMAC 40
Outputs an address designating an area on the DRAM 14 to the main bus 20, and writes the output transferred from the selection unit 38 to the DRAM 14 according to the address.

By the above processing operation, the Y signal, the U signal and the V signal output from the camera 5 are written as the Y output 51, the U output 52 and the V output 53 in the respective independent areas provided on the DRAM 14. Then, the transfer ends.

As described above in detail, the PDA 1 according to the embodiment of the present invention outputs the data from the camera 8
A digital video signal in which bit Y signals and U signals or V signals are alternately mixed is selected into Y signals, U signals, and V signals, packed into a 32-bit width, transferred in multiple words, and transferred. DR to write the signal
By outputting the address designating the area on the AM 14, the Y signal, the U signal, and the V signal can be written in the independent areas provided on the DRAM 14.

As a result, only one signal, for example, the Y signal, is copied from the DRAM 14 to the cache memory 11a, so that the PDA 1 encodes the digital video signal output from the camera 5 by, for example, MPEG. The use efficiency of the cache memory 11a can be improved.

Therefore, the PDA 1 is the cache memory 1
Since a general-purpose CPU having a small capacity of 1a can be mounted, cost reduction can be realized.

Further, the cache memory 11a has a DR
Since only one signal, for example, the Y signal, is copied from the AM 14, the CPU 11 does not need the processing of cutting out the necessary signal, which has been conventionally performed when encoding by MPEG or the like, and the processing of copying from the DRAM 14 is also reduced. be able to.

Therefore, the PDA 1 can reduce the load on the CPU 11 and can realize low power consumption.

Further, the PDA 1 can improve the processing speed and increase the frame rate and the image size as compared with the conventional one.

It should be noted that the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications can be made without departing from the gist of the present invention.

For example, although the present invention is applied to the PDA in the embodiment of the present invention, it may be applied to a mobile information terminal such as a mobile phone or a personal computer equipped with a camera.

In the embodiment of the present invention, the Y-FI
In the FO 35, the U-FIFO 36, and the V-FIFO 37, four 8-bit signals are collectively packed into a 32-bit width, but not limited to this, for example, eight together according to the word length specification handled by the CPU 11. May be packed into a 64-bit width, and 16 may be packed together into a 128-bit width.

[0058]

As described in detail above, the signal processing device according to the present invention is provided with a luminance signal, a first color difference signal and a second color difference signal.
In a signal processing device for processing a digital video signal in which the color difference signals are time-divided and arrayed, a selecting means for selecting the input digital video signal into a luminance signal, a first color difference signal and a second color difference signal, A luminance area, a first color difference area, and a second luminance area in which the luminance signal, the first color difference signal, and the second color difference signal sorted by the sorting means are stored, respectively.
And a writing control unit that writes the luminance signal, the first color difference signal, and the second color difference signal to the luminance region, the first color difference region, and the second color difference region, respectively.

As a result, the signal processing apparatus can process each signal by storing the luminance signal, the first color difference signal and the second color difference signal in independent areas, respectively. The speed can be improved.

The signal processing method according to the present invention is a signal processing method for processing a digital video signal in which a luminance signal, a first color difference signal and a second color difference signal are time-divided and arranged. A sorting step of sorting the digital video signal into a luminance signal, a first color difference signal and a second color difference signal, and a luminance signal, a first color difference signal and a second color difference signal sorted in the sorting step in a storage means. And a writing control step of writing in the luminance region, the first color difference region, and the second color difference region.

Thus, in this signal processing method, each signal can be processed by storing the luminance signal, the first color difference signal and the second color difference signal in independent regions. The speed can be improved.

Further, the program according to the present invention is applied to a digital video signal input to a signal processing device for processing a digital video signal in which a luminance signal, a first color difference signal and a second color difference signal are time-divided and arranged. Signal is a luminance signal, first
A color difference signal and a second color difference signal,
A process including a writing control process for writing the luminance signal, the first color difference signal, and the second color difference signal selected in the selecting step into the brightness region, the first color difference region, and the second color difference region of the storage unit is executed. Let

Thus, in this program, the luminance signal, the first color difference signal, and the second color difference signal are stored in independent areas, so that each signal can be processed, so that the processing speed is increased. Can be improved.

Further, the recording medium according to the present invention is such that a digital signal inputted to a signal processing device for processing a digital video signal in which a luminance signal, a first color difference signal and a second color difference signal are time-divided and arranged. Video signal to luminance signal, first
A color difference signal and a second color difference signal,
A process including a writing control process for writing the luminance signal, the first color difference signal, and the second color difference signal selected in the selecting step into the brightness region, the first color difference region, and the second color difference region of the storage unit is executed. The program that causes it is recorded.

Thus, in the program recorded on this recording medium, the luminance signal, the first color difference signal and the second color difference signal
Since the color difference signals are stored in independent areas, each signal can be processed, so that the processing speed can be improved.

[Brief description of drawings]

FIG. 1 is a diagram illustrating an external configuration of a PDA 1 according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a schematic configuration of the PDA 1.

FIG. 3 is a diagram illustrating a format of a digital video signal generated by a camera 5 included in the PDA 1.

FIG. 4 is a diagram illustrating a schematic configuration of a camera interface 12 included in the PDA 1.

FIG. 5 is a Y-FIFO 35, a U-FIFO 36, and a V-F of the camera interface 12 constituting the PDA 1.
It is a figure which shows an example of Y output, U output, and V output pushed out from IFO37.

FIG. 6 is a flowchart illustrating a processing operation of a camera interface 12 included in the PDA 1.

[Explanation of symbols]

1 PDA, 2 display unit, 3 touch pad, 4 operation unit, 5 camera, 6 rotary dial, 11 CPU, 11
a cache memory, 12 camera interface, 13 flash memory, 20 main bus, 31
Sorting unit, 32 Y-distribution unit, 33 U-distribution unit, 34
V-distribution unit, 35 Y-FIFO, 36 U-FIF
O, 37 V-FIFO, 38 selector, 39 timing generator, 40 DMAC

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H04N 11/24 F term (reference) 5B005 JJ13 LL15 MM01 5C055 AA06 AA07 BA07 CA01 EA02 EA04 FA18 FA19 FA22 HA12 5C057 AA06 BA05 CE06 DA06 EA02 EA07 EC01 EC02 EC03 EL01 5C066 AA03 BA04 CA01 GA02 GA05 GB01 GB02 GB03 HA01 HA03 HA04 KE07 KE09 KE11

Claims (12)

[Claims] 1. A signal processing apparatus for processing a digital video signal comprising a luminance signal, a first color difference signal and a second color difference signal arranged in a time division manner, wherein the input digital video signal is a luminance signal, Selecting means for selecting one color difference signal and second color difference signal, a luminance signal, a luminance area in which the first color difference signal and the second color difference signal are respectively stored, and a first color difference Area and a second color difference area, and writing control means for writing the luminance signal, the first color difference signal, and the second color difference signal in the luminance area, the first color difference area, and the second color difference area, respectively. A signal processing device comprising: 2. The digital video signal according to claim 1, wherein the luminance signal and the first color difference signal or the second color difference signal are alternately mixed in a bit width of pixel data. Signal processing equipment. 3. The signal according to claim 1, further comprising: temporary storage means for temporarily storing the luminance signal, the first color difference signal, and the second color difference signal selected by the selecting means. Processing equipment. 4. The luminance signal is stored in the temporary storage means,
4. The signal processing device according to claim 3, wherein the first color difference signal and the second color difference signal are packed in the bit width of the output word. 5. The luminance area, the first color difference area, and the second area.
2. The signal processing device according to claim 1, further comprising image processing means for performing image processing on the luminance signal, the first color difference signal, and the second color difference signal stored in the color difference area. 6. A signal processing method for processing a digital video signal in which a luminance signal, a first color difference signal and a second color difference signal are time-divided and arranged, wherein the input digital video signal is a luminance signal, A sorting step of sorting into the first color difference signal and the second color difference signal, and the luminance signal, the first color difference signal and the second color difference signal sorted in the sorting step, in the luminance region of the storage means, A signal processing method, comprising: a writing control step of writing in the color difference area and the second color difference area. 7. The digital video signal according to claim 6, wherein the luminance signal and the first color difference signal or the second color difference signal are alternately mixed in a bit width of pixel data. Signal processing method. 8. The luminance signal selected in the selecting step,
7. The signal processing method according to claim 6, further comprising a temporary storage control step of temporarily storing the first color difference signal and the second color difference signal in a temporary storage means. 9. The signal processing method according to claim 8, wherein, in the temporary storage control step, the luminance signal, the first color difference signal, and the second color difference signal are each packed in a bit width of an output word. . 10. An image processing step of performing image processing on the luminance signal, the first color difference signal and the second color difference signal stored in the luminance area, the first color difference area and the second color difference area. The signal processing method according to claim 6, further comprising: 11. A signal processing device for processing a digital video signal comprising a luminance signal, a first color difference signal and a second color difference signal which are time-divided and arrayed, and the input digital video signal is a luminance signal, A sorting step of sorting into the first color difference signal and the second color difference signal, and the luminance signal, the first color difference signal and the second color difference signal sorted in the sorting step, in the luminance region of the storage means, A program for executing processing including a writing control step of writing in the color difference area and the second color difference area. 12. A signal processing device for processing a digital video signal in which a luminance signal, a first color difference signal and a second color difference signal are time-divided and arrayed, and the input digital video signal is a luminance signal, A sorting step of sorting into the first color difference signal and the second color difference signal, and the luminance signal, the first color difference signal and the second color difference signal sorted in the sorting step, in the luminance region of the storage means, A recording medium on which a program for executing a process including a writing control step of writing in the color difference region and the second color difference region is recorded.