JP2003051600A - Thin film transistor and method of manufacturing the same - Google Patents

Abstract

(57) Abstract: Provided is a method for performing a heat treatment required at the time of manufacturing a thin film transistor (TFT) at a relatively low temperature. SOLUTION: In a heating step of crystallizing at least a part of the silicon-based semiconductor layer, silicide is generated in a source region and a drain region of the silicon-based semiconductor layer. The TFT of the present invention includes a silicon-based semiconductor layer including a channel region, a source region and a drain region arranged to sandwich the channel region, a source electrode electrically connected to the source region, and an And a gate electrode insulated from the source electrode and the drain electrode, and the source region and the drain region include silicide.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor, a method for manufacturing the same, an array substrate using the same, an image display device such as an active matrix type liquid crystal display device, and an active matrix type organic electroluminescence (EL) display device. .

[0002]

2. Description of the Related Art Conventionally, a thin film transistor (TFT) using polycrystalline silicon (polysilicon) as a semiconductor layer has been widely used as a pixel switching element of a liquid crystal display device or the like.

A typical structure of a polysilicon TFT is shown in FIG.
4 shows. In this TFT, an undercoat layer 82 is formed on a glass substrate 81, and a polysilicon semiconductor layer 83 is formed at a predetermined position on the surface of this layer. The semiconductor layer 83 includes a channel region 84, and a source region 85 and a drain region 8 arranged so as to sandwich the region.
Includes 6 and. Channel region 84 and source region 8
5 and the drain region 86, respectively, LDD
(Lightly Doped Drain) regions 87a and 87b are interposed. The polysilicon semiconductor layer 83 is covered with the gate insulating layer 88 except for the contact holes, and the gate electrode 89 is arranged above the channel region on the gate insulating layer 88. Source region 85 and drain region 86
Are connected to a source electrode 91a and a drain electrode 91b, which are connected to both regions through contact holes. An interlayer insulating film 90 and a passivation film 93 are formed for electrical insulation between the electrodes and the upper structure.

A method of manufacturing the thin film transistor having the above structure will be described with reference to FIGS.

(A) First, amorphous silicon is deposited on the surface of the undercoat layer 82 on the substrate 81 to form an amorphous silicon layer (a-Si layer) 100 (FIG. 16 (a)).

(B) Next, the a-Si layer 100 is irradiated with laser light to be melted and crystallized (laser annealing).
Then, the island-shaped (isolated) polysilicon layer (p) is formed by patterning by photolithography and etching.
-Si layer) 101 is formed (FIG.16 (b)).

(C) Subsequently, the island-shaped p-Si layer 101 is formed.
A gate insulating layer 88 is formed so as to cover (FIG. 16).
(C)).

(D) Further, a gate electrode 89 is formed on the gate insulating layer 88 and above the region to be the channel region (FIG. 16 (d)).

(E) Next, by using the gate electrode 89 as a mask, impurity ions (for example, phosphorus ions) having a lower dose amount are doped from the upper side of the substrate (first doping), so that the gate electrode of the p-Si layer 101 is doped. 8
The region except immediately below 9 is a low impurity concentration region. The low impurity concentration regions become n ⁻ regions 102a and 102b,
The region immediately below the gate electrode 89 becomes the channel region 84 (FIG. 16E).

(F) Subsequently, a resist mask 30 having openings in the regions to be the source region and the drain region is formed, and impurity ions (for example, phosphorus ions) having a higher dose than the upper direction are doped (second doping).
As a result, the LDD regions 87a and 87b having a low impurity concentration are formed on both sides of the channel region 84 of the p-Si layer, and the source region 85 and the drain region 86 having a high impurity concentration are further formed on both sides thereof (FIG. 16 (f)). )).

(G) Further, the resist mask is removed,
For example, heat treatment is performed at a high temperature of about 600 ° C. for about 1 hour. As a result, the crystal defects of the source region 85 and the drain region 86 caused by the impurity ion implantation are repaired (crystallized), and the impurity ions are activated (FIG. 16 (g)).

(H) Next, an interlayer insulating layer 90 is formed so as to cover the gate electrode 89 (FIG. 16 (h)).

(I) Subsequently, contact holes 103a, 1 penetrating the interlayer insulating layer 90 and the gate insulating layer 88.
03b is formed (FIG. 16 (i)).

(J) Further, the inside of the contact hole 103 is filled with metal to form a source electrode 91a and a drain electrode 91b, and a passivation film 93 is formed so as to cover these electrodes (FIG. 16 (j)). .

Thus, a thin film transistor (TFT) using polysilicon is obtained. Since this TFT uses polysilicon containing a large number of large-sized crystal grains for the semiconductor layer, it has a high electron mobility of 10 to several 100 cm ² / Vs.

[0016]

In this TFT, since the semiconductor layer is crystallized (activated) after the impurity ion implantation, heat treatment at a high temperature of about 600 ° C. or higher is required.
When such a high temperature heat treatment is performed, the impurity ions implanted in the source region, the drain region and the LDD region are easily diffused to the channel region, so that the variation in the driving characteristics between the TFTs becomes large.

The variation in driving characteristics becomes more remarkable as the TFT becomes finer. Therefore, this variation is
This is a big problem in an image display device in which a large number of fine TFTs are arranged on one substrate.

[0018]

The present inventor has found that the temperature of crystallization can be lowered by forming a silicide in the silicon-based semiconductor layer in the heat treatment step of the silicon-based semiconductor layer. It came to completion.

That is, the TFT of the present invention comprises a silicon-based semiconductor layer including a channel region and a source region and a drain region arranged so as to sandwich the channel region,
It includes a source electrode electrically connected to the source region, a drain electrode electrically connected to the drain region, and a gate electrode insulated from the source electrode and the drain electrode. Further, the source region and the drain region are characterized by containing silicide.

The present invention also provides a method of manufacturing the above TFT. This manufacturing method includes a step of forming a silicon-based semiconductor layer, a step of implanting impurity ions into at least a source region and a drain region of the silicon-based semiconductor layer, and heating the silicon-based semiconductor layer. A heating step of crystallizing at least a part of the silicon-based semiconductor layer is included, and the heating in the heating step causes silicide to be generated in the source region and the drain region of the silicon-based semiconductor layer.

If silicide is generated in the layer in the heating step, the silicide serves as crystal nuclei to promote crystallization, so that crystallization of the silicon-based semiconductor layer, for example, repair of crystal defects, can be performed at a lower temperature than before. Can be implemented. For this reason,
It is possible to manufacture a TFT with less variation in driving characteristics than ever before.

In this specification, the term "silicon-based semiconductor layer" means a semiconductor layer containing silicon, particularly a semiconductor layer in which the total amount of silicon and germanium, which is an element in the same group as silicon, accounts for 50 atomic% or more. Say.

[0023]

Preferred embodiments of the TFT of the present invention will be described below.

The silicon-based semiconductor layer may be polycrystalline silicon (polysilicon), and may contain silicon and germanium. In the latter case, it is preferable that the source region and the drain region include silicon and germanium, and the channel region is a silicon layer. The implantation of germanium reduces the bandgap in the source and drain regions.

The germanium concentration (Ge) in the source region and the drain region is preferably 1 atom% or more and 80 atom% or less. If the Ge concentration is less than 1 atomic%, the effect of Ge addition cannot be sufficiently obtained, and if the Ge concentration exceeds 80 atomic%, the defects of the source region and the like are sharply increased, and the characteristics of the TFT may be largely deteriorated. . A more preferable range of the Ge concentration is 20 atomic% or more and 60 atomic% or less.

The semiconductor layer containing silicon and germanium may be a silicon germanium layer, more specifically a polycrystalline silicon germanium layer.

The silicide is preferably formed at least at the interface with the source electrode in the source region and at the interface with the drain electrode in the drain region. When silicide is formed at the interface with each electrode, the contact resistance between the source and drain electrodes and the semiconductor layer is reduced. The reduction in contact resistance is effective in increasing the on-current. In this case, it is preferable that the silicide is not formed on the interface except the interface with the source electrode in the source region and the interface with the drain electrode in the drain region. In other words, at the interface between the source region and the drain region, the silicide is preferably formed only at the interface between the source region and the source electrode and the interface between the drain region and the drain electrode. This is to prevent an increase in off current.

In order to suppress the off current, it is preferable that no silicide is formed in the portions of the source region and the drain region which are in contact with the channel region (LDD region in some cases). In particular, when the source region and the drain region contain silicon and germanium, respectively, the resistance value becomes lower than that of the silicon layer, so that it becomes necessary to pay attention to the portion where the silicide is formed.

It is preferable that the channel region includes a portion thinner than any of portions including the silicide in the source region and the drain region when observed along the thickness direction of the silicon-based semiconductor layer. According to this preferable example, an increase in off-current due to the formation of silicide can be suppressed. When observed along the thickness direction, the thickness of the portion including the silicide in the source region and the drain region is 100 nm or more, and the thickness of the channel region is 4 nm.
It is preferable to include a portion of 0 nm or more and 70 nm or less.
According to this preferable example, it is easy to obtain a TFT having a sufficiently high on-current and a sufficiently low off-current.

The silicon-based semiconductor layer has a region where the impurity concentration is higher than that of the channel region and lower than that of the source region and the drain region, respectively, between the channel region and the source region and between the channel region and the drain region, for example. L
The DD area may be further included.

An insulating side wall may be formed on the side surface of the gate electrode. It is preferable that the side wall is arranged so as to contact at least a pair of side surfaces of the gate electrode which face each other. This side wall is effective in reducing the off current. Therefore, when the element is miniaturized, for example, when the distance between the pair of side surfaces in contact with the sidewall is, for example, 2 μm or less, particularly 1 μm or less, the sidewall may be formed as described above. The sidewall thickness (thickness measured in the in-plane direction of the silicon semiconductor layer) when the side surface of the gate electrode is defined as the bottom surface is preferably 1 μm or less, for example, 0.3 to 0.5 μm.

In the heating step, the silicon-based semiconductor layer 45
It is recommended to heat it to 0 ° C or lower. When the heating temperature is 450 ° C. or lower, a non-annealed glass or a glass substrate having a low strain point temperature (for example, 500 ° C. or lower) can be used as a substrate, so that an inexpensive product can be easily provided. The lower limit of the heating temperature is not particularly limited, but 350 ° C. or higher is suitable for directing crystallization.

In the manufacturing method of the present invention, for the above-mentioned reason, when the silicon-based semiconductor layer is observed in the thickness direction thereof, the channel region, the source region and the drain region have a higher density than that of the portion containing silicide. It may be formed so as to include a thin portion. Further, the method may further include the step of forming an insulating side wall on the side surface of the gate electrode.

In the manufacturing method of the present invention, before the heating step,
Even if a step of forming a metal layer so as to be in contact with the silicon-based semiconductor layer is performed, and a silicide (metal silicide) is generated from the metal included in the metal layer and the silicon included in the silicon-based semiconductor layer in the heating step. Good. In this case, before the step of forming the metal layer, a step of forming an insulating layer (mask) so as to cover a part of the silicon-based semiconductor layer is further performed, and in the step of forming the metal layer, it is covered with a mask. A metal layer may be formed so as to contact the surface of the silicon-based semiconductor layer that is not exposed. This is because the silicide is formed at a predetermined position. Then, the source (drain) electrode may be formed so as to be in contact with the same region as the region where the metal layer is formed using the mask.

In the manufacturing method of the present invention, before the heating step,
A step of implanting metal ions into the silicon-based semiconductor layer may be further included, and silicide may be generated from the metal ions and silicon contained in the silicon-based semiconductor layer.

The silicon-based semiconductor layer is formed on the substrate. Instead of being formed directly on the substrate, it may be formed via an undercoat layer.

The silicon-based semiconductor layer is preferably formed as an amorphous layer, and a layer obtained by crystallizing this amorphous layer is preferably used. Crystallization may be performed by, for example, laser annealing before the heating step, for example, before the step of implanting impurity ions. When impurity ions are implanted after crystallization, crystal defects are generated (amorphized) in at least a part of the silicon-based semiconductor layer. In this case, crystal defects in the source region and the drain region are repaired (crystallized) in the heating process.

The silicon-based semiconductor layer may be formed as an amorphous layer, and the amorphous layer may be crystallized in the above heating step. In this case, crystallization of the entire amorphous material and formation of silicide proceed in the same heating process. The heating when the crystallization of the entire amorphous layer and the formation of the silicide are simultaneously performed may be performed by laser light irradiation. The heating means in the heating step of the present invention is not particularly limited.

In one embodiment of the present invention, a step of forming a silicon-based semiconductor layer on a substrate, a step of implanting impurity ions into regions corresponding to the source region and the drain region of this layer, and a source region of this layer and A step of forming a metal layer on at least a part of the surface of the region corresponding to the drain region, and heating the silicon-based semiconductor layer into which impurity ions are implanted and in contact with the metal layer to crystallize the semiconductor layer, and A step of reacting silicon in the semiconductor layer with a metal contained in the metal layer to generate a silicide is performed.

According to this method, the metal diffuses from the metal layer into the silicon-based semiconductor and reacts with the silicon to generate silicide. Then, the silicide serves as a crystal nucleus to grow crystals. Therefore, the crystal defects of the silicon-based semiconductor layer can be repaired even at a temperature lower than that of the conventional heat treatment. Further, since the silicide is generated in the vicinity of the surface layer of the source region and the drain region, the contact resistance tends to be low.

In the above method, the impurity ion implantation may be carried out prior to the formation of the metal layer or after the formation of the metal layer.

According to another aspect of the present invention, a step of forming a silicon-based semiconductor layer on a substrate, a step of implanting impurity ions into regions corresponding to a source region and a drain region of this layer, and a source of this layer. A step of implanting metal ions into a region corresponding to the region and the drain region, and heating the silicon-based semiconductor layer implanted with the impurity ions and the metal ions to crystallize the semiconductor layer, and in the semiconductor layer, And a step of reacting silicon with metal ions to generate silicide.

Also in this method, since silicide is generated in the silicon-based semiconductor layer and this silicide acts as a crystal nucleus, crystallization can be carried out at a lower temperature than before. In this method, by controlling the implantation energy of the metal ions, the metal ions can be implanted at any concentration in any depth of the source region and the drain region. Therefore, there is an advantage that crystallization can be easily controlled.

Also in this method, the impurity ion implantation may be carried out prior to the metal ion implantation or after the metal ion implantation. Further, the impurity ions and the metal ions may be implanted at the same time.

According to another aspect of the present invention, a step of forming a metal layer on at least a part of a region corresponding to a source region and a drain region on a substrate, and a silicon-based semiconductor layer covering the metal layer. A step of forming, a step of implanting impurity ions into regions corresponding to the source region and the drain region of this layer, and heating the silicon-based semiconductor layer into which the impurity ions are implanted to crystallize the semiconductor layer, And a step of reacting silicon in the semiconductor layer with a metal contained in the metal layer to generate a silicide.

Also in this method, since silicide is generated in the layer and crystal growth is performed by using this silicide as crystal nuclei, crystallization can be performed at a temperature lower than that in the past.
This method has an advantage that a fine TFT can be easily manufactured with high precision because the metal layer having a small area is formed first.

In still another embodiment of the present invention, in the step of forming the silicon-based semiconductor layer, the region to be the channel region is thinner than at least a part of each of the source region and the drain region, A silicon-based semiconductor layer is formed. Then, silicide is formed on at least a part of the source region and the drain region. According to this method, it is easy to suppress the off-current due to the silicide.

As described above, in the TFT of the present invention, it is preferable to dispose the silicide so as not to contact the channel region.
Therefore, in each of the above modes, the metal layer is preferably formed in a region which is not in contact with the channel region, and the metal ions are preferably implanted in a region which is not in contact with the channel region.

The method for forming the silicon-based semiconductor layer having a difference in film thickness is not particularly limited, but, for example, after forming a thin film in advance, only a region to be a source region and a drain region of this layer is further formed. A film may be formed. Alternatively, for example, after forming a thick layer in advance, a part of the layer may be removed in a region of this layer other than the regions to be the source region and the drain region.

Further, another embodiment of the present invention may further include the step of implanting germanium ions into the regions which will be the source region and the drain region of the silicon-based semiconductor layer. According to this method, a TFT in which the source region and the drain region are the silicon germanium layer and the channel region is the silicon layer can be manufactured.

The TFT of the present invention can be applied to the following devices, for example. The following image display device includes an array substrate on which the TFT of the present invention is arranged.

[Liquid Crystal Display Device] In the active matrix liquid crystal display device 100 shown in FIG. 17, the switching transistors 113 arranged in a matrix drive the liquid crystal 114 corresponding to the transistors. The switching transistor 113 is connected to the gate line 111, the data line 112, and the ground line 115, respectively. Each gate line 111 is connected to the gate line drive circuit 101, and each data line 112 is connected to the data line drive circuit 102. By using the TFT of the present invention as the switching transistor 113, good display characteristics can be realized.

[Organic EL Display Device] In the organic EL display device 200 shown in FIG. 18, the switching transistor 214 and the holding transistor 215 arranged in a matrix drive the organic EL element 217 corresponding to this transistor. Switching transistor 214
Are connected to the gate line 211 and the data line 212, respectively, and further through the storage capacitor element 216, the power supply line 213.
It is connected to the. The holding transistor 215 is a switching transistor 214, a power supply line 213, and an organic EL.
It is connected to the element 217. The organic EL element 217 is
It is also connected to the ground line 218. Each gate line 21
1 is connected to the gate line drive circuit 201, and each data line 212 is connected to the data line drive circuit 202.
By using the TFT of the present invention for the switching transistor 214 and the holding transistor 215, good display characteristics can be realized.

The LDD of the embodiment of the present invention will be described below.
A top-gate thin film transistor having a region (gate length 1 μm) will be described as an example with reference to the drawings.

[Embodiment 1] (a1) First, Si of the glass substrate 1 is formed by plasma CVD or low pressure CVD.
An amorphous silicon layer (a-Si layer) 3 having a thickness of 50 nm is formed on the O ₂ layer (undercoat layer) 2, and dehydrogenation treatment is further performed at a temperature of 450 ° C. in a nitrogen atmosphere (FIG. 2A). ).

(B1) Next, laser anneal using an excimer laser with XeCl, KrF or the like as an excitation gas is performed to melt and crystallize the a-Si layer 3 (polysiliconization).
Then, photolithography and etching are performed to form an island-shaped polysilicon layer (p-Si) at a predetermined position.
Layer 4) is formed (FIG. 2B).

(C1) Subsequently, as the gate insulating layer 5, a SiO ₂ film having a thickness of 100 nm is formed so as to cover the p-Si layer 4.
A layer is formed (FIG. 2 (c)).

(D1) Further, a MoW alloy is formed into a film having a thickness of about 400 to 500 nm by a sputtering method or the like, and the gate electrode 6 is formed by photolithography and etching.
Then, a MoW alloy layer is formed (FIG. 2 (d)). In addition,
The gate electrode may be, for example, Ta instead of MoW alloy.
You may use the laminated structure of a MoW alloy.

(E1) Next, the first impurity doping is performed using the gate electrode 6 as a mask. For example, phosphorus ions are implanted at a dose of 5 × 10 ¹² ions / cm ² . As a result, immediately below the gate electrode 6 is the channel region 7 which is not doped with impurities, and the portions other than the channel region 7 are the n ⁻ regions 8a and 8b which are doped with impurities (FIG. 2 (e)).

(F1) Subsequently, a resist mask 3 having openings in the surfaces of the regions to be the source region and the drain region
0 is formed, and impurity doping is performed for the second time. For example, phosphorus ions are implanted at a dose of 1 × 10 ¹⁴ ions / cm ² . As a result, the region doped with the impurity ions at the first time and the region not doped with the impurity ions at the second time have a low impurity concentration (n ⁻ region; LDD).
The regions 9a and 9b), which have been doped with impurities twice, become regions (n ⁺ regions; source region 10 and drain region 11) having a high impurity concentration (FIG. 2 (f)).

(G1) Further, after removing the resist mask, the gate insulating layer 5 on the source region 10 and the drain region 11 is etched to expose a part of the surface of the source region 10 and the drain region 11 ( Figure 2
(G)). The portion to be etched is preferably the same as the contact hole opening described later, that is, the same portion as the junction with the source electrode and the drain electrode.

(H1) Next, a titanium film having a thickness of about 20 nm is formed as metal layers 12a and 12b by a sputtering method or the like in the portions opened by etching (FIG. 2 (h)). Note that a metal layer of cobalt, nickel, or the like may be used instead of the titanium film.

(I1) Subsequently, for example, at 450 ° C., about 1
Heat treatment for a period of time. As a result, titanium in the titanium film diffuses into the source region and the drain region. Then, a metal silicide (titanium silicide) is generated from the diffused titanium and silicon, and the generated titanium silicide serves as a crystal nucleus to crystallize the semiconductor layer which is made amorphous by the implantation of impurity ions.

Thereafter, the unreacted metal layer (titanium film) is
It is removed with an acid (for example, hot sulfuric acid) at about 120 ° C. Thus, in the vicinity of the surfaces of the source region 10 and the drain region 11, a portion (silicide portion) 13 containing metal silicide is formed.
a and 13b are formed (FIG. 2 (i)).

In FIG. 2 (i), the silicide portion 13
Although a and 13b are divided by a clear boundary line, the boundary line of the silicide portion is not always clear depending on the degree of diffusion of metal (titanium) (the same applies hereinafter).

(J1) Further, a silicon oxide film is formed as the interlayer insulating layer 14 so as to cover the gate electrode 6 (FIG. 2 (j)).

(K1) Next, the interlayer insulating layer 14 (thickness 3
00 nm) and contact holes 16a and 16b penetrating the gate insulating layer 5 (FIG. 2 (k)).

(L1) Subsequently, a titanium / aluminum film (thickness 80 nm / 4000 nm) is formed as the source electrode 17a and the drain electrode 17b, and a silicon nitride film (thickness 50) is formed as the passivation film 18.
0 nm) is formed. After that, heat treatment is performed at about 350 ° C. for about 1 hour in a hydrogen atmosphere or a nitrogen atmosphere. As a result, hydrogen is introduced into the polysilicon and the interface between the polysilicon and the gate insulating layer. Thus, a TFT in which the source region and the drain region contain silicide is obtained (FIG. 2 (l)).

The above steps (a1) to (l1) are shown collectively in FIG.

The TFT obtained from each of the above steps has a low contact resistance and a high on-current because it contains silicide in the source (drain) region in contact with the source (drain) electrode. Further, since the crystallization is performed while generating the silicide, the heat treatment temperature can be lowered. In addition, LDD
Since the area is provided to suppress generation of hot carriers, reliability can be improved.

The order of the steps is not necessarily limited to the above. For example, the metal layer (titanium film) is formed after the second impurity doping, but the metal layer may be formed before the second doping. When the doping is performed after forming the metal layer in this way, the metal (titanium) forming the metal layer and silicon are efficiently mixed, so that the homogeneity of the titanium silicide portion can be improved.

[Second Embodiment] In the present embodiment, first,
Similar to the first embodiment, (a1) to (e1) are performed (see FIGS. 1 and 2).

(F2) Next, the source region and the drain region
A resist mask 30 having an opening in the surface of the region
Then, the second impurity doping is performed. Resist 3
0 is formed so as to cover the gate electrode 6. doping
Is, for example, a dose amount of 1 × 10 ¹⁴Pieces / cm²In phosphorus ion
May be performed by injecting. Thus the channel
LDD regions 9a and 9b, source region 1 together with region 7
0 and the drain region 11 are formed (FIG. 3A).

(G2) Subsequently, metal ions (titanium ions) are implanted without removing the resist mask 30. By implanting titanium ions in this way, titanium ions can be implanted in the same region as the region into which the second impurity ions have been introduced (regions that will become the source region and the drain region). Instead of titanium ions, other metal ions such as cobalt and nickel may be used (FIG. 3).
(B)).

(H2) Further, the resist mask 30 is removed, and heat treatment is performed at a temperature of 450 ° C. for about 1 hour. Thereby, the source region 10 and the drain region 11
Silicon reacts with titanium ions inside to form titanium silicide portions 13a and 13b, and the semiconductor layer amorphized by doping with impurity ions is crystallized (FIG. 3C).

After that, (j1) -in the first embodiment
(11) is performed (see FIGS. 1 and 2). Thus, a TFT including silicide in the source region and the drain region is obtained.

In this embodiment, it is not necessary to expose the source (drain) region or remove the extra metal layer in order to form the metal layer, so that the manufacturing process can be simplified. Further, if the implantation energy of the metal ions is controlled, the metal ions can be implanted at an arbitrary concentration in the source (drain) region at an arbitrary concentration, so that crystallization can be easily controlled.

Also here, the metal ions may be implanted prior to the second impurity ion implantation. Further, the second impurity ion implantation and the metal ion implantation may be performed at the same time. Injecting at the same time has the advantage of improving manufacturing efficiency.

[Third Embodiment] (a3) First, island-shaped metal layers (titanium films) 12a and 12b having a thickness of 20 nm are formed on the SiO ₂ layer (undercoat layer) 2 of the glass substrate 1 by a sputtering method. Are formed at positions corresponding to the source region and the drain region which will be formed in a later step. Here, instead of the titanium film, another metal layer such as cobalt or nickel may be used (FIG. 4A).

(B3) Next, the metal layer (titanium film) 12
Then, an amorphous silicon layer (a-
Si layer) 3 is formed, and dehydrogenation treatment is performed at a temperature of 450 ° C. in a nitrogen atmosphere (FIG. 4B).

(C3) Subsequently, the a-Si layer 3 is melt-crystallized (polysiliconized) by laser annealing using an excimer laser using XeCl, KrF, etc. as an excitation gas, and further, photolithography and etching are performed. An island-shaped p-Si layer 4 is formed (FIG. 4).
(C)).

(D3) Further, as the gate insulating layer 5 so as to cover the p-Si layer 4, Si having a thickness of 100 nm is formed.
An O ₂ film is formed (FIG. 4 (d)).

(E3) Next, a MoW alloy film having a thickness of about 400 to 500 nm is formed by, for example, a sputtering method, and then photolithography and etching are performed to form the gate electrode 6 (FIG. 4 (e)). As the gate electrode, Ta and MoW were used instead of MoW alloy.
A laminated structure with an alloy may be used.

(F3) Subsequently, the gate electrode 6 is masked
As a first step, impurity doping is performed. doping
Is, for example, a dose amount of 5 × 10¹²Pieces / cm²In phosphorus ion
Should be injected. As a result, directly below the gate electrode
The channel region 7 is a region not doped with impurities.
The part except the channel region was doped with impurities.
n ^-Areas 8a and 8b are formed (FIG. 4 (f)).

(G3) Further, a resist mask 30 having openings in the regions to be the source region and the drain region is formed, and the second impurity doping is performed. Doping is
For example, phosphorus ions may be implanted at a dose of 1 × 10 ¹⁴ ions / cm ² . As a result, the regions doped with impurities at the first time and not doped with impurities at the second time have low impurity concentration regions (LDD regions) 9a and 9a.
b. Further, the regions doped with the impurities both times become regions (n ⁺ regions; source region 10 and drain region 11) having a high impurity concentration (FIG. 4G).

(H3) Next, after removing the resist mask, heat treatment is performed at a temperature of 450 ° C. for about 1 hour. As a result, silicon and titanium react in the source region 10 and the drain region 11, and the titanium silicide portion 13
a and 13b are formed (FIG. 4 (h)).

Then, (j1) -in the first embodiment
(11) is performed (see FIGS. 1 and 2). Thus, a TFT including silicide in the source region and the drain region is obtained.

In this embodiment, since the metal layer is formed by patterning in advance, there is an advantage that it can be easily applied to a fine TFT.

[Embodiment 4] In this embodiment, as shown in FIG. 5, first, (a1) to
(E1) is performed (see FIGS. 1 and 2).

(F4) Next, a resist mask having openings in the surfaces of the regions to be the source region and the drain region is formed, and the second impurity doping is performed. For the doping, for example, phosphorus ions may be implanted at a dose of 1 × 10 ¹⁴ ions / cm ² . As a result, the LDD region, the source region, and the drain region are divided.

(F4 ′) Subsequently, without removing the resist mask, for example, a dose amount of 1 × 10 ¹⁵ pieces / cm ² is formed at the same position as the position where the second impurity doping is performed.
Implants germanium ions. Thus, germanium ions are implanted into the regions to be the source region and the drain region, and the source region and the drain region are made of polycrystalline silicon germanium.

After that, (g1) to in the first embodiment
(11) is performed (see FIGS. 1 and 2). Thus, a TFT in which the source region and the drain region are composed of polycrystalline silicon germanium and which contains silicide is obtained.

In this embodiment, since the source region and the drain region are made of polycrystalline silicon germanium having a band gap smaller than that of polysilicon, it is easy to remove the carriers accumulated under the channel. Therefore, a TFT with high electron mobility can be provided.

Also in the present embodiment, the order of the steps is not limited to the above, and for example, germanium ions may be implanted prior to the second implantation of impurity ions. Further, germanium ions may be implanted after forming the titanium film. If the second impurity ion implantation or germanium ion implantation is performed after the titanium film is formed, titanium and silicon are efficiently mixed, and a homogeneous titanium silicide portion can be easily obtained. Alternatively, for example, germanium ions may be implanted at the same time as the second impurity ion implantation.

Germanium ions may be implanted also in the region corresponding to the LDD region. In this case, for example, germanium ions may be implanted after the first implantation of impurity ions.

Further, in each of the above steps, the silicide is formed using the metal layer, but the present invention is not limited to this, and for example, metal ion implantation may be adopted as described in the second embodiment.

FIG. 6 shows the relationship between the heat treatment temperature and the on-current of the TFT manufactured according to the above-described embodiment (Embodiment 4). Here, TF that generated silicide during heat treatment
The T was compared with the TFT that was heat-treated without generating silicide.

Sample A is a TFT in which the source region and the drain region contain silicide and are composed of polycrystalline silicon germanium (Ge concentration 40 atomic%). Sample B is a TF in which the source region and the drain region contain silicide and are made of polycrystalline silicon.
T. On the other hand, the sample C is a TFT in which the source region and the drain region do not contain silicide and are composed of polycrystalline silicon germanium (Ge concentration 40 atomic%). Sample D is a TFT in which the source region and the drain region do not contain silicide and are made of polycrystalline silicon. In FIG. 6, comparing sample A with sample C and sample B with sample D,
It can be seen that the heat treatment temperature for obtaining a predetermined on-current becomes relatively low by forming the silicide.

[Fifth Embodiment] (a5) First, Si of the glass substrate 1 is formed by plasma CVD or low pressure CVD.
A having a thickness of 100 nm on the O ₂ layer (undercoat layer) 2
-Si layer 3 is formed (FIG.7 (a)).

(B5) Next, the a-Si layer 3 is removed by photolithography and etching except the regions 3a and 3b corresponding to the source region and the drain region (FIG. 7B).

(B5 ') Subsequently, the a-Si layers 3a, 3
After removing the natural oxide film on the surface of b by etching with dilute hydrofluoric acid, the thickness is quickly increased to 50 nm by the plasma CVD method.
The a-Si layer 3c having a certain degree is formed. Further, this layer is subjected to dehydrogenation treatment at 450 ° C. in a nitrogen atmosphere. a-S
The i layer is a region 3 corresponding to the source region and the drain region.
a and 3b are thick (thickness 150 nm), and other portions are thin (thickness 50 nm) (FIG. 7C).

(B5 ″) Further, laser anneal using an excimer laser using XeCl, KrF or the like as an excitation gas is performed to melt and crystallize the a-Si layer 3 (p-Si conversion).
Then, the island-shaped p-Si layer 4 is formed by photolithography and etching. This island-shaped p-Si layer 4
In, the source and drain regions are relatively thick, and the region connecting both regions is relatively thin (FIG. 7D).

After that, (c1) -in the first embodiment
(11) is performed (see FIGS. 1 and 2). In this way, a TFT including silicide in the thickened source region and drain region is obtained.

In this embodiment, since the source region and the drain region are relatively thickened, the silicide is not present in the source region and the drain region at the junction with the region interposed between the two regions. So that it can be easily formed. A good bond can be achieved by eliminating the silicide from the bond. In addition, since it is possible to prevent silicide from becoming a source of leak current, it is possible to suppress an increase in off current.

[Embodiment 6] (a6) First, the thickness of 150 nm is formed on the SiO ₂ layer (undercoat layer) 2 of the glass substrate 1 by the plasma CVD method or the low pressure CVD method.
A-Si layer 3 is formed (FIG. 8A).

(B6) Next, a region corresponding to the channel region and the LDD region (region connecting the source region and the drain region) is thinned by photolithography and etching so as to have a thickness of about 50 nm.
The Si layer 3d is formed (FIG. 8B). Then, the natural oxide film on the surface of this layer is removed with dilute hydrofluoric acid, and dehydrogenation treatment is further performed at a temperature of 450 ° C. in a nitrogen atmosphere.

(B6 ') Subsequently, the melt crystallization (polysiliconization) of the a-Si layer 3 is performed by laser annealing using an excimer laser using XeCl, KrF or the like as an excitation gas, and photolithography and etching are performed. The island-shaped p-Si layer 4 is formed. This island-shaped p-S
The i-layer 4 has a relatively thick portion serving as a source region and a drain region and a relatively thin region connecting both regions (FIG. 8C).

After that, (c1) through in the first embodiment
(11) is performed (see FIGS. 1 and 2). According to this embodiment, a TFT including silicide in the thickened source region and drain region can be obtained as in the fifth embodiment. In this embodiment, the film formation of a-Si is required only once. This TF
T also has a good junction, and an increase in off current is suppressed.

Although the silicide is formed by using the metal layer in the fifth and sixth embodiments, the same effect can be obtained in the TFT in which the silicide is generated by implanting the metal ions.

The on-current and off-current of the TFT in which the thickness of each region of the silicon-based semiconductor layer was controlled were measured according to the present embodiment (embodiment 6). In FIG. 9, the thickness of the source region and the drain region including silicide is constant (100 nm).
The relationship between the thickness of the channel region and the on-current and off-current in the case of is shown. As shown in FIG. 9, when the thickness of the channel region was 40 nm or more and 70 nm or less, high on-current and low off-current could be realized at the same time.

FIG. 10 shows the relationship between the thickness of the source and drain regions containing silicide and the on-current and off-current when the thickness of the channel region (correctly, the channel region and the LDD region) is constant (50 nm). Indicates.
As shown in FIG. 10, when the thickness of the source region and the drain region was 100 nm or more, a high on-current and a low off-current could be realized at the same time.

From FIG. 9 and FIG. 10, when the thickness of the channel region is 40 nm or more and 70 nm or less and the thickness of the source region and the drain region containing silicide is 100 nm or more, a sufficient ON current and a sufficiently low OFF current can be obtained. It was confirmed that the thin film transistor has good driving characteristics.

[Embodiment 7] In this embodiment, an example in which the method of simultaneously forming a silicide and crystallizing an a-Si layer is applied to an a-Si layer having a different film thickness will be described. To do.

First, an a-Si layer having a thickness of about 100 nm is formed on the SiO ₂ film (undercoat film) of the glass substrate by the plasma CVD method or the low pressure CVD method, and annealed at about 450 ° C. in a nitrogen atmosphere for dehydration. Perform simplification. Then, the thickness is about 20n by the sputtering method.
A metal layer (titanium film) of m is formed, and the titanium film is patterned so that the film remains at the positions which will be the source region and the drain region. Subsequently, the a-Si layer other than the source region and the drain region is dry-etched by about 50 nm to cause a difference in thickness between the layers.

Further, the resist film used for etching is removed, and laser annealing is performed using an excimer laser using XeCl, KrF or the like as an excitation gas. By this laser annealing, while a metal silicide (titanium silicide) is generated in the a-Si layer, this layer is melted and crystallized.

Thereafter, for example, similar to the above-described embodiment,
A gate insulating film or the like may be sequentially formed (for example, d3 to h3 in Embodiment 3 and j1 to l1 in Embodiment 1 are sequentially performed).

When impurity ions are implanted in the subsequent steps, the ion-implanted silicon-based semiconductor layer becomes amorphous, but this amorphous portion is recrystallized by the subsequent heating step. Also in this heating step, the temperature of the heat treatment may be low because the silicide acts as a crystal nucleus.

As in this embodiment, when laser light is irradiated through the metal layer, or when titanium ions are previously injected into the surface layer of the semiconductor layer and then laser light is irradiated, the silicide is generated by the laser light irradiation. . When the metal layer is in contact with the semiconductor layer melted by irradiation with laser light, silicide is likely to be formed.

[Exemplary Film Structure of TFT] The TFT shown in FIG. 11 can be manufactured according to the first and second embodiments. In the second embodiment, the depth of the silicide portion may be controlled by controlling the implantation of titanium ions.

In this TFT, the semiconductor layer 20, the gate insulating layer 5, the gate electrode 6, the interlayer insulating layer 14, and the passivation film 18 are laminated in this order on the surface of the undercoat layer 2 on the glass substrate 1. The semiconductor layer 20 includes a channel region 7 located directly below the gate electrode 6, and a source region (n ⁺ region) 10 and a drain region (n ⁺ region) 11 arranged so as to sandwich the channel region 7 and having a high impurity concentration. And a region (LDD region, n ⁻ region) 9 a, 9 b having a low impurity concentration, which is arranged between the channel region 7 and the source region 10 and the drain region 11.

On the surfaces of the source region 10 and the drain region 11, there are silicide portions 13a and 13b, respectively. In this TFT, the silicide portions 13a, 13b
Are formed in contact with the source electrode 17a or the drain electrode 17b. The source electrode 17a and the drain electrode 17b are connected to the source region 10 and the drain region 11 via contact holes penetrating the gate insulating layer 5 and the interlayer insulating layer 14, respectively.

The TFT shown in FIG. 12 is the same as the TFT shown in FIG. 11 except that the source region 10 and the drain region 11 in the silicon semiconductor layer 20 are thicker than the other regions. This TFT can be obtained by the manufacturing method of the fifth and sixth embodiments.

[Embodiment 8] In this embodiment, a TFT in which an insulating side wall (sidewall) is arranged on the side surface of a gate electrode will be described. As shown in FIG. 13, by disposing the sidewalls 21a and 21b, it is possible to provide a TFT with improved insulation and a small off current.

The side wall has a thickness of about 500 by plasma CVD after the first impurity doping, for example.
If a silicon oxide film is anisotropically etched by a dry etching method under the condition that a silicon oxide film having a thickness of 1 nm is formed and then an etching selection ratio with respect to polycrystalline silicon can be sufficiently secured, it is self-aligned with the side surface of the gate electrode. Can be formed into

The side wall is not limited to the silicon oxide film, but may be a laminated film of a silicon oxide film and a silicon nitride film. In this case, a silicon oxide film having good adhesion to the gate electrode or the gate insulating film may be located on the gate electrode side or the like.

The TFT shown in FIG. 13 can be manufactured in the same manner as in the first and second embodiments except that the sidewall is formed.

The sidewall has a great effect on improving the insulating property when the gate length (GL in FIG. 13) is 2 μm or less.

The present invention is not limited to the form described above, and may be, for example, the following TFT. (1) Bottom gate type TF, not top gate type
It may be T. (2) Not limited to the n-channel TFT, a p-channel TFT using boron or the like as an impurity may be used. (3) A region having the same concentration as the impurity concentration of the channel region may be arranged between the channel region and the source and drain regions (the LDD region may not be formed). (4) Polycrystalline silicon germanium carbon may be used for the silicon-based semiconductor layer, instead of polycrystalline silicon or polycrystalline silicon germanium. (5) Polycrystalline silicon germanium may be used as the gate electrode. If this is used as a gate electrode, p
It is possible to use a p-type gate electrode for the type TFT and an n-type gate electrode for the n-type TFT. Therefore, the threshold voltage can be reduced.

[0129]

As described above, according to the present invention,
Silicide is generated by heat treatment of the silicon-based semiconductor layer. Since this silicide acts as a crystal nucleus, the silicon-based semiconductor layer can be crystallized at a lower temperature than in the past. Therefore, even in the case of a fine TFT, variations in driving characteristics are reduced. By using this TFT, it is possible to provide an inexpensive, small-sized and lightweight liquid crystal display device or organic EL display device.

[Brief description of drawings]

FIG. 1 is a flow chart for explaining an example of a method of manufacturing a thin film transistor (TFT) according to the present invention.

FIG. 2 is a process drawing for explaining the manufacturing method shown in FIG. 1 in more detail.

FIG. 3 is a process drawing for explaining a modified example of the manufacturing method shown in FIGS. 1 and 2.

FIG. 4 is a cross-sectional view for explaining another modification of the manufacturing method shown in FIGS. 1 and 2.

5 is a flowchart for explaining another modification of the manufacturing method shown in FIGS. 1 and 2. FIG.

FIG. 6 is a graph showing the relationship between the heat treatment temperature of the TFT and the on-current.

FIG. 7 is a cross-sectional view for explaining still another modified example of the manufacturing method shown in FIGS. 1 and 2.

FIG. 8 is a cross-sectional view for explaining still another modification of the manufacturing method shown in FIGS. 1 and 2.

FIG. 9 is a graph showing the relationship between the thickness of the channel region and the current value of the TFT.

FIG. 10: Thickness of source and drain regions and TF
It is a graph which shows the relationship with the electric current value of T.

FIG. 11 is a cross-sectional view showing an example of the TFT of the present invention.

FIG. 12 is a cross-sectional view showing another example of the TFT of the present invention.

FIG. 13 is a cross-sectional view showing another example of the TFT of the present invention.

FIG. 14 is a cross-sectional view of a conventional TFT.

FIG. 15 is a flowchart showing an example of a conventional TFT manufacturing method.

FIG. 16 is a process chart for explaining the conventional method shown in FIG. 15 in more detail.

FIG. 17 is a diagram showing wiring in an example of a liquid crystal display device using the TFT of the present invention.

FIG. 18 is a diagram showing wiring in an example of an organic EL display device using the TFT of the present invention.

[Explanation of symbols]

1 substrate 2 Undercoat layer 5 Gate insulation layer 6 Gate electrode 7 channel area 9a, 9b LDD region 10 Source area 11 drain region 13a, 13b silicide part 14 Interlayer insulation layer 17a Source electrode 17b drain electrode 18 Passivation film 20 Silicon semiconductor layer

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/78 616A 627G F term (reference) 2H092 JA24 KA02 KA07 MA06 MA27 MA28 MA29 NA24 5F052 AA01 AA02 BB07 DA02 DB02 DB03 EA13 EA15 FA19 HA03 HA07 JA01 5F110 AA01 AA03 AA06 BB01 CC02 CC04 DD02 DD13 EE04 EE06 EE08 EE09 EE14 EE32.2 PP16 PP26 PP35 PP36 QQ08 QQ11 QQ23 QQ24

Claims (23)

[Claims] 1. A silicon-based semiconductor layer including a channel region, a source region and a drain region arranged so as to sandwich the channel region, a source electrode electrically connected to the source region, and the drain A thin film transistor including a drain electrode electrically connected to a region, and a gate electrode insulated from the source electrode and the drain electrode, wherein the source region and the drain region include silicide. Thin film transistor. 2. The thin film transistor according to claim 1, wherein the silicon-based semiconductor layer contains silicon and germanium. 3. The thin film transistor according to claim 1, wherein the source region and the drain region contain silicon and germanium, and the channel region is a silicon layer. 4. The thin film transistor according to claim 3, wherein the germanium concentration in the source region and the drain region is 1 atom% or more and 80 atom% or less. 5. The thin film transistor according to claim 1, wherein the silicide is formed at least at an interface with the source electrode in the source region and an interface with the drain electrode in the drain region. 6. The thin film transistor according to claim 5, wherein the silicide is not formed on the interface except the interface with the source electrode in the source region and the interface with the drain electrode in the drain region. 7. The channel region, when observed along the thickness direction of the silicon-based semiconductor layer, includes a portion thinner than any portion including silicide in the source region and the drain region. The thin film transistor according to. 8. The thickness of a portion including silicide in the source region and the drain region is 100 nm or more when observed along the thickness direction of the silicon-based semiconductor layer,
The thin film transistor according to claim 1, wherein the channel region includes a portion having a thickness of 40 nm or more and 70 nm or less. 9. The silicon-based semiconductor layer has a higher impurity concentration than the channel region between the channel region and the source region and between the channel region and the drain region, respectively. The thin film transistor according to claim 1, further comprising a lower region. 10. The thin film transistor according to claim 1, further comprising an insulating side wall arranged so as to be in contact with at least a pair of side surfaces of the gate electrode facing each other. 11. The thin film transistor according to claim 10, wherein the distance between the pair of side surfaces contacting the side wall is 2 μm or less. 12. A silicon-based semiconductor layer including a channel region, a source region and a drain region arranged so as to sandwich the channel region, a source electrode electrically connected to the source region, and the drain A method of manufacturing a thin film transistor, comprising: a drain electrode electrically connected to a region; and a gate electrode insulated from the source electrode and the drain electrode, the method comprising: forming a silicon-based semiconductor layer; A step of implanting impurity ions into at least a region to be the source region and the drain region of the layer, and a heating step of heating the silicon-based semiconductor layer to crystallize at least a part of the silicon-based semiconductor layer. By heating in the heating step, the source region of the silicon-based semiconductor layer and In the drain region,
A method of manufacturing a thin film transistor, which comprises forming a silicide. 13. The method of manufacturing a thin film transistor according to claim 12, wherein the silicon-based semiconductor layer is heated to 450 ° C. or lower in the heating step. 14. The method of manufacturing a thin film transistor according to claim 12, wherein the silicon-based semiconductor layer contains silicon and germanium. 15. The silicon-based semiconductor layer is formed so that the channel region includes a portion thinner than any of the source-containing region and the drain-containing region when observed along the thickness direction of the silicon-based semiconductor layer. The thin film transistor according to claim 12, which is formed. 16. The thin film transistor according to claim 12, further comprising a step of forming an insulating side wall on a side surface of the gate electrode. 17. The method further comprises the step of forming a metal layer so as to contact the silicon-based semiconductor layer before the heating step, and in the heating step, the metal contained in the metal layer and the silicon-based semiconductor layer are included. The method of manufacturing a thin film transistor according to claim 12, wherein silicide is generated from silicon. 18. The method further comprises the step of forming an insulating layer so as to cover a part of the silicon-based semiconductor layer before the step of forming the metal layer, wherein the step of forming the metal layer is covered with the insulating layer. 18. The metal layer is formed so as to be in contact with the surface of the silicon-based semiconductor layer which is not exposed.
7. A method of manufacturing a thin film transistor according to. 19. The method further comprises the step of implanting metal ions into the silicon-based semiconductor layer before the heating step, wherein in the heating step, silicide is generated from the metal ions and silicon contained in the silicon-based semiconductor layer. The method for manufacturing a thin film transistor according to claim 12, wherein the method is used. 20. Before the step of implanting impurity ions,
A step of crystallizing a silicon-based semiconductor layer formed as an amorphous layer, wherein at least a part of the crystallized silicon-based semiconductor layer in the source region and the drain region is amorphized by implanting the impurity ions. Item 20. A method of manufacturing a thin film transistor according to any one of Items 12 to 19. 21. The method of manufacturing a thin film transistor according to claim 12, wherein the silicon-based semiconductor layer formed as an amorphous layer is crystallized in the heating step. 22. An array substrate including the thin film transistor according to claim 1 and a substrate, wherein the thin film transistor is arranged on the substrate. 23. An image display device comprising the thin film transistor according to claim 1 as a pixel switching element.