JP2003044540A - Layout verification device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a verification apparatus for layout capable of detecting simply and correctly wiring with a high probability of an occurrence of a cross- talk and of outputting wiring information to an apparatus for layout in the next stage. SOLUTION: The verification apparatus for layout to search wiring with a probability of an occurrence of a cross-talk when performing layout processing and wiring processing from a net list having no layout information according to an experience of a circuit designer, experimental data, etc., specifically, wiring with satisfaction at a specific connecting relation filled by wiring with a high probability of being parallel and adjacent, and to output information on the searched wiring, for example, as a layout rule specifying wiring not to be wired adjacently each other to the apparatus for layout in the next stage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout verification device for verifying the presence or absence of wiring that may cause crosstalk during layout design of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, when a plurality of metal wirings, especially signal lines run in parallel with each other over a long distance, the ratio of coupling capacitance increases and crosstalk may occur. It is known to be extremely high. In order to prevent the semiconductor circuit from malfunctioning due to the occurrence of the crosstalk, wirings that run in parallel for a long distance should be removed as much as possible in the design stage.

In order to prevent the occurrence of the above crosstalk,
There is known an automatic placement and routing method of performing layout verification after performing layout processing and wiring processing, detecting wirings in which crosstalk may occur, and correcting layout (Japanese Patent Laid-Open No. 10-308451). , JP-A-10-178100, JP-A-2000-29923.
No. Usually, the above-mentioned layout modification is repeatedly performed until the wiring that may cause crosstalk is not detected.

[0004]

In the above-described conventional automatic placement and routing method, layout processing and wiring processing are first executed based on a netlist having no layout information, and then layout verification and layout correction are performed.
Although there are differences depending on the scale of the semiconductor integrated circuit under design, layout processing and wiring processing require a very long time. In particular, in the first layout verification, the wiring to be subjected to the layout correction should be detected most, and the layout correction also requires a lot of time. In order to reduce the total time required for designing a semiconductor integrated circuit, it is preferable that the number of times the layout process and the wiring process are performed be small.

The present invention detects wirings that are likely to cause crosstalk easily and accurately before executing layout processing and wiring processing, and outputs the wiring information to the layout device of the next stage (the above-mentioned conventional method). It is an object of the present invention to provide a layout verifying device which outputs the data to the layout verification device including those adopting the automatic placement and routing method of.

[0006]

A first layout verifying apparatus of the present invention searches at least a wiring which satisfies a specific connection relation which a wiring in question lays out, from a netlist before layout processing. It is characterized by comprising a search means for performing.

According to a second layout verifying apparatus of the present invention, in the first layout verifying apparatus, the retrieving means determines from the netlist that a specific wiring which may cause crosstalk when laid out is satisfied. The feature is that the wiring that satisfies the connection relation is searched.

A third layout verifying apparatus of the present invention is the layout verifying apparatus according to any one of the above, further outputs information about the wiring searched by the searching means in the form of a layout rule usable by the layout apparatus. An output means is provided.

According to a fourth layout verifying apparatus of the present invention, in the second or third layout verifying apparatus, the searching means lays out wirings connected between the same functional blocks from the netlist. In this case, the search is performed as a group of wirings that may cause crosstalk.

According to a fifth layout verifying apparatus of the present invention, in the second or third layout verifying apparatus, the searching means is based on a netlist and arrangement information of signal output lines provided in each functional block. Of the plurality of signal output lines included in each functional block, at least adjacent signal output lines are searched as a group of wiring lines that may cause crosstalk when laid out.

According to a sixth layout verifying apparatus of the present invention, in the second or third layout verifying apparatus, the searching means is based on a netlist and arrangement information of signal input lines provided in each functional block. , Among the multiple signal input lines that each functional block has, search for the group of adjacent signal input lines to which the sync signal is input as the group of wiring lines that may cause crosstalk when laid out. Characterize.

A seventh layout verifying apparatus according to the present invention is the layout verifying apparatus according to the second or third aspect, wherein the searching means is a plurality of wirings provided between the same functional blocks from the netlist. Wiring having a predetermined number or less of cells to be searched is searched for as a group of wiring that may cause crosstalk when laid out.

According to an eighth layout verifying apparatus of the present invention, in the second or third layout verifying apparatus, the searching means includes a netlist, layout information of I / O pads of a semiconductor chip under design, Further, based on the arrangement information of the signal lines included in each functional block, the group of wirings connected to the adjacent I / O pads of the semiconductor chip under design among the adjacent signal lines included in each functional block is laid out. It is characterized in that it searches as a group of wirings that may cause crosstalk if they are given.

A first program of the present invention is a program which can be read by a computer, and a specific connection relationship which is satisfied by wiring which causes a problem when the computer is laid out from at least a netlist before layout processing. It is characterized in that it functions as a layout verification device having a search means for searching for wiring that satisfies the above condition.

In a second program of the present invention, in the first program, as the search means, a specific connection relation satisfied by a plurality of wiring lines which may cause crosstalk when laid out from the netlist is used. It is characterized in that the computer is made to function so as to search for a plurality of wirings satisfying

A third program of the present invention is any one of the above-mentioned programs, wherein the output means outputs the information about the wiring searched by the searching means in the form of a layout rule usable by the layout device. It is characterized by operating a computer.

A fourth program of the present invention is the second or third program, wherein the searching means lays out a plurality of wirings connected between the same functional blocks from the netlist. It is characterized in that the above-mentioned computer is operated so as to search for a group of wirings which may cause crosstalk in some cases.

A fifth program of the present invention is the above-mentioned second or third program, wherein the searching means uses each of the netlists as well as the arrangement information of the signal output lines provided in each functional block. Characterized in that the computer is made to function so as to search at least adjacent signal output lines among a plurality of signal output lines included in the functional block as a group of wiring lines that may cause crosstalk when laid out. To do.

A sixth program of the present invention is the above-mentioned second or third program, wherein the searching means uses each of the netlists and the arrangement information of the signal input lines provided in each functional block, based on the arrangement information. Among the plurality of signal input lines provided in the functional block, the group of adjacent signal input lines to which the synchronizing signal is input is searched for as a group of wiring lines that may cause crosstalk when laid out. It is characterized by operating.

A seventh program of the present invention is the second or third program, wherein the searching means is a plurality of wirings provided between the same functional blocks from the net list, and the intervening cells are present. Is characterized in that the computer is made to function so as to search for a wiring whose number is less than or equal to a predetermined number as a group of wiring which may cause crosstalk when laid out.

An eighth program of the present invention is the second or third program, wherein the searching means has a netlist, placement information of I / O pads of a semiconductor chip under design, and Based on the arrangement information of the signal lines included in each functional block, the group of wirings connected to the adjacent I / O pads of the semiconductor chip under design among the adjacent signal lines included in each functional block is laid out. It is characterized in that the above-mentioned computer is operated so as to search for a group of wirings which may cause crosstalk in some cases.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION (1) Outline of the Invention The layout verification apparatus of the present invention is used when a layout process and a wiring process are performed from a netlist having no layout information based on the experience of a circuit designer or experimental data. Satisfies a specific connection relationship (hereinafter, the specific connection relationship is referred to as a wiring rule) that is satisfied by a wiring that may cause crosstalk, specifically, a wiring that is likely to run in parallel in close proximity. It is characterized in that the wiring is searched and the information about the searched wiring is output to the layout device at the next stage, for example, as a layout rule for designating the wiring that should not be wired closely. As described above, the layout verification apparatus of the present invention verifies the layout without performing the layout process and the wiring process that require a long time.

According to the layout rule output from the layout analysis device, the layout device may, for example, space the wirings running in parallel, interpose another wiring capable of suppressing crosstalk, or delay one wiring. Take measures such as inserting the element. As a result, particularly in the first layout processing, the number of wirings searched for as wirings running in close proximity can be significantly reduced, and the time required for layout correction can be significantly reduced. Hereinafter, an embodiment of a layout verification device will be described with reference to the accompanying drawings.

(2) Embodiment <2-1> Overall Configuration FIG. 1 shows a layout verification apparatus 100 according to an embodiment.
It is a block diagram of. A central processing unit (referred to as CPU in the figure) 1 controls the entire apparatus. ROM2 has O
An S (Operation System) program is stored. The OS program is the layout verification device 10
It is executed when 0 is started. The RAM 3 is used as a work area when executing the layout verification process. The hard disk (referred to as HD in the drawing) 4 is an electromagnetic information recording medium, and stores a layout verification program described below and a netlist having no layout information of the semiconductor integrated circuit under design. ing. The layout verification program is executed after being read from the hard disk 4 to the RAM 3. Further, the layout verification program is recorded in a recording medium (for example, a CD-ROM) other than the hard disk 4, and the corresponding reading device (CD
A configuration may be adopted in which the RAM 3 is read by a (ROM reading device). Display 5, keyboard 7, and
The mouse 6 functions as a man-machine interface and is used when performing various settings in the layout verification processing, for example, setting of additional wiring rules. As described above, the above wiring rule is a wiring that is likely to cause crosstalk when layout processing and wiring processing are performed, specifically, a wiring that is likely to run in close proximity and meet. Connection relationship.

<2-2> Flow of Layout Verification Processing FIG. 2 is a diagram showing the processing contents executed by the CPU 1 in accordance with the layout verification program. First, the netlist 4a having no layout information is read from the hard disk 4 (step S4). Next, the first to fifth wiring rules 4b are read from the hard disk 4 (step S2). The contents of the first to fifth wiring rules will be described later. Then, the information about the arrangement of the input / output terminals of each block of the semiconductor chip and the arrangement information of the I / O pads provided on the semiconductor chip are read from the hard disk 4 (step S3). The net group specified according to each wiring rule is searched (step S4). The information of the net group obtained as a result of the search is output (step S5). Here, the information of the net group means that wirings belonging to the same group are apt to cause crosstalk, and therefore are separated by a predetermined value or more, and
It is a layout rule that does not run in parallel, and is of a type that can be used by the layout device used for design.

<2-3> Description of Each Functional Means FIG. 3 is a diagram showing each functional means as a layout verifying apparatus which is configured by executing the layout verifying program. The netlist reading means 1a reads the netlist 4a from the hard disk 4 when the layout verification is started.
Is read and output to the net group search means 1b.
The rule reading means 1c is the first from the hard disk 4.
~ Read the fifth wiring rule 4b and output it to the net group search means 1b. In addition to the first to fifth wiring rules, the wiring rules described by the rule description means 7a may be adopted. The rule description means 7a corresponds to the display 5, the mouse 6, and the keyboard 7.

The block information reading means 1d reads from the hard disk 4 the information 4c regarding the arrangement of the input / output terminals of the signals provided in each functional block, and outputs it to the net group searching means 1b. Here, the functional block is
A block in which necessary cells are gathered to perform one function. ROM, R configured in one semiconductor chip
AM, CPU, etc. correspond to this. The terminal layout reading means 1 is provided on the semiconductor chip from the hard disk 4.
The / O pad arrangement information 4d is read and output to the net group search means 1b. The arrangement information 4c of the signal input / output terminals and the arrangement information 4d of the I / O pad of each functional block are design items and are prepared separately from the netlist.

The net group search means 1b uses the net list and, if necessary, the block information 4c and the terminal arrangement information 4d in accordance with the first to fifth rules, and nets (wiring lines) that may run in parallel. The respective groups are searched and the information of the net group specified by the search process is output to the net group information output means 1f. The output unit 1f stores the net group information 4e collected for each rule in the hard disk 4 as a layout rule for designating wirings that should not run in parallel in parallel. A layout device 50 surrounded by a dotted line in this figure
In addition to the netlist 4a, the group information 4e collected for each rule from the hard disk 4 is read as a layout rule that specifies wirings that should not run in parallel in close proximity, and layout processing and wiring processing are executed. . It should be noted that the reference value for determining whether or not the wirings are "close to each other" is specified based on, for example, experimental data obtained by examining the distance between lines and the occurrence rate of crosstalk.

(3) Description of First to Fifth Wiring Rules The contents of the net group search processing executed in accordance with the first to fifth wiring rules in step S4 of FIG. 2 will be sequentially described below.

<3-1> First Wiring Rule The first wiring rule is based on an empirical rule that wirings connected between the same functional blocks are likely to run in parallel with each other. Yes, stipulates that the wiring having the relationship is searched based on the netlist 4a.

FIG. 4 is a diagram showing a state of wiring provided between the functional blocks when a part of the functional blocks X1 to X5 developed in the semiconductor chip under design is laid out. According to the first rule, the wirings A and B provided between the functional block X1 and the functional block X3 are searched for as a net group G ₁₁ that is highly likely to run in parallel with each other. Similarly, the wirings C and D are the net group G.
₁₂ , the wirings G, H, and M are in the net group G ₁₃ , the wirings I and J are in the net group G ₁₄ , the wirings B, L, and K are in the net group G ₁₅ , and the wirings B, C, and D are in the net group G _13. Searched as ₁₆ .

<3-2> Second Wiring Rule In addition to the netlist 4a, the second wiring rule is based on the arrangement information 4c of the signal input / output terminals of each functional block. Of the signal output terminals,
In particular, it is specified to search for wirings that are often provided adjacent to each other, such as parallel signal output terminals, as a group of wirings where crosstalk easily occurs.

FIG. 5 is a diagram showing signal input / output terminals provided in a certain functional block X6 and their positions. The functional block X6 has a total of x signal output terminals N0 to N.
with x. The wirings extending from these signal input / output terminals are searched for as a group G ₂₁ of wirings that run close to each other and easily cause crosstalk.

<3-3> Third Wiring Rule The third wiring rule is that, in addition to the netlist 4a, based on the arrangement information 4c of the signal input / output terminals provided in each functional block, the functional blocks are arranged adjacent to each other. Among the signal input terminals provided, the input signal lines output from the circuit elements (cells) that operate based on the same clock signal are
It specifies to search as a group of wirings that are prone to crosstalk.

FIG. 6 shows an input provided in a certain functional block X7.
It is a figure which shows an output terminal and its position. First clock signal
Flip-flop FF that operates based on CLK1₀~
FF _nSignal output terminals and signal input of functional block X7
Terminal A₀~ A_nWiring M connecting with₀~ M_nA single
Loop G₃₁Search as. Also, the second clock signal
Flip-flop FF that operates based on CLK2
_{n + 1}~ FF_yOf each signal output terminal and function block X7
Signal input terminal A_{n + 1}~ A_yWiring M connecting with_{n +1}
~ M_yA group G₃₂Search as. In addition,
Determine the type of signal from the netlist 4a, and
You may make it search only the input terminal of the number.

<3-4> Fourth Wiring Rule The fourth wiring rule is an extension of the first wiring rule. The smaller the number of cells included in the wiring between the functional blocks, the longer the wiring. Therefore, it is determined that crosstalk is likely to occur, and the netlist is searched for adjacent wires having two or less intervening cells as a group of wires that easily cause crosstalk. Stipulate.

FIG. 7 shows wiring provided between the functional blocks X8 and X9. The route A includes a total of three circuit elements s1, s2, and s3 in between. The route B has only one circuit element s4 in between. The route C includes a total of four circuit elements s5, s6, s7, and s8. According to the fourth rule,
None of the wirings between the functional block X8 and the functional block X9 illustrated are searched for as a group of wirings that easily cause crosstalk.

<3-5> Fifth Wiring Rule The fifth wiring rule is that, in addition to the netlist 4a, arrangement information 4c of signal input / output terminals provided in each functional block, and
Based on the information 4d about the arrangement of the I / O pads provided on the semiconductor chip under design, when the adjacent wirings of the same functional block are connected to the adjacent I / O pads at the opposite positions, It is specified that the book wires are searched as a group that easily causes crosstalk.

FIG. 8 shows functional blocks X10 and X11,
It is a figure which shows the I / O pad provided in the said functional block vicinity. As illustrated, a total of n wirings N1 to Nn connected to I / O pads P1 to Pn provided in parallel are provided.
_Are searched as one group G ₅₁ . Further, a total of four wirings Nn + 1 to Nn + 4 connected to the I / O pads Pn + 1 to Pn + 4 provided in parallel are searched as one group G ₅₂ . For example, I / O pad Py
The wirings Ny and Nz connected to the pads provided apart from each other with the corner interposed therebetween are not grouped like P and Pz.

As described above, the layout analysis apparatus 100 is highly likely to cause crosstalk before actually executing the layout processing according to the experience of the designer and the wiring rule obtained based on the experimental data. The wiring is searched, and information about the net group based on the search result is output as layout data.

[0041]

The first layout verifying apparatus of the present invention and the layout verifying apparatus realized by executing the first program have a problem when the layout is performed from the net list before the layout processing. By searching for the wiring that satisfies the specific connection relationship that the
Wiring that is likely to cause a problem when laid out can be specified. The processing time can be significantly shortened as compared with the case of searching for a wiring that causes a problem after actually performing the layout processing and the wiring processing.

The second layout verifying apparatus of the present invention and the layout verifying apparatus realized by executing the second program cause crosstalk when laid out from the netlist before the layout processing. By searching for a wiring that satisfies a specific connection relationship that the wiring satisfies, it is possible to specify a wiring that is likely to cause crosstalk when laid out. The processing time can be significantly shortened as compared with the case of searching for a wiring that causes a problem after actually performing the layout processing and the wiring processing.

In the third layout verifying apparatus of the present invention and the layout verifying apparatus realized by executing the third program, the layout apparatus can use the information about the wiring retrieved by any of the above apparatuses. By outputting the information in various forms, it becomes possible to take measures against wiring that may cause problems such as crosstalk when executing the first layout process, aiming at the end of semiconductor chip design time. be able to.

The fourth layout verifying apparatus of the present invention and the layout verifying apparatus realized by executing the fourth program are the same as those in the second or third layout verifying apparatus described above. A plurality of wirings to be connected are searched for as wirings that may cause crosstalk when laid out. As a result, it is possible to significantly reduce the processing time as compared with the case of searching for a wiring that causes a problem after actually performing the layout processing and the wiring processing.

A fifth layout verifying apparatus of the present invention and a layout verifying apparatus realized by executing a fifth program are the plurality of functions provided in each functional block in the second or third layout verifying apparatus. Among the signal output lines of, adjacent wirings are searched for as wirings that may cause crosstalk when laid out.
As a result, it is possible to significantly reduce the processing time as compared with the case of searching for a wiring that causes a problem after actually performing the layout processing and the wiring processing.

A sixth layout verifying apparatus of the present invention and a layout verifying apparatus realized by executing a sixth program are the same as those of the second or third layout verifying apparatus, each of which has a plurality of functional blocks. Among the signal input lines of, the signal input line to which the synchronization signal is input is searched for as a wiring that may cause crosstalk when laid out. As a result, it is possible to significantly reduce the processing time as compared with the case of searching for a wiring that causes a problem after actually performing the layout processing and the wiring processing.

A seventh layout verifying apparatus of the present invention and a layout verifying apparatus realized by executing a seventh program are the same as those in the second or third layout verifying apparatus described above, which have the same function blocks. A plurality of wirings to be provided, which are adjacent to each other through a predetermined number of cells or less, are searched for as wirings that may cause crosstalk when laid out. As a result, it is possible to significantly reduce the processing time as compared with the case of searching for a wiring that causes a problem after actually performing the layout processing and the wiring processing.

An eighth layout verifying apparatus according to the present invention and a layout verifying apparatus realized by executing the eighth program are provided in each functional block of the second or third layout verifying apparatus. Among the output lines, a plurality of wirings connected to adjacent input / output pads of the designed semiconductor chip are searched for as wirings that may cause crosstalk when laid out.
As a result, it is possible to significantly reduce the processing time as compared with the case of searching for a wiring that causes a problem after actually performing the layout processing and the wiring processing.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a layout verification device.

FIG. 2 is a flowchart of a layout verification process.

FIG. 3 is a diagram for explaining each functional unit configured with execution of a layout verification program.

FIG. 4 is a diagram showing a wiring example of a functional block for explaining a first wiring rule.

FIG. 5 is a diagram showing a wiring example of a functional block for explaining a second wiring rule.

FIG. 6 is a diagram showing a wiring example of a functional block for explaining a third wiring rule.

FIG. 7 is a diagram illustrating a wiring example of a functional block for explaining a fourth wiring rule.

FIG. 8 is a diagram showing a wiring example of a functional block for explaining a fifth wiring rule.

[Explanation of symbols]

1 CPU, 1a Netlist reading means, 1b
Net group search means, 1c rule reading means,
1d block information reading means, 1e terminal arrangement information reading means, 1f net group information output means, 2
ROM, 3 RAM, 4 HD, 4a Netlist information, 4b rule information, 4c block information, 4d
Terminal layout information, 4e group information, 5 display, 6 mouse, 7 keyboard, 50 layout device.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Akihiro Ninomiya             1-3-3 Nakamagome, Ota-ku, Tokyo Stocks             Company Ricoh (72) Inventor Yasushi Fukushima             1-3-3 Nakamagome, Ota-ku, Tokyo Stocks             Company Ricoh F term (reference) 5B046 AA08 BA06 CA04 GA01 JA03                 5F064 BB09 BB13 BB15 BB35 DD20                       DD25 EE14 EE46 HH02 HH06                       HH09 HH10 HH11 HH14 HH17

Claims (16)

[Claims] 1. A layout verifying apparatus, comprising: at least a searching unit for searching a netlist before layout processing for a wire satisfying a specific connection relationship satisfied by a wire in layout. 2. The layout analysis device according to claim 1, wherein the search means searches the netlist for wirings satisfying a specific connection relationship satisfied by wirings that may cause crosstalk when laid out. A layout verification device characterized by searching. 3. The layout verifying device according to claim 1, further comprising an output unit that outputs information about the wiring searched by the searching unit in the form of a layout rule usable by the layout device. A layout verification device, characterized by comprising: 4. The layout verifying device according to claim 2, wherein the searching unit causes crosstalk when the wirings connected between the same functional blocks are laid out from the netlist. A layout analysis device, which searches for a group of wiring lines having a possibility. 5. The layout verification apparatus according to claim 2, wherein the search unit includes each net based on a layout information of a signal output line included in each functional block, in addition to a netlist. A layout analysis device, wherein at least adjacent signal output lines among a plurality of signal output lines are searched for as a group of wiring lines that may cause crosstalk when laid out. 6. The layout verifying device according to claim 2, wherein the searching unit includes each net based on a layout information of a signal input line included in each functional block, in addition to the netlist. A layout analysis device, wherein a group of adjacent signal input lines to which a synchronization signal is input is searched from among a plurality of signal input lines as a group of wiring lines that may cause crosstalk when laid out. . 7. The layout verifying device according to claim 2, wherein the searching unit is a plurality of wirings provided between the same functional blocks from the netlist, and the number of intervening cells is predetermined. A layout analysis apparatus, which searches for less than a few wirings as a group of wirings that may cause crosstalk when laid out. 8. The layout verifying device according to claim 2, wherein the searching means includes a netlist, I / O pad placement information of a semiconductor chip being designed, and functional blocks of each functional block. Based on the arrangement information of the provided signal lines, among the adjacent signal lines provided in each functional block, a group of wirings connected to the adjacent I / O pads of the semiconductor chip under design is laid out for crosstalk. A layout analysis device that searches as a group of wiring lines that may cause 9. A program readable by a computer, wherein the computer searches at least a netlist before layout processing for a wiring satisfying a specific connection relationship satisfied by a wiring that causes a problem when laid out. A program characterized by causing it to function as a layout verification device having a search means. 10. The program according to claim 9, wherein, as the search means, a specific connection relation satisfied by a plurality of wiring lines that may cause crosstalk when laid out is satisfied from the netlist. A program that causes the computer to function so as to search for a plurality of wirings. 11. The program according to claim 9 or 10, wherein the computer is used as output means for outputting information about the wiring found by the searching means in the form of a layout rule usable by a layout device. A program characterized by making a function of. 12. The program according to claim 10 or 11, wherein the search means crosstalks when a plurality of wirings connected between the same functional blocks are laid out from the netlist. A program that causes the computer to search for a group of wires that may cause 13. The program according to claim 10 or 11, wherein the search unit includes each net based on the arrangement information of the signal output lines included in each of the functional blocks, in addition to the netlist. A program that causes the computer to search at least adjacent signal output lines among a plurality of signal output lines as a group of wiring lines that may cause crosstalk when laid out. 14. The program according to claim 10 or 11, wherein the search means comprises each net in addition to the netlist, based on arrangement information of signal input lines provided in each functional block. Functioning the computer to search for a group of adjacent signal input lines to which a synchronization signal is input among a plurality of signal input lines as a group of wiring lines that may cause crosstalk when laid out. A program characterized by. 15. The program according to claim 10, wherein the search means is a plurality of wirings provided between the same functional blocks from the netlist, and the number of intervening cells is predetermined. A program that causes the computer to search for less than a few wires as a group of wires that may cause crosstalk if laid out. 16. The program according to claim 10 or 11, wherein the search means includes a netlist, I / O pad layout information of a semiconductor chip being designed, and functional blocks of each functional block. Based on the arrangement information of the provided signal lines, among the adjacent signal lines provided in each functional block, a group of wirings connected to the adjacent I / O pads of the semiconductor chip under design is laid out for crosstalk. A program that causes the computer to search for a group of wires that may cause