JP2002533990A - Clock synchronization of telecommunications networks using system frame numbers - Google Patents

Abstract

(57) [Summary] The telephone communication system (18) of the present application employs a system frame number (SFN) to synchronize a plurality of real-time clocks (206) provided from one or more nodes. To the processor (202) with the slave clock (206) that needs to be synchronized with the master clock, signal frame sources (210 and 310) distribute system frame signals (eg, pulses). The master processor (202 _M, 302 _T) transmits a reference master clock time (506) and clock setting message containing a reference system frame number (504) and (500) to the receiver processor. The processor that has received the clock setting message synchronizes the slave clock with the reference master clock time based on the timing of the reference system frame number.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001] 1. FIELD OF THE INVENTION The present invention relates to telecommunications, and more particularly, to synchronizing a real-time clock maintained by multiple processors in a telecommunications network.

[0002] 2. 2. Related Art and Issues to Consider Cellular telephone systems employ a wireless link (eg, an air interface) between a (mobile) user equipment unit and a base station (BS) node. The base station node includes a transmitter and a receiver for establishing a wireless connection with a plurality of user equipment units. The one or more base station nodes are connected (e.g., by land line or microwave) and connected to a radio network controller node (also
In some networks, it is known as a base station controller [BSC]. ). The radio network controller nodes are sequentially connected to the core communication network through the control nodes. The control node can take various forms, depending on the type of service or network to which the control node is connected. In connection oriented connections such as PSTN and / or ISDN, switched networks, the control node will correspond to a mobile switching center (MSC). When connecting to a packet-switched data service such as the Internet (for example), the control node corresponds to a gateway data support node,
A connection will be established via the wired data network and one or more serving nodes.

[0003] Accordingly, telecommunication connections between a mobile user equipment unit and another party (eg, a core communication network or another mobile user equipment unit) include mobile units, base stations and radio network controllers (RNCs).
) And a downlink in a direction opposite to the uplink. In some types of telecommunications systems, control information and user information are transmitted in both uplink and downlink frames.

Some of the nodes included in the cellular communication network are equipped with a plurality of processors for handling transmission processing of frames and the like, and each of them is equipped with a real-time operating system that operates on a real-time clock.
In maintaining and controlling a telecommunications network and processing connections, it is important to synchronize real-time clocks. Accordingly, it is an object of the present invention to provide a technique for synchronizing a real-time clock of a telecommunications network.

SUMMARY OF THE INVENTION The telecommunications system of the present application employs a system frame number to synchronize multiple real-time clocks provided at one or more nodes in a network. System frame signals (eg, pulses) are distributed from signal sources (eg, oscillators) to equipment or units with slave clocks that need to be synchronized with the master clock. The master processor sends a clock setting message to the processor, and the clock setting message includes
A reference master clock time and a reference system frame number are included. The receiving processor receiving the clock setting message resynchronizes its own slave clock using the reference master clock time and the reference system frame number.
In one mode, the clock setting message instructs the receiving processor to set the slave clock to the reference master clock time when the receiving processor obtains the reference system frame number. In the other mode, the clock setting message informs the receiving processor of the actual master clock time at the time of the reference system frame number, so that the receiving processor can calculate the adjusted slave clock time. Become.

[0006] The location of the master processor associated with the receiving processor will vary with different embodiments. For example, in one embodiment, the master processor and the receiving processor are located at the same node in the telecommunications network, for example, a base station node. In such an embodiment, the master processor and the receiving processor will be located on different device boards within the same node of the telecommunications network. In other embodiments, the master processor and the receiving processor may be located at different nodes in the telecommunications network, for example, the master processor is located at a radio network controller node,
One or more receiving processors may be located at a base station node of a telecommunications network.

DETAILED DESCRIPTION OF THE INVENTION In the following description, specific architectures, interfaces, techniques, etc. are used as specific details in order to provide a thorough understanding of the present invention, which is intended to limit the present invention. It is used for illustrative purposes only. It will also be apparent to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known devices, circuits, and methods may be omitted so as not to obscure the description of the present invention with unnecessary description.

FIG. 1 shows a telecommunications network 18, wherein a user equipment unit 20 comprises:
It communicates with one or more base stations 22 via an air interface 23 (e.g., a wireless interface). Base station 22 is connected by a land line (or microwave) to a radio network controller (RNC) 24 [also known in some networks as a base station controller (BSC)]. A radio network controller (RNC) 24 communicates through a control node known as a mobile switching center 26 with a circuit switched telephone network (PSTN / I
SDN). Further, the radio network controller (RNC) 24 is connected to the serving GPRS support node (SGSN) 25 and the gateway GRPS support node (GGSN) 30 through the backbone network 27, and the connection is established by the cloud 32
(Eg, Internet, X.25 external network, etc.)
Established by the packet switching network.

As will be appreciated by those skilled in the art, when the user equipment unit 20 participates in a mobile telephone connection, the signaling information and user information from the user equipment unit 20 over the air interface 23 of the designated radio channel. Is transmitted to one or more base stations 22. The base station includes a wireless communication device that transmits and receives a wireless signal included in a connection or a session. The base station includes a wireless communication device for transmitting and receiving a wireless signal related to a connection or a session. The base station acquires information on the uplink from the user equipment unit 20 to another party related to the connection from the radio signal, converts the information into a digital signal, and transfers the digital signal to the radio network controller (RNC) 24. A radio network controller (RNC) 24 comprises a plurality of base stations 2 that may be involved in a connection or session.
Consolidate the participation of the base station 2
This is because it may handover to 2. On the uplink, the radio network controller (RNC) 24 establishes a connection between the user equipment unit 20 and a party on the PSTN / IDSN 28 or a packet-switched network 32 (such as the Internet). Extract frames from one or more base stations 22 containing user information.

[0010] The embodiment illustrated here happens to employ code division multiple access (CDMA), wherein the information transmitted between a particular mobile station and a base station utilizes the same radio frequency. Modulated by a mathematical code (such as a spreading code) to distinguish it from other mobile station information. Therefore, in CDMA, individual radio links are distinguished based on codes. Various aspects of CDMA are described in Prentice Hall (1997), a CDMA application in wireless / personal communications by Garg, Vijay K. et al. In consideration of CDMA diversity, the user equipment unit 20 of FIG. 1 includes a plurality of base stations 22 (eg, base station 22, and base station 22).
222).

The present invention is particularly concerned with real-time clock synchronization in telecommunications network 18 where information is transmitted in both uplink and downlink frames or information packets. Individual frames are sequentially numbered to include a frame identification number (FN). The frame number (FN) is based on a system frame number (SFN) maintained in both the base station 22 and the radio network controller (RNC) 24.

The SFN is synchronized between a radio network controller (RNC) 24 and a base station 22.
In this regard, the base station 22 includes a system frame number (SFN) oscillator that distributes system frame numbers to all boards in the base station 22. Thus, when the base station 22 wakes up, the SFN oscillator synchronizes with the radio network controller (RNC) 24, after which each base station 22 maintains its own SFN counter using the SFN oscillator. . Thereafter, when the radio network controller (RNC) 24 sends a user data frame to the base station 22 for final transfer to the user equipment unit 20, all frames are marked with a frame number (FN). Have been. Actually, this frame number (FN) is, for example, SFN mod 72, such as SFN
It is derived by calculation from N. By using the frame number FN and the SFN maintained by the base station 22, the base station 22 can transmit a frame at a designated time.

The real-time clock synchronization of the present invention is applicable to the various embodiments of FIG. 2 that provide a first example. In particular, FIG. 2 shows a representative base station of the telecommunications network 18.
22 is exemplified. The example base station 22 of FIG. 2 includes a plurality of units or device boards 200 _M , 200 _S1 ,..., 200 _Sn . Each device board 200 includes a board processor 202 and executes a real-time operating system (RTOS) 204 with a real-time clock 206.

In FIG. 2, a real-time clock 206 _M is a master real-time clock ( _M ).
Since it is considered to be the master clock 206 _M), the device board 200 _M are referred to as "master board". Further, in the illustrated embodiment, as the source of the system frame signal, i.e., a SFN oscillator 210 to the device board 200 _M. Processor 202 _M of the master board 200 _M passes through an interface 212, further in communication with the processor of the other device board 200 via the control bus 214.

In the example of FIG. 2, other device boards 20 except for the master device board 200 _M
0 is called a slave board that performs synchronization according to the present invention. Slave board 200 _S1 -2
The real time clock 206 on 00 _Sn is synchronized with the master clock 206 _M
Dependent synchronization. Further, slave boards 200 _{S1 to} 200 _Sn receive a system frame from SFN oscillator 210 via SFN signal line 216.

In the illustrated embodiment, SFN oscillator 210 outputs a pulse every 10 milliseconds. The pulse output from the SFN oscillator 210 is applied to each of the slave boards 200 _{S1-200 Sn}
Applied to SFN counter 220. SFN counter 220 continues to calculate pulses containing the system frame signal received on SFN signal line 216. Further, the master processor 202 _M receives system frame signal, counts. Master processor
200 _M is, the full set of system frame signal is determined to be output from the SFN oscillator 210, the master processor 200 _M issues a reset signal at the reset line 222.

Each of the slave boards 200 _S1 -200 _Sn has one or more unique functions, and each function is generally represented as a function block 230 _S1 -230 _Sn . Each functional block 230 _S1 -230 _Sn can perform one or more base station functions. For example, function block 230 _S1
It may be a transmitter / receiver to provide communication over the air interface 23. The function block 230 _Sn may be an interface to other nodes in the telecommunications network 18 (such as, for example, a radio network controller (RNC) 24), in which case the board 200 _Sn functions as an expansion board. . Also, base station 2
Some of the second device boards 200 will function as transmitter / receiver boards. However, the particular identity and function combination provided by the base station 22 is not closely related to the present invention and is provided only for illustrative purposes along with said functions.

It should be understood that transmission of a user data frame or the like between the device boards 200 of the base station 22 is not illustrated in FIG. For example,
Transmission of user data frames and the like may be achieved using conventional methods such as ATM frame encapsulation. Thus, in some embodiments, for example,
A switch, such as an ATM switch, may be provided to facilitate transmission of user data frames between device boards within base station 22.

The present invention seeks to synchronize the slave clock 206 _S with the master clock 206 _{M. Assuming} that the master clock 206M is correctly maintained or maintained (eg, by the radio network controller (RNC) 24), the SFN counters of the master processor are properly synchronized (eg, at startup, etc.). ). The synchronization of the present invention is characterized by the system frame number (SFN) maintained on the various device boards 200 of the telecommunications network 18. Based on this perspective, the SFN oscillator 210 outputs a pulse on line 216 as described above. By counting the pulse on line 216, the SFN counter 220 can know the frame number (FN) and SFN of each user data frame, so that each device board 200 can read the frame on the air interface at the appropriate time. Be able to send. further,
Master processor 202 _M counts the system frame pulses, when determining whether to reset the system frame number to 0. Master processor 202 _M is, when a system frame number determines that it should reset to zero, the master processor 2
02 _M sends a reset signal on line 222.

According to the present invention, the master processor 202 _M sends a clock setting message (CS) on the control bus 214 to each of the receiving processors 202 of the slave boards 200 _S1 -200 _Sn.
M) Send 500. FIG. 5 shows an example of a typical format of the clock setting message (CSM) 500. To identify the clock setting message CSM from other types of messages transmitted on the control bus 214, the clock setting message (CSM
) 500 includes a message type identification field 502. In addition, the clock setup message (CSM) 500 stores the reference system frame number (known as the reference system frame number field 504) in a field 506;
Stores the reference master clock time (known as the reference master clock time field 506). Reference master clock time field 506 specifies the reference master clock time in hours, minutes, and seconds (hh.mm.ss) format. If the control bus 214 uses addressing instead of dedicated connection between the master device board 200 _M and the various slave boards 200 _S1 -200 _Sn , an address field is provided in the clock setting message (CSM) 500. Would need to. Other fields may also be included, such as parity or checksum fields.

In the first mode according to the present invention, the SF of the slave processor 202 _S on the receiving side is
N counter 220 is the slave processor 202 _S on the receiving side detects that it is now equal to the value contained in (e.g., SFN = X as as shown) reference system frame number field 504, a slave clock 206 _S to set to a specific real-time clock, the reception side of the slave processor 202 _S clock setting message (
CSM) 500.

The mode of the first invention, prepared is illustrated in FIG. 4A, in step 4A-1, the master processor 202 _M is the clock setting message (CSM) 500 having a format shown in FIG. 5 and, via the (interface 212 _M, control bus 214
Above) to send. In step 4A-2 of FIG. 4A, the slave processor 202 receives the clock setting message (CSM) 500 and processes it, for example, by storing the values received in the reference system frame number field 504 and the reference master clock time field 506. . The SFN oscillator 210 converts the system frame signal (pulse)
The pulse which keeps SFN = X is emitted (at step 4A-3). The system frame pulse count maintained by the SFN counter 220 is
Slave processor 202 _S monitors. SFN as shown by steps 4A-4
When the count of the counter 220 reaches the value contained in the reference system frame number field 504 (eg, SFN = X), the corresponding slave processor 202
The slave clock 206 is reset to the time specified in the clock setting message (CSM) 500. When the counted number for the signal related to the system frame number, which is maintained by the SFN counter 220, has a predetermined relationship with the value of the reference system frame number field 504, the slave clock 206 becomes the reference master clock time field 506. Is reset to the value of hh.mm.ss that was stored and carried. That is, as soon as SFN = X is reached as specified in the reference system frame number field 504, the slave clock 206 is synchronized with the actual time specified in the reference master clock time field 506 of the clock setup message (CSM) 500. Reset.

In the second mode according to the present invention, the reference system frame number field 504
That the actual master clock time (as specified in the reference master clock time field 506) occurs at the reference system frame number carried at
The clock setting message (CSM) 500, and notifies to the receiving-side processor on the slave board 200 _S1 -200 _Sn. In this second mode, the receiving processor calculates an adjusted slave clock time, which is the time at which the associated slave clock 206 should be reset.

The mode of the second invention is shown in FIG. 4B. In step 4B-1, the master processor 202 _M transmits a clock setting message (CSM) 500 having a format as shown in FIG. And (via interface 212 _M ,
(On control bus 214). In step 4B-2 of FIG. 4B, the slave processor 202 receives the clock setting message (CSM) 500 and processes it, for example, as storing the values received in the reference system frame number field 504 and the reference master clock time field 506. I do. In step 4B-3, SFN oscillator 2
10 supplies to the SFN signal line 216 a system frame signal (pulse) counted so that SFN = Y. In step 4B-4, when grasping the current system frame number SFN = Y, the slave processor 202 stores the current system frame number SFN = Y, the value of the reference system frame number field 504, and the reference master clock time field 506. Using the stored actual time, the adjusted slave clock time is calculated. Therefore, the adjusted slave clock time calculated in step 4B-4 is equal to the reference master clock time field 50.
Unlike the actual time stored in 6, it will be another value calculated using the time stored in the reference master clock time field 506. That is, the master clock 206 _M actual time, when storing the specific system frame number to the reference system frame number field 504, a reference master clock time field
This value is stored in 506, and the slave processor 202 can calculate the master clock time at the current system frame number SFN = Y by knowing the value. The pulses of the system frame on signal line 216 are at known intervals (eg,
Due to the fact that every 10 ms in the illustrated embodiment)
Calculation of the master clock time is simplified. Using the adjusted slave clock time calculated in step 4B-4, in step 4B-5, the slave processor 202 replaces the slave clock 206 _S of the slave processor 202 with the adjusted slave clock time. Set to.

FIG. 4B shows that a system frame signal in which SFN = Y (step 4B-3) is transmitted after the clock setting message (CSM) 500 is transmitted in step 4B-1. It should be understood that in FIG. 4B, step 4B-3 may be executed prior to step 4B-1. That is, in the second mode according to the present invention, it is important that the slave processor 202 knows the current system frame number when performing the calculation in step 4B-4. Whether knowing or updating the current system frame number is before or after receiving the clock setup message (CSM) 500, as long as the correct current system frame number is utilized, It is not essential.

FIG. 3 is a representative example of the second embodiment, and illustrates real-time clock synchronization according to the present invention. Especially, the master clock 306 _M is one or more base stations 22 ₁ -
22 are used for synchronization of the slave clock 306 _S in _q, 3, a master clock 306 _M, the radio network controller (RNC) 24 is illustrated a scenario for maintaining.

The master clock 306 _M is located on the timing board 300 _T of the radio network controller (RNC) 24, in particular a real-time operating system (RTOS) for the processor 302 _T located on the timing board 300 _T , among others. Part of 304 _T. Analogously to the procedure of the master board 200 _M according to Figure 2, timing board 30
0 _T comprises an interface 312 _T for the processor 302 _T to communicate on the control line 314 with the processor of the base station 22. The timing board 300 _T is in Figure 2 SFN
SFN oscillator that outputs a system frame signal (pulse) using the same method as oscillator 210
It has 310.

The timing board 300 _T has a port 313 _T through which communication with the other of the radio network controller (RNC) 24 via the switch 315 is established.
Between the timing board 300 _T and the switch 315, port 3 different types of information
Transmitted over 13 _T , including those corresponding to system frame signals and reset signals carried by signal lines 216 and 222 in FIG. switch
315 provides a connection between the different units from the radio network controller (RNC) 24, as such units, (timing board 300 _T as well) diversity handover unit 340, (e.g., MSC 26 or SGSN25 A control node interface 342 (as with an interface with
Base station interfaces 344 ₁ -344 _q, etc., which are connected to the respective nearby base stations 22 ₁ -22 _q via terrestrial lines).

Each base station 22 is connected to a radio network controller (RNC) 24 via an extension board 350. As previously described, expansion board 350 is just one of several types of device boards that may be located at base station 22. Expansion board 35
0 receives the system frame signal from the SFN oscillator 310 _T , resets the signal from the processor 302 _{T of} the radio network controller (RNC) 24, and further comprises, in one embodiment, a plurality of Such a signal is provided to each of the device boards 200 via a switch 352. 3, the base station 22 ₁ has been shown that it comprises a device board from 200 _{1 -s1} to 200 _1-sn, the base station
22 _q is shown to have device boards from 200 _q-s1 to 200 _q-sn .

The device board 200 of the base station 22 of FIG. 3 is similar to the device board 2, the port 354 _1-s1 of the device board 200 _1-s1, port 3 of the device board 200 _q-s1
The only exception is that each device board 200 has a port 354, as shown as 54 _q-s1 . The port 354 handles communication between the unit including the device board 200 including the SFN counter 220 and the processor 202 and the switch 352. Further, for each device board 200, its processor 202 is connected to a control line 314 via an interface 212. Control line 314 carries a clock setting message (CSM) 500 and may be in the same format as in the embodiment of FIG. 3 as illustrated in FIG. 5 and the preceding discussion.

In the embodiment of FIG. 3, each of the device boards 200 of each base station 22 uses the synchronization scheme depicted by the device boards 200 _{1 -S 1} , the mode of FIG.
Can be equipped with a synchronization scheme for the slave clock 206, such as the synchronization scheme described above for each of the modes. That is, each device board 200 receives a system frame signal from the SFN oscillator 31 of the radio network controller (RNC) 24,
Clock setting message (CSM) 500 from radio network controller (RNC) 24
And can be received. In this case, the control line 314 is connected to each device board 200 of the base station having the slave clock 106 that requires synchronization, in which case the base station to which the clock setting message (CSM) 500 is supplied The address field for specifying the 22 specific device boards 200 is set in the clock setting message (C
SM) 500.

Alternatively, the master clock 306 _T of the radio network controller (RNC) 24 is initially provided at each individual base station by a predetermined device board 200 (eg, base station 2
2 ₁ is used to synchronize the slave clock 206 of the device board 200 _{1 -S 1} ), and this first synchronized slave clock 206 is the slave clock of the other remaining device boards 200 in the same base station 22. Used as an auxiliary master clock to synchronize 206. After the initial synchronization, the auxiliary master clock is supervised by the radio network controller (RNC) 24 and the phase is corrected. In the practice of this alternative, the individual devices board 200 of the base station 22 is comprised to directly receive the system frame signal from the SFN oscillator 310 _T, clock setting message (CSM) 500 is initially synchronized with the slave clock Device board 200 with
Is relayed to another device board 200 of the base station 22 in order to synchronize the slave clock on the other device board 200.

As described above, the clock setting message (CSM) 500 according to the embodiment of FIG. 3 may be used in the mode of FIG. 4A or the mode of FIG. 4B. Such a mode will be understood by considering the preceding discussion of FIG.

The embodiment of FIG. 3 illustrates a node that uses a switch to route information through the node. An example of such a switch is via a node
It could be an ATM switch that routes ATM cells. If desired, other types of routing techniques may be utilized, and (alternatively) these signals may be passed directly from the radio network controller (RNC) 24 to the appropriate device board 200 of the base station 22. It will be appreciated that they may be supplied in a different or different way. Further, although not explicitly illustrated herein, it will be appreciated that the local node switch can be used in the embodiment of FIG.

From the foregoing description, the master processor and master clock may be located in a control node of the telecommunications network 18, such as the mobile switching center 26. In such an embodiment, the master processor would be used to reset the slave clock of a lower node (eg, radio network controller (RNC) 24 and / or base station 22).

Advantageously, the present invention uses a separate function (SFN) of the telecommunications network 18 to provide a real-time clock for not only a single node, but even between multiple nodes of the telecommunications network 18. Facilitates accurate synchronization of Thus, the use of the synchronization technique of the present invention allows a real-time operating system (RTOS) to correctly handle timestamp events occurring in telecommunications network 18. For example, these events may be an alarm report to be transmitted to another node, a log event recorded in a log file at the time of system debugging, or the like.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred, the present invention is not limited to the disclosed embodiments, but rather, the following claims It is intended to cover various modifications and equivalent arrangements that may be included within the spirit and scope of the section.

[Brief description of the drawings]

The foregoing and other objects, features, and advantages of the invention will be more apparent from the following more particular description of the preferred embodiments, which are set forth in the accompanying drawings, with reference characters referring to the same parts throughout the different views. Would. The drawings do not necessarily require emphasis or scale to illustrate the principles of the invention.

FIG. 1 is a schematic diagram of an embodiment of a telephone communication system to which the present invention is applied.

FIG. 2 is a schematic diagram when the synchronization technique of the present invention is adopted in a base station.

FIG. 3 is a schematic diagram when the synchronization technique of the present invention is adopted between a radio network controller (RNC) and a base station.

FIG. 4A is a flowchart showing a first mode using a clock setting message (CSM) of the present invention.

FIG. 4B is a flowchart showing a second mode using the clock setting message (CSM) of the present invention.

FIG. 5 is a schematic diagram showing a format example of a clock setting message (CSM) according to the present invention.

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Claims (22)

[Claims] 1. A master processor having a master clock, a receiving processor having a slave clock, and a signal source of a system frame number supplied to the receiving processor, the master processor comprising: A clock setting message including a reference master clock time and a reference system frame number is transmitted to the receiving processor, and the receiving processor regenerates the slave clock using the reference master clock time and the reference system frame number. A device of a telecommunications network, characterized in that it is synchronized. 2. The clock setting message, when the receiving processor acquires the reference system frame number, instructs the receiving processor to set the slave clock in a designated real time. The apparatus according to claim 1, wherein: 3. The receiving processor further includes a counter that counts a signal of a system frame number in the receiving processor, wherein the receiving processor calculates a number counted for the signal of the system frame number with respect to the reference system frame number. 3. The apparatus of claim 2, wherein the slave clock is set to the reference master clock time when a predetermined relationship is reached. 4. The clock setting message notifies a receiving processor of an actual master clock time with the reference system frame number, and the receiving processor calculates an adjusted slave clock time by the notification. The device according to claim 1, characterized in that: 5. The apparatus of claim 1, wherein said master processor and said receiving processor are located in a same node of said telecommunications network. 6. The apparatus according to claim 5, wherein the same node of the telecommunications network is a base station node. 7. The apparatus of claim 5, wherein the master processor and the receiving processor are located on different device boards within the same node in the telecommunications network. 8. The apparatus of claim 1, wherein the master processor and the receiving processor are located at different nodes of the telecommunications network. 9. The telecommunications network of claim 8, wherein the master processor is located at a radio network controller node of the telecommunications network, and the receiving processor is located at a base station node of the telecommunications network. An apparatus according to claim 1. 10. The master processor is located at a radio network controller node, the first receiving processor is located at a first base station node, and the second receiving processor is located at a second base station. The apparatus of claim 8, wherein the apparatus is located at a node. 11. The apparatus according to claim 1, wherein the signal source of the system frame number is an oscillator. 12. A method of operating a cellular communication system in which a master processor maintains a master clock and uses a system frame number, wherein the master processor sends a reference master clock time to a receiving processor. And transmitting a clock setting message including a reference system frame number and the reference system frame number, wherein the receiving processor resynchronizes a slave clock using the reference master clock time and the reference system frame number. 13. The clock setting message, when the receiving processor obtains the reference system frame number, instructs the receiving processor to set the slave clock in a designated real time. The method according to claim 12, wherein 14. A signal relating to a system frame number is periodically transmitted to the receiving processor, a signal relating to the system frame number is counted in the receiving processor, and a signal relating to the system frame number is counted. 14. The method of claim 13, wherein when a number has a predetermined relationship to the reference system frame number, the slave clock is set at the reference master clock time. 15. The clock setting message notifies a receiving processor of an actual master clock time with the reference system frame number, and the receiving processor calculates the adjusted slave clock time by the notification. 13. The method of claim 12, wherein: 16. A clock setting message is prepared so that when the system frame number becomes the reference system frame number, the reference master clock time in the clock setting message refers to an actual master clock time. Periodically transmitting the system frame number to the receiving processor; maintaining, at the receiving processor, a current count number for the signal related to the system frame number; and a current count for the signal related to the system frame number. The method of claim 15, wherein the adjusted slave clock time is calculated using a number, the reference system frame number, and the reference master clock time. 17. The method of claim 12, wherein the master processor and the receiving processor are located in a same node of the telecommunications network. 18. The method according to claim 17, wherein the same node of the telecommunications network is a base station node. 19. The method of claim 12, wherein the master processor and the receiving processor are located on different device boards of the telecommunications network. 20. The method of claim 12, wherein the master processor and the receiving processor are located at different nodes in the telecommunications network. 21. The telecommunications network of claim 20, wherein the master processor is located at a radio network controller node of the telecommunications network, and the receiving processor is located at a base station node of the telecommunications network. The described method. 22. The master processor is located at a radio network controller node, a first receiving processor is located at a first base station node, and the second receiving processor is located at a second base station. The method of claim 20, wherein the method is arranged at a node.