JP2002368141A - Nonvolatile semiconductor memory device - Google Patents

Abstract

[PROBLEMS] To significantly reduce the cell area per bit of a nonvolatile memory transistor having a charge storage function inside a gate dielectric film without narrowing the room for improvement in characteristics and scaling. I do. A plurality of dielectric layers are stacked between a semiconductor in which a channel of a memory cell is formed and a gate electrode (word line), and a channel is formed inside the plurality of dielectric layers. The present invention is applied to a nonvolatile semiconductor memory device including charge storage means discretized in opposing planes. A conductive layer and an interlayer insulating layer INT1, INT are formed on a semiconductor substrate SUB.
2 is laminated. One or a plurality of sub-arrays (MC
A1) is formed on the semiconductor substrate SUB, and the remaining sub-array (MCA2) of the memory cell array is arranged in a stacked structure.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a plurality of dielectric layers between a semiconductor in which a channel is formed and a gate electrode for controlling the semiconductor. The present invention relates to a nonvolatile semiconductor memory device including means (for example, a charge trap of a MONOS type or MNOS type, or a conductor having a small particle size).

[0002]

2. Description of the Related Art In a nonvolatile semiconductor memory, an FG (Floating) in which a charge storage means for holding a charge is formed of a single conductive layer.
Gate) type, a charge is stored in a charge storage layer made of silicon nitride or the like containing a large number of charge traps.
There is an ONOS (Metal-Oxide-Nitride-Oxide-Silicon) type or the like.

In the FG type nonvolatile memory, a NAND type cell connection system in which memory transistors are connected in series to reduce the number of contacts per cell to perform a NAND operation is known. This cell connection method facilitates miniaturization of cells, and is suitable for a large-capacity memory, for example, because the theoretical value of the cell area is 4F ² .

On the other hand, CHE (Channel Hot Electron)
Paying attention to the fact that charges can be locally injected into a part of the distribution region of the discrete traps by the injection method, by independently writing binary information on the source side and the drain side of the charge storage layer, 2 bits per memory cell can be obtained. A technology capable of recording bits was reported. For example, “Extended Abstract of the19
99 International Conference on Solid State Devices
and Materials, Tokyo, 1999, pp.522-523 ”, switch the direction of voltage application between source and drain, write 2-bit information by CHE injection, and apply a predetermined voltage between source and drain in the opposite direction of writing. In this case, the data is read out by a so-called “reverse read” method, so that even if the writing time is short and the amount of accumulated electric charge is small, the data can be read.
Bit information can be read reliably. Erasing is performed by hot hole injection. This technology has made it possible to shorten the write time and significantly reduce the bit cost. The cell area in this case is 6F
^{If 2} , the cell area per bit is 3F ² .

[0005]

In recent years, the capacity of nonvolatile memories has been increasing, and even if the cell area is reduced,
The area of the memory cell array tends to increase. Therefore, the occupied area of the memory unit including the peripheral circuit is large, which hinders the reduction of the bit cost.

[0006] The applicant of the present invention is disclosed in Japanese Patent Application Laid-Open No. 11-8754.
As described in Japanese Patent Application Publication No. 5 (1993) -5, an inexpensive insulating substrate made of glass or plastic is used for one purpose of cost reduction, and a so-called TFT (Thin Film T
An invention related to a nonvolatile semiconductor memory device in which a memory transistor having a ransistor structure is formed was previously filed. According to the present invention, in addition to the cost reduction, various parasitic capacitances of the memory transistor are reduced, and the voltage of the nonvolatile memory can be reduced.

However, in this nonvolatile memory, although the material cost has been somewhat reduced by changing the substrate material, since the memory cell array having the TFT type transistors is one layer, the chip area per bit and the bit cost are reduced. The reduction was insufficient.

[0008] On the other hand, Japanese Patent No. 3109537 discloses that
In a read-only memory, for example, a memory cell array structure in which a plurality of semiconductor thin films made of polycrystalline silicon are stacked with an interlayer insulating layer interposed therebetween is disclosed. Thereby, the bit area can be significantly reduced.

However, when this technique is applied to an electrically rewritable nonvolatile memory (EEPROM), the insulation characteristics of an insulating film formed on a semiconductor thin film such as polycrystalline silicon are poor. There is a problem that application to the EEPROM is not easy. Hereinafter, this problem will be described.

In the FG type of the EEPROM, which is currently being put to practical use, the first potential barrier film (generally referred to as a tunneling film) such as silicon oxide is interposed on a semiconductor on which a channel is formed. A floating gate as charge storage means is stacked, and a control gate is stacked thereon with a second potential barrier film (for example, an ONO film) interposed therebetween. And
At the time of writing or erasing, charge is input / output to / from the floating gate through the lowest tunneling film. It is important to reduce the thickness of the tunneling film in order to increase the speed of the writing operation and the erasing operation or to lower the voltage. At present, the thickness of the tunneling film is about 10 nm, which is close to the theoretical limit value of 8 nm. . When this thin tunneling film is formed on a semiconductor thin film made of, for example, polycrystalline silicon, the leak characteristics are remarkably reduced as compared with the case where it is formed on single crystal silicon. In the FG type,
This increase in leakage current is fatal. Because the floating gate is formed of a single conductive layer, if there is a leak in the tunneling film below the floating gate, all the accumulated charges disappear to the substrate over time.
In other words, when the FG type memory transistor is formed in a semiconductor thin film, the scaling of the device dimensions including the tunneling film thickness makes it possible to achieve a high-speed operation at a low voltage and a charge retention characteristic at a practical level. Was difficult.

On the other hand, when the memory element is read-only as in the above-mentioned patent publication, the storage data is previously incremented in the memory element depending on whether the transistor is to be enhanced or depleted. For this reason, there is no operation step (electrical writing and erasing steps) for exchanging charges through the gate insulating film as in the EEPROM. Therefore, there is no need to make the insulating film between the semiconductor thin film and the gate electrode very thin, as exemplified by the gate insulating film thickness of about 25 nm in the above-mentioned patent publication. For the above reasons, conventionally, it has been easy to realize a transistor in a cell using a TFT only in a nonvolatile memory such as a read-only memory having a single-layer MOS transistor as a gate insulating film.

An object of the present invention is to provide a semiconductor device in which a channel is formed and a plurality of dielectric layers laminated between a gate electrode and a semiconductor.
A part of the memory cell array is composed of TFTs and is laminated above the semiconductor substrate without narrowing the room for improvement of the scalability and characteristics of the non-volatile memory cell having a charge storage function therein. It is an object of the present invention to provide a nonvolatile semiconductor memory device in which the cell area is significantly reduced.

[0013]

In a nonvolatile semiconductor memory device according to the present invention, a plurality of dielectric layers are stacked between a semiconductor in which a channel of a memory cell is formed and a gate electrode, and the plurality of dielectric layers are stacked. A non-volatile semiconductor memory device including charge storage means discretized in a plane facing a channel inside a layer, having a stacked structure in which a plurality of conductive layers and interlayer insulating layers are stacked on a semiconductor substrate, One or more sub-arrays forming the memory cell array are formed on the semiconductor substrate, and the remaining sub-arrays of the memory cell array are arranged in the stacked structure. In the present invention, the sub-array arranged in the laminated structure has a plurality of memory transistors formed on a semiconductor thin film on an interlayer insulating layer. A peripheral circuit for selecting and operating a memory cell is preferably formed in the semiconductor substrate region and / or the stacked structure around the sub-array. The peripheral circuit includes a select transistor group arranged in a stacked structure around the subarray and selecting one of the plurality of subarrays. Alternatively, the peripheral circuit has a function of simultaneously selecting a plurality of sub-arrays having different hierarchies and writing data at the same time.

In this nonvolatile semiconductor memory device, a sub-array having a TFT type memory cell is stacked in a stacked structure of an upper layer of a sub-array having a bulk type memory cell formed on a semiconductor substrate. In a memory transistor constituting each sub-array, charge storage means is discretely planarized in a gate dielectric film in which a plurality of dielectric layers are stacked. Therefore, even if the potential barrier layer between the charge storage means and the semiconductor thin film is made thinner and a leak path is generated in the potential barrier layer, if the frequency of occurrence is small to some extent, the charge retention characteristic does not suddenly decrease. . This is because the charge storage means (charge trap or small-diameter conductor) is discretized, so that the local stored charge around the leak path only disappears in the semiconductor thin film.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a nonvolatile semiconductor memory device according to the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing one embodiment of a nonvolatile semiconductor memory device according to the present invention.

This non-volatile memory is roughly classified on a plane into a memory cell array arrangement area and a peripheral circuit arrangement area. A p-type or n-type well W is formed in the area where the memory cell array is arranged on the semiconductor substrate SUB.
P-type or n-type wells W
0 is formed. The substrate surface region between the wells W and W0 is separated by a dielectric separation layer ISO. The dielectric isolation layer ISO is formed by a LOCOS method, a trench method, or a field isolation method. In the illustrated example, the dielectric isolation layer ISO is an STI (Shallow Trench Isolat).
ion) method.

On the surface of well W0 of the peripheral circuit, gate electrodes of various MOS transistors or inter-gate wiring layers are arranged with a gate insulating film of, for example, several tens nm to several tens nm interposed therebetween. An impurity of the conductivity type opposite to that of the well is appropriately added to the well surface between the gate electrodes, thereby forming source / drain regions. Thus, bulk type transistors Q1, Q2, and SW for peripheral circuits such as various decoders, various buffers, a control circuit, and a power supply circuit are formed. Incidentally, these bulk type MOS transistors Q1, Q2, and SW may be of a CMOS type formed separately in a p-type well and an n-type well. The gate electrode is made of polycrystalline silicon to which p-type and / or n-type impurities are added. For example, the gate insulating film may be thickened in a power supply circuit to increase the breakdown voltage, and may be thinned in other logic circuits to enhance the operation performance.

A first interlayer insulating layer INT1 is formed on these transistors. First interlayer insulating layer INT1
Various contacts WC1 to WC3 and an interconnect layer IC are embedded therein. Various contacts WC1-WC
Reference numeral 3 is formed of, for example, a tungsten (W) plug or the like, and is in contact with the gate electrode or the interconnect layer IC, or the source / drain regions. Interconnection layer IC
Appropriately contacts the upper surface of the contact to electrically connect the elements.

A semiconductor thin film STF is formed on the first interlayer insulating layer INT1, and a part of a peripheral circuit is also formed on the semiconductor thin film STF. Here, a TFT type select transistor SW is formed as a means for selecting a sub-array of the memory cell array. The second interlayer insulating layer INT2 covers the TFT type select transistor SW. One source of the select transistor SW
The drain region is connected via a word contact WC3 to one source / drain region of another select transistor SW in the lower layer. The remaining source / drain regions of the select transistor SW formed in each of the upper and lower layers are connected to the corresponding word line of the subarray via the word contact WC2, the interconnect layer IC, and the word contact WC1. Although FIG. 1 illustrates an example in which means for selecting a sub-array is provided in each layer, the present invention is not limited to this. For example, all of these select transistors SW may be of a bulk type or a TFT type. Further, functional blocks of other peripheral circuits may be appropriately arranged in an upper layer.

The configuration and operation of a memory cell applicable to the present invention and an array thereof will be described below with reference to the drawings. The memory cell array according to the present embodiment includes a sub-array having a bulk-type memory transistor formed on a semiconductor substrate (hereinafter, referred to as a bulk-type sub-array) and a sub-array having a TFT-type memory transistor formed in a stacked structure on the sub-array. (Hereinafter, referred to as a TFT type sub-array). The TFT type sub-array may have two or more layers, but here it is assumed to be a single layer.

Memory Cell Array 1 The memory cell array shown in FIG.
L) is a NOR type memory cell array. FIGS. 2A and 2B are circuit diagrams of the SSL-NOR type memory cell array. FIG. 2A shows an equivalent circuit for four memory cells of the bulk type sub-array MCA1,
(B) shows an equivalent circuit for four memory cells of the TFT type sub-array MCA2.

The configurations of these sub-arrays MCA1 and MCA2 are the same on an equivalent circuit. Hereinafter, this array configuration will be described with reference to the TFT type sub-array MCA2 in FIG. The memory cells M11, M21, ..., M12, M22,
Are arranged in a matrix. The gate of the memory cell transistor in the first row is connected to the word line WL21,
The gate of the memory cell transistor in the row is connected to word line WL2
2 are connected. Select transistors SW1, SW2 controlled by a common array select line SGA2 are connected to the word lines WL21, WL22, respectively. The drain of the memory cell transistor in the first column is connected to bit line BL21, and its source is connected to source line SL2.
1 connected. Similarly, the drain of the memory cell transistor in the second column is connected to the bit line BL22, and the source is connected to the source line SL22. Select transistors SB1 and SB2 controlled by a common select gate line SG1 are connected to the bit lines BL21 and BL22. Select transistors SS1, SS2 controlled by a common select gate line SG2 are connected to the source lines SL21, BL22.

As shown in FIG. 1, the bit lines and source lines in the bulk type sub-array MCA1 are composed of n ⁺ -type impurity regions (source / drain regions) S / D formed in parallel stripes on the surface of the well W. . The cell between the source line SL11 in the first column and the bit line BL12 in the second column, and the source line SL12 in the second column and the bit line BL13 in the third column are separated by a dielectric isolation layer ISO. I have. Therefore, an unintended current does not flow when the parasitic transistor between the cells is turned on. The well region sandwiched between the source / drain regions S / D in each cell is called a channel formation region.
This channel forming region necessarily has a parallel stripe shape long in the column direction.

In a row direction orthogonal to the channel forming region and the source / drain region S / D, a gate dielectric film G is formed.
D is interposed between the word line WL1 and the well.
1, WL12,... Are arranged.

FIG. 3 is an enlarged sectional view of a MONOS type memory cell. This gate dielectric film GD is composed of three layers of a so-called ONO type. Specifically, the gate dielectric film G
D comprises a lowermost bottom dielectric layer BTM, an intermediate charge storage layer CHS, and an uppermost top dielectric layer TOP. The bottom dielectric layer BTM is made of, for example, thermally oxidized silicon formed by thermally oxidizing the substrate surface, or silicon oxynitride formed by nitriding the thermally oxidized silicon. Charge storage layer CHS
Is made of, for example, silicon nitride or silicon oxynitride, and includes a large number of charge traps therein as discrete charge storage means. Top dielectric layer TOP is made of, for example, silicon oxide. In the case of the so-called MNOS type, the top dielectric layer TOP is omitted, and the charge storage layer CHS (nitride film) is formed relatively thick. Instead of the MNOS type nitride film, a high dielectric film such as Ta ₂ O ₃ may be formed directly on the semiconductor thin film. In the case of the so-called nanocrystal type, innumerable fine particles made of, for example, polycrystalline silicon are discretely embedded between the bottom dielectric film and the oxide film.

The word lines WL11, WL12,... May adopt a word line arrangement in which the space width is reduced to the limit by two patterning operations as described later. It is formed by one patterning with a space width. The word lines are made of doped polycrystalline silicon or doped amorphous silicon, and the corresponding select transistors SW1, SW2,.
Is connected to A first interlayer insulating layer INT1 is formed on the bulk type sub-array MCA1 thus formed, and its surface is planarized.

On the first interlayer insulating layer INT1, for example, p
Semiconductor thin film S made of polycrystalline silicon doped with type impurities
TF is formed. TF is added to this semiconductor thin film STF.
A T-shaped sub-array MCA2 is formed. Specifically,
An n-type impurity is added to the semiconductor thin film STF, so that the source / drain regions S / D are formed apart from each other. The source / drain region S / D is connected to the bit line B
L21, BL22,... And source lines SL21, SL2
2,... The bit lines and source lines are long in the column direction and arranged in parallel stripes in the entire subarray. The semiconductor thin film portion between the bit line and the source line located at the cell boundary is insulated, thereby forming a dielectric isolation layer ISO. Note that, similarly to the memory cell array 2 described later, the source / drain regions S
A dielectric isolation layer may be formed on the portion above / D by, for example, a field isolation method.

With the gate dielectric film GD interposed on the semiconductor thin film STF, the word lines WL21, WL2
Are arranged in parallel stripes. This FT
Similarly to the bulk type, the gate dielectric film GD in the F type is formed of an ONO film, an NO film, or a laminated dielectric film in which a conductor having a small grain size is embedded. The word line is made of doped polycrystalline silicon or doped amorphous silicon, and is connected to corresponding select transistors SW1, SW2,. The TFT sub-array MCA2 thus formed
A second interlayer insulating layer INT2 is formed thereon, and its surface is planarized.

At the time of writing, when charge is injected into the storage unit 1 shown in FIG. 3, a positive drain voltage (for example, 4.5 V) is applied to the bit line BL, and the source line SL and the well W or the body of the semiconductor thin film STF are applied to the bit line BL. Apply a reference voltage of 0V,
A predetermined positive voltage (for example, 9 V) is applied to word line WL. At this time, the right source
The electrons supplied from the drain region S / D are accelerated in the channel, and high energy is obtained on the left source / drain region S / D side constituting the bit line BL, and exceeds the potential barrier of the bottom dielectric layer BTM. Injected into the storage unit 1 and stored. When injecting charges into the storage unit 2, the peripheral circuit switches the voltage between the bit line BL and the source line SL. Accordingly, the side on which electrons are supplied and the side on which electrons become hot in terms of energy are opposite to the above case, and electrons are injected into the storage unit 2.

At the time of reading, the bit line B is set so that the storage unit side on which the bit to be read is written becomes the source.
A predetermined read drain voltage is applied between L and the source line SL. For example, with the bit line BL grounded, a negative voltage of -1.5 V is applied to the source line SL. Further, a channel section sandwiched between the storage sections at both ends can be turned on, but is low enough not to change the threshold voltage of the storage section, and an optimized positive voltage (for example, 3 V) is applied to the word line WL. Apply. At this time, the conductivity of the channel changes effectively depending on the amount of accumulated charge in the storage unit to be read or the presence or absence of the charge. As a result, the stored information is converted into the amount of current or the potential difference between the source and the drain and read. It is. When reading the other storage unit, the peripheral circuit
Reading is performed in the same manner as described above by switching the voltage of the bit line and the voltage of the source line so that the storage unit side becomes the source.

At the time of erasing, the channel forming region and the source
An erase voltage is applied in the direction opposite to that during the writing so that the drain region S / D side is high and the word line WL side is low. As a result, the accumulated charge is extracted from one or both of the storage units to the substrate SUB or the semiconductor thin film STF by FN tunneling or direct tunneling,
The memory transistor returns to the erased state. The erasing time at this time is about 1 ms. As another erasing method, high-energy charge generated on the source / drain region S / D side and having a polarity opposite to that of the accumulated charge and generated due to band-band tunneling is removed by the electric field of the control gate. It is also possible to adopt a method of injecting into the storage unit by drawing.

Memory Cell Array 2 FIG. 4 is a cross-sectional view in the row direction of a memory cell array connected in a virtual ground (VG) form. FIG.
FIG. 5A is a plan view of a TFT type sub-array, and FIG.
FIG. 3 shows a cross-sectional view in the column direction along line -A.

When the memory cell array shown in FIG. 4 is compared with FIG. 1, the dielectric isolation layer ISO for separating cells is not formed in the well W and the semiconductor thin film STF. Therefore, the channel formation region and the source / drain regions S / D are repeatedly arranged in the column direction. All the source / drain regions S / D function as bit lines at one time and as source lines at other times, depending on the storage unit to be written or read. Therefore, they are all called bit lines. As shown in FIG. 5A showing a TFT type, bit lines BL21, BL22, BL23, BL2
Are arranged in parallel stripes. As shown in FIG. 4, a dielectric isolation layer ISO formed by, for example, a field isolation method is formed in substantially the same pattern on the impurity region forming the bit line. Due to the presence of the dielectric isolation layer ISO, the parasitic capacitance between the gate and the source or drain is reduced, and charge is prevented from being injected into unnecessary parts.

As shown in FIG. 5A, in the row direction orthogonal to the channel formation region and the bit lines, the word lines WL2
1, WL22, WL23, WL24, WL25,...

The word lines may be collectively formed in the same space width as the line width as usual, but here, a word line arrangement is used in which the space width is reduced to the minimum by patterning twice. For this reason, FIG.
As shown, even-numbered word lines WL22, WL2
(Hereinafter referred to as a first word line) and odd-numbered word lines WL21, WL23, WL25,... (Hereinafter referred to as a second word line) have slightly different cross-sectional shapes. The first word lines WL22, WL24,... Are formed on the semiconductor thin film STF with the gate dielectric film GD1 interposed therebetween.

A gate dielectric film GD2 is formed so as to cover the surfaces of the first word lines WL22, WL24,... And the surface of the semiconductor thin film portion exposed between the first word lines. The odd-numbered word lines WL21, WL23, WL25,... Are formed between the first word lines with the gate dielectric film GD2 interposed therebetween. All word lines are
The word lines and the second word lines are arranged alternately. The relationship between the first and second word lines will be described in more detail. The bottom surface of the second word line is formed by the gate dielectric film GD2
In a state where the semiconductor region is interposed between the first word lines. The main side surface of the second word line faces the side surface between the first word lines with the gate dielectric film GD2 interposed therebetween. Further, both ends in the width direction of the second word line are
Two adjacent first word lines run over each other in the width direction with the gate dielectric film GD2 interposed therebetween. In this manner, the word line in the illustrated example is
The two word lines are insulated and separated by a gate dielectric film GD2 interposed therebetween so that the dimension in the direction of separation becomes a film thickness. The word line is made of doped polycrystalline silicon or doped amorphous silicon.

Each of the gate dielectric films GD1 and GD2 is formed of an ONO film, an NO film, a laminated dielectric film in which a conductor having a small grain size is embedded, or the like. Gate dielectric film GD1, G
D2 has a total thickness of about ten and several nm in terms of silicon dioxide. Also, the gate dielectric films GD1 and GD2
It is preferable that the structure and composition including the thickness of each layer are substantially equal at least in a portion in contact with polycrystalline silicon (semiconductor thin film STF). The basic cell structure in the case of the MONOS type is the same as in FIG.

In the case where charge is injected into the storage section 1 shown in FIG. 3 during writing, the left source / drain region S / D
Has a positive drain voltage, and the right source / drain region S /
A reference voltage is applied to D, and a predetermined positive voltage is applied to word line WL. At this time, the right source / drain region S /
The electrons supplied from D are accelerated in the channel, obtain high energy on the source / drain region S / D side on the left side, and cross the potential barrier of the bottom dielectric layer BTM to store the data.
Injected and accumulated. When charges are injected into the storage unit 2, the peripheral circuit switches the voltage between the source / drain regions S / D. Accordingly, the side on which electrons are supplied and the side on which electrons become hot in terms of energy are opposite to the above case, and electrons are injected into the storage unit 2.

At the time of reading, a predetermined read drain voltage is applied between the two source / drain regions S / D so that the storage portion side where the bit to be read is written becomes the source. Further, a channel portion sandwiched between the storage portions at both ends can be turned on, but a low and optimized positive voltage is applied to the word line WL so as not to change the threshold voltage of the storage portion. At this time, the conductivity of the channel changes effectively depending on the amount of accumulated charge in the storage unit to be read or the presence or absence of the charge. As a result, the stored information is converted into the amount of current or the potential difference between the source and the drain and read. It is. When reading the other storage unit, the peripheral circuit performs reading in the same manner as described above by switching the voltage between the source and drain regions S / D so that the storage unit side becomes the source.

At the time of erasing, the channel forming region and the source
An erase voltage is applied in the direction opposite to that during the writing so that the drain region S / D side is high and the word line WL side is low. As a result, the accumulated charges are drawn from one or both of the storage units toward the substrate SUB or the semiconductor thin film STF, and the memory transistor returns to the erased state. As another erasing method, a high-energy charge generated on the source / drain region S / D side and having a polarity opposite to that of the accumulated charge and tunneling between the bands is attracted by the electric field of the control gate. It is also possible to adopt a method of injecting into the storage unit.

Next, the procedure for forming the VG type memory cell array will be briefly described by taking a TFT type sub-array as an example.

On the first interlayer insulating layer INT1, a polycrystalline silicon film (semiconductor thin film STF) is deposited. As this deposition method, amorphous silicon is deposited by a CVD method or a stuttering method, and thereafter, grains are grown by annealing at 550 ° C. for several tens of hours or laser annealing to be modified into polycrystalline silicon. Although not necessary in the VG type memory cell array, for example, in the case of a source line isolation (SSL) type, a semiconductor thin film portion around a channel formation region is removed by lithography and etching to separate elements.

A mask layer such as a resist is formed on the semiconductor thin film STF, and p-type impurities are doped by selective ion implantation at a dose that determines the channel concentration. After removing the mask layer, another mask layer is formed and n-type impurities are selectively ion-implanted to form source / drain regions S / D (bit lines BL21, BL22,...). Similarly, another mask layer is formed, and p-type impurities are selectively ion-implanted,
A p ⁺ contact region for applying a potential of the semiconductor thin film is formed. Annealing is performed by the RTA method to activate the introduced impurities.

The gate dielectric film G is formed on the semiconductor thin film STF.
Form D1. For example, the surface of the semiconductor thin film STF is thermally oxidized to form a bottom dielectric layer BTM, and if necessary, the bottom dielectric layer BTM is nitrided to form a bottom dielectric layer BTM.
A charge storage film CHS made of silicon nitride or silicon oxynitride is formed on the TM, and the top dielectric layer TOP is formed by a method such as thermally oxidizing the surface of the charge storage film CHS. A conductive film made of doped polycrystalline silicon or doped amorphous silicon is deposited on gate dielectric film GD1 by, for example, a CVD method. A resist pattern is formed on the conductive film, and anisotropic etching such as RIE is performed to pattern the conductive film. Subsequently, the gate dielectric film GD1 exposed between the conductive film patterns is removed by, for example, CF ₄ / CHF ₃ /
Patterning is performed using a dry etching apparatus using Ar. After that, the resist pattern is removed. As a result, the gate dielectric film GD1 and the first word line WL22
Alternatively, a laminated pattern composed of WL24 is formed in a parallel stripe pattern orthogonal to the source / drain regions S / D.

Next, the semiconductor thin film STF surface layer is etched. This etching may be ordinary dry etching, but a method using sacrificial oxidation is desirable. That is, the surface of the semiconductor thin film is thermally oxidized to form a thin sacrificial oxide film, which is removed by wet etching or the like. As a result, the polycrystalline silicon surface layer consumed during the sacrificial oxidation is etched uniformly and without any damage. This sacrificial oxidation condition is based on the gate dielectric film GD
1 is determined in advance so that nitrogen atoms introduced into the surface layer of the semiconductor thin film STF at the time of forming 1 are sufficiently removed.

A second gate dielectric film GD2 is formed under the same conditions as the gate dielectric film GD1 described above. Further, a conductive film WLF that completely fills the space between the word lines WL22, WL24,..., For example, a film of doped polycrystalline silicon or doped amorphous silicon is deposited. On this conductive film WLF, a resist opening above the word lines WL22, WL24,... Is formed.

Thereafter, using this resist as a mask, R
Perform anisotropic etching such as IE. Thereby, the conductive film WLF is separated, and the word lines WL21, WL23, W
L25,... Are formed.

Memory cell array 3 FIG. 6 shows an SSL-N in which bit lines and source lines are hierarchized.
1 shows an equivalent circuit diagram of an OR type memory cell array. In this memory cell array, bit lines are hierarchized into main bit lines and sub-bit lines, and source lines are hierarchized into main source lines and sub-source lines. The sub-bit line SBL1 is connected to the main bit line MBL1 via the select transistor S11,
The sub-bit line SBL2 is connected to the main bit line MBL2 via the select transistor S21. The sub-source line SSL1 is connected to the main source line MSL1 via the select transistor S12, and the sub-source line SSL is connected to the main source line MSL2 via the select transistor S22.
2 are connected. The sub-bit lines SBL1 and SBL2 and the sub-source lines SSL1 and SSL2 are each composed of a source / drain region S / D, are arranged in parallel stripes as in FIG. 1, and have a dielectric isolation layer ISO between cells.
Separated by Main bit lines MBL1 and MBL2 and main source lines MSL1 and MSL2 are formed by upper wiring layers.

The sub bit line SBL1 and the sub source line SSL1
, Memory transistors M11 to M1n (for example, n = 128) are connected in parallel, and sub bit line SBL2
Between the memory transistor M and the sub-source line SSL2.
21 to M2n are connected in parallel. The n memory transistors connected in parallel to each other and two select transistors (S11 and S12 or S21 and S2
2) constitutes a unit block constituting the memory cell array.

Each gate of the memory transistors M11, M21,... Adjacent in the word direction is connected to a word line WL1. Similarly, memory transistors M12, M2
, Are connected to the word line WL2.
Each gate of the memory transistors M1n, M2n,... Is connected to a word line WLn. The select transistors S11,... Adjacent in the word direction are connected to a select gate line SG1.
, And the select transistors S21,... Are controlled by a select gate line SG21. Similarly, the select transistors S12,... Adjacent in the word direction are controlled by the select gate line SG12, and the select transistors S22,. It should be noted that FIG.
As in (B), select transistor SW controlled by a common array select line to select a sub-array
1, SW2,... Are connected.

The basics of the writing, reading and erasing operations are the same as those in FIGS. 2A and 2B, and the description is omitted here.

Memory Cell Array 4 FIG. 7 is a plan view of a bulk type sub-array of a NAND type memory cell array. Further, FIG.
FIG. 8B is a cross-sectional view along line A, and FIG. 8B is an enlarged cross-sectional view of a part of FIG.

This memory cell array has a semiconductor thin film STF made of, for example, polycrystalline silicon doped with a p-type impurity.
Is formed. The word line W is formed on the semiconductor thin film STF.
L21, WL22,... WL2n are formed. The odd-numbered word lines WL21, WL23,..., WL2n (first word lines) are formed on the semiconductor thin film STF with the gate dielectric film GD1 interposed therebetween. A gate dielectric film GD2 is formed to cover the surfaces of the first word lines WL21, WL23,..., WL2n and the surface of the semiconductor thin film portion exposed between the first word lines. Then, even-numbered word lines WL22, WL24,... (Second word lines) are formed between the first word lines with the gate dielectric film GD2 interposed therebetween. In this manner, the two adjacent word lines are insulated and separated by the interposed gate dielectric film GD2 such that the dimension in the direction of separation becomes a film thickness. The word line is made of doped polycrystalline silicon or doped amorphous silicon.

The gate dielectric films GD1 and GD2 are made of, for example, an ONO film, an NO film, or a laminated dielectric film in which a small-diameter conductor is embedded. Here, as shown in FIG. 8B, each gate dielectric film includes a lowermost bottom dielectric layer BTM, an intermediate charge storage layer CHS, and an uppermost top dielectric layer TOP.

Outside the word line WL21, for example, a select gate line SG1 separated by a gate dielectric film GD2
Are arranged in parallel. Similarly, outside the word line WL2n, for example, a select gate line SG2 separated by a gate dielectric film GD2 is arranged in parallel. These select gate lines SG1 and SG2 also serve as the gate electrodes of the select transistors, and are in contact with the semiconductor thin film STF via the gate dielectric film GD3. Gate dielectric film GD
3 is formed of, for example, a single-layer silicon dioxide film. In this case, although the manufacturing process is slightly complicated, a single-layer gate dielectric film is formed only in this portion, and the select transistor becomes a normal MOS type. Alternatively, the gate dielectric film G
D2 and GD3 may be the same film, and charge injection may not be performed to the gate dielectric film GD3 depending on the applied bias condition.

Outside the select gate line SG1, a drain region DR formed of an n-type impurity region is formed. This drain region DR is shared with another NAND string not shown. Further, outside the select gate line SG2, a common source line CSL including an n-type impurity region is formed. The common source line CSL is shared by one row of NAND strings arranged in the row direction and another unillustrated one row of NAND strings adjacent in the column direction.

A second interlayer insulating layer INT2 is formed on the transistors constituting these NAND strings. Although parallel stripe-shaped bit lines may be arranged on the second interlayer insulating layer INT2, here, the drain region D
R is bit contact BC, drain wiring metal layer C
It is connected to lower peripheral circuits via the MD. Also, at a location not shown in the cross-sectional view, the common source line CS
Similarly, L is connected to a lower peripheral circuit via a source contact and a source wiring metal layer.

At the time of writing, the storage unit 1 shown in FIG.
When charge injection is performed, a positive drain voltage is applied to the drain region DR, and a reference voltage is applied to the common source line CSL.
A voltage for turning on one select transistor is applied to select gate lines SG1 and SG2. Further, to the other word lines WL21, WL22, WL24,... WL2n other than the word line WL23 to which the cell to be written is connected, a pass voltage capable of transmitting the drain voltage or the reference voltage to the cell to be written is applied. I do. As a result, a predetermined write drain voltage is applied between the source and the drain of the memory transistor forming the cell to be written. In this state, a predetermined program voltage is applied to the word line WL23. At this time, electrons supplied to the channel from the right side of FIG. 8B are accelerated in the channel, and high energy is obtained at the left end of the channel, so that the bottom dielectric layer BT
It is injected into the storage unit 1 over the potential barrier of M and stored. When injecting charges into the storage unit 2, the peripheral circuit switches the voltage between the drain region DR and the common source line CSL. Accordingly, the side on which electrons are supplied and the side on which electrons become hot in terms of energy are opposite to the above case, and electrons are injected into the storage unit 2.

As another more desirable writing method,
The source side injection method can be adopted. In this case, the storage unit 1
At the time of writing to the memory cell, a reference voltage is supplied from the drain region DR, and a drain voltage is supplied from the common source line CSL. Further, the word line W connected to the cell to be written is connected.
The voltage applied to the word line WL22 near one source of L23 is not a simple pass voltage but a voltage optimized to enable source side injection. Thereby, the word line WL
The lateral electric field is increased near the boundary between the word line WL23 and the word line WL23, and electrons can be more efficiently injected into the source end (storage unit 1) of the memory transistor.

In the case of injecting charges into the storage unit 2, the peripheral circuit switches the voltage between the drain region DR and the common source line CSL, and changes the voltage value of the word line WL24 to a value that allows source side injection. To optimize. This allows
The side on which electrons are supplied and the side on which electrons become hot in terms of energy are opposite to those described above, and electrons are injected into the storage unit 2.

At the time of reading, a predetermined read drain voltage is applied between the drain region DR and the common source line CSL so that the memory portion side where the bit to be read has been written becomes the source, and the word to which the cell to be read is connected is applied. A pass voltage is applied to a word line other than the word line. In addition, a channel portion sandwiched between the storage units at both ends can be turned on, but a low and optimized positive voltage is applied to the word line WL23 so as not to change the threshold voltage of the storage unit. At this time, the conductivity of the channel is effectively changed depending on the amount of charge stored in the storage unit to be read or the presence or absence of the charge, and as a result, the stored information is converted into the amount of current flowing through the bit line or the amount of potential change thereof. Read out. When the other bit is read, the peripheral circuit switches the voltage between the drain region DR and the common source line CSL so that the read is performed in the same manner as described above so that the storage unit side in which the bit is written becomes the source. Do.

At the time of erasing, collective erasing is performed by extracting charges to the substrate side by using FN tunneling on the entire surface of the channel or extracting charges to the word line side.

Next, the procedure for forming the NAND type sub-array will be briefly described.

A semiconductor thin film STF is formed on the first interlayer insulating layer INT1 by the same method as that for the memory cell array 2. The semiconductor thin film portion around the channel formation region is removed by lithography and etching to separate elements. A mask layer such as a resist is formed on the semiconductor thin film STF, and p is applied at a dose that determines the channel concentration by selective ion implantation.
Doping with type impurities. Another mask layer is formed, and a p-type impurity is selectively ion-implanted to form ap ⁺ contact region for giving a potential of the semiconductor thin film. Annealing is performed by the RTA method to activate the introduced impurities.

A gate dielectric film GD1 shown in FIG. 8B is formed on the semiconductor thin film STF by the same method as that for the memory cell array 2. A conductive film made of doped polycrystalline silicon or doped amorphous silicon is deposited on gate dielectric film GD1 by, for example, a CVD method. A resist pattern is formed on the conductive film, and anisotropic etching such as RIE is performed to pattern the conductive film. Subsequently, the first charge storage film GD1 exposed between the conductive film patterns is patterned using, for example, a dry etching apparatus using CF ₄ / CHF ₃ / Ar. After that, the resist pattern is removed. Thereby, the gate dielectric film GD
, WL2n are formed in a parallel stripe pattern.

Next, if necessary, for example, the surface layer of the semiconductor thin film STF is lightly etched by a method using sacrificial oxidation. Subsequently, a second gate dielectric film GD2 is formed under the same conditions as the gate dielectric film GD1. Further, if necessary, the gate dielectric film GD2 in the region outside the word line WL1 and the region outside the word line WLn is selectively removed, and a single-layer dielectric film GD3 is selectively formed in this portion.

The first word lines WL21, WL23,..., W
A conductive film completely filling the space between L2n, for example, a film of doped polycrystalline silicon or doped amorphous silicon is deposited. On this conductive film, first word lines WL21, WL23,.
A resist opening above WL2n is formed.

Thereafter, using this resist as a mask, R
Perform anisotropic etching such as IE. As a result, the conductive film is separated, and the second word line WL2 shown in FIG.
, WL24,... And select gate lines SG1, SG2.

An n-type impurity is ion-implanted into the semiconductor thin film portion outside the select gate lines SG1 and SG2. At this time,
Source / drain regions are not formed in the word line arrangement region because ions do not pass therethrough. Thereafter, the NAND type sub-array is completed through deposition of the second interlayer insulating layer INT2, formation of the bit contact BC, and formation of the upper wiring layer.

Memory Cell Array 5 FIG. 9A is a sectional view showing the structure of a memory cell constituting this array, and FIG. 9B is a plan view thereof.

Semiconductor thin film STF doped with p-type impurities
In addition, two source / drain regions S / D formed by introducing n-type impurities at a high concentration are formed apart from each other. The source / drain regions S / D are arranged in parallel stripes, like the other memory cell arrays described above. A region between the two source / drain regions S / D is a channel forming region. The channel forming region includes an inner channel region Ch2 formed substantially at the center thereof, and two outer channel regions Ch1a and Ch1b between the inner channel region Ch2 and the source / drain region S / D. The inner channel region Ch2 is the outer channel region Ch1a, C
The concentration of the activated p-type impurity is lower than that of h1b, and the threshold is increased.

On the inner channel region Ch2, for example, 1
A single-layer gate dielectric film GD0 made of silicon dioxide having a thickness of about 10 nm to 10 nm is formed. The gate dielectric film GD0 is a single layer, and has relatively few carrier traps in the film and does not have a charge holding ability. On gate dielectric film GD0, control gate electrode CG made of polycrystalline silicon or amorphous silicon to which impurities are added is formed. The control gate electrode CG is provided between the source / drain regions S / D in the space separated from the source / drain regions S / D.
It is arranged long in the column direction in parallel with D. The control gate electrode CG forms a control line CL of the memory cell array.
There is no limitation on the gate length of the control gate electrode CG, but it is preferable to make the control gate electrode CG ultra-fine, for example, 50 nm or less, since carriers in the channel run quasi-ballistically. That is,
Depending on the electric field conditions, when the gate length is made extremely small in this way, when carriers supplied from the source move through the channel, they undergo fine small-angle scattering due to impurities, but large-angle scattering that bends the orbit greatly. Carriers will run ballistically without being affected.

The gate dielectric film GD0 and the control gate electrode C
A gate dielectric film GD having, for example, three layers of BTM, CHS, and TOP and having a charge storage capability is formed so as to cover the surface of the G stacked pattern and the surface of the semiconductor thin film. The control gate electrode CG is formed on the gate dielectric film GD.
The gate electrode of the memory transistor that intersects with the gate electrode is formed. The gate electrode is made of, for example, polycrystalline silicon or amorphous silicon to which impurities are added, and forms a word line WL of the memory cell array.

This memory cell comprises a memory transistor,
A MOS transistor and a memory transistor have a three-transistor configuration in which two transistors are connected in series between two bit lines BL (source / drain regions S / D). The gates of the two memory transistors are controlled by a word line WL, and the gate of the central MOS transistor is a bit line B
It is controlled by a control line CL parallel to L. The threshold voltage of the memory transistor in the erased state is set lower than the threshold voltage of the MOS transistor due to the above-mentioned channel concentration difference and various conditions of the material, thickness and structure of the dielectric films GD0 and GD. I have. The main function of the central MOS type transistor is to perform auxiliary operations for improving characteristics at the time of operation (writing, reading, erasing) of the memory transistor, and to form a contact portion between the channel formation region and the gate dielectric film GD. Stipulate. A contact portion between the channel formation region and the gate dielectric film GD becomes a storage unit. The single-layer dielectric film GD0 between the two storage units 1 and 2 cannot contribute to data storage because it has no charge storage capability.

FIG. 10 shows this memory cell as SSL-NO
3 shows a memory cell array connected in an R type. Source lines SL1, S composed of odd-numbered source / drain regions S / D
, SL6, and bit lines BL1, BL2,..., BL formed of even-numbered source / drain regions S / D.
Are alternately arranged in the row direction and long and parallel in the column direction. Also, word lines WL1, WL2, WL3,.
Are arranged long and parallel to the row direction. A memory cell is arranged near an intersection between a word line W and a source line / bit line pair. In the first column, between the source line SL1 and the bit line BL1, the memory cells M11, M12, M13,
Are connected in parallel, two gate electrodes of the memory cell M11 are connected to the word line WL1, and two gate electrodes of the memory cell M12 are connected.
One gate electrode is connected to word line WL2, and two gate electrodes of memory cell M13 are connected to word line WL3. Such a connection relationship is repeated for other columns. The control lines CL1, CL2,..., CL6,. The source line and the bit line are controlled by a column decoder, the word line is controlled by a row decoder, and the control line CL is controlled by a column division control circuit.

FIG. 11 is a circuit diagram of a memory cell array in which memory cells are connected in a VG type. In this memory cell array, adjacent cells in the row direction in FIG. 10 share a bit line. Specifically, the wirings in the column direction include bit lines BL1, BL2,..., BL7,.
, CL6,... Are arranged alternately in the row direction.
Other configurations are the same as those in FIG. In such a VG type memory cell array, compared to the case of FIG. 10, a space for disposing the S / D impurity region on one side is not required, and the cell area is small because there is room for the upper metal wiring.

Next, a method of manufacturing this memory cell will be described. A semiconductor thin film STF is formed on the first interlayer insulating layer INT by a method similar to that for other memory cell arrays. If necessary, a dielectric isolation layer IS may be added to this semiconductor thin film.
O is formed, and the surface of the channel formation region is thermally oxidized to form a gate dielectric film GD0. This gate dielectric film GD0
Is used as a through film, and channel doping for determining a relatively high threshold voltage of the central MOS transistor is performed by, for example, ion implantation over the entire region of the channel formation region. Thus, as shown in FIG. 9A, a high-threshold channel doping layer to be the inner channel region Ch2 is formed. Subsequently, polycrystalline silicon or amorphous silicon to which impurities are added is deposited on the gate dielectric film GD0 and patterned in a long line in the column direction to form the control gate electrode CG.
To form

Using the control gate electrode CG as a mask and ion implantation using the gate dielectric film GD0 as a through film, impurities of the opposite conductivity type are introduced into the channel formation region around the control gate electrode CG (counter doping). This allows
In the region around the control gate electrode CG, the control gate electrode C
The p-type is weaker than the region below G. As a result, as compared with the inner channel region Ch2, the outer channel regions Ch1a and Ch1
The threshold voltage of 1b decreases. Thus, a lower channel resistance can be obtained even when the same gate voltage is applied.

Next, after processing the gate dielectric film GD0 into the same pattern using the control gate electrode CG as a mask,
A gate dielectric film GD is formed on the entire surface. Specifically, for example, 1000 times by a short-time high-temperature heat treatment method (RTO method).
A heat treatment at 10 ° C. for 10 seconds is performed to form a silicon dioxide film (bottom dielectric layer BTM). Next, a silicon nitride film (charge storage layer CHS) is deposited on the bottom dielectric layer BTM by LP-CVD so as to be thicker than the final film thickness. This CV
D is performed at a substrate temperature of 730 ° C. using, for example, a gas obtained by mixing dichlorosilane (DCS) and ammonia. The surface of the formed silicon nitride film is oxidized by a thermal oxidation method to form, for example, a 3.5 nm silicon dioxide film (top dielectric layer TO).
P) is formed. This thermal oxidation is performed, for example, in a H ₂ O atmosphere at a furnace temperature of 950 ° C. for about 40 minutes.

Next, sidewalls made of a conductive material are formed on both sides of the step of the gate dielectric film GD formed by reflecting the shape of the control gate electrode CG. Specifically, polycrystalline silicon or amorphous silicon to which impurities are added is deposited thickly, and the entire surface is etched (etched back) under the condition of strong anisotropy. If necessary, an n-type or p-type impurity is removed from the semiconductor thin film ST by oblique ion implantation using the formed sidewall and control gate electrode CG as a mask.
F is introduced to a relatively deep position. This makes it possible to adjust the threshold voltage or enhance the punch-through resistance.

Subsequently, an n-type impurity is doped into a region outside the sidewall by substantially vertical ion implantation using the sidewall and the control gate electrode CG as a mask, thereby forming a source / drain region S / D. afterwards,
For example, polycrystalline silicon or amorphous silicon having the same impurity doping conditions as the material forming the sidewalls is thickly deposited on the entire surface and patterned in a long line in a direction orthogonal to the control gate electrode CG, and the word line WL is formed. Form.

Thereafter, the non-volatile memory is completed by depositing a second interlayer insulating layer INT2, forming a contact, forming an upper wiring layer, and the like.

Next, the operation of the memory cell will be described. For writing, there are a first method using CHE injection and a second method for injecting high-energy charges by breakdown.

In the first method, a reference voltage is applied to the impurity region S / D serving as a source, and a drain voltage is applied to the impurity region S / D serving as a drain, and the control gate electrode CG (control line C / D) is applied.
L) and a predetermined positive voltage to the word line WL. Under these conditions, an inversion layer (channel) is formed in the channel formation region, electrons supplied from the source are accelerated in the channel, and a part thereof forms a bottom dielectric layer BTM of the charge retention film 6 on the drain side. Energy electrons (hot electrons) that exceed the energy barrier of the silicon dioxide film. Some of the hot electrons are injected into the drain-side portion (memory portion) of the gate dielectric film GD with a certain probability.

The channel electrons at the time of writing are accelerated as a whole while losing some of the energy received from the electric field due to impurity scattering and collision with the semiconductor lattice. The kinetic energy of this electron peaks near the drain end, and the source / drain S / D is full of electrons.
When entering, it decreases sharply. If the peak point of the kinetic energy can be increased as much as possible, the injection efficiency of hot electrons is improved.

In this memory cell, the resistance of the inner channel region Ch2 is relatively increased by providing a channel with a resistance difference, the electric field in this region is increased, and the acceleration efficiency is increased. Therefore, electrons are most efficiently energized immediately before injection, and as a result, the injection efficiency of hot electrons is improved as compared with the conventional case in which the channel has no resistance difference. In particular, when the inner channel length is shortened, electrons travel quasi-ballistically in a high-energy electric field, and the injection efficiency is further improved.

On the other hand, if it is desired to write data into the other storage unit, hot electrons are injected into the other storage unit on the same principle by exchanging the voltage relationship between the two impurity regions S / D. When electrons are injected, the threshold voltage of the memory transistor rises, and the memory transistor enters a write state.

In the second write method, a negative voltage is applied to the word line WL, and a positive voltage is applied to the write-side impurity region S / D. Under this condition, the surface of the n-type impurity region is in a deep depletion state, and the energy band is sharply bent. Then, an inversion layer is formed, and finally, avalanche breakdown occurs. Due to this breakdown, a pair of electrons and holes having high energy is generated, and the high-energy electrons are attracted to a positive voltage to form an n-type impurity region S / D.
Is absorbed into. On the other hand, most of high-energy holes (hot holes) flow into the semiconductor thin film STF, but a part thereof drifts toward the channel formation region side, where it is attracted to the electric field by the word line WL and crosses the dioxide film barrier. It is implanted into the gate dielectric film GD. In the second method, hot holes can be similarly injected into the storage section on the opposite side. Since this method does not form a channel, it is possible to write to two storage units simultaneously.

In the read operation, the two source / drain regions S / D are arranged such that the storage portion holding the storage data to be read is used as a source and the other storage portion is used as a drain.
In the meantime, for example, a drain voltage of about 1.5 to 3 V is applied, and a predetermined positive voltage is applied to each of the gate electrodes CG and WL. As a result, on / off of the channel or a difference in the amount of current occurs depending on the presence or absence of a charge or a difference in the amount of charge in the storage unit to be read, and as a result, a potential change in the impurity region on the drain side appears. By reading out this potential change by a sense amplifier (not shown), the logic of the stored data can be determined. Reading of other storage units
The same operation is performed with the source and drain exchanged. Thereby, the 2-bit storage data can be read independently.

In erasing, the retained charges are extracted or charges of the opposite polarity are injected. In the latter case, when writing is performed by the above-described first method, the second method is used for erasing. Conversely, when writing is performed by the second method, the first method is used for erasing. In the former method of extracting the retained charges, a predetermined electric field having a magnitude and direction in which the charges are extracted by the tunneling phenomenon is generated between the word line WL and the source / drain regions S / D. As a result, the retained charges are drawn to the substrate side, and the memory transistor enters an erased state where the threshold voltage is low.

This memory cell has two storage units having a charge storage capability, and the two storage units are separated by a single-layer dielectric film GD0 having no charge storage capability. Therefore, at the time of holding the 2-bit storage data, 2-bit storage information is reliably distinguished. The reason is that even if an excessive amount of charge is injected into each storage unit, the single-layer dielectric film GD0 having no data retention characteristic capability exists therebetween, so that the charge injection does not proceed beyond a certain region. This is because the distribution regions do not mix with each other. In addition, even if the retained charges drift at the time of high-temperature retention, the distribution regions of the charges are not mixed with each other. In addition, providing a resistance difference in the channel formation region Ch increases the charge injection efficiency and realizes high-speed operation during writing or erasing.

The current-voltage characteristics of the bulk type MONOS memory cell in the written state and the erased state were examined.
The memory cell used in this study has the structure of FIG.
(A) and those connected to the SSL-NOR type shown in FIG. 2 (B) were used. As a result, the off-leak current value from an unselected cell at a drain voltage of 1.5 V was about 1 nA.
Since the read current in this case is 10 μA or more, erroneous read of a non-selected cell does not occur. It was also found that the MONOS memory transistor having a gate length of 0.18 μm had a sufficient margin for punch-through withstand voltage at the time of reading. The read disturb characteristics at a gate voltage of 1.5 V were also evaluated, and it was found that reading was possible even after a lapse of 3 × 10 ⁸ sec or more.
It was found that the number of times of data rewriting was satisfactory because the charge traps were spatially discretized, and satisfied 1 × 10 ⁶ times. The data retention characteristics satisfy 85 ° C. and 10 years after data rewriting 1 × 10 ⁶ times.

Similarly, the characteristics of various memory transistors of the TFT type MONOS memory cell were evaluated. As a result, data comparable to the above-mentioned bulk type MONOS memory cell was obtained. In addition, bulk type MO
It has also been found that in order to obtain exactly the same characteristics as the NOS memory cell, it is better to slightly increase the design rule of the TFT type MONOS memory cell.

In the above description, the peripheral circuit selects one of the sub-arrays. However, in the present invention, the peripheral circuit may be configured so that a plurality of sub-arrays having different hierarchies are simultaneously selected and simultaneously written. For example, the bulk type sub-array MCA1 shown in FIG.
When the TFT type sub-array MCA2 shown in FIG. 8B is selected simultaneously, the array selection lines SGA1 and SGA2 are simultaneously activated, and the selection gate line SG1 in each sub-array is activated.
And the select gate lines SG2 are simultaneously activated. Then, the bit line, the source line, and the word line in each sub-array are simultaneously driven, and the bulk type sub-array MCA
1 and the TFT type sub-array MCA2. As a result, the writing speed per unit time can be significantly reduced.

In any of the above-described memory cell arrays, the charge storage means is planarized and discretized in the gate dielectric films GD, GD1, and GD2 in which a plurality of dielectric layers are stacked for multi-layering. I have. Even if the potential barrier layer BTM between the charge storage means and the semiconductor thin film STF is made thinner and a leak path is generated in the potential barrier layer BTM, the charge holding characteristic does not sharply decrease if the frequency of occurrence is small to some extent. . This is because the charge storage means (charge trap or small-diameter conductor) is discretized, so that only local stored charges around the leak path disappear into the semiconductor thin film STF.

Further, as described in detail in the memory cell arrays 2 and 4, when the word lines are partially overlapped, the distance between the word lines is reduced by the dielectric film (gate dielectric film GD).
Since it is determined by the film thickness of 2), the distance between word lines is significantly smaller than the word line width. Therefore, 2F ² (F:
A memory cell having an extremely small area can be realized as a cell for storing the resolution limit of lithography or the design rule) and 2 bits.

[0097]

According to the nonvolatile semiconductor memory device of the present invention, a part of the memory cell array is arranged in a stacked structure in which a plurality of conductive layers are stacked above a semiconductor substrate with an interlayer insulating layer interposed therebetween. It became possible. With this multi-layered memory cell array, the occupied area of the memory cell array in the chip can be reduced, and the bit cost can be significantly reduced. In addition, connection of peripheral circuits to each subarray has been facilitated.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a schematic structure of a nonvolatile memory according to an embodiment.

FIG. 2 relates to the memory cell array 1 of the embodiment, and FIG.
3 is an equivalent circuit diagram of a bulk type sub-array, and FIG. 3 (B) is an equivalent circuit diagram of a TFT type sub-array.

FIG. 3 is a cross-sectional view showing a structure of a memory cell according to the memory cell array 1 of the embodiment;

FIG. 4 is a sectional view showing a schematic structure of a memory cell array 2 of the embodiment.

FIG. 5A relates to the memory cell array 2 according to the embodiment;
Is a plan view of a TFT type sub-array, and FIG.
It is sectional drawing along the A line.

FIG. 6 is an equivalent circuit diagram showing a basic configuration of the memory cell array 3 of the embodiment.

FIG. 7 is a plan view of a TFT type sub-array according to the memory cell array 4 of the embodiment.

FIG. 8 relates to the memory cell array 4 of the embodiment,
FIG. 8 is a cross-sectional view taken along line AA of FIG. 7, and FIG. 8B is a cross-sectional view in which a part of FIG.

FIG. 9 relates to the memory cell array 5 of the embodiment,
FIG. 3 is a cross-sectional view illustrating a structure of a memory cell, and FIG. 3B is a plan view of the memory cell.

FIG. 10 is an equivalent circuit diagram when the memory cells of the memory cell array 5 according to the embodiment are connected in an SSL-NOR type.

FIG. 11 is an equivalent circuit diagram when the memory cells of the memory cell array 5 of the embodiment are connected in a VG-NOR type.

[Explanation of symbols]

SUB: semiconductor substrate, W, W0: well, S / D: source / drain region, ISO: dielectric separation layer, INT1,
INT2: interlayer insulating layer, WC1 to WC3, BC: contact, IC: interconnecting layer, STF: semiconductor thin film, GD,
GD1, GD2: gate dielectric film, BTM: bottom dielectric layer, CHS: charge storage layer, TOP: top dielectric layer,
MCA1: bulk type sub-array, MCA2: TFT type sub-array, M11, etc .: memory cell, SW1, SW2: select transistor for selecting sub-array, SB1, SS
1 etc. select transistor, SGA1 etc ... array select line, SG1, SG2 ... select gate line, WL, WL21 etc ... word line, BL, BL21 etc ... bit line.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F083 EP17 EP18 EP22 EP32 EP76 EP77 ER02 ER09 ER11 ER14 ER19 GA09 HA02 JA06 KA06 LA12 LA16 MA06 MA19 NA01 NA08 PR33 5F101 BA45 BA54 BB02 BC02 BD22 BD30 BD34 BE05 BE06 BF05

Claims (11)

[Claims] A plurality of dielectric layers are stacked between a semiconductor in which a channel of a memory cell is formed and a gate electrode, and charges are discretized within the plurality of dielectric layers in a plane facing the channel. What is claimed is: 1. A nonvolatile semiconductor memory device including storage means, comprising: a stacked structure in which a plurality of conductive layers and interlayer insulating layers are stacked on a semiconductor substrate, wherein one or a plurality of sub-arrays forming a memory cell array are provided on the semiconductor substrate. A nonvolatile semiconductor memory device formed, wherein the remaining sub-arrays of the memory cell array are arranged in the stacked structure. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said sub-array disposed in said laminated structure has a plurality of memory transistors formed on a semiconductor thin film on an interlayer insulating layer. 3. The nonvolatile semiconductor memory device according to claim 1, wherein a peripheral circuit for selecting and operating a memory cell is formed in a semiconductor substrate region and / or a stacked structure around said sub-array. 4. The nonvolatile semiconductor memory device according to claim 3, wherein said peripheral circuit includes a select transistor group arranged in a stacked structure around said sub-array and selecting one of a plurality of sub-arrays. 5. The design rule of a memory cell forming a sub-array formed on the semiconductor substrate is equal to or less than a design rule of a memory cell forming a sub-array formed on a semiconductor thin film and arranged in the laminated structure. 3. The nonvolatile semiconductor memory device according to item 2. 6. The non-volatile semiconductor memory device according to claim 1, wherein two or more of said sub-arrays are stacked in said stacked structure with an interlayer insulating layer interposed therebetween. 7. The nonvolatile semiconductor memory device according to claim 3, wherein said peripheral circuit has a function of simultaneously selecting a plurality of sub-slays having different hierarchies and writing data at the same time. 8. The peripheral circuit according to claim 1, wherein the charge injection location is changed to
4. The nonvolatile semiconductor memory device according to claim 3, further comprising a function of switching a voltage applied to a source and a drain of each memory transistor in order to store a bit. 9. The gate dielectric film includes a potential barrier layer formed on the semiconductor thin film, a charge storage layer including a charge trap as charge storage means, and an oxide layer on the charge storage layer. Item 2. The nonvolatile semiconductor memory device according to Item 1. 10. The non-volatile memory according to claim 1, wherein said gate dielectric film is formed on said semiconductor thin film and includes a charge storage layer including a charge trap as a charge storage means, and an oxide layer on said charge storage layer. Semiconductor memory device. 11. A gate dielectric film comprising: a potential barrier layer formed on the semiconductor thin film; a plurality of small-diameter conductors formed discretely on the potential barrier layer as charge storage means; 2. The nonvolatile semiconductor memory device according to claim 1, further comprising: an insulating layer covering the small-grain conductor.