JP2002367395A - TAG-RAM test method and apparatus therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for testing functions of a TAG-RAM without loading all capacity of actual memories for all patterns of address data stored in a TAG-RAM, and to provide its device. SOLUTION: The TAG-RAM test device for testing functions of a TAG-RAM 22 used for control of cache memory constituting a CPU, is provided with a floating address converting section 23 allotting a mounted physical address space of a main memory 21 to arbitrary physical address space, and a diagnosis section diagnosing whether a TAG-RAM is written correctly in a non-mounted physical address space of the main memory 21 allotted by the mounted physical address space of the main memory 21 and the floating address converting section 23 or not.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a TAG-RAM test method for testing the performance of a TAG-RAM used for controlling a cache memory constituting a CPU and an apparatus therefor, and more particularly, to a method for testing all of address data stored in a TAG-RAM. The performance of the TAG-RAM does not depend on whether or not the real memory is actually mounted for the entire capacity of the pattern, that is, includes not only the real memory space where the real memory is mounted but also the virtual memory space where the real memory is not mounted. T that can test
The present invention relates to an AG-RAM test method and an apparatus therefor.

[0002]

2. Description of the Related Art In recent years, an increase in main memory space and an increase in cache memory capacity have occupied a large weight as computer systems have become faster.
Along with this, the capacity of the TAG-RAM used for controlling the cache memory forming the CPU has been greatly increased.

FIG. 6 is a diagram showing the principle of a conventional TAG-RAM test apparatus. In FIG. 6, 61 is a main memory,
Reference numeral 62 denotes a TAG-RAM used for controlling a cache memory (not shown) in a CPU (not shown). The main memory 61 is divided into (1) to (6) as shown.
(1) The test program space is not the test target memory space but the space in which the test program itself operates. (2) The actual test memory space is the memory space to be tested and is the space where the memory is actually mounted. (3) Test memory space MIN
Through (4) test memory space n and (5) test memory space MA
The space up to X is a test target space, and is a space in which real memories are sequentially transferred and mounted as indicated by arrows 63, 64, and 65 by hand or the like when testing the TAG-RAM 52. (6) The physical address data indicates data written in the TAG-RAM 62.

In the first TAG-RAM test system according to the prior art, since the data pattern stored in the TAG-RAM is the physical address of the main memory to be accessed, the most significant bit of the address on the main memory is determined. In order to test all included patterns, it is necessary to actually mount a memory of the entire capacity at the main memory mounting position in the test system. Although the total capacity of the main memory to be mounted varies depending on the system, recently, a system having a main memory with a capacity of gigabytes to terabytes has become uncommon.
Implementing the full amount of memory for each AM test is a time and labor consuming and inefficient task.

Therefore, a TAG-RAM test method capable of testing all patterns of address data stored in a TAG-RAM without mounting a memory of the entire capacity at a main memory mounting position in the test system, and a method for testing the same. Equipment is becoming necessary. Generally, in a TAG-RAM test according to the related art, address data in the memory space is written in the TAG-RAM by successively accessing a mounting memory space in which a memory is actually mounted at a main memory mounting position. We are testing using that.

In this method, since addresses other than the mounting memory space at the main memory mounting position cannot be accessed, they are not written as data patterns in the TAG-RAM. To test all patterns of TAG-RAM,
The physical address can be set by mounting the memory of the full capacity at the main memory mounting position, or by mounting some memory without mounting the memory of the full capacity at the main memory mounting position and shifting the mounting position of the memory in order. Are tested for all physical addresses.

Further, a second TAG-RA according to the prior art
In order to improve the TAG-RAM test method, the M test system is considered to be provided with a mechanism for directly writing / reading an arbitrary pattern to / from the TAG-RAM. There is a mechanism provided with a mechanism for incorporating the direct access mechanism. In this test system, by providing the above-described mechanism, an arbitrary pattern can be used, so that all the patterns of the TAG-RAM can be easily tested.

However, usually, the test program itself has a TA
In order to use the G-RAM unconsciously, it is necessary to manage the test memory area (test space) and the memory area (operating space) storing the TAG-RAM test program very carefully. For this reason, the above mechanism is not general-purpose because it depends on the mechanism.

[0009]

In the TAG-RAM test system according to the first prior art, every time a test is performed, the entire memory is mounted or the memory is sequentially replaced by hand to change the mounting position of the memory. There is a problem of spending time and effort because it has to be tested.

The above-mentioned TAG-RAM according to the second prior art
In the test system described above, the TAG-RAM access is realized by a different mechanism between the actual and the test, so that it is not possible to expect a test in the same operation as the actual operation, and there is a problem that the test accuracy is hindered. Also, with the speeding up of CPU,
The operating time allowed for each mechanism and the timing with other mechanisms are becoming very critical, and therefore TAG
In a RAM test, not only a TAG-RAM pattern test but also a test of the entire mechanism operation using an actual access mechanism is required. As in the second prior art, a different test from the actual access mechanism is required. Using a mechanism for
In the test of the G-RAM, a difference occurs from the actual mechanism using the actual access mechanism, and the verification accuracy is reduced. Therefore, in a TAG-RAM test, a system using an actual mechanism under the same environment as possible is desired.

As described above, the present invention provides a TAG-RA
For all the patterns of the address data stored in M, regardless of whether or not the real memory is actually mounted for the entire capacity, that is, not only the mounting memory space where the real memory is mounted but also the virtual memory where the real memory is not mounted TAG-RAM performance can be tested including space, and TAG-RAM
An object of the present invention is to provide a TAG-RAM test method in which access is performed using the same mechanism in actual and test, and an apparatus therefor.

[0012]

A TAG-RAM test method according to the present invention for achieving the above object is a TAG-RAM test method for testing the performance of a TAG-RAM used for controlling a cache memory forming a CPU. A first step of setting the head address of the memory space of the memory as a pointer, a second step of reading the capacity of the cache memory corresponding to the TAG-RAM to be tested, and The address of the test memory space this time is
A third step of writing to the RAM, determining whether or not the address written in the TAG-RAM matches a test address previously written in a memory space other than the memory space to be tested; A fourth step of adding the capacity of the cache memory to the value of the pointer to update the value of the pointer; and determining from the updated address of the pointer to an address corresponding to the capacity of the cache memory. It is determined whether or not the next test memory space is mounted. If it is determined that the memory space is mounted, the process returns to the third step. If it is determined that the test memory space is not mounted, the process proceeds to the sixth step. A step of allocating an address of the next test memory space to the present test memory space, and returning to the third step; and a sixth step. When it is determined that the mismatch-flop, characterized in that the TAG-RAM is provided with a seventh step, to diagnose as abnormal.

The TAG-RA of the present invention that achieves the above object.
The M test apparatus is a TAG-RAM for testing the performance of a TAG-RAM used for controlling a cache memory forming a CPU.
In the test apparatus, a floating address conversion unit that allocates a physical address space mounted on a main memory to an arbitrary physical address space, and a physical address space mounted on the main memory and an unmounted physical address of the main memory allocated by the floating address conversion unit The TAG-
A diagnostic unit for diagnosing whether the RAM has been correctly written;
It is characterized by having.

The TAG-RAM test apparatus of the present invention simultaneously tests each TAG-RAM in each CPU in a multi-CPU configuration.

[0015]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a block diagram of a TAG-RAM test apparatus according to an embodiment of the present invention. In FIG. 1, a TAG-RAM test apparatus 10
Are a plurality of n CPs denoted by 100, 101,..., 10n
U # 0, # 1,..., #N, one main memory 11, floating address converter 13, and system cache controller 15
And Each CPU is connected to the main memory 11 and the system cache control unit 15 via a data bus 16 and an address bus 17.

Each CPU 100, 101,..., 10n has a cache memory and a TAG-RAM for storing data stored in the cache memory, ie, address data of the main memory 11. The address data of the TAG-RAM is used as a tag for controlling data transfer between the cache memory and the main memory 11. The main memory 11 has a TAG-RAM test program for executing the present invention and an address / data control program.
The address / data control program uses the TAG in each CPU.
A program for controlling the address stored in the RAM, the data stored in the cache memory, the memory address stored in the system TAG-RAM in the system cache control unit 15, and the CPU number.

System cache control unit (SCC) 15
The system TAG-RAM manages the latest data stored at the address in the main memory 11 in which TAG-RAM is stored in which CPU, and the system TAG-RAM in the main memory shared by a plurality of CPUs The address of the data and the number of the CPU having the data are managed. For example, when the CPU # 1 requests data of an address in the SCC 15, the SCC 15 receives the data and searches the system TAG-RAM. If the search result is the CPU # 2, the CPU # 1 determines that the CPU # 2 has the data. Notify CPU # 1. Then, the CPU # 1 sets C
The data is moved from PU # 2 to its own cache memory. SCC15 is the system TAG-
Change the RAM. Such control is referred to as cache coherency control, and therefore the system TAG-RA
M is also called a TAG-RAM for coherency control.

FIG. 2 is a diagram showing the principle of the TAG-RAM test apparatus according to the present invention, and FIG. 3 is a flowchart showing the processing of the TAG-RAM test apparatus shown in FIG. 2, the main memory 21 includes (1) a test program space, (2) an actual test memory space, (11) a test memory shadow space MIN to (12) a test memory, a shadow space n to (13) a test memory It has a shadow space MAX. (1) The test program space is a space in which the test program itself operates, and is a space in which a memory is actually mounted. (2) The actual test memory space is the space in which the memory is actually mounted in the test target memory space. (11) Test memory shadow space MIN-(12) Test memory shadow space n-(13) Test memory shadow space MAX is a memory space but an expanded space of the test memory space in which no real memory is mounted ( Shadow), which is a test space that is accessible so as to be converted by the address conversion of the test memory space of (2) by the floating address conversion unit of (10).

(6) The physical address data is the C
Refers to a data image written in the TAG-RAM 22 in the PU. (10) The floating address conversion unit 23 is a mechanism that makes it appear that a memory is mounted in all physical spaces (addresses) including a physical space (address) in which no memory is mounted. In other words, the floating address converter 23 has a function of converting a physical address to be accessed to another physical address, and has a function of allocating a mounted memory space to an unmounted memory space.

(15) The pointer points to the start address of the test memory space. However, no special hardware is provided, and the pointer is provided on the logic of the test program. A method of testing a TAG-RAM according to the present invention will be described below with reference to the flowcharts of FIGS. By sequentially shifting the addresses of the actually implemented (2) test memory space by the (10) floating address translation unit, it is possible to perform a test equivalent to the fact that the entire space is implemented. The (10) floating address conversion unit is a mechanism for converting a physical access address into an arbitrary physical access address according to an internal address conversion mechanism and a set value.

In the flowchart of FIG. 3, the numbers following S indicate step numbers. Step S1: The start address of the memory space to be tested is set to a pointer indicating the memory space address. Step S2: Read the capacity of the cache memory corresponding to the TAG-RAM to be tested.

Step S3: The current address of the test memory space in the memory space to be tested from the address indicated by the pointer to the address corresponding to the capacity of the cache memory is written to the TAG-RAM. Step S4: Read the address written in the TAG-RAM and the test address previously written in the memory space other than the memory space to be tested.

Step S5: T read in step S4
When it is determined that the address written in the AG-RAM matches the test address, the process proceeds to step S6, and when it is determined that the addresses do not match, the process proceeds to step S10. Step S6: Update by adding the capacity of the cache memory to the value of the pointer. Step S7: It is determined whether or not the value of the pointer has reached the maximum address. If it is determined that the value has reached the maximum address, the routine is terminated. If it is determined that the pointer has not reached the maximum address, the process proceeds to Step S8.

Step S8: The memory space from the address of the updated pointer to the address corresponding to the capacity of the cache memory is set as the next test memory space, and it is determined whether or not the space is implemented. If so, the process returns to step S3, and if it is determined that the device is not mounted, the process proceeds to step S9. Step S9: After allocating the address of the next test memory space to the current test memory space, the process returns to step S3.

Step S10: Diagnose that the TAG-RAM is abnormal. By executing the processing of the above flowchart, all physical address spaces can be accessed, and all address data patterns of the TAG-RAM can be tested. Although the above description does not refer to (1) the test of the TAG-RAM for the test program space for storing the test program,
According to the prior art, the test of the G-RAM is performed by (2) storing a test program in an actual test memory space, (1) performing a test using the test program space as an actual test memory space, or (1) testing a test program space. Is operated normally, and the TAG-RAM is regarded as normal and substituted.

FIG. 4 is a detailed explanatory diagram of a specific example of the floating address converter shown in FIG. Usually, (2) When testing the TAG-RAM only in the actual test memory space, the TAG-RAM
Only the physical address of the memory space mounted on the main memory is written (registered) in the RAM. Therefore, in this case, (2) the test can be performed only with the bit pattern (address) data that can be generated at the physical address in the actual test memory space. Therefore, according to the present invention, the physical address of the unmounted memory space (test memory shadow space) to be tested in the TAG-RAM is moved to the memory space (real test memory space) where the memory is mounted by the floating address converter. All the physical space of the main memory can be test-tested.

In FIG. 4, the physical address space before conversion by the floating address converter 43 of the main memory 41 is shown on the left, and the physical address space after conversion is shown on the right. In the main memory 41, memories are mounted from address # 000000000 to address # 000003000, and no memory is mounted after address # 000003000. The floating address conversion unit 43
It has a conversion target address register 401, an address extraction register 402, a conversion address register 403, a valid address register 404, and a conversion control unit 405.

The conversion target address register 401 stores a physical address to be converted. The address extraction register 402 as a mask register stores bit configuration data for extracting a target bit of a conversion target address by a logical product. The conversion address register 403 stores the post-conversion address. The effective address register 404 stores bit configuration data for extracting an effective bit to be reflected in the post-conversion address of the pre-conversion address by logical product of the address target bit. The translation control unit 405 controls address translation in the floating address translation unit.

The floating address conversion unit 43 stores an arbitrary physical address (address before conversion) and an address extraction register 40.
When the logical product of the values set to 2 matches the value of the conversion target address register 401, the conversion address register 40
Then, the converted address is generated. FIG. 5 is a flowchart of the processing of the floating address conversion unit. In the flowchart of FIG. 5, numbers following S indicate step numbers.

Step S51: The logical product of the value of the address before conversion and the value of the address extraction register 401 is calculated. Step S52: The result of step S51 is compared with the value of the conversion target address register 401. When these values match, the process proceeds to step S53, and when they do not match, the process ends without converting the address.

Step S53: The logical product of the value of the pre-conversion address and the value of the effective address register 404 is calculated. Step S54: The logical sum of the result of step S53 and the value of the translation address register 403 is calculated. Step S55: The result of step S54 is set as the post-conversion address.

As a specific example, 000100000 (hexadecimal) and an address extraction register 4
02, ffffff000 (hexadecimal), conversion address register 40
3, 000003000 (hexadecimal), effective address register 404
Set 000000fff (hexadecimal) to 0 as the pre-conversion address.
00100050 (hexadecimal) is converted. Then, the address before conversion 00
0100050 (hexadecimal) and the value fffff of the address extraction register 402
The logical product with f000 (hexadecimal) is 000100000 (hexadecimal), which matches the value of the conversion target address register 401, and is therefore converted to the value 000003000 (hexadecimal) of the address register 403. Furthermore, the value 000000ff of the effective address register 404
The value of the logical product of f (hexadecimal) and the address before conversion, 000000050 (16
Hex) is added, the converted address is 000003050 (1
Hexadecimal). Thus, in the above example, 000100050 (16
Hex) is converted to 000003050 (hex). The above conversion processing by the conversion control unit 405 is executed for access to all addresses.

(Supplementary Note 1) TA for testing performance of TAG-RAM used for control of cache memory forming CPU
In the G-RAM test method, a first step of setting a start address of a memory space to be tested as a pointer, a second step of reading a capacity of a cache memory corresponding to the TAG-RAM to be tested, A third step of writing the current address of the test memory space up to the address corresponding to the capacity of the cache memory into the TAG-RAM, and storing the address written in the TAG-RAM and the memory space other than the memory space to be tested. It is determined whether or not the test address matches the previously written test address. If it is determined that the address is the same, the capacity of the cache memory is added to the value of the pointer to update the value of the pointer. Step, the next test method from the updated address of the pointer to the address corresponding to the capacity of the cache memory. Determines whether re space is implemented, the time when it is determined to be mounted back to the third step, it is determined not to be implemented sixth
A fifth step of proceeding to a step, a sixth step of returning to the third step after allocating an address of the next test memory space to the present test memory space, and , The TAG
A TAG-RAM test method, comprising: a seventh step of diagnosing that the RAM is abnormal.

(Supplementary Note 2) Supplementary note 1 for simultaneously testing each TAG-RAM in each CPU in a multi-CPU configuration
TAG-RAM test method. (Supplementary Note 3) In a TAG-RAM test apparatus for testing the performance of a TAG-RAM used for controlling a cache memory forming a CPU, a floating address conversion unit allocating a physical address space mounted on a main memory to an arbitrary physical address space; The TAG-R is used for the physical address space of the main memory and the physical address space of the main memory which is allocated by the floating address converter.
A TAG-RAM test device, comprising: a diagnosis unit that diagnoses whether the AM has been correctly written.

(Supplementary Note 4) Supplementary note 3 for simultaneously testing each TAG-RAM in each CPU in a multi-CPU configuration
The TAG-RAM test apparatus according to item 1. (Supplementary Note 5) A TAG used for controlling a system cache memory in the system cache control unit, the system cache control unit controlling a coherency of each cache memory in each CPU in the multi-CPU configuration.
The TAG-R of Appendix 4 for testing the performance of RAM;
AM test equipment.

[0036]

As described above, according to the present invention, the TAG-RAM of the CPU in a device having a large-capacity main memory does not need to be completely mounted or to replace the memory manually. When the test is performed, it does not depend on whether or not the real memory is installed for all the patterns of the address data stored in the TAG-RAM. The performance of the TAG-RAM can be tested including the virtual memory space where no memory is installed.

Further, in the direct access of the TAG-RAM using the mechanism dedicated to the test of the TAG-RAM, although the corruption of the RAM can be detected, the access is far from the actual access, and the test of the TAG-RAM is not sufficiently guaranteed. However, according to the present invention, it is possible to perform a TAG-RAM test under the same environment as when all memories are actually mounted.
The AG-RAM access can be tested using the same mechanism for actual and test, that is, with the same access as the actual access, and the TAG-RAM test is sufficiently guaranteed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a TAG-RAM test apparatus according to an embodiment of the present invention.

FIG. 2 is a principle diagram of a TAG-RAM test apparatus according to the present invention.

FIG. 3 is a flowchart of a process of the TAG-RAM test apparatus shown in FIG.

FIG. 4 is a detailed explanatory diagram of a specific example of a floating address conversion unit shown in FIG. 2;

FIG. 5 is a flowchart of a process performed by a floating address converter.

FIG. 6 is a diagram illustrating the principle of a TAG-RAM test apparatus according to the related art.

[Explanation of symbols]

 11, 21, 41, 61: Main memory 22, 62: TAG-RAM 13, 23, 43: Floating address converter 24: Pointer 15: System cache controller 100, 101, 10n: CPU

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (reference) G11C 11/41 G11C 11/34 Z F term (reference) 2G132 AA08 AB20 AE14 AE22 AE23 AL09 AL11 5B005 JJ01 KK13 MM01 MM31 RR01 VV22 5B015 HH01 HH03 JJ21 KB52 MM07 RR06 5B018 GA03 HA01 MA03 PA03 QA13 5L106 AA02 DD21 GG05

Claims (3)

[Claims] 1. A TAG-RAM for testing the performance of a TAG-RAM used for controlling a cache memory forming a CPU
In the test method, a first step of setting a start address of a memory space to be tested as a pointer, a second step of reading a capacity of a cache memory corresponding to a TAG-RAM to be tested, A third step of writing the current address of the test memory space up to the address corresponding to the capacity into the TAG-RAM, and writing the address written in the TAG-RAM and a memory space other than the memory space to be tested in advance A fourth step of determining whether or not the read test addresses match, and when determining that they match, adding the capacity of the cache memory to the value of the pointer to update the value of the pointer; Of the next test memory from the address of the pointer to the address corresponding to the capacity of the cache memory. It is determined whether or not is implemented. When it is determined that the package is implemented, the process returns to the third step. When it is determined that the package is not implemented, the process proceeds to the sixth step. After allocating the address of the test memory space to the current test memory space, when it is determined that there is a mismatch in the sixth step returning to the third step and in the fourth step, it is determined that the TAG-RAM is abnormal. TAG-R, comprising a seventh step of diagnosing.
AM test method. 2. A TAG-RAM for testing the performance of a TAG-RAM used for controlling a cache memory forming a CPU.
In the test apparatus, a floating address conversion unit that allocates a physical address space mounted on a main memory to an arbitrary physical address space; a physical address space mounted on the main memory and an unmounted physical address of the main memory allocated by the floating address conversion unit A diagnostic unit for diagnosing whether or not the TAG-RAM has been correctly written into a space. 3. The TAG-RAM test apparatus according to claim 2, wherein each TAG-RAM in each CPU in the multi-CPU configuration is tested simultaneously.