JP2002264095A - Method of manufacturing on-insulator silicon and polysilicon wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing an optical micro electronic mechanical device by forming a composite wafer having polysilicon and an insulator embedded under a top monocrystal silicon layer. SOLUTION: This method comprises a step of processing a first wafer with two faces and providing at least one semiconductor layer patterned and made plane, on at least one face of these two faces, and a step of connecting a second wafer of monocrystal silicon to the semiconductor layer on the first wafer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure and a method for manufacturing an optical MEM, also called a MEMS (Micro Electro Mechanical System), and a MOEMS (Micro Opto Electro Mechanical System). Further, the present invention is directed to a need for a solution for integrating microelectronics into an optical MEM system.
This need is particularly strong in the fields of communications and spectral analysis. However, it finds applicability in other applications such as, for example, microfluidic applications and ink jet printers.

[0002]

BACKGROUND OF THE INVENTION Various current approaches to optical MEMS fabrication tend to limit the number of material layers and mold flexibility available to designers. Specifically, the mirror, a key structure of MOEMS, is a material that is more mechanically robust and has more consistent mechanical properties than the micromachined polysilicon commonly used in the field. There is a demand for

US Pat. No. 6,014,240 to Floyd et al. Discloses the integration of a light source with a solid state scanning system having a single crystal silicon deflection mirror and scanning mirror. The separation of the microelectromechanical system and the light emitter on a separate substrate allows the use of flip chip and solder bump bonding techniques for light source mounting. Thereafter, the separated substrates are bonded together into a complete wafer to form an integrated solid state scanning system.

[0004]

There is a need for improved process methods that are structurally more robust and have better design flexibility for building micro-opto-mechanical systems. For example, it would be desirable to be able to construct mirrors with excellent flatness and consistent performance, which would break the limits of typical pure polysilicon MEMS devices and mirrors. Specifically, a need exists for a technique that provides the advantages of a single crystal silicon structure along with traditional polysilicon device technologies and methods. CMOS
It is also desirable to further improve compatibility with. This is because this allows for greater device and circuit complexity and increases the implementation of the various support circuits required for a complete MEMS solution. That is, this is the optical ME
This means that the amplifier for feedback control, which gives the required positioning accuracy for a successful MS device, can be made on-board.
Accordingly, it is desirable to address this and other difficulties and deficiencies currently known in the MEMS field with improved optical MEMS processing methods.

[0005]

SUMMARY OF THE INVENTION The present invention relates to a method for manufacturing a micro device. The method processes a first wafer and places a patterned and planarized semiconductor layer on at least one of two surfaces of the first wafer. Then, a second wafer of single crystal silicon is bonded to the semiconductor layer on the first wafer.

More specifically, the present invention relates to a method of processing a first wafer having two surfaces and forming at least one patterned semiconductor layer on at least one of the two surfaces. Then, a second wafer of single crystal silicon having two faces is processed to form at least one patterned semiconductor layer on at least one of these faces. Next, the semiconductor surface of the second single crystal silicon wafer is bonded onto the semiconductor layer of the first wafer, after which the second single crystal silicon wafer is thinned to an appropriate device thickness. Finally, patterning of the thinned second wafer is performed using a typical preparation sequence of MEM devices.

[0007]

FIG. 1 shows the initial steps in a preferred embodiment of the manufacturing process. On the first wafer 100, a silicon nitride layer 110 is deposited. First wafer 100 is single crystal silicon in a preferred embodiment. However, the wafer 100 can be made of, for example, quartz, glass, fused silica, or Pyrex ^™ . Next, a silicon oxide layer 120 is deposited on the silicon nitride layer 110 and the surface is etched to form a depression 130. On the resulting surface, a first polysilicon layer 140 is deposited. When the first polysilicon layer 140 is deposited in this manner, the recess 130 is filled with polysilicon. This filled recess 130
Will become smaller projections if the release step is subsequently performed. These small protrusions ultimately reduce the friction of the operation of the device. First polysilicon layer 140
Are lithographically patterned and etched using common methods well understood in the art to provide hinge plates 142 and 144, and slider 1
46 are formed.

In FIG. 2, on polysilicon 140,
Oxide layer 20 on exposed silicon oxide layer 120
0 is deposited. This oxide layer 200 is planarized in a preferred embodiment using chemical mechanical polishing (CMP). By performing the CMP, a structure substantially as shown in FIG. 2 is obtained.

FIG. 3 shows the wafer 100 after the via 300 has been etched. In a preferred embodiment, this etching is accomplished using reactive ion etching, but wet etching can be used as well. Etching can be stopped when via 300 reaches nitride layer 110 or when first polysilicon layer 140 is reached. Of course,
This is a problem with the limiting mask used.

Referring to FIG. 4, a second polysilicon layer 40 is formed.
0 is deposited on the wafer and the via 300 is filled.
Next, in a preferred embodiment, the second polysilicon layer 400 is chemically and mechanically polished to form a flat surface. In the preferred embodiment, the only remaining second polysilicon layer 400 is that found in via 300 as shown in FIG. An alternative embodiment leaves some polysilicon layer 400, which is due to the material purity,
Therefore, it is a compromise between the mechanical flatness and robustness of the MEMS mirror manufactured by the process steps described below.

In FIG. 5, single crystal silicon (SCS)
Is fused onto the silicon nitride layer, the silicon oxide layer, the first and second polysilicon layers 400, and thus to the processed wafer 100. The bonded wafer is etched back, much as in a BESOI (bonded and etched back silicon on insulator) wafer, and polished to a suitable device thickness and thinned (preferably by CMP). BESOI
Is a technique known in the art. For example, the Journal of the Elect of January 1991 referred to herein.
WPM from rochemical Society , Vol. 138, No. 1
aszara's dissertation “Silicon-On-Insulator by Wafer Bondin
g: A Review ". Due to this fusion of wafer 100 and wafer 500, in a preferred embodiment, a sandwich of SCS, polysilicon layer, silicon oxide layer, and SCS is formed as shown in FIG. However, the order, number, and type of intermediate layers sandwiched between the two SCS layers can be varied in other embodiments, all of which are within the scope of the present invention. Please understand that.

For example, in an alternative embodiment, the second wafer 500 can have various layers of silicon oxide and polysilicon on its surface, which is bonded to the wafer 100. The surface of the wafer 100 to which the second wafer 500 is bonded has its own layers, such as polysilicon and oxide or silicon nitride, as described above. Therefore, this is also a multilayer sandwich. Providing a few layers on one wafer and a few layers on a second wafer is inherently higher in flatness than being realized as an intermediate layer, and monocrystalline silicon is obtained as the top layer. The result is greater design flexibility. This greater flatness can further simplify the process performed.

[0013] When the second wafer 500 is bonded to the processed wafer 100, a custom wafer can be constructed with polysilicon and insulators buried under the top single crystal silicon layer. This achieves the desired result while allowing the positioning of the single crystal layer, but also allowing the formation of a surface micromechanical structure consisting of, for example, a micro hinge and a slider. Furthermore, integration of the CMOS process is more straightforward because the single crystal is on top.

Wafers 100 and 5 with an intermediate layer interposed
There are many methods in the art for combining two wafers, such as 00. A preferred approach is silicon fusion, also known as direct silicon bonding.
This type of linkage is known in the art.

In order to obtain single crystal silicon on an insulator,
Various approaches have been used. For example, BE
In SOI (bonded and etched back silicon on insulator), the two wafers are thermally bonded and etched to remove the backside, forming a silicon device layer of the desired thickness. Subsequent processing forms a CMOS layer on this polysilicon wafer,
Thereby, the polysilicon is buried. The present invention contemplates breaking this limitation and providing a polysilicon layer on top of the CMOS layer.

One problem is associated with the integration of MEMS and CMOS (circuit) processes that the present invention seeks to solve. The problem is that the CMOS process must be built on single crystal silicon, and that the CMOS process must not be contaminated from any MEMS processing. In the first approach, which first uses a standard surface micromachining process, the SCS surface is covered by polysilicon, so to build the CMOS layer, open a "window" at the end of the MEMS process and
It is necessary to reach CS. This also requires that the MEMS device is somehow well passivated. Alternatively, the CMOS layer can be built first, followed by MEMS processing. This is accomplished only if the MEMS process does not compromise CMOS performance, but is difficult to achieve given typical CMOS device thermal budget constraints.
Therefore, one must choose between "MEMS first" and "CMOS first", but both approaches have problems. The present invention provides single crystal silicon on top of all patterned MEMS device layers,
This is an example of covering the MS device layer. As a result, no additional passivation is required and additional polysilicon or metal C on top of it to complete the typical preferred embodiment MEMS device.
It is only necessary to perform a MOS step. Of course, one step is any CMO that follows
Compatible with S device processing. This ability to be taken over by CMOS device processing, thereby achieving the desired integration of electrical circuits and MEMS devices, is an important contribution of the present invention.

The first two wafers described above are combined with an additional single crystal wafer to form a multiple single crystal layer,
There is no reason why the design flexibility cannot be further improved. Such additional wafer bonding is clearly anticipated in the present invention. The multiple single crystal silicon layers can be patterned and have several other semiconductor layers (these layers are also patterned) between these SCS layers. The term “semiconductor layer” generally refers to a material typically used in semiconductor processing, including, for example, metals and conductors such as silicides, and insulators such as oxides and nitrides. This means that the material is not limited to a material having semiconductive properties. In fact, if processing is more difficult, it is possible to build a structure that is entirely made of stacked multi-patterned single crystal silicon wafers without any polysilicon. This potentially eliminates all of the material reliability issues associated with building various MEMS structures using polysilicon. Multiple single-crystal silicon layers are also desirable because they allow the circuit to be in close contact with where it is needed to support the circuit and avoid the problem of long wiring paths by vertical versus horizontal integration.

In FIG. 6, patterning of the single crystal silicon layer 500 into discrete shapes or sub-portions is performed. This is because the combined single crystal silicon layer 500
This is achieved by RIE etching the via 600 down. The oxide is then deposited and the field oxide 610 is grown. This step also fills via 600 with oxide.

Referring to FIG. 7, a third level polysilicon layer 700 is deposited and patterned. In an alternative embodiment, metal 700 can be provided instead. For either type of material, the patterned shape is as shown at 700 in FIG.

In FIG. 8, an oxide etch has been performed and the remaining oxide layers 120, 200 and 610 have been etched.
Is essentially eliminated. This releases the micromechanical device (shown in exemplary form), as shown in FIG. The stationary hinge 800 is made of polysilicon 400 and single crystal silicon 500. The pivot hinges 810 and 820 are connected to the first polysilicon 140, SCS50.
0 and third level polysilicon / lift-off metal 700. The head plate 830 is made of single crystal silicon 500 and may have a thin layer of a metal such as gold or platinum attached to its surface to enhance its reflection quality. Finally, the slider 840 is composed of the second polysilicon 400 and the single crystal silicon 500. It will be apparent to one skilled in the art that other arrangements are possible.

FIG. 9 is a perspective view of an example of the micromechanical device shown in cross section in FIG. In the figure, a stationary hinge 80 is shown.
0, pivot hinges 810 and 820, and end plate 83
0 is shown. In one preferred embodiment, a thin metal layer 900 is applied to enhance the reflective properties of the head 830.

Finally, FIG. 10 is a perspective view of an example of a micromechanical device, also shown in cross section in FIG. In the figure,
A pin 1000 made of second polysilicon 400 and single crystal silicon 500 is shown. Also, a slider 1001 made of the first polysilicon 140 is shown. An arrow 1002 indicates the traveling direction of the slider 1001. Of course, those familiar with the field of MEMS will appreciate that the staple hinges and sliders shown are only two examples of many other MEMS structures that can be implemented using the methods described above. . As described above, an example of a method for manufacturing an optical MEM mirror has been provided.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor wafer having a first level of polysilicon deposited thereon.

2 is a cross-sectional view of the semiconductor wafer of FIG. 1 after further processing to obtain an additional oxide layer.

FIG. 3 is a cross-sectional view after further processing has been performed on the semiconductor wafer shown in FIG. 2 to provide via openings.

FIG. 4 is a cross-sectional view of the semiconductor wafer shown in FIG. 3 after further processing to provide a second level polysilicon layer.

FIG. 5 shows a second semiconductor wafer bonded to the semiconductor wafer shown in FIG. 4;
FIG. 11 is a cross-sectional view after performing further processing to provide the wafer of FIG.

FIG. 6 is a cross-sectional view of the semiconductor wafer shown in FIG. 5 after a topographic etch has been performed and further processing has been performed to further deposit oxide.

FIG. 7 is a cross-sectional view of the semiconductor wafer shown in FIG. 6 after further processing to provide a third level polysilicon layer.

8 is a cross-sectional view of the semiconductor wafer shown in FIG. 7 after further processing to perform oxide release etching.

FIG. 9 is a perspective view of the device shown in cross section in FIG.

FIG. 10 is a schematic perspective view of the device shown in cross section in FIG.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 first layer 110 silicon nitride layer 120 silicon oxide layer 130 recess 140 first polysilicon layer 142, 144 hinge plate 146 slider 200 second oxide layer 300 via 400 second polysilicon layer 500 second wafer 600 Via 610 Field oxide 700 Third polysilicon layer (or metal layer) 800 Static hinge 810, 820 Pivot hinge 830 End plate 840 Slider 900 Metal layer 1000 Pin 1001 Slider 1002 Slider running direction

Claims (8)

[Claims] 1. A method of manufacturing a micro device, comprising: processing a first wafer having two faces;
Providing at least one patterned and planarized semiconductor layer on at least one of the two surfaces; bonding a second wafer of single crystal silicon to the semiconductor layer on the first wafer A method comprising the steps of: 2. The method of claim 1, further comprising the step of thinning said second wafer to obtain a suitable thickness. 3. The method of claim 2, wherein said thinning is accomplished using chemical mechanical polishing. 4. The method of claim 3, further comprising treating an exposed surface of the second wafer to provide at least one additional semiconductor layer. 5. A method of manufacturing a micro device, comprising: processing a first wafer having two surfaces and providing at least one first wafer patterned semiconductor layer on at least one of the two surfaces. Processing a second wafer of single crystal silicon having two surfaces and providing at least one second wafer patterned semiconductor layer on at least one of these two surfaces; Bonding a semiconductor surface of a second wafer onto a semiconductor layer of the first wafer; thinning the second wafer to a suitable device thickness; and patterning the thinned second wafer. And a step. 6. The method of claim 5, further comprising treating an exposed surface of the second wafer to provide at least one additional semiconductor layer. 7. The method of claim 6, further comprising performing an oxide liberation etch to liberate the MEM device. 8. A method of manufacturing a microdevice, comprising: processing a first wafer having two surfaces and providing at least one first wafer patterned semiconductor layer on at least one of the two surfaces. Treating a second wafer of single-crystal silicon having two faces and providing at least one second wafer-patterned semiconductor layer on at least one of these two faces; Bonding a semiconductor surface of a second wafer onto a semiconductor layer of the first wafer; thinning the second wafer to a suitable device thickness; and patterning the thinned second wafer. Bonding a third wafer of single crystal silicon to the patterned and thinned second wafer; Wherein the containing.