JP2002141798A - PLL circuit and semiconductor integrated circuit - Google Patents

Abstract

(57) Abstract: Provided is a technique for easily optimizing characteristics of a PLL circuit according to a system environment to which the PLL circuit is applied. SOLUTION: Phase comparing means (202) for comparing a phase of a reference clock signal with a phase of a feedback clock signal.
And a phase correction unit (203) for correcting the phase of the clock signal output from the oscillation unit in accordance with the result of the phase comparison.
And a feedback loop (22) for feeding back the clock signal output from the oscillating means to the phase comparing means.
And phase correction amount adjustment means (207, 208) for adjusting the amount of phase correction by the phase correction means in accordance with the ratio between the delay in the feedback loop and the phase comparison interval. The characteristics of the PLL circuit can be optimized by adjusting the amount of phase correction according to the ratio with the interval.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (Phase Lo
cked Loop (Phase Locked Loop)
For example, the present invention relates to a technology effective when applied to a semiconductor integrated circuit including a PLL macro cell.

[0002]

2. Description of the Related Art The speed of semiconductor integrated circuits has been increasing year by year, and microprocessors operating at several hundred MHz to 1 GHz have been announced one after another. In such a semiconductor integrated circuit, one clock cycle is as small as 1 ns to 2 ns, and therefore, it is required to reduce the jitter of the clock signal. Jitter is required to be 100 ps (picoseconds) or less. In order to reduce the jitter of the clock signal, in a semiconductor integrated circuit, P
An LL circuit is built in, and a clock signal whose phase is corrected by the PLL circuit is supplied to each logic circuit. PL
The L circuit has a function of generating an ultra-high-speed clock signal and matching the phase of an output clock signal with the phase of a reference clock supplied from outside the semiconductor integrated circuit. The PLL circuit includes an input terminal for a reference clock serving as a phase reference, an input terminal for a feedback clock whose phase is to be compared, and an output terminal for a clock generated based on the phase comparison result between the reference clock and the feedback clock. And The clock output via this output terminal is taken in as a feedback clock via a frequency divider, a clock buffer tree or the like. The speed of the reference clock signal is increased with the improvement of the input circuit performance, and may exceed 100 MHz. At this time, the phase comparison cycle is set to 10 ns (nanosecond) or less. On the other hand, the delay of the feedback loop is about several ns if the loop is built in the semiconductor integrated circuit. However, when a plurality of semiconductor integrated circuits are arranged on a component mounting board and it is desired to synchronize each semiconductor integrated circuit with a delay of a clock transmission line, an external transmission line is inserted in a feedback loop. Over 10 ns. In this case, the feedback delay may be longer than the phase comparison cycle.

[0003] An example of a literature describing a PLL is, for example, "How to Use a PLL-IC (page 9-)" issued by the Industrial Information Center Co., Ltd. in 1985.

[0004]

As described above, when a plurality of semiconductor integrated circuits are arranged on a component mounting board and it is desired to synchronize the respective semiconductor integrated circuits with a delay of a clock transmission line, an external circuit is required in a feedback loop. Due to the insertion of the transmission line, the delay there exceeds 10 ns. In this case, the feedback delay may be longer than the phase comparison cycle. Here, as shown in FIG. 3 (A), if the delay in the feedback loop is smaller than the phase comparison cycle, the frequency fluctuation of the oscillator due to the phase comparison is applied to the PLL circuit before the next phase comparison is performed. Since the feedback is performed, the next phase comparison is performed after the result of the previous phase comparison is reflected. That is, □
If the phase is behind the reference clock phase as shown by the mark, the phase is advanced according to the up (UP) signal output from the phase comparator of the PLL, and the phase is delayed from the reference clock phase as shown by the circle. If so, the phase is delayed according to the down (DN) signal output from the phase comparator of the PLL.

[0005] However, as shown in FIG.
If the delay in the feedback loop is larger than the phase comparison cycle, the next phase comparison is performed before the previous phase comparison result is fed back, resulting in excessive phase correction. This excessive phase correction causes an increase in jitter. Since the jitter increases as the delay in the feedback loop increases, it is necessary to reduce the amount of phase correction by changing the characteristics of the charge pump and the loop filter to reduce the jitter. For this purpose, for example, a large number of PLL macros whose characteristics have been changed for each delay in a feedback loop are released in advance, and a first method in which a user selects an appropriate one from among them, or a PLL macro using a control signal, is used. A second method is conceivable in which the characteristic of the above can be changed, and the control signal is set by the user according to the user environment. According to this, jitter can be reduced by reducing the amount of phase correction as shown in FIG. However, the first method and the second method require time and effort for selection and setting by the user, and such selection and setting depend on the system environment to which the PLL circuit is actually applied. It is not always done properly.

An object of the present invention is to provide a technique for easily optimizing characteristics of a PLL circuit according to a system environment to which the PLL circuit is applied.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, an oscillating means for forming a clock signal, a phase comparing means for comparing a phase of a reference clock signal with a phase of a feedback clock signal, and a phase of a clock signal outputted from the oscillating means are provided. A phase compensator for compensating according to a phase comparison result in the phase comparator, and a feedback loop for feeding back the clock signal generated by the oscillator to the phase comparator as the feedback clock signal. When the PLL circuit is constituted by the above, a phase correction amount adjusting means for adjusting the amount of phase correction by the phase correcting means according to the ratio between the delay in the feedback loop and the phase comparison interval by the phase comparing means. Is provided.

According to the above means, the phase correction amount adjusting means adjusts the phase correction amount by the phase correction means according to the ratio of the delay in the feedback loop to the phase comparison interval by the phase comparison means. I do. The jitter increases as the delay in the feedback loop increases. To reduce this jitter, it is necessary to change the characteristics of the charge pump and the loop filter to reduce the amount of phase correction. By adjusting the amount of phase correction by the phase correction means in accordance with the ratio of the delay in the feedback loop to the phase comparison interval in the phase comparator, the PLL circuit can be adjusted according to the system environment to which the PLL circuit is applied. Characteristics are optimized.

Also, an oscillating means for forming a clock signal, a phase comparing means for comparing a phase of a reference clock signal with a phase of a feedback clock signal, and a phase of a clock signal outputted from the oscillating means are provided. A phase compensator for compensating according to a phase comparison result in the phase comparator, and a feedback loop for feeding back the clock signal generated by the oscillator to the phase comparator as the feedback clock signal. When the PLL circuit is configured by the first circuit, a first circuit for generating a pulse signal having a width corresponding to the delay in the feedback loop, and the width of the pulse signal generated by the first circuit and the phase comparator And a control signal for adjusting the amount of phase correction by the phase correction means is formed in accordance with the ratio. 2 providing a circuit.

According to the above means, the first circuit generates a pulse signal having a width corresponding to a delay in the feedback loop, and the second circuit generates a pulse signal having a width corresponding to the width of the pulse signal generated by the first circuit. A ratio with a phase comparison period in the phase comparator is obtained, and a control signal for adjusting a phase correction amount in the phase correction means is formed in accordance with the ratio. The jitter increases as the delay in the feedback loop increases. To reduce this jitter, it is necessary to change the characteristics of the charge pump and the loop filter to reduce the amount of phase correction. By adjusting the amount of phase correction by the phase correction means in accordance with the ratio between the delay in the feedback loop and the phase comparison interval in the phase comparator, the PL
The characteristics of the PLL circuit are optimized according to the system environment to which the L circuit is applied.

Oscillating means for forming a clock signal, phase comparing means for comparing the phase of the reference clock signal with the phase of the feedback clock signal, and the phase of the clock signal output from the oscillating means is determined by the phase Phase correcting means for correcting according to the phase comparison result in the comparing means,
When the PLL circuit includes a feedback loop for feeding back the clock signal generated by the oscillating means to the phase comparator as the feedback clock signal, the clock signal generated by the oscillating means is fed back to the feedback circuit. A selector capable of selectively realizing a first state supplied to the loop and a second state transmitting a signal for determining a delay in the feedback loop to the feedback loop; and a selector in the feedback loop based on a reference clock signal. A first circuit for determining a start of a pulse signal having a width corresponding to a delay, and determining an end of the pulse signal based on a signal transmitted through the feedback loop in the second state;
A ratio between the width of the pulse signal obtained by the circuit and the phase comparison period of the phase comparator is obtained, and a control signal for adjusting the amount of phase correction by the phase correction means is formed in accordance with the ratio. Two circuits are provided.

According to the above means, the selector transmits to the feedback loop a first state in which the clock signal generated by the oscillating means is supplied to the feedback loop, and a signal for obtaining a delay in the feedback loop. The second state is selectively realized. Then, the first circuit determines the start of the pulse signal having a width corresponding to the delay in the feedback loop based on the reference clock signal, and based on the signal transmitted via the feedback loop in the second state. The end of the pulse signal is determined. The second circuit obtains a ratio between the width of the pulse signal obtained by the first circuit and the phase comparison period of the phase comparator, and adjusts the amount of phase correction by the phase correction means according to the ratio. Control signals for
The jitter increases as the delay in the feedback loop increases. To reduce this jitter, it is necessary to change the characteristics of the charge pump and the loop filter to reduce the amount of phase correction. By adjusting the amount of phase correction by the phase correction means in accordance with the ratio of the delay in the feedback loop to the phase comparison interval in the phase comparator, P is adjusted according to the system environment to which the PLL circuit is applied.
The characteristics of the LL circuit are optimized.

At this time, the phase correction means includes a charge pump for forming a voltage of a level corresponding to a result of comparison by the phase comparison means, and a filter capacitor charged and discharged by the charge pump. The charge pump may include a current adjusting circuit for adjusting a charge current amount and a discharge current amount of the filter capacitor according to a control signal formed by the second circuit.

Further, the PLL circuit having the above configuration and its P
A semiconductor integrated circuit can be configured to include a logic circuit operated in synchronization with a clock signal output from the LL circuit.

[0017]

FIG. 2 shows a board device on which a semiconductor integrated circuit (LSI) according to the present invention is mounted.

The board device 17 shown in FIG. 2 includes an oscillator 19 for generating a clock signal, and a plurality of LSIs 1 to 5 to which the generated clock signal is supplied, mounted on a substrate 18. Multiple LSI1 to LSI5
Are formed on one semiconductor substrate such as a single-crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique. The clock signal generated by the oscillator 19 is supplied to the corresponding LSI1 to LSI5 via transmission lines L1 to L5 formed on the substrate 18. LSI1 to L
SI5 includes a PLL macro cell 20 that generates a clock signal to be supplied to a logic circuit based on the clock signal transmitted from the oscillator 19, and a plurality of logic circuits that operate in synchronization with the clock signal output from the PLL macro cell 20. And a circuit. Here, the PLL macro cell 20 is an example of the PLL circuit in the present invention.

Since the LSIs 1 to 5 have the same configuration as far as the PLL macro cell and its periphery are concerned, only the LSI 1 will be described in detail in the following description.

Although the LSI 1 is not particularly limited, the LSI 1
C (Application Specific I)
C). The LSI 1 is provided with a clock input terminal T11 for receiving a clock signal generated by the oscillator 19, and the clock signal input via the clock input terminal T11 is transmitted to the PLL circuit. . A plurality of clock buffer trees 21 are formed for transmitting a clock signal inside the LSI. The clock signal output from the PLL macro cell 20 is supplied to a logic circuit inside the LSI via a frequency divider (not shown) or the clock buffer tree 21. The clock buffer tree 21 has a clock transmission path formed in a tree shape, and the delay amounts from the PLL macro cell 20 to the clock input terminals of a plurality of logic circuits such as flip-flop circuits (FF) are equalized. Part of the plurality of clock buffer trees 21 is P
It functions as an LL feedback loop 22. LS
I1 includes a feedback loop forming terminal T12 connected to the PLL macro cell 20 and a feedback loop forming terminal T13 connected to a part of the clock buffer tree 21 functioning as the feedback loop 22.
Is provided. This feedback loop forming terminal T
A transmission line L10 is connected between 12 and 13. This transmission line L10 has the same signal delay amount as the transmission line L1 for transmitting the clock signal generated by the oscillator 19 to the LSI1. By including such a transmission line L10 in the feedback loop 22, the clock phase of a logic circuit such as a flip-flop circuit inside the LSI 1 matches the clock phase of the oscillator 19 on the substrate 28.

FIG. 1 shows a configuration example of the PLL macro cell 20.

The PLL macro cell 20 shown in FIG.
Although not particularly limited, the input divider 201 and the phase comparator 2
02, a charge pump and loop filter 203, an oscillator 204, an output frequency divider 205, a selector 206, a pulse width determination circuit 207, and a pulse generation circuit 208.

The input frequency divider 201 divides the frequency of the clock signal input via the feedback loop forming terminal T12 shown in FIG. The frequency-divided output of the input frequency divider 208 is used as a feedback clock signal in the subsequent phase comparator 20.
2 is transmitted. The phase comparator 202 performs a phase comparison between the reference clock signal and the feedback clock signal input via the clock input terminal T11 in FIG. The phase comparison result of the phase comparator 202 is used as an up signal UPB and a down signal DN. In the phase comparison by the phase comparator 202, if the phase of the feedback clock signal is delayed as compared with the phase of the reference clock signal, the up signal UPB is asserted, and conversely, the up signal UPB is compared with the phase of the reference clock signal. When the phase of the feedback clock signal is advanced, the down signal DN is asserted. Such an up signal UPB and a down signal DN are transmitted to the subsequent charge pump and loop filter 203. The charge pump and loop filter 203 forms a voltage having a level according to the phase comparison result of the phase comparator 202. This voltage is transmitted to the oscillator 204 at the subsequent stage. The oscillator 20 outputs a clock signal by an oscillating operation. This oscillator 204
Is controlled by the voltage level output from the charge pump and loop filter 203. The clock signal output from the oscillator 20 is frequency-divided by the output frequency divider 205 at the subsequent stage.

The pulse generation circuit 208 generates a pulse signal having a width equal to the delay in the feedback loop 22. The pulse signal generated by the pulse generation circuit 208 and the output signal of the output frequency divider 205 are selected by the selector 206 and output to the outside of the PLL macro cell 20 via the output terminal. PLL macrocell 20
A frequency divider 300 is coupled to the output terminal of the PLL macrocell 20 so that the output signal of the PLL macro cell 20 is frequency-divided by the frequency divider 300. The divided output is supplied to the clock buffer tree 21. Here, the pulse generation circuit 208 is an example of a first circuit in the present invention.

The pulse width determination circuit 207 calculates the ratio of the pulse width output from the pulse generation circuit 208 to the phase comparison period, and generates a control signal for controlling the characteristics of the charge pump and the loop filter 203. This control signal has a 16-bit configuration. Here, the pulse width determination circuit 207 is an example of a second circuit in the present invention.

A PLL enable signal for enabling the PLL macro cell 20 is output from the PLL macro cell 2
0 is input from outside. This PLL
When the enable signal is asserted high,
The charge pump and loop filter 203, oscillator 204, pulse width determination circuit 207, and pulse generation circuit 208 are activated.

FIG. 9 shows the operation timing of the phase comparator 202.

As shown in FIG. 9A, when the phase of the feedback clock signal lags behind that of the reference clock signal, the up signal UPB is asserted low to advance the phase of the feedback clock signal. Is done. FIG.
As shown in (B), when the phase of the feedback clock signal is ahead of the phase of the reference clock signal, the down signal DN is asserted to a high level so as to delay the phase of the feedback clock signal.

When the feedback clock (the feedback clock of the PLL output clock) is behind the reference clock, the UPB outputs an L-side pulse having the same width as the phase difference to charge the loop filter. . When the phase of the feedback clock is ahead of the phase of the reference clock, the DN outputs a high-level pulse having the same width as the phase difference to discharge the charge from the loop filter.

FIG. 4 shows a configuration example of the pulse generation circuit 208.

The pulse generation circuit 208 shown in FIG.
Although not particularly limited, the inverter INV1 and the gate G
1, G2, and flip-flop circuits FF1 to FF4.

Flip-flop circuits FF1, FF2, F
F3 and FF4 each have a data input terminal D, a clock input terminal, a reset terminal R, a non-inverted output terminal Q, and an inverted output terminal Q * (* means signal inversion).
In the flip-flop circuit FF1, the data input terminal D is supplied with a high level from the high-potential-side power supply Vdd, the clock input terminal is supplied with a reference clock signal, and the non-inverted output terminal Q is connected to the gate G1. The reset terminal R of the flip-flop circuit FF1 has a PL
The L enable signal is input via the inverter INV1.

In the flip-flop circuit FF2, the data input terminal D is connected to the flip-flop circuit FF1.
The output signal of the non-inverting output terminal Q is transmitted via the gate G1. A reference clock signal is input to a clock input terminal of the flip-flop circuit FF2. The output signal of the non-inverting output terminal Q of the flip-flop circuit FF2 is transmitted to the reset terminal R of the flip-flop circuit FF2.

In the flip-flop circuit FF3, an output signal from the non-inverting output terminal Q of the flip-flop circuit FF1 is transmitted to the data input terminal D. The signal output through the selector 206 is fed back to the clock input terminal via the frequency divider 300 and the clock buffer tree 21. The input node for this feedback is denoted by n1. The PLL enable signal is input to the reset terminal R of the flip-flop circuit FF3 via the inverter INV1. The selection operation of the selector 206 is controlled by a signal output from the non-inverting output terminal Q of the flip-flop circuit FF3.

In the flip-flop circuit FF4, the output signal of the inverted output terminal Q * is transmitted to the data input terminal D. An output signal from the non-inverting output terminal Q of the flip-flop circuit FF2 and a signal fed back via the frequency divider 300 and the clock buffer tree 21 are transmitted to the clock input terminal via the gate G2. . Non-inverting output terminal Q of flip-flop circuit FF4
Is transmitted to the pulse width determination circuit 207 at the subsequent stage.

FIG. 5 shows the operation timing of the main part of the pulse generation circuit 208.

First, when the PLL enable signal is asserted to a high level, the flip-flop circuits FF1 and F
The reset state of F3 is released, and the data input terminal D of the flip-flop circuit FF2 is set to the high level. PL
When the reference clock signal first rises to the high level after the L enable signal is asserted to the high level, the outputs (FF1_Q and FF2_Q) of the flip-flop circuits FF1 and FF2 go to the high level. Since the non-inverted output terminal Q of the flip-flop circuit FF2 is connected to its own reset terminal R, the logic of the non-inverted output terminal Q of the flip-flop circuit FF2 immediately falls to a low level. When the non-inverted output signal of the flip-flop circuit FF3 is at a low level, the selector 206 selectively outputs the output signal of the flip-flop circuit FF2 to the PLL.
It outputs to the outside of the macro cell 20. In this state, a waveform delayed from the non-inverting output terminal Q of the flip-flop circuit FF2 by the delay in the feedback loop 22 including the frequency divider 300 and the clock buffer tree 21 appears at the node n1. The OR logic of the output signal from the non-inverting output terminal D of the flip-flop circuit FF2 and the signal at the node n1 is obtained by the gate G2. By obtaining the OR logic at the gate G2, two pulse signals having a predetermined time difference can be obtained. The time difference between the two pulse signals is determined by the feedback loop including the frequency divider 300 and the clock buffer tree 21. 22
Shows the delay at.

The output (FF) of the flip-flop circuit FF3
3_Q) is initially set to the low level. Thereby, the flip-flop circuit FF4 is enabled, and the output signal of the flip-flop circuit FF2 is selectively transmitted to the feedback loop 22 by the selector 206. However, when a time corresponding to the delay in the feedback loop 22 elapses, the node n1 becomes high level, and the output (FF3_Q) of the flip-flop circuit FF3 becomes high level, so that the flip-flop circuit FF4 is reset. Then, the output signal of the output frequency divider 205 is selectively output by the selector 206, so that the normal operation of the PLL macro cell 20 is started. The output of the flip-flop circuit FF4 (FF4_
Q) becomes high level with the first pulse signal of the OR output from the gate G2, and becomes low level with the second pulse signal. Therefore, the width of the pulse signal output from the flip-flop circuit FF4 is equal to the delay in the feedback loop 22 including the frequency divider 300 and the clock buffer tree 21. The flip-flop circuit FF4 is
After outputting the pulse signal, the flip-flop circuit FF4 does not output anything because the reset is applied by the FF3_Q. Since the selector selects the output frequency divider, the PLL performs a normal pull-in operation.

That is, immediately after the PLL enable signal is asserted to the high level, the output signal of the flip-flop circuit FF2 is selectively supplied to the feedback loop 22 by the selector 206, which corresponds to the delay in the feedback loop 22. After a pulse signal having a width which is determined by the following formula is obtained and the output signal of the output frequency divider 205 is selected by the selector 206 after the pulse signal is obtained, the normal operation of the PLL macro cell 20 is started.

When the PLL enable signal is asserted to a low level, the flip-flop circuits FF1 and FF3 are returned to the initial state by reset.

FIG. 6 shows a configuration example of the pulse width determination circuit 207.

The pulse width determination circuit 207 shown in FIG.
Includes, but not limited to, an inverter INV2, a delay circuit 61, a flip-flop circuit FF9, an AND gate G3, a counter 300, and a decoder 400.

The delay circuit 61 is provided to delay the reference clock signal. A flip-flop circuit is applied to the delay circuit 61. This delay circuit 6
The output signal of 1 is transmitted to a subsequent AND gate G3.
The AND gate G3 obtains AND logic between the output signal from the non-inverting output terminal Q of the delay circuit 61 and the output signal from the pulse generation circuit 208. The output signal of AND gate G3 is transmitted to counter 300 at the subsequent stage. A flip-flop circuit can be applied to the delay circuit 61. In that case, a reference clock signal is input to the clock input terminal, and a delayed signal is obtained from the non-inverted output terminal Q. The flip-flop circuit FF9 has a data input terminal D, a clock input terminal, a reset terminal R, a non-inverted output terminal Q, and an inverted output terminal Q *. The data input terminal D of the flip-flop circuit FF9 is connected to the high-potential-side power supply Vdd.
Is combined with A reference clock signal is input to a clock input terminal of the flip-flop circuit FF9. The output terminal of the inverted output terminal Q * of the flip-flop circuit FF9 is
Node nA, which is coupled to reset terminal R of delay circuit 61. The PLL enable signal is inverted by the inverter INV2 and transmitted to the reset terminal R of the flip-flop circuit FF9 and the counter 300.

The counter 300 is provided by the AND gate G3.
, And the count state is cleared by the output signal of the inverter INV2. Although not particularly limited, such a counter 300 includes four flip-flop circuits FF5 to FF8. Each of the four flip-flop circuits FF5 to FF8 has a data input terminal D, a clock input terminal, a reset terminal R, a non-inverted output terminal Q, and an inverted output terminal Q *. The output signal from the inverted output terminal Q * in each of the flip-flop circuits FF5 to FF8 is transmitted to its own data input terminal D. The output signal of the AND gate G3 is input to the clock input terminal of the flip-flop circuit FF5. The output signal of the non-inverting output terminal Q of the flip-flop circuit FF5 is transmitted to the clock input terminal of the flip-flop circuit FF6, and the output signal of the non-inverting output terminal Q of the flip-flop circuit FF6 is transmitted to the clock input terminal of the flip-flop circuit FF7. And the output signal of the non-inverting output terminal Q of the flip-flop circuit FF7 is transmitted to the clock input terminal of the flip-flop circuit FF8. Output nodes nC, nD, nE, and nF of the counter 300 are extracted from the non-inverting output terminals Q of the flip-flop circuits FF5 to FF8. The output signal of counter 300 is decoded by decoder 400 at the subsequent stage.

FIG. 7 shows the operation timing of the main part of the pulse width determination circuit 207.

In the initial state, the counter output node n
C, nD, nE, and nF are all at the low level, and only the output OUT0 of the decoder 400 is at the low level.

First, the PLL enable is asserted to a high level to activate the PLL. Thus, the reset state of the flip-flop circuit FF9 is released.
The reset state of the counter is released by releasing the reset state of FF5 to FF8 in the counter 300.

In the initial state, since the flip-flop circuit FF1 is reset and the node nA is at the high level, the delay circuit 61 is in the reset state. Therefore, at this time, even if the reference clock signal is input to the delay circuit 61, the first one clock is ignored. However, after the input of the reference clock, the output logic of the flip-flop circuit FF1 is inverted, the node nA becomes low level, and the reset of the delay circuit 61 is released. The signal output from is valid.

In the AND gate G 3, AND logic of the output signal of the pulse generation circuit 208 and the output signal of the delay circuit 61 is obtained, and the result is input to the counter 300. When the pulse width of the pulse generation circuit 208 is smaller than the phase comparison period (which is equal to the reference clock period), the counter 300 does not count up because the node nB remains at the low level.

In this example, since the pulse width is between twice and three times the phase comparison period, the rise edge is 2 at the node nB.
After appearing twice and counting twice in the counter 300, the nodes nC, nE, and nF go low,
D goes high, and only OUT2 at the output of the decoder 400 goes high.

When the PLL enable signal is negated to the low level, the flip-flop circuit FF9 and the counter 300 are reset, and they are returned to the initial state.

FIG. 8 shows a configuration example of the charge pump and loop filter 203.

Charge pump and loop filter 203
Includes a charge pump 203A and a loop filter 203B disposed downstream of the charge pump 203A.

Although not particularly limited, the loop filter 203B includes a filter resistor Rf and a filter capacitor Cf connected in series. The other end of the filter resistor Rf is coupled to the output terminal of the charge pump 203A,
The other end of f is coupled to the lower potential power supply Vss.

The charge pump 203A includes a charge pump section 81 for charging and discharging the filter capacitance Cf via the filter resistor Rf.
And a current adjusting circuit 80 capable of adjusting the amount of current for charging and discharging the filter capacitor Cf according to a control signal from the pulse width determination circuit 207. In the charge pump 203A, the phase correction of the clock signal is performed, and by adjusting the charge current amount and the discharge current amount of the filter capacitance, the correction amount in the phase correction by the charge pump 203A can be adjusted.

The charge pump unit 81 is not particularly limited, but may be a p-channel type MOS transistor MP1, MP
2, MP3 and n-channel MOS transistor MN
3, MN4 and MN5. p-channel type M
The OS transistor MP1 and the n-channel MOS transistor MN3 are connected in series. p-channel type MO
The source electrode of the S transistor MP1 is a high-potential-side power supply Vd
d and an n-channel MOS transistor MN
The third source electrode is coupled to the lower potential side power supply Vss. p
The channel type MOS transistor MP2 is current mirror-coupled to the p-channel type MOS transistor MP1. p-channel type MOS transistors MP2 and MP
3, and n-channel MOS transistors MN5, MN
N4 is connected in series. The source electrode of the p-channel MOS transistor MP2 is coupled to the high potential power supply Vdd, and the source electrode of the n-channel MOS transistor MN4 is coupled to the low potential power supply Vss. The up signal UPB from the phase comparator 202 is transmitted to the gate electrode of the p-channel MOS transistor MP3, and the down signal DN from the phase comparator 202 is transmitted to the gate electrode of the n-channel MOS transistor MN5. Accordingly, when the phase of the feedback clock signal is delayed as compared with the reference clock signal, the p-channel MOS transistor MP3 is turned on by the up signal UPB, so that the charge is charged in the filter capacitor Cf, and the charge is charged as compared with the reference clock signal. When the phase of the feedback clock signal is advanced, an n-channel MOS
When the transistor MN5 is turned on, the charge of the filter capacitor C is discharged. p-channel type M
An output terminal of the charge pump 203A is drawn from a series connection node of the OS transistor MP3 and the n-channel MOS transistor MN5, and is connected to the loop filter 203B and the oscillator 204.

Although the current adjusting circuit 80 is not particularly limited, the p-channel MOS transistors MPA, MPA
0 to MPA15, MPB0 to MPB15, and n-channel MOS transistors MN1 and MN2. A p-channel MOS transistor MPA and an n-channel MOS transistor MN1 are connected in series. The source electrode of the p-channel MOS transistor MPA is coupled to the high potential power supply Vdd. The source electrode of the n-channel MOS transistor MN1 is coupled to the lower potential side power supply Vss. The gate electrode of the n-channel MOS transistor MN1 is coupled to the high potential side power supply Vdd. p-channel type MOS transistors MPA0-M
PA15 is the p-channel type MOS transistor M
The current mirror is coupled to the PA. p-channel type MO
Source electrodes of the S transistors MPA0 to MPA15 are coupled to the high-potential-side power supply Vdd. Further, the p-channel MOS transistors MPA0 to MPA15 correspond to the corresponding p-channel MOS transistors MPB0 to MPB0, respectively.
It is connected to the MPB 15 in series. The control signal OU generated by the pulse width determination circuit 207 is provided to the gate electrodes of the p-channel type MOS transistors MPB0 to MPB15.
T0 to OUT15 (output signals of the decoder 400) are transmitted. The n-channel MOS transistor MN2 has p
It is connected in series to the channel type MOS transistor MPB15. The source electrode of the n-channel MOS transistor MN2 is coupled to the lower potential power supply Vss. The n-channel MOS transistor MN3 in the charge pump unit 81 is current mirror-coupled to the n-channel MOS transistor MN2.

P-channel type MOS transistor MPA
The current that flows through is denoted by Icp0,
When the gate width of the transistor MPA is denoted by Wmpa and the gate width of the p-channel MOS transistors MPA0 to MPA15 is denoted by Wmpan, the n-channel MO
The current Icp flowing through the S transistor MN2 is Icp =
Indicated by Icp0 × Wmpan / Wmpa. Here, n-channel MOS transistors MN2 and MN
3 have the same gate width and the p-channel MOS transistors MP1 and MP2 have the same gate width, the charge pump current for charging and discharging the filter capacitance Cf is the current flowing through the n-channel MOS transistor MN2. It becomes equal to Icp.

FIG. 10 shows the ratio between the phase comparison period and the feedback delay Tdfb, and the output n of the counter 300.
C, nD, nE, nF and the output OUT of the decoder 400
The relationship between n and the charge pump current Icp is shown.

Phase comparison cycle and feedback delay T
A value corresponding to the ratio with respect to dfb is output from the counter 300, which is decoded by the subsequent decoder 400, and the charge pump current Icp is determined according to the decoding result. In this manner, the charge and discharge current (Icp) in the charge pump 203A is determined by the ratio of the phase comparison period and the delay in the feedback loop, and thus the p-channel MOS transistors MPA and MPA
The phase correction amount of the charge pump can be adjusted by the gate width of 0 to 15. The amount of phase correction per phase comparison is proportional to the charge current or discharge current of the charge pump 203A. Since the phase correction amount needs to be reduced as the delay in the feedback loop increases, the gate width of the p-channel MOS transistor MPA0 is maximized, and the MP1 to MP15
Are set so that the gate width becomes smaller in this order. That is, the p-channel MOS transistors MPA0 to MPA
When the gate width of A15 is represented by Wmpa0 to Wmpa15, the gate widths of the p-channel MOS transistors MPA0 to MPA15 are set so that the relationship represented by the following inequality holds.

[0061]

## EQU1 ## Wmpa0>Wmpa1>Wmpa2> Wmp
a3 >> ... Wmpa15

According to the above example, the following functions and effects can be obtained.

Immediately after the PLL enable signal is asserted to a high level, the output signal of the flip-flop circuit FF2 is selectively supplied to the feedback loop 22 by the selector 206, so that the width corresponding to the delay in the feedback loop 22 is obtained. Is obtained, and after this pulse signal is obtained, the selector 2
When the output signal of the output frequency divider 205 is selected by 06, the normal operation of the PLL macro cell 20 is started. On the other hand, the phase comparison period and the feedback delay T
A value corresponding to the ratio with respect to dfb is output from the counter 300, which is decoded by the subsequent decoder 400, and the charge pump current Icp is determined according to the decoding result. In this manner, the charge and discharge current (Icp) in the charge pump 203A is determined by the ratio of the phase comparison period and the delay in the feedback loop, and thus the p-channel MOS transistors MPA and MPA
The phase correction amount of the charge pump can be adjusted by the gate width of 0 to 15. Thus, each time the PLL enable signal is asserted to a high level, a pulse signal having a width corresponding to the delay in the feedback loop 22 is actually obtained, and the phase correction amount of the charge pump is adjusted based on the pulse signal. So that P
The PLL according to the system environment to which the LL circuit is applied.
The characteristics of the circuit can be easily optimized.

Next, another configuration example will be described.

In the above example, the case where the phase correction amount in the charge pump 203A is bit-controlled by the multiple output control line has been described. However, the phase correction amount in the charge pump 203A can be controlled in an analog manner. FIG.
7 shows a configuration example of the pulse width determination circuit 207 in that case.

In FIG. 11, components having the same functions as those shown in FIG.
A detailed description thereof will be omitted.

A flip-flop circuit FF21 is provided, and an output signal of the AND gate G3 is transmitted to a clock input terminal of the flip-flop circuit FF21. The data input terminal D of the flip-flop circuit FF21 is coupled to the high potential side power supply Vdd. An output signal from the non-inverting output terminal Q of the flip-flop circuit FF21 is transmitted to the reset terminal R via the buffer 101.

Further, a flip-flop circuit FF22 is provided, and a PLL input signal is transmitted to a clock input terminal of the flip-flop circuit FF22. The data input terminal D of the flip-flop circuit FF22 is coupled to the high potential side power supply Vdd. An output signal from the non-inverting output terminal Q of the flip-flop circuit FF21 is transmitted to the reset terminal R via the buffer 101.

P-channel type MOS transistor MP2
4, MP23 and n-channel MOS transistors MN23 and MN24 are connected in series. The source electrode of the p-channel MOS transistor MP24 is coupled to the high potential power supply Vdd, and the source electrode of the n-channel MOS transistor MN24 is coupled to the low potential power supply Vss. p-channel MOS transistors MP22 and n
The channel type MOS transistor MN22 is connected in series. The source electrode of the p-channel MOS transistor MP22 is coupled to the high potential power supply Vdd, and the source electrode of the n-channel MOS transistor MN22 is coupled to the low potential power supply Vss. The gate electrodes of the p-channel MOS transistors MP22 and MP24 are coupled to the lower potential side power supply Vss. The n-channel MOS transistor MN24 is an n-channel MOS transistor M
It is mirror-coupled to N22. The output signal from the inverted output terminal Q * of the flip-flop circuit FF22 is transmitted to the gate electrode of the p-channel MOS transistor MP23, and the non-inverted output terminal of the flip-flop circuit FF21 is connected to the gate electrode of the n-channel MOS transistor MN23. The output signal from Q is transmitted. Further, a p-channel type MOS transistor MP23 and an n-channel type
A capacitor C1 is coupled to a series connection node with the OS transistor MN23. The other end of the capacitor C1 is connected to the low potential side power supply Vs
s. The p-channel type M is output by the output signal from the inverted output terminal Q * of the flip-flop circuit FF22.
The capacitor C1 is charged by the current I1 flowing when the OS transistor Q23 is turned on, and the current I2 flows when the n-channel MOS transistor MN23 is turned on by the output signal from the non-inverting output terminal Q of the flip-flop circuit FF21. The capacitance C1 is discharged. The terminal voltage of the capacitor C1 is transmitted as an output signal of the pulse width determination circuit 207 to the charge pump unit 81 shown in FIG.

FIG. 12 shows the operation timing of the main part in pulse width determination circuit 207 shown in FIG.

In the initial state, the PLL enable signal is at the low level, and the delay circuit 61 and the flip-flop circuit F
F9 is in a reset state, and the output voltage is 0V. P
When the LL enable signal is asserted high,
The reset of the flip-flop circuit FF9 is released.
Further, the output (FF22_Q *) from the inverted output terminal of the flip-flop circuit FF22 outputs a low-side pulse signal, and the p-channel MOS transistor MP23
Is turned on, and the capacitor C is charged with electric charge, the output potential increases. At this time, the charge current I1, the output pulse width of the flip-flop circuit FF22,
The value of the capacitor C is set so that a desired initial voltage Vini is obtained.

When the reference clock is first input after the PLL enable signal is asserted to the high level, the delay circuit 61 does not output anything because it is still in the reset state. At this time, the flip-flop circuit FF9
Since the reset has been released, the node nA goes low, and the reset of the flip-flop circuit FF9 is released. Therefore, the output of the delay circuit 61 becomes possible from the input of the next reference clock signal. Since the output signal from the pulse generation circuit 208 is a flip-flop output, the output signal is in phase with the output of the delay circuit 61. Therefore, output node nB of AND gate G3 for obtaining these AND logics
Remains at the low level when the output pulse width of the pulse generation circuit 208 is smaller than the phase comparison period. In this example, since the output pulse width of the pulse generation circuit 208 is between twice and three times the phase comparison period, two pulses are output from the output node nB of the AND gate G3. The flip-flop circuit FF21 shapes the pulse signal at the node nB to output a signal having a constant pulse width. Output FF of flip-flop circuit FF2
While 2_Q is at the high level, the n-channel MOS transistor MN23 is turned on to discharge the electric charge from the capacitor C, so that the output voltage is reduced. At this time, the inverted output signal FF21 from the flip-flop circuit FF21
The discharge current I2, the width of the output pulse from the flip-flop circuit FF21, and the value of the capacitor C1 are set so that the voltage Vstep which decreases by one pulse of _Q becomes a desired value.

The output voltage Vout in this example is obtained by outputting two pulses from the flip-flop circuit FF21.
“Vini−Vstep × 2”. When the PLL enable signal is asserted to a high level, the delay circuit 61 and the flip-flop circuit FF9 are reset, and the n-channel MOS transistor MN5 is turned on to discharge all the charge of the capacitor C.
The output voltage becomes 0 V, and the pulse width determination circuit 207 returns to the initial state.

FIG. 13 shows a configuration example of the charge pump 203A in which the phase correction amount adjustment is adjusted based on the output signal of the pulse width determination circuit 207 shown in FIG.

In FIG. 13, components having the same functions as those of the circuit shown in FIG. 8 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The charge pump 203A includes a charge pump section 81 and a current adjusting circuit 80.

The charge pump section 81 includes p-channel MOS transistors MP2, MP3, MP32, and n
Channel type MOS transistors MN4, MN5, MN
33. p-channel MOS transistor MP32 and n-channel MOS transistor MN33
Are connected in series. The source electrode of the p-channel MOS transistor MP32 is coupled to the high potential power supply Vdd, and the source electrode of the n-channel MOS transistor MN33 is coupled to the low potential power supply Vss. The n-channel MOS transistor MN4 is an n-channel MOS transistor MN4.
The current mirror is coupled to the S transistor MN33.
p-channel type MOS transistors MP32 and MP2
Is current mirror-coupled to the p-channel MOS transistor MP31 in the current adjustment circuit 80.

The current adjusting circuit 80 is a p-channel type MO
It comprises an S transistor MP31 and n-channel MOS transistors MN31 and MN32. p-channel type MOS transistor MP31 and n-channel type MO
S transistor MN32 is connected in series. The source electrode of the p-channel MOS transistor MP31 is coupled to the high potential power supply Vdd, and the source electrode of the n-channel MOS transistor MN32 is coupled to the low potential power supply Vss. p-channel type MOS transistor MP3
2 is current mirror-coupled to a p-channel type MOS transistor MP31. Further, n-channel MOS transistors MN31 and MN32 are connected in parallel. The gate electrode of the n-channel MOS transistor MN31 is coupled to the high-potential-side power supply Vdd,
The output signal of pulse determination circuit 207 shown in FIG. 11 is transmitted to the gate electrode of transistor MN32. p
Channel type MOS transistors MP31, MP32,
By setting the gate widths of MP2 to be equal to each other and the gate widths of n-channel MOS transistors MN33 and MN4 to be equal to each other, the charge and discharge current Icp becomes the sum of the current Icp0 and the current Icp1. The n-channel MOS transistor MN31 is
The gate electrode is always turned on by being coupled to the high potential side power supply Vdd, and the current Icp0 flowing therethrough is constant. The n-channel MOS transistor MN31 is provided to prevent the current Icp from becoming 0. Since the gate of the n-channel MOS transistor MN32 is connected to the output terminal of the pulse width determination circuit 207, the output potential of the pulse width determination circuit 207 decreases as the delay in the feedback loop increases. For this reason,
The current Icp1 flowing through the n-channel MOS transistor MN32 becomes smaller. Therefore, the charge pump current I
Since cp also decreases, the amount of phase correction also decreases.

FIG. 14 shows an operation example when the circuits shown in FIGS. 11 and 13 are employed.

As shown in FIG. 14, the phase comparison period T
The output voltage Vout of the pulse determination circuit 207 is controlled according to the ratio of the delay time Tdfd to the feedback loop, and the charge pump current Icp is adjusted according to the output voltage Vout. The voltages Vini and Vstep are set so that the output voltage Vout of the pulse width determination circuit 207 does not become negative.

As described above, even when the charge pump 203A is controlled in an analog manner, the charge pump unit is controlled in accordance with the ratio between the delay in the feedback loop and the phase comparison interval in the phase comparator as in the above-described example. By adjusting the amount of phase correction 81, the PL is adjusted according to the user environment.
The characteristics of the L macro cell 20 can be optimized. Further, in the case where the configuration shown in FIGS. 11 and 13 is employed, the number of elements and the number of wirings can be reduced as compared with the case where the configuration shown in FIGS. 6 and 8 is employed. , The area occupied by the chip of the PLL macro cell can be reduced.

Although the invention made by the inventor has been specifically described above, the present invention is not limited to this, and it goes without saying that various modifications can be made without departing from the gist of the invention.

For example, in the above example, it was assumed that the delay in the feedback loop did not exceed 16 times the phase comparison period. However, the multiple is not limited and optimum characteristics can be obtained under the delay conditions in each feedback loop. As described above, constant setting of each element can be performed.

The pulse generation circuit 208 only needs to output a pulse having a width equal to the delay in the feedback loop, and may have a circuit configuration other than that of this embodiment. Also, the pulse width determination circuit 207 need only be able to recognize the ratio between the pulse width and the phase comparison period, and may have another circuit configuration. In addition, each functional block can be configured by applying a MOS transistor having a different conductivity type from the above example.

In the above example, the case where the charge pump characteristics are controlled by the pulse width determination circuit 207 has been described.
Depending on the configuration of L, a circuit such as a voltage-current conversion circuit may be additionally provided. In such a case, a plurality of circuit characteristics including a charge pump may be controlled by the pulse width determination circuit 207. .

In the above description, the invention made mainly by the present inventor is described in terms of the application field of
Although the description has been given of the case where the present invention is applied to C, the present invention is not limited thereto, and can be widely applied to various semiconductor integrated circuits.

The present invention can be applied on condition that at least a clock signal is handled.

[0088]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the amount of phase correction by the phase correction means is adjusted by the phase correction amount adjustment means in accordance with the ratio of the delay in the feedback loop to the phase comparison interval in the phase comparison means, thereby enabling the PLL circuit to operate. The characteristics of the PLL circuit can be easily optimized according to the applied system environment.

Further, the first circuit generates a pulse signal having a width corresponding to the delay in the feedback loop, and the second circuit generates a pulse signal having a width corresponding to the delay in the feedback circuit. A ratio with the comparison cycle is obtained, and a control signal for adjusting the amount of phase correction by the phase correction means is formed in accordance with the ratio. Characteristics can be easily optimized.

Further, the first circuit determines the start and end of the pulse signal having the width corresponding to the delay in the feedback loop based on the reference clock signal, and the second circuit determines the pulse obtained by the first circuit. The ratio between the signal width and the phase comparison period in the phase comparator is obtained, and a control signal for adjusting the amount of phase correction by the phase correction means is formed in accordance with the ratio. The characteristics of the PLL circuit can be easily optimized according to the applied system environment.

[Brief description of the drawings]

FIG. 1 shows a PL included in a semiconductor integrated circuit according to the present invention.
FIG. 3 is a block diagram illustrating a configuration example of an L macro cell.

FIG. 2 is a block diagram showing a configuration example of a board device on which the semiconductor integrated circuit is mounted.

FIG. 3 is an explanatory diagram showing a relationship between a feedback delay and a PLL phase variation.

FIG. 4 is a circuit diagram illustrating a configuration example of a pulse generation circuit included in the PLL macro cell.

FIG. 5 is an operation timing chart of a main part in a pulse generation circuit included in the PLL macro cell.

FIG. 6 is a circuit diagram illustrating a configuration example of a pulse width determination circuit included in the PLL macro cell.

FIG. 7 is an operation timing chart of a main part in the pulse width determination circuit.

FIG. 8 is a circuit diagram illustrating a configuration example of a charge pump and a loop filter included in the PLL macro cell.

FIG. 9 is an operation timing chart of a phase comparator included in the PLL macro cell.

FIG. 10 is an explanatory diagram of an operation of a main part in the PLL macro cell.

FIG. 11 is a circuit diagram illustrating another configuration example of the pulse width determination circuit included in the PLL macro cell.

12 is an operation timing chart of a main part in the pulse width determination circuit shown in FIG.

FIG. 13 is a circuit diagram illustrating another configuration example of the charge pump and the loop filter included in the PLL macro cell.

FIG. 14 is an operation explanatory diagram of a main part in the PLL macro cell when the configuration shown in FIGS.

[Explanation of symbols]

 17 Board Device 20 PLL Macrocell 21 Clock Buffer Tree 22 Feedback Loop 80 Current Adjustment Circuit 81 Charge Pump Unit 201 Input Divider 202 Phase Comparator 203 Charge Pump and Loop Filter 203A Charge Pump 203B Loop Filter 300 Counter 400 Decoder 204 Oscillator 205 Output Frequency divider 206 selector 207 pulse width determination circuit 208 pulse generation circuit 300 frequency divider

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J106 AA04 CC01 CC24 CC41 CC52 CC58 DD09 EE01 FF07 FF08 GG07 GG15 HH04 JJ08 KK02 KK05 LL04 5K047 AA01 AA05 GG02 GG09 MM28 MM33 MM46 MM50 MM52 MM55 MM63MM

Claims (5)

[Claims] An oscillator configured to form a clock signal; a phase comparator configured to compare a phase of a reference clock signal with a phase of a feedback clock signal; and a controller configured to determine a phase of the clock signal output from the oscillator. A phase correction unit for correcting according to a phase comparison result in the phase comparison unit; a feedback loop for feeding back the clock signal generated by the oscillation unit to the phase comparator as the feedback clock signal; And a phase correction amount adjusting means for adjusting the amount of phase correction by the phase correcting means according to the ratio of the delay in the feedback loop to the phase comparison interval by the phase comparing means. circuit. 2. An oscillating means for forming a clock signal; a phase comparing means for comparing a phase of a reference clock signal with a phase of a feedback clock signal; and a phase of a clock signal output from the oscillating means. A phase correction unit for correcting according to a phase comparison result in the phase comparison unit; a feedback loop for feeding back the clock signal generated by the oscillation unit to the phase comparator as the feedback clock signal; A first circuit for generating a pulse signal having a width corresponding to a delay in a feedback loop; and determining a ratio between a width of the pulse signal generated by the first circuit and a phase comparison period in the phase comparator. A second circuit for forming a control signal for adjusting the amount of phase correction by the phase correction means according to the ratio.
L circuit. 3. Oscillating means for forming a clock signal; phase comparing means for comparing the phase of a reference clock signal with the phase of a feedback clock signal; and the phase of a clock signal output from the oscillating means. A phase correction unit for correcting according to a phase comparison result in the phase comparison unit; a feedback loop for feeding back the clock signal generated by the oscillation unit to the phase comparator as the feedback clock signal; A selector capable of selectively realizing a first state in which a clock signal formed by an oscillating means is supplied to the feedback loop and a second state in which a signal for determining a delay in the feedback loop is transmitted to the feedback loop. And the delay corresponding to the feedback loop based on the reference clock signal. A first circuit for determining a start of a pulse signal having a width, and determining an end of the pulse signal based on a signal transmitted through the feedback loop in the second state; and a pulse obtained by the first circuit. A second circuit for determining a ratio between a signal width and a phase comparison period in the phase comparator, and forming a control signal for adjusting a phase correction amount in the phase correction means according to the ratio. PLL characterized by the above-mentioned.
circuit. 4. The phase correction means includes a charge pump for forming a voltage of a level corresponding to a comparison result by the phase comparison means, and a filter capacitance charged and discharged by the charge pump. 2. The charge pump according to claim 1, further comprising a current adjustment circuit for adjusting a charge current amount and a discharge current amount of the filter capacitor according to a control signal formed by the second circuit.
The PLL circuit according to any one of claims 1 to 3. 5. The PL according to claim 1, wherein:
A semiconductor integrated circuit including an L circuit and a logic circuit operated in synchronization with a clock signal output from the PLL circuit.