JP2002099253A - Driving circuit and display device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] In a conventional INV function, R, R
It has been difficult to suppress an increase in the number of change points that occurs when the change tendency differs for each of the G and B components. SOLUTION: A liquid crystal panel 7 having at least an image signal wiring, a scanning signal wiring intersecting with the image signal wiring and forming a plurality of grid regions, an image signal driving circuit group 6 for applying a voltage to the image signal wiring, and A scanning signal driving circuit group 5 for applying a voltage to the scanning signal wiring, and processing the video data and supplying it to the image signal driving circuit group 6 as an image signal and supplying the scanning signal driving circuit group 5 as a scanning signal. A signal processing circuit 1 for dividing video data of one pixel unit of the liquid crystal panel by a predetermined number of divisions and performing inversion control on each of the divided data; Then, re-inversion control is performed on the divided data subjected to the inversion control, and the divided data is combined.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit for a liquid crystal panel and a display device in which the liquid crystal panel and the driving circuit are combined.

[0002]

2. Description of the Related Art FIG. 5 is a schematic block diagram showing a conventional digital liquid crystal display device. This liquid crystal display device includes a signal processing circuit 101 including a data signal / data inversion control (hereinafter referred to as INV) signal processing circuit 102 and a control signal processing circuit 103, and a scan electrode including a plurality of scan electrode driving circuits 105a. Drive circuit group 105
A signal electrode driving circuit 106 including a plurality of signal electrode driving circuits 106a; a liquid crystal panel 107; a data signal bus 110; an INV signal bus 108; a signal electrode driving control signal bus 109; And an image signal / synchronization signal input unit 104.

FIG. 6 is a detailed diagram illustrating the data signal / INV signal processing circuit 102 in more detail. As shown, the data signal / INV signal processing circuit 102
Is composed of an RGB image data signal inverting circuit 201, an RGB image data signal comparing circuit 202, an RGB data signal holding circuit 203, a synchronizing signal generating circuit 205, and an INV signal generating circuit 204.

FIG. 7 shows the signal electrode driving electrode circuit 10.
FIG. 6B is a detailed diagram illustrating 6a in more detail. As shown in the figure, the signal electrode drive electrode circuit 106a includes an RGB image signal inversion circuit 301, an INV signal processing circuit 302, a shift register circuit 306, a latch circuit 305, and a D / A
It comprises a converter 304 and an output circuit 303.

FIG. 8 is a diagram showing signal waveforms of the (N-1) th dot and the Nth dot of the clock signal, the RGB data signal, and the INV signal.

The operation around the INV signal of the conventional liquid crystal display device configured as described above will be described with reference to FIGS.
This will be described with reference to FIG.

First, as shown in FIG. 5, based on the image signal / synchronous signal input from the image signal / synchronous signal input unit 104, the control signal processing circuit 103
In step 6, a start pulse signal, a clock signal, and a load signal are generated.

[0008] Next, as shown in FIG.
The NV signal processing circuit 102 firstly outputs the RGB image data of the current cycle (Nth dot) and the cycle (N
At the (-1st dot), the RGB image data of one dot before stored in the RGB data signal holding circuit 203 is extracted, and
Output to the RGB data signal comparison circuit 202. The RGB data signal comparison circuit 202 outputs the input R in the current cycle.
The GB image data is compared with the RGB image data of the cycle one dot before.

Here, when the data signals of the R, G, and B components are each 6 bits, the total of the RGB components is 18 bits.
When the data of 10 bits or more out of the bits changes from the data of one dot before, the INV data signal generation circuit 204
Generates an INV signal, and supplies the INV signal to the signal electrode drive circuit group 106 via the INV signal bus 108. For example, as shown in FIG. 8, the RGB data signal of the (N-1) th dot is # 3FFFF (R = # 3F, G = #
3F, B = # 3F) and the value of the Nth dot is # 00000
If (R = # 00, G = # 00, B = # 00), the INV signal is generated because 18 bits of 18 bits change between both data.

On the other hand, the RGB data signal inverting circuit 201
Is a signal electrode drive circuit group 1 which outputs an inverted signal obtained by inverting the RGB image data via a signal electrode drive control bus 110.
06.

Next, as shown in FIG. 7, the signal electrode drive circuit 106a receives the inverted signal of the RGB image data by the RGB image signal inverting circuit 301, and outputs the INV signal to the INV signal.
The signal is received by the signal processing circuit 302. INV signal processing circuit 3
02 generates a control signal from the INV signal and outputs it to the RGB image signal inversion circuit 301.

The RGB image signal inverting circuit 301 inverts the inverted signal of the input RGB image data again based on the received control signal, and supplies the inverted signal to the latch circuit 305.

Thereafter, the data signal / INV signal processing circuit 1
02, based on the input INV signal and the RGB image signal, and continuously outputs R signal to the latch circuit 305.
A GB data signal is provided.

On the other hand, the latch circuit 305 synchronizes with the load signal supplied from the control signal processing circuit 103 via the control signal bus 109 and, based on the control signal supplied from the shift register 306, based on the RGB image signal inversion circuit 3
Latch the RGB data signal output from 01. The latched RGB data signal is sent to the D / A converter circuit 304 at the subsequent stage, converted into analog data, and supplied to the liquid crystal panel 107 via the panel output circuit 303 to drive the liquid crystal panel.

A start pulse, a clock signal, and the like are supplied to the pixels in the liquid crystal panel 107 from the control signal processing circuit 103 to the scan electrode circuit group 105 via the scan electrode drive control signal bus 111, and the signal electrode circuit 106 The data signal supplied from the pixel is taken into the pixel and the liquid crystal panel 107
An image is displayed on the screen.

Next, as shown in FIG. 6, in the RGB data signal comparing circuit 202, when each of the data signals of R, G, and B is 6 bits, a total of 18 bits of RGB is used.
When the data of 10 bits or more does not change from the data of one dot before, the INV data signal generation circuit 204
No INV signal is generated in the INV signal bus 10
8, the INV signal is not supplied to the signal electrode drive circuit group 106.

At the same time, in the RGB data signal inverting circuit 201, based on the control signal supplied from the INV data signal generating circuit 204, the normal rotation signal of the RGB image data is transmitted via the signal electrode driving control bus 110 to the signal electrode driving circuit. Supply to group 106.

In the signal electrode drive circuit 106a, R
The RGB image signal inverting circuit 3 converts the normal rotation signal of the GB image data
01 and supplied to the latch circuit 305.

Thereafter, signal processing is performed based on the RGB image signals, and RGB data signals are continuously supplied to the latch circuit 305.

The latch circuit 305 has a control signal bus 109
The RGB data signal is latched based on the control signal supplied from the shift register 306 in synchronism with the load signal supplied from the control signal processing circuit 103. The latched RGB data signal is sent to a subsequent D / A converter circuit, converted into analog data, supplied to the liquid crystal panel 107 via the panel output circuit 303, and drives the liquid crystal panel.

A start pulse, a clock signal and the like are supplied to the pixels in the liquid crystal panel 107 from the control signal processing circuit 103 through the scan electrode drive control signal bus 111 to the scan electrode circuit group 105. The supplied data signal is taken into the pixel, and an image is displayed on the liquid crystal panel 107.

[0022]

As described above, in the operation of the conventional liquid crystal panel, in particular, in the INV signal control, the entire RGB image data, and in the conventional example, R, G, and B are each 6 bits × 3 (R, G, B (3 components) = 18 bits
In this case, it is determined whether INV signal control is performed or not by comparing whether or not more than half of the data has changed with the data of the immediately preceding pixel.

However, b of the entire RGB image data
As the number of ITs increases and the tendency of data change for each of R, G, and B becomes different, a problem has arisen that the variation probability of a data signal when the INV function is used does not decrease. Therefore, there has been a problem that an effective effect cannot be obtained even when the INV function is used.

The present invention has been made to solve the above-mentioned problem, and a display device capable of effectively utilizing the INV function by increasing the variation probability of a data signal when the INV function is used. The purpose is to provide.

[0025]

In order to achieve the above object, a first aspect of the present invention (corresponding to claim 1) comprises an image signal wiring and a plurality of grid regions intersecting with the image signal wiring. A driving circuit of a display device having a display panel having at least a scanning signal wiring for forming an image signal driving circuit for applying a voltage to the image signal wiring,
A scanning signal driving circuit for applying a voltage to the scanning signal wiring, and a signal processing for processing video data and supplying the image data to the image signal driving circuit as an image signal and supplying the scanning signal driving circuit as a scanning signal And a circuit,
The signal processing circuit divides the video data of one pixel unit of the display panel by a predetermined division number, performs inversion control on each of the divided data, and the image signal driving circuit includes: A drive circuit for performing reinversion control of the divided data subjected to inversion control and combining the divided data.

The second invention (corresponding to claim 2)
, The predetermined number of divisions is the RG of the video data.
The present invention is characterized in that the image data is divided into three parts corresponding to R image data, G image data, and B image data, which are B components.

The third invention (corresponding to claim 3)
A signal processing circuit configured to decompose the video data into the R image data, the G image data, and the B image data; and the R image of a predetermined (N-1) th pixel on the display panel. Data, G image data, B image data, and a predetermined Nth (N: natural number) on the display panel
The image data component comparing means for comparing the R image data, the G image data, and the B image data for each corresponding data sequence, and the N-th data based on the comparison result of the image data component comparing means. Image data component inverting means for performing inversion control for each of the R image data, G image data, and B image data; and informing that the Nth R image data, G image data, and B image data have been inverted. Generating means for generating an INV signal shown for each image data; an image signal driving circuit configured to process the INV signal; and a processing result of the INV signal processing means. Based on the N-th R image data, G image data,
Image data component reinversion means for performing reinversion control of B image data; and image data combining means for combining the R image data, G image data, and B image data output from the image data component reinversion means. The present invention is characterized by comprising the above.

The fourth invention (corresponding to claim 4)
The image data component inverting means determines whether the comparison result of the image data component comparing means is a comparison between the image data of each component of the (N-1) th pixel and the image data of each of the Nth component. The present invention is characterized in that the inversion control is performed when a majority of the corresponding data strings change between the data strings.

The fifth invention (corresponding to claim 5)
Comprises a driving circuit according to any one of the first to fourth aspects of the present invention, an image signal wiring, and a display panel having at least a scanning signal wiring intersecting with the image signal wiring to form a plurality of grid regions. A display device characterized in that:

The sixth invention (corresponding to claim 6)
Is an image display application device equipped with the display device of the fifth invention.

Further, a seventh aspect of the present invention (corresponding to claim 7)
Is a medium carrying a program and / or data for causing a computer to execute all or some of the functions of all or some of the first to fourth drive circuits of the present invention, A medium that can be processed by a computer.

The eighth invention (corresponding to claim 8)
Is a program and / or data for causing a computer to execute all or a part of the functions of all or a part of the driving circuit according to any one of the first to fourth aspects of the present invention. It is an aggregate.

The liquid crystal display device of the present invention as described above comprises, for example, a liquid crystal display panel in which scanning electrodes and signal electrodes are formed in a matrix, a scanning electrode drive circuit group for driving the scanning electrodes, and a signal electrode. A liquid crystal display device comprising a signal electrode driving circuit group to be driven and a signal processing circuit for supplying a data signal to each of the electrode driving circuit groups, wherein a data signal / data inversion control (INV) constituting the signal processing circuit is provided.
A signal control circuit having a function of performing data inversion control on each of the R image data, the G image data, and the B image data;
A signal inversion control signal generated for each of the R image data, the G image data, and the B image data; It has a function of separating an inversion control signal into data inversion control signals for each of the R image data, the G image data, and the B image data.

[0034]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment) FIG. 1 is a schematic block diagram showing a liquid crystal display device according to an embodiment of the present invention.
This liquid crystal display device includes a signal processing circuit 1 including a data signal / data inversion control (hereinafter referred to as INV) signal processing circuit 2 and a control signal processing circuit 3, and a scan electrode including a plurality of scan electrode driving circuits 5a. A drive circuit group 5, a signal electrode drive circuit 6 including a plurality of signal electrode drive circuits 6a, a liquid crystal panel 7, a data signal bus 10,
An NV signal bus 8, a control signal bus 9 for driving signal electrodes,
It comprises a scanning electrode driving signal bus 11 and an image signal / synchronization signal input unit 4.

FIG. 2 is a detailed diagram illustrating the data signal / INV signal processing circuit 2 in more detail. The data signal / INV signal processing circuit 2 includes an R image data signal inversion circuit 51a, a G image data signal inversion circuit 51b,
B image data inverting circuit 51c, R image data signal comparing circuit 52a, G image data signal comparing circuit 52b,
An image data signal comparison circuit 52c, an RGB data signal holding circuit 53, a synchronization signal generation circuit 54, an R-INV signal generation circuit 55a, and a GINV signal generation circuit 55b;
It comprises a BINV signal generation circuit 55c, an INV signal merge circuit 56, an image data decomposition circuit 57a and an image data decomposition circuit 57b.

FIG. 3 shows the signal electrode driving electrode circuit 6a.
FIG. The signal electrode drive electrode circuit 6a includes an R image signal inversion circuit 71a, a G image signal inversion circuit 71b, a B image signal inversion circuit 71C,
V signal processing circuit 72, shift register circuit 76, latch circuit 75, D / A converter 74, output circuit 7
3 and an image data composite circuit 77.

FIG. 4 shows a clock signal and R, G, B R
5 shows signal waveforms of the GB data signal and arbitrary N-1th dot and Nth dot (N: natural number) of the INV signal for each of R, G, and B. Here, as an example, the RGB data values of the (N−1) th dot are R = # 3F, G = # 3F, B = #
3F, and the RGB data value of the N-th dot is R = # 0
0, G = # 30, B = # 33.

The operation of the liquid crystal display according to the embodiment of the present invention configured as described above will be described with reference to FIGS.

First, as shown in FIG. 1, based on the image signal / synchronous signal input from the image signal / synchronous signal input section 4, the control signal processing circuit 3 starts the start pulse signal used in the signal electrode circuit group 6. , A clock signal and a load signal.

Next, as shown in FIG.
The NV signal processing circuit 2 first includes the RGB image data of the current cycle (the cycle of transferring the N-th dot) and the RGB data signal holding circuit 53 in the previous cycle (the cycle of transferring the (N-1) -th dot). And the RGB image data one dot before stored in the image data is extracted and output to the image data decomposing circuits 57a and 57b, respectively. Upon receiving the input of the RGB image data, the image data decomposing circuits 57a and 57b decompose the RGB image data into R, G, and B components, and
Then, it generates many data, G data, and B data, and outputs them to the R data signal comparison circuit 52a, the G data signal comparison circuit 52b, and the B data signal comparison circuit 52c. The R data signal comparison circuit 52a, the G data signal comparison circuit 52b, and the B data signal comparison circuit 52c perform the processing of the N-th dot image for each of the R, G, and B image data for each data row in the image data. The data is compared with the image data of the N-th dot.

When the RGB data signals of the R, G, and B components are each 6 bits, each of the RGB data signals is 6 bits.
As for t, when the data of 4 bits or more changes from the data of one dot before, the R-INV data signal generation circuit 55
a, G-INV data signal generation circuit 55b, B-INV
In the data signal generation circuit 55c, R, G,
An INV signal for each B is generated.

The INV data signal merging circuit 56 uses the synchronizing signal input from the image signal / synchronizing signal input terminal 4 to generate an R-INV based on the internal synchronizing signal generated by the internal synchronizing signal generating circuit 54. Data signal generation circuit 55a, G
-Combine the INV signals output from the INV data signal generation circuit 55b and the B-INV data signal generation circuit 55c into one.

In this embodiment, as shown in FIG. 4, in the cycle of N dots, time is divided into three stages corresponding to the R, G, and B components, and the INV belonging to the R, G, and B image data is divided. Includes signal information. The INV signal thus generated is supplied to the signal electrode drive circuit group 6 via the INV signal bus 8. For example, FIG.
As shown in the above, the RGB data signals of the N-th and -1st dots are R = # 3F, G = # 3F, B = # 3F, and the values of the Nth dot are R = # 00, G = # 30, B = # In the case of 33, the R component changes by 6 bits, the G component changes by 4 bits, and the B component changes by 2 bits, and the R-INV and G-INV signals are generated.

On the other hand, in parallel with the above operation, the R data signal inverting circuit 51a, the G data signal inverting circuit 51b, and the B data signal inverting circuit 51c transmit the inverted signal obtained by inverting the RGB image data to the signal electrode drive control. The signal is supplied to the signal electrode drive circuit group 6 via the bus 10.

Next, as shown in FIG. 3, in the signal electrode driving circuit 6a, an inverted signal obtained by inverting the RGB image data is supplied to the R image signal inverting circuits 71a, 71b for R, G, and B, respectively.
G image signal inversion circuit 71b, B image signal inversion circuit 71c
, And the INV signal is received by the INV signal processing circuit 72. The INV signal processing circuit 72 converts R-INV signals corresponding to R image data, G image data, and B image data, G-IN
A V signal and a B-INV signal control signal are generated and output to the R image signal inversion circuit 71a, the G image signal inversion circuit 71b, and the B image signal inversion circuit 71c, respectively.

R, G, B image signal inverting circuits 71a to 71a to
71b, based on the received R-INV signal, G-INV signal and B-INV signal, input R, G, B
Are inverted again, and the three types of data are combined into one by the image data combining circuit 77, and then supplied to the latch circuit 75.

Thereafter, signal processing is performed on the basis of the INV signal output 8 and the RGB data signal output 10 in the same manner as in the conventional example, and the RGB data signal is continuously supplied to the latch circuit 75.

The latch circuit 75 latches the RGB data signal based on the control signal supplied from the shift register 76 in synchronization with the load signal supplied from the control signal processing circuit 3 via the control signal bus 9. Latched RG
The B data signal is sent to a D / A converter circuit 74 at the subsequent stage, where it is converted into analog data,
Is supplied to the liquid crystal panel 7 via the controller and drives the liquid crystal panel.

The pixels in the liquid crystal panel 7 are supplied with a start pulse, a clock signal, and the like from the control signal processing circuit 3 to the scan electrode circuit group 5 by lightening the scan electrode drive control signal bus 11 from the control signal processing circuit 3. The supplied data signal is taken into the pixel, and an image is displayed on the liquid crystal panel 7.

Similarly, out of 6 bits for each of RGB, 4b
When the data of “it” or more does not change from the data of one dot before, the R-INV data signal generation circuit 55a and the G-INV
The data signal generation circuit 55b and the B-INV data signal generation circuit 55c do not generate the INV signal for each of R, G, and B, and do not supply the INV signal to the signal electrode drive circuit group 6 via the INV signal bus 8. .

In the signal electrode drive circuit 6a, RGB
The non-inverted signal of the image data is received by the R image signal inverting circuit 71a, the G image signal inverting circuit 71b, and the B image signal inverting circuit 71c for each of R, G, and B, and supplied to the latch circuit 75.

Thereafter, signal processing is performed on the basis of the INV signal and the RGB image signal.
A GB data signal is provided.

The latch circuit 75 latches the RGB data signals based on the control signal supplied from the shift register 76 in synchronization with the load signal supplied from the control signal processing circuit 3 via the control signal bus 9. Latched RG
The B data signal is sent to a D / A converter circuit 74 at the subsequent stage, where it is converted into analog data,
And is supplied to the liquid crystal panel 7 via the liquid crystal panel 7 to drive it.

A start pulse, a clock signal, and the like are supplied to the pixels in the liquid crystal panel 7 from the control signal processing circuit 3 to the scan electrode circuit group 5 via the scan electrode drive control signal bus 11, and from the signal electrode circuit 76. The supplied data signal is taken into the pixel, and an image is displayed on the liquid crystal panel 7.

As described above, according to the present embodiment, the image data is compared with the amounts of change in accordance with the R, G, and B components in each pixel, and the data is inverted and the INV signal is output. As a result, it is possible to reduce the number of change points finely, and to reduce the current consumption and the amount of electromagnetic radiation. Looking at the case shown in the above example, R
When the data of the GB pixel changes as shown in the following (Table 1), it is apparent that the number of change points is reduced and this effect can be obtained.

[0057]

[Table 1] In particular, when there is a bias in the number of change points among the R, G, and B components, the number of change points increases in the conventional method, and thus the present embodiment has an effect of reducing the number of change points. It turns out that it becomes large.

In the above embodiment, the description has been made assuming that the image data is divided into three components of R, G, and B, and the data change amount is compared for each of the components. However, the present invention is not limited to this, and the present invention can be realized irrespective of components such as R, G, and B, and the number of divided data. For example, if the image data is RGB 18 bits, the data is divided into the first 9 bits and the second 9 bits, and the data of a certain cycle is compared with the data of the previous cycle for each of the 9 bits. May be reversed.

Although the display device of the present invention has been described in the embodiment as a liquid crystal display device, the present invention is not limited to this. The drive circuit of the present invention is not limited to a display panel, but may be a plasma display device. It may be used for displays, EL (electroluminescence) displays, and the like.

The image signal driving circuit of the present invention corresponds to the signal electrode driving circuit group 6 of the embodiment, and the scanning signal driving circuit of the present invention corresponds to the scanning electrode driving circuit group 5 of the embodiment. The image data decomposing means of the present invention corresponds to the image data decomposing circuit of the embodiment. The image data component-by-image comparing means of the present invention is the image data signal comparing circuits 52a to 52 of the embodiment.
2c, the image data component inverting means of the present invention corresponds to the image data signal inverting circuits 51a to 51c of the embodiment, and the INV data signal component generating means of the present invention corresponds to the INV signal generating circuit of the embodiment. Circuits 55a-55c and IN
The image signal component reinversion means of the present invention corresponds to the V signal merge circuit 56, and the image signal inversion circuit 71a of the embodiment
The INV signal processing means of the present invention corresponds to the INV processing circuit 72 of the embodiment, and the image data combining means of the present invention corresponds to the image data combining circuit 77 of the embodiment.

Further, by using the display device of the present invention for a notebook personal computer or a monitor display as an image display application device, a power-saving image display application device can be obtained.

In the above description, the driving circuit, the display device, and the driving method of the display device according to the embodiment of the present invention have been described. However, the present invention relates to all or a part of the present invention. A medium that carries a program and / or data for causing a computer to execute all or a part of the function of the means. The medium is readable by a computer, and the program and / or data read therefrom cooperate with the computer. It may be realized as a medium for executing the above functions.

Further, the present invention is a program and / or data for causing a computer to execute all or a part of the functions of all or part of the above-described means of the present invention. It may be realized as an information aggregate that performs a function.

In the above description, data includes a data structure, a data format, a data type, and the like.
The medium includes a recording medium such as a ROM, a transmission medium such as the Internet, and a transmission medium such as light, radio waves, and sound waves. Further, the carried medium is, for example, a recording medium on which a program and / or data is recorded, or a program and / or
Or a transmission medium for transmitting data.

Further, the fact that it can be processed by a computer means that it can be read by a computer in the case of a recording medium such as a ROM, and that in the case of a transmission medium, the program and / or Or that the data can be handled by a computer as a result of transmission,
For example, it includes software such as a program and / or data.

Therefore, as described above, the configuration of the present invention may be realized by software or hardware.

[0067]

As described above, according to the present invention,
By setting the INV function individually for each divided image data, and combining and transmitting the individual functions, the change in the data from the signal processing circuit to the signal electrode drive circuit group is smaller than that of the conventional method. It is possible to reduce the number of points, and it is possible to obtain power consumption and EMI reduction effects.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a detailed diagram of a data signal / INV signal processing circuit in the liquid crystal display device according to the embodiment of the present invention.

FIG. 3 is a detailed diagram of a signal drive control circuit according to the embodiment of the present invention.

FIG. 4 is an INV signal timing diagram according to the embodiment of the present invention;

FIG. 5 is a schematic block diagram of a conventional liquid crystal display device.

FIG. 6 is a detailed diagram of a data signal / INV signal processing circuit in a signal processing circuit according to a conventional technique.

FIG. 7 is a detailed diagram of a signal drive control circuit according to a conventional technique.

FIG. 8 is a timing chart of an INV signal according to the related art.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 signal processing circuit 2 data signal / INV signal processing circuit 3 control signal processing circuit 4 image signal / synchronous signal input terminal 5 scan electrode drive circuit group 5 a scan electrode drive circuit 6 signal electrode drive circuit group 6 a signal electrode drive circuit 7 liquid crystal panel 8 INV signal bus wiring 9 signal electrode drive control signal bus wiring 10 data signal bus wiring 11 scan electrode drive control signal bus wiring 51a to 51c image data signal inverting circuits 52a to 52c image data signal comparing circuit 53 RGB data signal holding circuit 54 inside Synchronization signal generation circuit 55a to 55c INV signal generation circuit 56 INV signal merge circuit 57a, 57b Image data decomposition circuit 77 Image data composite circuit

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 623 G09G 3/20 623V H04N 5/66 102 H04N 5/66 102B F-term (Reference) 2H093 NA16 NC13 NC14 NC22 NC24 NC26 NC49 NC59 ND39 5C006 AA16 AA22 AC21 AC26 AF45 BB12 BC16 FA33 5C058 AA06 BA01 BA02 BA19 BA26 BA33 BB05 BB07 5C080 AA10 BB05 CC03 DD29 EE29 EE30 FF12 JJ02 JJ04

Claims (8)

[Claims] 1. A driving circuit for a display device, comprising: a display panel having at least an image signal line and a scanning signal line which crosses the image signal line to form a plurality of grid regions, wherein the image signal line includes An image signal driving circuit for applying a voltage, a scanning signal driving circuit for applying a voltage to the scanning signal wiring, processing video data, and supplying the processed image data to the image signal driving circuit as an image signal; A signal processing circuit that supplies a scanning signal to a scanning signal driving circuit, wherein the signal processing circuit divides the video data of one pixel unit of the display panel by a predetermined number of divisions, and The image signal drive circuit performs re-inversion control of the inversion-controlled divided data, and performs the inversion control on the divided data. A drive circuit characterized by combining the above. 2. The method according to claim 1, wherein the division of the predetermined division number is three divisions corresponding to R image data, G image data, and B image data, which are RGB components of the video data. 2. The driving circuit according to 1. 3. The signal processing circuit according to claim 1, wherein the video data is converted into the R image data, the G image data, and the B image data.
Image data decomposing means for decomposing into image data; R image data, G image data, and B image data of a predetermined (N-1) th pixel on the display panel; and a predetermined Nth (N : Natural number) of the R image data, the G image data, and the B image data, for each corresponding data sequence. Image data component inversion means for performing inversion control for each of the N-th R image data, G image data, and B image data; and inversion control of the N-th R image data, G image data, and B image data. Generating means for generating an INV signal for each image data, wherein the image signal drive circuit processes the INV signal. An INV signal processing unit that performs reinversion control of the Nth R image data, G image data, and B image data based on a processing result of the INV signal processing unit; 3. The driving circuit according to claim 2, further comprising image data combining means for combining the R image data, the G image data, and the B image data output from the image data component reinverting means. 4. The image data component inverting means, wherein the comparison result of the image data component comparing means is N-
When the image data of each component of the first pixel and the image data of each of the Nth components change to the corresponding data string of a majority, the inversion control is performed. The drive circuit according to claim 3, wherein 5. A display panel, comprising: the drive circuit according to claim 1; an image signal line; and a scan signal line intersecting with the image signal line to form a plurality of grid regions. A display device comprising: 6. An image display application device comprising the display device according to claim 5. 7. A medium carrying a program and / or data for causing a computer to execute all or a part of the functions of all or a part of the drive circuit according to claim 1. A medium which can be processed by a computer. 8. A program and / or data for causing a computer to execute all or a part of functions of all or a part of the drive circuit according to any one of claims 1 to 4. Information aggregate to do.