JP2002062340A - Semiconductor test equipment - Google Patents

Abstract

(57) [Summary] (with correction) [PROBLEMS] To reduce the overall test time when testing a circuit under test. SOLUTION: A waveform generating section 4 which supplies a driver under test signal Sd to a circuit under test based on input data d4,
In a semiconductor test apparatus including a logic judgment unit 5 for comparing a comparator output signal Sc returned from a circuit under test with expected value data d5 and outputting a pass / fail judgment signal S1, a timing generation unit 3, a waveform generation unit 4, a logic judgment In setting the register setting data d2 or d6 in the registers 61, 62, and 63 for storing the condition data corresponding to each unit 5,
Registers 61 are set such that data that is regularly used having a fixed pattern is set from the pattern memory 2 through the decoding unit 11, and condition data variably given from the tester controller 8 is set from the decode circuit 7. , 62 and 63 are set at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test apparatus, and more particularly, to a configuration for setting test conditions in a tester having a perpin architecture.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram of a conventional semiconductor test apparatus, and particularly illustrates a configuration employing a perpin architecture.

As shown in the figure, in the configuration of the per-pin architecture, a per-pin logic unit 1 is arranged for each test channel.

These per-pin logic units 1 include a pattern memory 2, a timing generation unit 3, a waveform generation unit 4, a logic judgment unit 5, a first register 61, a second register 62,
The third register 63 and the decoding circuit 7 are provided.

Incidentally, a first register 61, a second register 62, and a third register 63 are provided corresponding to the timing generator 3, the waveform generator 4, and the logic determiner 5, respectively. It has a function of storing test conditions such as information and waveform information.

The pattern memory 2 stores input data d4 necessary for generation of a test waveform and logic judgment, pattern data d3 such as expected value data d6 at the time of testing, and a pattern given from a pattern memory address generator 9. Access is performed based on the memory address data d1.

The timing generator 3 generates the edge timing of the input waveform and the timing of the expected value comparison,
The timing clock CL is supplied to the waveform generator 4 and the logic determiner 5.
Give K.

The waveform generator 4 receives the input data d4 from the pattern data d3 output from the pattern memory 2 and outputs a test waveform according to the timing clock CLK output from the timing generator 3 (not shown). To generate a driver input signal Sd for sending out to the driver.

[0009] The logic determination unit 5 determines the expected value data d5 from the pattern data d3 output from the pattern memory 2.
And compares the comparator output signal Sc returned from the semiconductor device under test with an expected value in accordance with the timing clock CLK output from the timing generation section 3,
An s / Fail pass / fail judgment signal S1 is output.

Further, the first register 61 holds data necessary for operating the timing generator 3. Further, the second register holds data necessary for operating the waveform generation unit 4. On the other hand, the third register
The data necessary for operating the logic determination unit 5 is held.

The decoding circuit 7 includes a tester controller 8
Generates register setting data d6 and a write signal C2 for the registers 61, 62 and 63 based on test condition data such as timing information and waveform information sent from the tester bus 10 via the tester bus 10.

Although not shown, the per-pin logic unit 1 includes circuits having various other functions.

On the other hand, in order to control the per-pin logic unit 1, a tester controller 8
And a pattern memory address generator 9 are connected. Among them, the pattern memory address generator 9 generates the pattern memory address data d1 for the pattern memory 2 in accordance with the data from the tester controller 8 provided through the tester bus 10 and the pattern instruction PI and system clock SCLK provided from other systems. It has occurred.

Next, the operation of the above-described configuration will be described.

A process of writing test condition data such as timing information and waveform information to various registers 61, 62, and 63 included in the per-pin logic unit 1 is given from the tester controller 8 to the decode circuit 7 via the tester bus 10. Is performed based on the data obtained. The register setting data d6 from the decoding circuit 7 is written to the first register 61, the second register 62, and the third register 63 based on the write signal C2.

On the other hand, the pattern memory address generator 9 sends the pattern memory address data d1 to the pattern memory 2 based on the data supplied from the tester controller 8 via the tester bus 10 and the pattern instruction PI and the system clock SCLK. Is output. As a result, the pattern memory 2 generates the pattern data d3 based on the specified address, and outputs it to the waveform generator 4 and the logic determiner 5.

The input data d4 included in the pattern data d3 is taken into the waveform generator 4 based on the timing clock CLK from the timing generator 3, and is output to the circuit under test as a driver input signal Sd.

On the other hand, the expected value data d5 included in the pattern data d3 is taken into the logic judgment unit 5 based on the timing clock CLK from the timing generation unit 3, and
The comparison process is performed with the comparator output signal Sc from the circuit under test, and as a result, the logic judgment unit 5 outputs the pass / fail judgment signal S1.

Basically, in the case of a semiconductor test apparatus employing a per-pin logic architecture, it is possible to set different waveforms, input timings, expected value comparison timings, and the like for each tester channel.

However, in other words, when writing test conditions such as timing information and waveform information from the tester controller 8 to the registers 61, 62 and 63 of each per-pin logic unit 1, serial processing is inevitable. I have no choice.

[0021]

As described above, in the conventional semiconductor test apparatus, each of the first register 61, the second register 62, and the third register 63 is transmitted from the tester controller 8 through the decode circuit 7. Is set so as to set necessary data corresponding to the constant data. Therefore, the steady data such as timing information and waveform information used for a test performed according to a certain pattern must be similarly set. In other words, even for stationary data whose data pattern is known in advance, the data setting process must be set individually and serially for each per-pin logic unit 1 from the tester controller 8, so the more the number of tester channels, the more Registers 61, 62, 6
3, the time required for the writing process to the file 3 increases. As a result, the total test time increases, and LS
This causes a decrease in the throughput of the I test.

Therefore, the present invention solves the above-mentioned problems of the prior art and solves the problem of constantly used data having a certain pattern in test conditions such as timing information, waveform information, and expected value data. It is an object of the present invention to provide a semiconductor test apparatus capable of shortening the overall test time even when the number of tester channels is large by enabling the setting to the corresponding registers at high speed. .

[0023]

In order to achieve the above object, the present invention provides a waveform generating means for applying a test waveform to a circuit under test on the basis of pattern data, and a method for converting a signal returned from the circuit under test into a pattern. Logic determination means for comparing with an expected value based on data; timing generation means for providing a timing signal to the waveform generation means and the logic determination means; and test conditions such as timing information and waveform information provided for each tester channel. A plurality of register means for storing;
A pattern memory unit for storing the data of the test condition; and when the output of the pattern memory unit is pattern data, the pattern data is supplied to the waveform generation unit and the logic judgment unit. In the case of the above data, there is provided a semiconductor test apparatus characterized by comprising condition means for transferring the data to necessary ones of the plurality of register means as necessary.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a semiconductor test apparatus according to an embodiment of the present invention. 3 is different from the configuration of FIG. 3 in that the pattern memory 2 stores known steady data of a data configuration used for a test of a predetermined pattern. That is, a decoding unit 11 having a function of selectively extracting is provided.

That is, when writing variable data relating to test conditions such as timing information and waveform information into the first register 61, the second register 62, and the third register 63, the tester controller 8 , Through the decode circuit 7, the register setting data d6 is given.

On the other hand, when writing steady data indicating test conditions used for testing a predetermined pattern, the decoding unit 11
In step (1), the data is discriminated and extracted as the register setting data d2, and is set in each of the registers 61, 62, and 63.

In order to realize the above function, the decoding unit 11 sends data d from the pattern memory 2 to the decoding unit 11.
In addition to 31, a pattern instruction PI indicating whether the pattern memory address data d1 indicates the output of the pattern data d32 or the register setting data d2 is provided.

The operation of the above configuration will be described with reference to the data flow diagram of FIG.

The process of writing variable data to the various registers 61, 62 and 63 included in the per-pin logic unit 1 is given from the tester controller 8 to the decode circuit 7 via the tester bus 10 as in the conventional case. It is based on the data. The register setting data d6 from the decode circuit 7 is a register write signal C2
, The first register 61, the second register 62,
The data is written to the third register 63.

On the other hand, the pattern memory address generator 9
Is a data or pattern instruction P provided from the tester controller 8 via the tester bus 10.
I, the pattern memory address data d1 is generated based on the system clock SCLK. The pattern memory address data d1 is given to the pattern memory 2.

As described above, when the pattern memory 2 is accessed by the pattern memory address data d1 output from the pattern memory address generator 9,
Data d31 is output from the pattern memory 2.

The data d31 and the pattern instruction PI are given to the decoding unit 11, which decodes the pattern data d31 corresponding to the data d31.
Alternatively, it generates the register setting data d2 and the register write signal C1.

That is, the decoding unit 11 determines whether the data d31 from the pattern memory 2 is an input pattern or an expected value pattern, or is data to be written to the registers 61, 62, and 63 by a pattern instruction PI.
And if the pattern includes an input pattern or an expected value, the pattern data d32 to the waveform generator 4 or the logic determiner 5 is output and the registers 61, 62, 6
If it is write data for No. 3, register setting data d2 is output.

The above operation will be described in more detail.

Generally, the pattern memory 2 has a width of 3 bits. With these 3-bit data, input data "0", "1", negative logic pulse N, positive logic pulse P, expected value data "0", "1", high impedance Z,
The pattern data d32 representing the mask X is output, and the waveform generator 4 and the logic determiner 5 operate based on the pattern data d32.

In the case of a plurality of pattern programs in which test conditions are continuously executed, writing from the decoding unit 11 to each of the registers 61 to 63 is not performed in order to shorten the test time. That is, the transfer from the pattern memory 2 to each of the registers 61 to 63 is performed only to the register of the necessary channel as needed. here,
The determination of whether or not to transfer is performed based on the pattern instruction P1 or by the decoding unit 11. In any of these cases, the operation is managed by the tester controller 8.

On the other hand, the register setting data d2 given to the registers 61, 62 and 63 has different data widths depending on the types of the data. For example, timing data is 20 to 30 bits wide. For this reason, since the 3-bit data output from one address of the pattern memory 2 cannot be used as register data, the decoding unit 11 has a function of converting the data output from a plurality of addresses of the pattern memory 2 into bits. ing.
For this reason, the decoding unit 11 has a structure in which 3-bit data output from a plurality of addresses is stored and accumulated, and this is collectively output as register setting data d2.

The decoding unit 11 also uses the pattern instruction PI as a keyword, and if the data output from the pattern memory 2 is register data,
Performs bit conversion processing, and further registers 61, 62,
A register write signal C1 which is a signal for writing to a specific register from among 63 is output.

The register setting data d2 obtained as described above is stored in the first register based on the register write signal C1.
, The second register 62, and the third register 63.

On the other hand, the input data d4 included in the pattern data d31 output from the decoding unit 11 is taken into the waveform generation unit 4 based on the timing clock CLK from the timing generation unit 3, and is received as the driver input signal Sd. Output to test circuit.

The expected value data d5 included in the pattern data d31 is taken into the logic judgment unit 5 based on the timing clock CLK from the timing generation unit 3, and is compared with the comparator output signal Sc from the circuit under test. As a result, a pass / fail judgment signal S1 is output from the logic judgment unit 5.

In an actual test, waveform data, timing data, and the like are described in a file other than the pattern program, which is generally called a test file, and is written to each register by the tester controller.

In this embodiment, since a mechanism is provided for providing waveform data, timing data, and the like from the pattern memory, it is necessary to store the data in the pattern program, but the pattern program can be easily generated. is there.

Conventionally, a pattern program in which only pattern data is described and a test program in which waveform information, timing information, and the like are described are managed independently of each other. For example, waveform information, timing information, and the like are described in the pattern program and managed collectively. This facilitates pattern debugging in a test off-line environment, that is, an environment in which a test is simulated on a computer. There is also an advantage that a tester program can be generated from CAD data, and porting of a tester program to another tester model becomes easy.

The configuration of the present embodiment is characterized by high-speed processing when the waveform data and timing data are stationary data. However, when other variable data is required, as described above, , The register setting data d6 and the write signal C based on the data supplied from the tester controller 8 to the decode circuit 7 through the tester bus 10.
2 is generated and data is written to the registers 62, 62, and 63, so that the semiconductor test apparatus can be operated flexibly.

[0047]

As described above, according to the semiconductor test apparatus of the present invention, for the steady data used when the test pattern is known in advance, the output of the pattern memory for giving the pattern data to the waveform generation unit and the logic judgment unit. Since it is configured to generate from the data through the decoding unit, the test conditions such as timing information and waveform information can be applied to the timing generator, waveform generator, and logic judgment unit in the semiconductor test equipment to which the per-pin architecture is applied. The setting time of the condition data to each of the provided registers can be shortened,
This has the effect of shortening the overall test time.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor test apparatus according to a first embodiment of the present invention.

FIG. 2 is a data flow diagram for explaining the operation of the configuration of FIG. 1;

FIG. 3 is a block diagram of a conventional semiconductor test apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Per pin logic part 2 Pattern memory 3 Timing generation part 4 Waveform generation part 5 Logic judgment part 61 First register 62 Second register 63 Third register 7 Decoding circuit 8 Tester controller 9 Pattern memory address generator 10 Tester bus 11 Decoding Department

Claims (8)

[Claims] Claims: 1. A waveform generating means for giving a test waveform to a circuit under test based on pattern data; a logic determining means for comparing a signal returned from the circuit under test with an expected value based on pattern data; Means, a timing generating means for providing a timing signal to the logic judging means, a plurality of register means provided for each tester channel and storing test conditions such as timing information and waveform information, and storing data of the test conditions. When the output of the pattern memory means is pattern data, the pattern data is supplied to the waveform generation means and the logic judgment means. When the output of the pattern memory means is the data of the test condition, Condition means for transferring to a necessary one of the plurality of register means as necessary. Semiconductor testing equipment. 2. The method according to claim 1, wherein the output of the pattern memory means is test condition data. If the test condition is a plurality of pattern programs to be continuously executed, the test condition data is stored in the register. The semiconductor test apparatus according to claim 1, wherein transfer to the semiconductor test device is not performed. 3. The apparatus according to claim 2, further comprising decoding means for decoding an output from said pattern memory means and applying the decoded result to said waveform generation means, said logic judgment means and said plurality of registers. The semiconductor test apparatus according to the above. 4. The semiconductor test according to claim 3, wherein whether or not the test condition is a plurality of pattern programs to be continuously executed is performed based on pattern instructions or by the decoder. apparatus. 5. The semiconductor test apparatus according to claim 1, further comprising another test condition means for giving an arbitrary test condition to said plurality of registers. 6. A waveform generating means for giving a test waveform to the circuit under test based on the pattern data, a logic judging means for comparing a signal returned from the circuit under test with an expected value based on the pattern data, Means and timing generating means for providing a timing signal to the logic judging means; first register means arranged corresponding to the timing generating means for storing test conditions; and test condition means arranged corresponding to the waveform generating means. Second register means for storing test conditions, third register means arranged corresponding to the logic determination means for storing test conditions, and the first register,
First condition means for variably giving test conditions to be given to the second register and the third register; pattern data for the waveform generating means and the logic judgment means; Pattern memory means for storing stationary test condition data to be given to the register, the second register, and the third register; and when the output of the pattern memory means is pattern data, the pattern memory means When the output of the pattern memory means is stationary test condition data, the data is supplied to the first register means, the second register means, and the third register means.
And a second condition means to be applied to the register means. 7. The semiconductor test apparatus according to claim 6, wherein said first condition means has a function of decoding data transmitted from a tester controller via a tester bus. 8. The data processing apparatus according to claim 2, wherein the second condition means outputs, based on the instruction, data output from the pattern memory,
8. The semiconductor test apparatus according to claim 6, further comprising a decoding function for determining whether the data is pattern data or stationary condition data.