JP2001136751A - Pwm drive circuit of motor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PWM drive circuit of motor for preventing generation of a through-current flowing into output upper/lower transistor by an inverse transistor operation, depending on the characteristic parasitic effect of an integrated circuit. SOLUTION: A parasitic current eliminating transistor is provided, where the emitter collector is connected to a base collector of the lower output transistor of the output upper/lower transistor for PWM drive of motor and the base is grounded. Thereby, an inverse current due to an inverse recovery time of a diode, formed with the base collector junction of the lower output transistor resulting from inverse transistor operation, is removed to prevent generation of a through-current which flows, when the output upper/lower transistor are turned on simultaneously.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PWM drive circuit for a motor, and more particularly to a PWM drive circuit for a motor in which a through current is prevented from being generated by an inverse transistor operation caused by a parasitic effect of an integrated circuit.
It relates to a drive circuit.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional PWM drive circuit for a motor. PWM from DC power supply 31 to chopper bridge 32
Variable speed control of the motor 33 is performed by variable duty control based on (pulse width modulation). Since the upper and lower transistors of the chopper bridge 32 are connected in series to the DC power supply 31, it is necessary to take measures to prevent them from turning on at the same time. In addition, this chopper bridge 32 is 3
In the case of a phase, the six transistors are turned on and off according to the six truth values, and the upper and lower output transistors connected in series are not simultaneously turned on in the same mode. FIG.
4 is an equivalent circuit diagram of one phase extracted from FIG. In FIG. 4, an intermediate point Y between DC power supplies 1A and 1B and DC power supply 1
A, a transistor Q1 connected in series to both ends of 1B,
One phase of the motor is connected to the midpoint X of Q2. The diodes D1 and D2 are for commutation of the energy stored in the inductance of the motor. Square terminals indicate Vcc connected to a DC power supply, OUT connected to one phase of a motor, a terminal RF for current detection, and a ground terminal GND. The terminal RF is connected via a detection resistor Rf of about 0.2Ω. And the ground terminal GND is grounded. The resistor Rb connected between the base and the emitter of the transistor Q2 has a function of preventing an output leak current when the transistor Q2 is off. Next, the operation will be described. When the transistor Q1 is turned on and the transistor Q2 is turned off, the one-phase X side of the motor has a positive voltage. When the transistor Q1 is turned off and the transistor Q2 is turned off, the one-phase X side of the motor has a negative voltage due to kickback. Become. When the lower output transistor Q2 is off, the midpoint X is at a negative voltage, the collector of the transistor Q2 is biased to a negative voltage, and the emitter of the transistor Q2 is grounded from the terminal RF via the detection resistor Rf. ing. Therefore, as will be described in detail later, a base current is supplied from the semiconductor substrate to the base of the transistor Q2 due to a parasitic effect, and a current flows from the emitter to the collector of the transistor Q2 by the reverse transistor operation. Next, when the upper output transistor Q1 is turned on from off, the intermediate point X, that is, the output terminal OUT changes from a negative voltage to a positive high voltage. At this time, it is considered that the diode formed at the PN junction between the base and the collector of the transistor Q2 is reversely rapidly biased from the forward bias by the reverse transistor operation described above. However, a diode generally has a reverse recovery time, and a reverse current flows for a moment (about 1 to 2 μS).
The transistor Q2 is turned on by this reverse current, and a large through current of several amps flows through the transistors Q1 and Q2 during this period. This parasitic effect will be described with reference to FIG. An N-type epitaxial layer 52 is provided on a P-type semiconductor substrate 51, and a P + -type isolation region 53 is provided.
Thus, a plurality of island regions are formed through the epitaxial layer 52. The first island region 54 and the second island region
Island region 55 and a third island region 56. The first island region 54 is located at a position away from the output transistor Q2, and the isolation region 53 is grounded via a ground terminal GND. In the second island region, an N-type collector region 58, a P-type base region 59, and an N-type emitter region 60 are formed in the lower output transistor Q2. Although not shown, other elements are formed in the third island region 56. Here, the collector region 5 of the second island region 55
8 is connected to the output terminal OUT via the intermediate point X, and the emitter region 60 is connected from the current detection terminal RF to the ground via the detection resistor Rf. Also, the transistor Q2
The shunt resistor Rb is connected between the base region 59 and the emitter region 60 as described above. Such an integrated circuit is structurally isolated when the collector region 58 is at a negative voltage.
The PNP-type parasitic transistor Tr1 is formed by the semiconductor substrate 51, the collector region 58 and the base region 59 connected to
Is formed inevitably, and a parasitic current flows from the semiconductor substrate 51 to the base region of the transistor Q2 here as shown by the arrow by the parasitic transistor Tr1. When the transistor Q1 is turned off in such a state, a negative voltage is applied to the intermediate point X. The collector region 58 to which the output terminal OUT is connected has a negative voltage, the base region 59 is supplied with a base current by the parasitic transistor Tr1, and the emitter region 60 has a slight positive potential of the terminal RF.
For this reason, the transistor Q2 performs an inverse transistor operation using the collector region 58 as an emitter and the emitter region 60 as a collector.
Is supplied to the base region of the transistor Q2, and the reverse transistor operation is continued. Therefore, the diode formed by the PN junction formed by the base region 59 and the collector region 58 of the transistor Q2 is forward biased.

Thereafter, when the transistor Q1 is turned on from off, the output terminal OUT changes from a negative voltage to a positive high voltage. At this time, the diode formed by the PN junction formed by the base region 59 and the collector region 58 of the transistor Q2 switches from the forward bias to the reverse bias, but because of the reverse recovery time when the diode switches from the forward direction to the reverse direction. A reverse current flows momentarily through this diode, the transistor Q2 is momentarily turned on, and a through current flows through both transistors Q1 and Q2.

[0004]

SUMMARY OF THE INVENTION The present invention relates to a direct PW of a motor for preventing the occurrence of a through current flowing through transistors Q1 and Q2 by causing an inverse transistor operation due to a substrate current due to a parasitic effect generated due to an integrated circuit.
It is intended to realize an M drive circuit. In particular, when the output terminal OUT has a negative voltage, the direct P of the motor prevents the reverse transistor operation caused by the parasitic effect and prevents the generation of a through current flowing through the transistors Q1 and Q2.
It is intended to realize a WM drive circuit.

[0005]

According to the present invention, a motor is provided with a PW motor.
An emitter collector is connected to the base collector of the lower output transistor Q2 of the output upper and lower transistors Q1 and Q2 driven by M, and a parasitic current removing transistor Q3 whose base is grounded is provided.
3 is turned on by the reverse transistor operation first, and the transistor Q
2 to steal the base current due to the parasitic effect flowing into the base of the transistor 2 and prevent the reverse transistor operation of the transistor Q2.
It is characterized in that generation of a through current flowing through the output upper and lower transistors Q1 and Q2 is prevented.

[0006]

FIG. 1 shows one embodiment of the present invention. FIG. 1 is a circuit diagram in which one phase is extracted, which is the same as FIG. Transistors Q1 and Q2 are connected in series with DC power supplies 1A and 1B to form output upper and lower transistors. The diodes D1 and D2 are for commutation of the energy stored in the inductance. Transistor Q1
One end of one phase of the motor is connected to an intermediate point X connected to the emitter of the transistor and the collector of the transistor Q2 via the output terminal OUT of the integrated circuit. The other end of one phase of the motor is connected to an intermediate point Y between DC power supplies 1A and 1B. Further, the other end of the DC power supply 1A is connected to a power supply terminal Vcc of the integrated circuit, and the other end of the DC power supply 1B is grounded. The current detection terminal RF of the integrated circuit is grounded via the detection resistor Rf. The terminal GND is a ground terminal. A feature of the present invention resides in that a parasitic current removing transistor Q3 is provided. The collector of the transistor Q3 is connected to the intermediate point X, the emitter is connected to the base of the transistor Q2, further connected to the terminal RF of the integrated circuit via the shunt resistor Rb, and the base is connected to the ground.

Next, the operation will be described. When the transistor Q1 is turned on and the transistor Q2 is turned off, the one-phase X side of the motor has a positive voltage. Then, when the transistor Q1 is turned off and the transistor Q2 is turned off, the one-phase X of the motor is turned off.
The side becomes a negative voltage. When the lower output transistor Q2 is off, the intermediate point X becomes a negative voltage due to kickback, and the transistor Q2 supplies the base current as the base current due to the parasitic effect peculiar to the integrated circuit to the base by the same principle as the conventional one. Have been. However, transistor Q3
Is connected to the midpoint X, the base is connected to ground,
Since the emitter is connected to the base of the transistor Q2, the transistor Q3 performs the reverse transistor operation earlier than the transistor Q2. That is, when the intermediate point X has a negative voltage, the transistor Q3
Substrate current is supplied directly from the ground terminal GND to the base of No. 3 and turned on as an inverse transistor prior to the transistor Q2. As a result, the substrate current due to the parasitic effect supplied to the base of transistor Q2 is deprived and output terminal OU
Since the current flows through the transistor T, a forward bias voltage (VF) is not generated at the PN junction formed by the base and collector of the transistor Q2, the reverse transistor operation of the transistor Q2 is prevented. No through current flows through the circuit. The operation of the present invention will be described with reference to FIG. An N-type epitaxial layer 21 is provided on a P-type semiconductor substrate 20, and a plurality of island regions are formed by penetrating the epitaxial layer 21 with a P + -type isolation region 22. Assuming that the first island region 23, the second island region 24, and the third island region 25 are conveniently located on the left side, the first island region 23 has a parasitic current elimination transistor Q
3, a P-type base diffusion region 26 and an N-type emitter region 27 are formed. In the second island region 24, an N-type collector region 28, a P-type base region 29 and a P-type base region 29 forming a lower output transistor Q2. An N-type emitter region 30 is formed therein. The third island region 25 has no diffusion region. Here, the base region 2 of the first island region 23
6 is grounded via a ground terminal GND, the emitter region 27 is connected to the base region 29 of the transistor Q2, and the collector region is connected to the output terminal OUT via the intermediate point X. Collector region 28 of second island region 24
Is connected to the output terminal OUT via the intermediate point X, and the emitter region 30 is connected to the ground via the current detection terminal RF. When the transistor Q1 is turned off in such a state, a negative voltage is applied to the intermediate point X. In the transistor Q3 formed in the first island region, the collector region has a negative voltage, the base region has a ground potential 26, and the emitter region is connected to the base region of the transistor Q2. Therefore, the transistor Q3 turns on as a reverse transistor earlier than the transistor Q2. Therefore, the substrate current of the parasitic transistor Tr1 due to the parasitic effect supplied to the base region of the transistor Q2 immediately flows to the output terminal OUT as shown by the arrow, and the base transistor and the collector of the transistor Q2 are short-circuited by the reverse transistor of the transistor Q3. As a result, the diode formed at the PN junction between the base and the collector of the transistor Q2 does not generate a forward bias voltage, so that the reverse transistor operation of the transistor Q2 is prevented.

Thereafter, when the transistor Q1 is turned on from off, the output terminal OUT changes from a negative voltage to a high positive voltage. At this time, since the transistor Q2 has no reverse transistor operation, no reverse current occurs due to a reverse recovery time when a diode between the base and the collector of the transistor Q2 is reverse biased from a forward bias. Therefore, no through current flows through the transistors Q1 and Q2.

[0009]

According to the present invention, the reverse transistor operation generated in the transistor Q2 by the substrate current due to the parasitic effect peculiar to the integrated circuit is performed by utilizing the reverse transistor operation by the transistor Q3 connected to the base collector of the output transistor Q2. Since the transistor can be completely removed, the reverse transistor operation of the output transistor Q2 can be completely prevented. As a result, even if the output transistor Q1 is turned on from off, there is no reverse current due to the reverse recovery time of the diode between the base and the collector of the output transistor Q2, so that no through current flows through the transistors Q1 and Q2.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a PWM drive circuit for a motor according to the present invention.

FIG. 2 is a cross-sectional view illustrating a parasitic effect generated in the integrated circuit of the present invention.

FIG. 3 is a circuit diagram illustrating a conventional PWM drive circuit of a motor.

FIG. 4 is a circuit diagram illustrating the principle of one-phase operation of a conventional PWM drive circuit for a motor.

FIG. 5 is a cross-sectional view illustrating a parasitic effect occurring in a conventional integrated circuit.

[Explanation of symbols]

 Q1, Q2 Upper and lower output transistors Q3 Parasitic current elimination transistor D1, D2 Diode for commutation Vcc power supply terminal OUT output terminal RF current detection terminal GND Ground terminal X Midpoint 1A, 1B DC power supply

Claims (6)

[Claims] 1. A PWM drive circuit for a motor comprising at least a pair of output upper and lower transistors connected in series and a PWM control signal applied to a base of the transistor, wherein a base collector of the lower output transistor is provided. A PWM drive circuit for a motor, wherein a transistor is connected between the transistors to prevent the reverse transistor operation when the lower output transistor is off. 2. The PWM drive circuit according to claim 1, wherein a base current supplied to a base of the lower output transistor is generated from a substrate due to a parasitic effect of an integrated circuit. 3. A PWM drive circuit for a motor comprising at least a pair of output upper and lower transistors connected in series between a DC power supply and a PWM control signal applied to the bases of the two transistors. A PWM drive circuit for a motor, wherein a transistor is connected between the base and collector of the output transistor on the side to prevent reverse transistor operation when the lower output transistor is off. 4. The PWM drive circuit according to claim 3, wherein a base current supplied to a base of the lower output transistor is generated from a substrate due to a parasitic effect of an integrated circuit. 5. A PWM drive circuit for a motor comprising at least one pair of output upper and lower transistors connected in series between a DC power supply and a PWM control signal applied to the bases of both transistors. When the lower output transistor is off, a transistor is connected between the base and collector of the lower output transistor, and when the lower output transistor is off, the drive current supplied by the parasitic effect is absorbed to perform the reverse transistor operation. A PWM drive circuit for a motor, characterized in that the PWM drive circuit prevents the PWM drive. 6. The PWM drive circuit according to claim 5, wherein the base current supplied to the base of the lower output transistor is generated from a substrate due to a parasitic effect of an integrated circuit.