JP2001119138A - Circuit board manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a circuit board capable of forming a resistor between wiring layers formed so as to sandwich an insulating layer in a multilayer circuit board using a resin material such as polyimide for an insulating layer. . An insulating layer is formed on a surface of a first wiring layer, and an opening is formed in the insulating layer.
A metal oxide film layer having a large number of columnar gaps is formed on the surface of the first wiring layer 12 which is exposed from the surface and becomes the bottom surface 18b of the opening 18 by using metal oxide having electrical insulation. The bottom surface 18 of the opening 18 in which the metal oxide film layer is formed on the surface of the insulating layer 14 and / or the metal oxide film layer
b, and a voltage is applied between the first and second wiring layers 12 and 20 to form a bottom surface 18 of the opening 18.
b, a conductor having a predetermined resistance value which is made of a metal forming a first and a second wiring layer 12, 20 in a columnar gap of the metal oxide film layer by dielectric breakdown of a part of the metal oxide film layer on the metal oxide film layer. A path 24 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a circuit board, and more particularly to a method of manufacturing a circuit board in which wiring layers are electrically connected to each other via a conductor path having a predetermined resistance value.

[0002]

2. Description of the Related Art In a method of manufacturing a multilayer circuit board constituting a semiconductor package, a metal film is formed on a surface of an insulating layer by plating or vapor deposition, and the metal film is etched to form a wiring layer having a predetermined pattern. There is a method in which a wiring layer is electrically connected between layers by a via. Generally, copper is often used as a metal for forming a wiring layer on such a circuit board, and polyimide is often used for an insulating layer. This is because copper can form wiring with low resistance, and polyimide can form a thick interlayer insulating layer with low dielectric constant.

FIG. 4 shows a method of forming a metal film on the surface of an insulating layer to form a multilayer circuit board having vias. FIG.
1A shows a state in which a first wiring layer (first wiring layer) 12 is formed on the surface of a substrate 10. First wiring layer 12
Can be formed by forming a conductor layer on the surface of the substrate 10 by sputtering or plating, and patterning the conductor layer by etching. The etching of the conductor layer may be performed by a photolithography method generally used as a method for forming a wiring.

Next, polyimide having fluidity is applied to the surfaces of the substrate 10 and the first wiring layer 12 to form an insulating layer 14 (FIG. 4B). The electrical connection between the first wiring layers 12 between the layers is made by forming vias 16 in the insulating layer 14. As shown in FIG. 4C, the via 16 has the opening 1 in the insulating layer 14.
8 is formed, and the inner surface of the opening 18 and the surface of the first wiring layer 12 exposed from the opening 18 (the bottom surface of the opening 18) are formed by, for example, copper plating. When plating is performed on the inner region of the opening 18, first, electroless plating is performed, and then, electrolytic plating is performed. At this time, a plating layer (conductor layer) is also formed on the surface of the insulating layer 14.
The second wiring layer (second wiring layer) 20 can be formed. Thus, the first wiring layer 12 and the second wiring layer 20
Are electrically connected via the via 16 (FIG. 4D).
Thus, a multilayer circuit board in which the wiring layers are electrically connected between the layers can be obtained by sequentially forming the insulating layer 14 and the wiring layer and forming the vias 16 as appropriate.

The function of the via 16 is to electrically connect the wiring layers 12 and 20 formed via the insulating layer 14 with as low resistance as possible.
It is a technical issue how to reduce the resistance between the bottom surface of the substrate and the wiring layer 12 according to the structure and the manufacturing method, and the applicant of the present application has already disclosed in Japanese Patent Application Laid-Open No. 10-224031.
Application as in Japanese Patent Publication

[0006]

On the other hand, in recent years, the frequency of input / output signals to / from a semiconductor chip mounted on such a multilayer circuit board (or mounted when the multilayer circuit board is a semiconductor package) tends to increase. In order to reduce signal deterioration and loss due to reflection at the end of the wiring layer of the multilayer circuit board, there is a demand to match the characteristic impedance of the wiring layer through which a high-frequency signal passes to a predetermined resistance value. In order to match the characteristic impedance of the wiring layer to a predetermined resistance value, a configuration in which a terminating resistor interposed between the wiring layer and the ground layer is disposed at each end of the wiring layer is considered. Also, Japanese Patent Application Laid-Open No. 64-44050 discloses the structure of a ceramic package in which a terminating resistor is formed.

However, the multi-layer circuit board in this application is a ceramic substrate, and a multi-layer circuit board using a resin material such as polyimide for an insulating layer has a manufacturing method for forming a terminating resistor between a ground layer and a wiring layer. However, there is still no arrangement in which a terminating resistor is arranged, and its development has been desired. By the way, as described in the conventional example, a problem of the via in the multilayer circuit board using the resin material such as polyimide for the insulating layer is that a resistance component exists in a contact portion between the bottom surface of the via and the lower wiring layer. From the idea of reducing this resistance component as much as possible in the past, if this resistance component can be controlled to a predetermined resistance value, by replacing one of the wiring layers with a ground layer,
We thought that the terminating resistor could be formed in the multilayer circuit board.

SUMMARY OF THE INVENTION The present invention provides a method for manufacturing a circuit board in which a resistor can be formed between wiring layers formed so as to sandwich an insulating layer in a multilayer circuit board using a resin material such as polyimide for an insulating layer. Things.

[0009]

The present invention has the following arrangement to achieve the above object. That is, a step of forming an insulating layer on a surface of the first wiring layer, a step of forming an opening in the insulating layer, and a step of forming the first wiring layer exposed from the opening and serving as a bottom surface of the opening. Forming a metal oxide film layer having a large number of columnar gaps by using a metal oxide having an electrical insulation property on the surface of the insulating layer and / or the surface of the insulating layer and / or the metal oxide film layer; Forming a second wiring layer covering a bottom surface of the opening in which the metal oxide film layer is formed, and applying a voltage between the first wiring layer and the second wiring layer, A part of the metal oxide film layer located on the bottom surface of the opening is subjected to dielectric breakdown, and is formed of a metal forming a first wiring layer and a second wiring layer in a columnar gap of the metal oxide film layer, and is formed of a predetermined metal. Forming a conductor path having a resistance value. According to this, the resistor composed of the conductor path can be formed on the bottom surface of the opening.

Preferably, the metal oxide film layer is formed using magnesium oxide. Further, it can be formed using aluminum oxide.

In addition, the first wiring layer or the second wiring layer
If one of the wiring layers is a ground layer, a resistor constituted by a conductor path can be used as a terminating resistor.

[0012]

Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In the method of manufacturing a circuit board according to the present invention, when a multilayer circuit board is formed, a conductor path having a predetermined resistance value is formed between two wiring layers formed with an insulating layer interposed therebetween, thereby forming a resistor, for example, The terminal resistor is formed in the multilayer circuit board.

A method for manufacturing a multilayer circuit board according to the present embodiment will be described with reference to FIG. The same components as those of the conventional example are denoted by the same reference numerals, and detailed description thereof will be omitted. FIG. 1A shows a first wiring layer (first wiring layer) on the surface of a substrate 10.
(Wiring layer) 12 is formed. First wiring layer 1
2 can be formed by forming a conductor layer on the surface of the substrate 10 by sputtering or plating, and patterning this conductor layer by etching using a photolithography method or the like. Here, as the substrate 10, a ceramic substrate such as an alumina ceramic, a resin substrate such as a glass epoxy substrate and a BT substrate can be used. Further, the first wiring layer 12 is formed by attaching a copper foil to the substrate 10,
The copper foil may be formed by etching.

Next, a fluid polyimide or polyphenylene ether resin is applied to the surfaces of the substrate 10 and the first wiring layer 12 to form an insulating layer 14 (FIG. 1B).
In addition, it is also possible to form by bonding these resin sheets. Next, an opening 18 is formed in a portion of the insulating layer 14 where the resistor is to be formed by laser light irradiation or photolithography (FIG. 1C). Since the resistor is formed between the first wiring layer 12 and a second wiring layer 20 to be described later, a part of the first wiring layer 12 is exposed from the opening 18. The exposed part of the first wiring layer 12 forms a bottom surface of the opening 18.

Next, the entire surface of the insulating layer 14, the opening 18
A metal oxide film layer 22 is formed on the inner surface 18a of the first wiring layer 12 and the surface (bottom surface of the opening 18) 18b of the first wiring layer 12 exposed from the opening 18 (FIG. 1 (d)). As a forming method, sputtering is considered, and the thickness of the metal oxide film layer 22 is 25
It is formed to about 0 to 1000 microns. The metal oxide film layer 22 is formed into a structure having a large number of columnar gaps by using an insulating material having electrical insulation. As a specific insulating material, for example, magnesium oxide or aluminum oxide can be adopted. The metal oxide film layer 22
May be formed at least on the bottom surface 18 b of the opening 18 or at least on the bottom surface 18 b of the opening 18 and the inner surface 18 a of the opening 18, and need not necessarily be formed on the surface of the insulating layer 14 other than the opening 18. In particular, when another opening (not shown) to be finally formed in the via exists in the same insulating layer 14, a mask or the like is used for the internal region of the opening to be formed in the via. So that the metal oxide film layer 22 which is an electrically insulating layer is not formed. The unnecessary portion of the metal oxide film layer 22 may be removed by etching.

Next, the entire surface of the insulating layer 14 on which the metal oxide film layer 22 is formed is plated with copper to form a conductor layer, and the conductor layer is patterned by etching to form the second wiring layer 20. It is formed (FIG. 1 (e)). The second wiring layer 20 has a configuration in which at least a part thereof covers the bottom surface of the opening 18, in other words, the second wiring layer 20 covers the opening 18. The conductive layer is formed by first performing electroless plating and then performing electrolytic plating to form the conductive layer also on the inner surface 18a and the inner region of the bottom surface 18b of the opening 18. The etching of the conductor layer may be performed by a photolithography method generally used as a method for forming a wiring. Next, as shown in FIG. 1E, a power supply P / P is selectively provided between the first wiring layer 12 and the second wiring layer 20 where a resistor is to be formed therebetween.
A voltage (for example, 100 volts AC) is applied from S to form a plurality of conductor paths 24 that penetrate the metal oxide film layer 22 existing on the bottom surface of the opening 18. Referring to FIG. 2 schematically showing the bottom surface of the opening 18, the conductor path 24 is formed along the columnar gap of the metal oxide film layer 22 along the first wiring layer 12 and the second wiring layer 20. The metal (copper) constituting each of the layers 12 and 20 is moved into the metal oxide film layer 22 by the electric field discharge (field emission) from the respective layers to form a plurality of layers. The shape of the conductor path 24 is cylindrical or conical.

The diameter of the conductor path 24 is determined by the voltage value, the application time, and the diameter of the columnar gap of the metal oxide film layer 22. Specifically, the diameter is about 10 nanometers. In the case of the conductor path 24 having such a small thickness, the conductor path itself has resistance. The density and the like of the conductor paths 24 are also determined to be a certain value by factors such as the applied voltage value and the application time and the columnar crystal structure of the metal oxide film layer 22 in the same manner as the diameter of the conductor paths 24. The diameter of the portion 18, the crystal structure and thickness of the metal oxide film layer 22, the applied voltage,
By setting the forming conditions such as the application time to predetermined conditions, the entire resistance value of the plurality of conductor paths 24 formed between the first wiring layer 12 and the second wiring layer 20 is reduced to a predetermined resistance value. It is possible to do. The formation conditions can be determined by experiments and the like.

There are various possible locations for forming the above-described conductor paths 24 in the multilayer circuit board. Land portion 28 for mounting semiconductor chip 26 shown in FIG.
A description will be given using the multilayer circuit board 30 on which is formed. In the multilayer circuit board 30, a ground layer 32 is formed on the substrate 10, and two layers of an insulating layer 34 and a wiring layer 36 formed on the surface thereof are formed on the ground layer 32 as an example. ing. For the sake of explanation, the insulating layers are referred to as a first insulating layer 34a and a second insulating layer 34b in order from the lower layer side. The wiring layer 36 is a first wiring layer 36a and a second wiring layer 36b in order from the lower layer side. A resist layer 38 is formed on the uppermost layer such that the land 28 is exposed. Then, the insulating layer 14 described above
Is the first insulating layer 34a, the above-described first wiring layer 12 is the ground layer 32, and the second wiring layer 20
Becomes the first wiring layer 36a formed on the surface of the first insulating layer 34a.

If the insulating layer 14 described above is used as the second insulating layer 34b, the first wiring layer 12 described above can be used.
Denotes a first wiring layer 36a formed on the surface of the first insulating layer 34a, and the second wiring layer 20
It becomes the second wiring layer 36b formed on the surface of b. When forming a terminating resistor for matching the characteristic impedance of the wiring layer, it is necessary to connect one end of the resistor to the ground layer 32. Therefore, the first insulating layer 34a of the portion A in FIG. A resistor is formed on the bottom surface of the opening 18 formed in the substrate. When a resistor is interposed in the middle of the signal line in series, the resistor may be formed on the portion B in FIG. 3, that is, on the bottom surface of the opening 18 formed in the second insulating layer 34b. .

As described above, since the resistance can be formed in the multilayer circuit board in which the insulating layer is made of a material such as polyimide, the land portion 28 connected to the electrode 40 of the semiconductor chip 26 via the bump 42 as shown in FIG. Can be arranged in the vicinity of, and ideal characteristic impedance matching can be achieved.

Further, the step of forming a via described in the conventional example and the step of forming a resistor according to the present invention basically share the same plurality of steps. After the step of forming the part 18, the metal oxide film layer 2 is formed.
2 and the step of applying a voltage between the second wiring layer 20 and the first wiring layer 12 for forming a resistor after forming the second wiring layer 20. Lies in the point of existence. Therefore, when the metal oxide film layer 22 is formed on the surface of the insulating layer 14 in FIG. 1D, the metal oxide film layer 22 is selectively formed only in the internal region of the opening 18 where the resistor is to be formed. Openings 18 to be formed and vias to be formed
The metal oxide film layer 22 is not formed in the inner region of the above.

When a voltage is applied from a power supply after the formation of the second wiring layer 20, the first wiring layer 12 and the second wiring layer If a voltage is selectively applied to the substrate 20, the formation of the via and the formation of the resistor can be included in the same manufacturing process.
When a voltage is applied between the first wiring layer 12 and the second wiring layer 20, the electrical connection between the first wiring layer 12 and the second wiring layer 20 at the bottom of the via is made. In order to secure a secure connection, it is also possible to simultaneously apply the technology described in Japanese Patent Application Laid-Open No. H10-224031 which has been cited as a conventional example.

[0023]

According to the method of manufacturing a circuit board according to the present invention, a resistor can be formed between wiring layers formed so as to sandwich an insulating layer of a multilayer circuit board using a resin material such as polyimide for the insulating layer. There is an effect that matching of the characteristic impedance of the wiring layer can be performed without using an external resistor. Further, when the circuit board is a semiconductor package on which a semiconductor chip is mounted, it is desirable to dispose a resistor for characteristic impedance matching at a position as close as possible to an electrode terminal of the semiconductor chip connected to the wiring layer. By forming the resistor therein, the resistor can be formed near the land portion by being connected to the electrode terminal of the semiconductor chip via the bump, so that ideal impedance matching can be achieved.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram for explaining a method for manufacturing a circuit board according to the present invention.

FIG. 2 is an explanatory diagram schematically showing a bottom surface portion of an opening in which a resistor is formed.

FIG. 3 is a cross-sectional view showing a state where a semiconductor chip is mounted on a circuit board manufactured by the method for manufacturing a circuit board of FIG. 1;

FIG. 4 is an explanatory diagram for explaining a conventional method for manufacturing a circuit board.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Substrate 12 1st wiring layer 14 Insulating layer 18 Opening 18b Bottom of opening 20 Second wiring layer 24 Conductor path

Continued on the front page F term (reference) 5E317 AA24 BB03 BB12 BB30 CC31 CC44 CC51 CC60 CD25 CD32 CD36 GG17 GG20 5E346 AA02 AA15 AA35 AA43 BB02 BB04 BB07 BB13 BB15 CC10 CC25 CC31 CC32 DD02 DD03 DD09 DD31 FF12 FF31 FF32 FF32 GG08 GG15 GG17 HH03 HH32

Claims (4)

[Claims] A step of forming an insulating layer on a surface of a first wiring layer; a step of forming an opening in the insulating layer; and a step of exposing from the opening to serve as a bottom surface of the opening.
Forming a metal oxide film layer having a large number of columnar gaps on the surface of the wiring layer using metal oxide having electrical insulation; and a surface of the insulating layer and / or the metal oxide film layer. Forming a second wiring layer covering a bottom surface of the opening in which the metal oxide film layer is formed; and applying a voltage between the first wiring layer and the second wiring layer. The metal oxide film layer located at the bottom surface of the opening is caused by dielectric breakdown, and is formed of a metal that forms a first wiring layer and a second wiring layer in a columnar gap of the metal oxide film layer. Forming a conductor path having a predetermined resistance value by using the above method. 2. The method according to claim 1, wherein the metal oxide film layer is formed using magnesium oxide. 3. The method according to claim 1, wherein the metal oxide film layer is formed using aluminum oxide. 4. The method for manufacturing a circuit board according to claim 1, wherein one of said first wiring layer and said second wiring layer is a ground layer.