JP2001186011A - Integrated circuit device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] In designing a system LSI or the like in which each functional block is combined by utilizing IP (design assets), it is possible to facilitate design evaluation and measures for evaluation results,
Improve design quality. SOLUTION: In an integrated circuit device including a plurality of functional blocks 11 to 14 and a glue logic (GLUE LOGIC) for operating the functional blocks 11 to 14 in parallel and cooperatively, the function blocks 11 to 14 and the glue logic are controlled. FPGA that interconnects some or all of the logic
15 is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IP (Intel
The present invention relates to an integrated circuit device such as a system LSI which is realized by combining a plurality of functional blocks referred to as “electrical property”.

[0002]

2. Description of the Related Art In recent years, with the rapid progress of IC (integrated circuit) design and manufacturing techniques, a plurality of ICs and
A system LSI in which several million gates are integrated in one chip is designed so that the system function configured by the above can be realized by a chip having a small number of dedicated functions. Generally, it is rare to design several million gates at the flat gate level from the beginning for all functions because of the development period, reliability evaluation, and the like. In addition, with the emergence of new services and the development of individuality, electronic devices are frequently changed in models, and have a short product life and are diversified and diversified. For this reason, it is necessary to shorten the design period of a system LSI or the like mounted on these electronic devices and avoid risks.

[0003] Therefore, a processor or a DSP (digital
An arithmetic unit such as an al signal processor is reused in many cases, for example, by reusing a functional block designed and proven in the past, or by using an IP (Intellectual).
A system LSI is realized by procuring a function block called lProperty (design property) from the outside and combining the function blocks.

That is, IP refers to each functional block of a system LSI designed by each company in the semiconductor industry, and is distributed or reused like a component. In a system LSI, since various functional blocks are integrated into one silicon chip and combined, it is efficient to newly develop a functional block for each LSI. IP includes various functional circuits such as high-integration and high-performance CPUs and DSPs, filter circuits, various large-capacity memories, audio and video processing circuits, various interface circuits, and mixed analog / digital signal processing circuits. Block (library)
Are in circulation.

FIG. 5 is a block diagram showing a configuration of a conventional system LSI. The conventional system LSI 1 has a configuration in which functional blocks A to D (2 to 5) having different functions are interconnected by a GLUE LOGIC 6. That is, GLUE LOGI
By C6, for the plurality of different functions of the functional blocks A to D, control between the functional blocks is provided,
They work in concert with each other.

Now, a complicated and large-scale LSI test requires a large amount of time to create a test program. Therefore, the test facilitation design attempts to reduce the load of test evaluation. Here, a method is used in which measures are implemented in test design (Testing Design) so that test patterns can be easily generated in advance. Specific design methods for testability include:
Ad-hoc method, scan design method, built-in method, etc.

As a reference technical document related to the present invention, for example, Japanese Patent Application Laid-Open No. Hei 7-281923 discloses an "electronic circuit using a programmable logic circuit". Here, jumper pins provided with a plurality of pins for test or jumper connection are provided between a plurality of PLDs on a printed circuit board so that jumpers can be performed even when a design change occurs during circuit debugging. The wires can be easily handled by jumper sockets without connecting the wires by soldering or the like. Also, FPGA
Japanese Patent Laid-Open Publication No.
No. 63704, "Semiconductor test apparatus", JP-A-6-8
It is disclosed in Japanese Patent No. 5214. These are G
It does not replace LUE LOGIC with FPGA.

[0008]

However, when a system LSI is designed by a conventional method as shown in FIG. 5, there are the following problems. First, IP (design assets) procured from the outside vary in design quality, and the accuracy of supplied simulation models also varies. If the accuracy of the simulation model is low, the operation differs from that of the completed real chip, or a defect due to timing accuracy occurs. When this problem occurs, each function block is GLUE LOG
Since they are interconnected by an IC, each functional block cannot be directly accessed, and its analysis is difficult.

Second, the test (evaluation) of the completed chip is performed by a boundary scan (Boundary Sc), which is a standardized method of testability design for each functional block.
anDesign) method in many cases. in this case,
A lot of time is required to create a test program, and the chip can be tested only with a clock that is slower than the actual clock.
There is a problem that improvement in design quality is hindered.

The present invention has been made in view of the above, and in designing a system LSI or the like in which functional blocks are combined by utilizing IP (design assets), it is possible to facilitate design evaluation and measures for evaluation results. The purpose is to realize and improve the design quality.

[0011]

In order to achieve the above object, in the integrated circuit device according to the first aspect, a plurality of functional circuit blocks and the functional circuit blocks are operated in parallel and cooperatively. Glue logic
And a programmable logic for interconnecting the functional circuit blocks and part or all of the glue logic.

According to the present invention, for example, when a system LSI is designed by arranging functional circuit blocks on one chip by utilizing IP (design assets), a program can be executed between the arranged functional circuit blocks. By interconnecting with programmable logic, even if a timing failure occurs in each functional block, if it is a setup / hold problem, it can be handled by adjusting the number of gates with programmable logic. Will be possible. In addition, if a fatal failure occurs in each functional circuit block, and it is difficult to replace some or all of the functions with programmable logic, debugging can be performed by separating the failed functional circuit block. It becomes possible.

Further, in the integrated circuit device according to the present invention, an external input / output terminal is further provided, and a part or all of the external input / output terminal is connected to the functional circuit block via the programmable logic. What is connected.

According to the present invention, a part or all of the external input / output terminals are connected to the functional circuit block via the programmable logic, so that the IP
Test verification can be realized in (design assets) units.

Further, in the integrated circuit device according to the third aspect, the programmable logic is further divided into a plurality of blocks, and the divided blocks are connected by fixed wiring. .

According to the present invention, the programmable logic is divided into a plurality of blocks, and the blocks are connected by fixed wiring, thereby enabling high-density wiring between the blocks.

According to a fourth aspect of the present invention, in the integrated circuit device, the programmable logic comprises an FPGA.
(Field program gate array).

According to the present invention, by using an FPGA (field program gate array) as the programmable logic, test verification of a large-scale integrated circuit of several hundred thousand to one million gate levels and its countermeasures can be performed. .

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of an integrated circuit device according to the present invention will be described below in detail with reference to the accompanying drawings. The present invention is not limited by the embodiment.

As an integrated circuit device according to this embodiment, a system LSI will be described as an example. The system LSI here includes a plurality of IPs (Ins) on one chip.
teleproperty (design assets)
(Integration) of each IP connection and GLU
The design quality is improved by configuring the ELOGIC to be programmable.

FIG. 1 is a block diagram showing a first configuration of a system LSI according to an embodiment of the present invention. The system LSI 10 includes four functional blocks (A to D) 11, 12, 13, and 14, as shown. The input and output of each function block is a programmable P
LD (programmable logic dev)
ice). In particular, in this example, a large-scale FPGA (fie
ld programmable gateara
y) interconnected via 15;

The PLD (programmable logic device) has an arrangement of AND gates and an arrangement of OR gates, and has a structure in which the output of the AND gate is connected to the input of the OR gate. The structure of the arrangement of the AND gate and the OR gate is determined by the user electrically selecting and destroying the fuse formed on the chip. P
The number of available gates of the LD is limited to 2 to 3 k. When a large scale is required, for example, an FPGA (field programmable gate array) as shown in FIG. 4 is used.

The FPGA arranges a logic module composed of a basic logic circuit and unconnected wiring on a chip, and completes the wiring by a user using a program element.
This implements a desired function. For example, FP
As shown in FIG. 4, the GA 15 has logical blocks 30 of variable logical structure arranged in an array.
Between 0, a switch matrix 31 and a wiring channel 32 are provided. A programmable element (switch matrix 31) is used at the intersection of the logic structure determination in the logic block 30 and the wiring between the logic blocks. There are two methods of realizing a programmable element: a method using a switch transistor whose gate is connected to a memory cell, and an antifuse method in which a dielectric is sandwiched between two electrodes to cause dielectric breakdown by an electric pulse and conduct bidirectionally. The selection should be made in consideration of the features.

The functional blocks A to D are, for example, a microprocessor or a digital signal process (DSP) by utilizing an IP (design resource).
sor), a filter circuit, an input / output circuit, an interface circuit, and other various function libraries. Further, as a system LSI, for example, as a control LSI of a laser printer, a processor core, a cache memory,
It incorporates a core such as a PLL circuit. Alternatively, when a system LSI is used for a digital set top box, functional blocks such as an MPEG2 decoder, a D / A converter, a video encoder, a graphic engine, a stream decoder, a PLL, and a CPU core are highly integrated on one chip. Be mounted.

Now, the system L configured as described above
The desired function is verified in the SI. That is, for the functional blocks A to D, F having a logical block structure is used.
The PGA 15 performs a program in a state where the PGA 15 is incorporated in the device, and causes the respective functions to cooperate in parallel to execute different functions (specifications required by the mounted device) on one chip. Here, even if a timing defect occurs in the functional blocks A to D, a setup / hold problem can be dealt with by adjusting the number of gate stages in the FPGA 15.

When a fatal defect occurs in each of the functional blocks A to D, even if it is difficult to replace a part or all of the functions with the FPGA 15 (programmable logic), the functional block in which the defect has occurred Can be debugged by separating.

As described above, in an integrated circuit such as a system LSI including a plurality of function blocks and a GLUE LOGIC connecting the respective function blocks, a wiring between the blocks and a part or the whole of the GLUE LOGIC are set to P.
By configuring with LD / FPGA, even if a failure occurs in the test evaluation of the system LSI utilizing IP,
As described above, the countermeasure can be easily performed.

Next, an example in which test evaluation can be performed for each IP unit will be described. FIG. 2 is a block diagram illustrating a second configuration of the system LSI according to the embodiment of the present invention. This is a configuration in which an input / output terminal 16 is added to the configuration of FIG. 1 described above. That is, some or all of the input / output terminals 16 connected to the functional blocks A to D are connected via the FPGA 15 (programmable logic).

A configuration in which an input / output terminal 16 is added, and the input / output signals of each of the functional blocks A to D are programmed so as to be directly connected to the input / output terminal 16, so that the test in units of functional blocks, that is, in units of IP, Evaluation can be performed easily.

FIG. 3 is a block diagram showing a third configuration of the system LSI according to the embodiment of the present invention. Here, it is assumed that the FPGA is divided into four blocks as shown in the configuration of FIGS. 1 and 2 described above. That is, the function block A and the function block B are
Then, the functional block A and the functional block C are
Thus, the function block C and the function block D are
Then, the function block B and the function block D are
Connect with. Further, the above four FPGAs 17
As shown in the figure, to 20 connect the central part where the wiring is concentrated by a fixed line 21 having a high wiring density.

As described above, the FPGA is divided into a plurality of blocks, and the central portion where the wiring is concentrated between the blocks is connected by the fixed wiring 21 having a high wiring density, thereby facilitating the above-described test verification and its countermeasures. In addition to improving the performance, the central portion where the wiring is concentrated is wired with a high density, so that the chip size can be further reduced.

In this embodiment, the programmable logic has a gate size of several hundred thousand to one million or more gates.
PGA (field programmable ga)
Although the description has been made using the “tearray”, the PLD (programmable logic) is appropriately set according to the number of gates, for example, several k gates (low-end region).
device).

As described above, in this embodiment, the distribution I
By utilizing P (design assets), logic simulation (test verification) can be performed before or in parallel with the process of metal wiring of processors and DSPs on a single chip according to customer specifications. And its measures PLD
By using / FPGA, it is possible to provide a system LSI requested by a customer in a short time.

[0034]

As described above, according to the integrated circuit device of the present invention (claim 1), a plurality of functional circuit blocks are interconnected by a programmable logic capable of executing a program, thereby enabling each functional circuit block to be interconnected. When a timing defect occurs in a functional block, it is handled by adjusting the number of gate stages using programmable logic.On the other hand, when a fatal defect occurs in each functional circuit block, a part of the function or Even in cases where it is difficult to replace all of them with programmable logic, debugging can be performed by separating the functional circuit block in which the defect has occurred. The actual design evaluation can be performed via programmable logic, and the Measures are easily performed by the programmable logic, as a result, since allows the cycle of evaluation and measures in a short time increases its reliability, design quality is improved.

Further, according to the integrated circuit device of the present invention (claim 2), part or all of the external input / output terminals are
Since the configuration is such that connection is made to the functional circuit block via the programmable logic, it is possible to easily perform debugging in units of the functional circuit block arranged utilizing IP (design assets).

Further, according to the integrated circuit device of the present invention, the programmable logic is divided into a plurality of blocks, and each block is connected by fixed wiring, thereby providing a high-density circuit. Since wiring between the blocks can be performed, the chip size can be further reduced, and a small-sized integrated circuit can be provided.

Further, according to the integrated circuit device of the present invention (claim 4), the programmable logic is F
By using PGA (field program gate array), it is possible to test and verify a large-scale integrated circuit of several hundred thousand to one million gate levels, so that a large-scale circuit design is evaluated and measures taken in a short time. Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a first configuration of a system LSI according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a second configuration of the system LSI according to the embodiment of the present invention;

FIG. 3 is a block diagram showing a third configuration of the system LSI according to the embodiment of the present invention;

FIG. 4 is an explanatory diagram illustrating a configuration example of an FPGA according to the embodiment of the present invention;

FIG. 5 is a block diagram showing a configuration of a conventional system LSI.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 System LSI 11-14 Function block A-D 15, 17-20 FPGA 16 I / O terminal 21 Fixed wiring

Claims (4)

[Claims] 1. An integrated circuit device comprising: a plurality of functional circuit blocks; and a glue logic (GLUE LOGIC) for operating the functional circuit blocks in parallel and cooperatively. An integrated circuit device comprising a programmable logic for interconnecting a part or all of the integrated circuit. 2. The device according to claim 1, further comprising an external input / output terminal, wherein a part or all of the external input / output terminal is connected to the functional circuit block via the programmable logic. An integrated circuit device according to claim 1. 3. The integrated circuit device according to claim 1, wherein the programmable logic is divided into a plurality of blocks, and each of the divided blocks is connected by fixed wiring. . 4. The programmable logic according to claim 1, wherein
4. The integrated circuit device according to claim 1, wherein the integrated circuit device comprises a GA (field program gate array).