JP2001168298A - Development and production method of embedded integrated circuit - Google Patents

Abstract

(57) [Problem] To reduce the development period of a DRAM embedded LSI. SOLUTION: A memory chip 8 pre-manufactured by another process is mounted on a formation area of a memory unit of a prototyping chip 7 having a microcomputer unit function manufactured by a microcomputer manufacturing process to form a prototype inspection integrated circuit. Then, the result is evaluated. If the result is good, a final DRAM-embedded LSI is manufactured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a DRAM embedded LS.
The present invention relates to a method for developing and producing a hybrid integrated circuit such as I.

[0002]

2. Description of the Related Art Mixed-process LSIs have high commercial value in terms of space factor and performance and are attractive. In the LSI development maker, the LSI development time is more urgent in the development process to complete the LSI development than in the conventional LSI development. The reason is that the prototype technology time for the DRAM, Fe-RAM, and flash mixed process LSI is longer than the normal process LS.
This is because the length is longer than that of I.

For example, a normal LSI process of three weeks is more than doubled by incorporating a DRAM. Further, a microcomputer or the like in which a DRAM and a flash are mounted together has a more complicated process, and the development period is further extended. On the other hand, competition for accelerating the product development cycle is becoming increasingly intense, and the current situation is competing to increase the development speed of each company.

FIG. 4 shows a conventional DRAM embedded LSI.
The embedded LSI 2 placed in the package 1 is configured by connecting user input / output pads of a microcomputer section (hereinafter, referred to as a microcomputer section) to the electrode terminals 3 of the package 1 by wire bonding, TAB mounting, or the like. As shown in FIG. 5, the embedded LSI 2 forms a microcomputer section 5 and a memory section 6 having different processes on a single silicon substrate 4 by processing and processing an ordinary microcomputer process and a DRAM process sequentially to expose and diffuse. It is configured.

[0005]

As described above, the microcomputer 5 and the memory 6 having different processes are exposed and diffused to form a mixed L.
There is a problem that the work of trial manufacturing the SI2 requires a long development period. SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for developing and producing an embedded integrated circuit that can develop and provide an embedded LSI in a short time.

[0006]

The method for developing and producing an embedded integrated circuit according to the present invention, which can solve this problem, is based on the technical idea that a memory unit uses a chip that has been developed in advance, and is newly developed. It is a technical idea that after manufacturing only the chip of the microcomputer section by a normal process, these two chips are electrically connected chip-on-chip to evaluate and check.

[0007] If there is any unsatisfactory evaluation result, the microcomputer chip portion is re-manufactured, the two chips are electrically connected again on a chip-on-chip basis, and the evaluation is confirmed. It is a technical idea that it can be turned. According to a first aspect of the present invention, there is provided a method for developing and producing an embedded integrated circuit, which is used to develop and produce an integrated integrated circuit in which a memory unit and a microcomputer unit having different manufacturing processes are formed on a single substrate. In the formation area of the memory unit of the prototype chip manufactured by the process and equipped with the microcomputer unit function, a memory chip equipped with the function of the memory unit manufactured in advance by another process is mounted to form a prototype inspection integrated circuit, Verifying the operation of the prototype inspection integrated circuit, and using the mask layout of the prototype chip that satisfies the intended function to produce a hybrid integrated circuit in which a memory unit and a microcomputer unit are formed on a single substrate. .

According to a second aspect of the present invention, there is provided a method for developing and producing a hybrid integrated circuit according to the first aspect, wherein a non-defective memory chip which has been confirmed to operate correctly after completion of the diffusion inspection step is used. It is characterized in that the prototype chip is connected with the circuit surfaces facing each other via the connection electrode. According to a third aspect of the present invention, there is provided a method for developing and manufacturing an embedded integrated circuit according to the first or second aspect, wherein the pattern of the memory chip is a mirror inversion pattern of a pattern to be exposed when the embedded integrated circuit is formed. I do.

According to a fourth aspect of the present invention, there is provided a method for developing and producing an embedded integrated circuit according to the first or second aspect, wherein the user input / output pads of the prototype chip are connected to a user input / output pad arranged on the embedded integrated circuit. The layout is set at the same coordinates as the output pad. According to a fifth aspect of the present invention, there is provided an integrated circuit development and production method according to the first or second aspect, wherein the process of the prototype chip is performed by skipping only the process steps necessary for the function of the memory unit. Features.

According to a sixth aspect of the present invention, there is provided a method for developing and manufacturing an embedded integrated circuit, wherein a custom logic is manufactured as a prototype chip when manufacturing an integrated integrated circuit in which a memory section and a custom logic having different manufacturing processes are formed on a single substrate. Prototype chips manufactured in a process and equipped with a custom logic unit function are prepared, and a memory chip having a function of the memory unit manufactured in advance by another process and mounted in a formation area of the memory unit of the prototype chip is tested and inspected. Forming an integrated circuit, verifying the operation of the prototype inspection integrated circuit, and using the mask layout of the prototype chip that satisfies the desired function, producing a mixed integrated circuit with a memory section and a custom logic section formed on a single substrate It is characterized by doing.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for developing and producing an embedded integrated circuit according to the present invention will be described with reference to specific embodiments.
Figure 1 shows a microcontroller with embedded DRAM used for evaluation by prototype.
As shown in FIG. 1, a second chip 8 as a memory chip is connected to a first chip 7 as a prototype chip by bumps 9.

As shown in FIG. 2A, the first chip 7 has a prototype microcomputer section 10 formed on a silicon substrate 4. Reference numeral 11 denotes a “non-operating memory unit”. The "non-operating memory unit" 11 will be described in detail. In a conventional prototype process before mass production, a manufacturing process is performed in which a DRAM process for forming a memory unit and a microcomputer process for forming a microcomputer unit on a silicon substrate 4 are sequentially diffused. On the other hand, in this method of developing and manufacturing an embedded integrated circuit, the prototype microcomputer unit 10 and the memory unit 11 are formed by diffusion only in the microcomputer process. Unfortunately, the memory unit 11 of the DRAM does not operate. The “non-operating memory unit” 11 means that the mask does not change, but such a state occurs because the process is different.

The second chip 8 is a non-defective memory chip which has been confirmed to operate correctly after the diffusion inspection process, and is formed on the bump pads 13 formed on the second chip 8 and the first chip 7. Are connected to each other via the bumps 9 with the circuit surfaces facing each other. More specifically, the "non-operating memory unit" 11 of the first chip 7 and the second chip 8 are connected by an address signal and a data signal, a control signal necessary for reading and writing, a power supply, and a ground. Further, the connection signal is also electrically connected to the bump pad 12. The mask pattern of the memory unit 11 is designed so that it can be used as it is when a DRAM process is applied. Further, although it depends on the circuit configuration, when the memory unit 11 is diffused by the microcomputer process, the memory unit 1 is not affected.
The output of the memory unit 11 is configured to be high impedance by the output inhibition control of 1.

FIG. 3 shows a state before the package.
The arrangement of the bump pads 13 when viewed from the rear side is the same as the arrangement of the bump pads 12. Bump pad 1
No. 2 uses a mask layout laid out at the same coordinates as the user input / output pads arranged on the embedded integrated circuit to be finally produced. In order to arrange the pads in this manner, a general-purpose DRAM cannot match the pad density and the arrangement surface.
A chip is prepared so that it can be adapted to more microcomputers with embedded DRAM.

That is, unless the area of the memory section is smaller than the area of the microcomputer, the development concept cannot be applied well. Therefore, a dedicated small DRAM is prepared. D
The advantage of the RAM embedded microcomputer is that the signal line for connection to the DRAM can be inserted inside the LSI,
The data bus width between DRAM and microcomputer is a general-purpose DRA
M is generally wider than M, and the number of bumps is several hundred. The desire to reduce the size of the DRAM is inconsistent with the need to increase the number of pins,
Micro bumps with high density are used for the bumps.

As is apparent from the bump arrangements of FIGS. 2 and 3, the second chip 8 is not the same as the pattern of the memory section 11, but is mirror-inverted. This is the most important point of the present invention. Even if mirror inversion is not performed, a functionally similar product can be obtained, but it is an important technical idea to eliminate the difference in electrical characteristics.

As described above, the first chip 7 and the second chip 8 are operably connected to each other so that the second chip 8 and the "non-operating memory unit" 11 do not output each other. Mediated. A specific arbitration method is to control, via the bump pad 13, a control signal that disables the output of the “non-operating memory unit” 11 when the second chip 8 is connected. First chip 7
Side output control terminal is pulled down by high resistance,
If nothing is connected, output is permitted.

In order to connect the user input / output pad from the microcomputer section 10 of the first chip 7 to the electrode terminal of the package, an existing wire bond or TAB mounting method is used. Function evaluation is performed with the module in the state of FIG. If there is a problem with the microcomputer function, we will repeat the process of re-creating only the microcomputer and proceed with design verification.

If the quantity is not large, it is also an option to evaluate the return on investment by coping with small-scale production with this multi-chip module. As described above, according to the embodiment of the present invention, the DRAM portion in which the diffusion period is prolonged can be covered by the second chip 8 whose operation is already guaranteed.
It can be manufactured by a microcomputer process with a shorter diffusion period than that of.

Although a multi-chip module can be provided, a DRAM-embedded microcomputer is generally used in large quantities. After verifying operation, the chip shown in FIG. It operates even if there is no chip 8. Furthermore, DRAMs manufactured by the embedded process can be used for the main application of DRAM embedded microcomputers, but if speed and capacity are not enough,
Niche field in a multi-chip module state (narrow field)
It also has the property that it can be supplied to applications.

In the above description, a microcomputer equipped with a DRAM has been described as an example, but a flash memory, a Fe-RA
The same applies to a microcomputer embedded with processes such as M memory, EEPROM, and FPGA. Also, the newly developed part has been described as a microcomputer, but the same effect can be obtained even if the newly developed part is a custom logic.

Furthermore, the process of combining the DRAM and the flash microcomputer is a complicated and long process, so that the development method of the present invention is effective.

[0023]

As described above, the method for developing and producing an embedded integrated circuit according to the present invention is applied to the development and production of an integrated integrated circuit in which a memory section and a microcomputer section having different manufacturing processes are formed on a single substrate. A prototype inspection integrated circuit in which a memory chip having a function of the memory unit manufactured in advance by another process is mounted in a formation area of the memory unit of a prototype chip having a microcomputer unit function manufactured by a microcomputer manufacturing process. To verify the operation of the prototype inspection integrated circuit, and to produce a mixed integrated circuit in which a memory unit and a microcomputer unit are formed on a single substrate by using the mask layout of the prototype chip satisfying the intended function. LS with long diffusion process
I can be developed in a short time.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a package of a prototype inspection integrated circuit during execution of a method of developing and manufacturing an embedded integrated circuit according to the present invention.

FIG. 2 is a floor plan view of a prototype chip of the embodiment and a plan view of the memory chip viewed from a side opposite to a circuit surface;

FIG. 3 is a plan view showing a state in which a memory chip is mounted on a prototype chip;

FIG. 4 is a sectional view of a package of a conventional DRAM embedded LSI.

FIG. 5 is a floor plan diagram of a conventional DRAM embedded LSI.

[Explanation of symbols]

 Reference Signs List 4 silicon substrate 7 first chip (prototype chip) 8 second chip (memory chip) 9 bump 10 prototype microcomputer section 11 non-operational memory section 12 first chip bump pad 13 second chip bump pad

Claims (6)

[Claims] When developing and producing a hybrid integrated circuit in which a memory section and a microcomputer section having different manufacturing processes are formed on a single substrate, a prototype manufactured by the microcomputer manufacturing process and equipped with a microcomputer section function is manufactured. In the formation area of the memory portion of the chip, a memory chip mounted in advance by another process and having the function of the memory portion is mounted to form a prototype inspection integrated circuit, and the operation of the prototype inspection integrated circuit is verified. A method of developing and manufacturing an embedded integrated circuit for manufacturing an embedded integrated circuit in which a memory unit and a microcomputer unit are formed on a single substrate using a mask layout of the prototype chip satisfying the functions. 2. A non-defective memory chip that has been confirmed to operate correctly after the diffusion inspection process is performed, and the memory chip and the prototype chip are connected with their circuit surfaces facing each other via connection electrodes. Item 7. A method for developing and producing an embedded integrated circuit according to Item 1. 3. The method according to claim 1, wherein the pattern of the memory chip is a mirror-inverted pattern of a pattern to be exposed when the integrated circuit is formed. 4. An input / output pad for a user of a prototype chip,
3. The method according to claim 1, wherein the layout is set at the same coordinates as the user input / output pads arranged on the embedded integrated circuit. 5. The method according to claim 1, wherein the process of the prototype chip is performed by skipping only process steps necessary for the function of the memory unit. 6. In producing an embedded integrated circuit in which a memory section and a custom logic having different manufacturing processes are formed on a single substrate, a prototype chip manufactured by a custom logic manufacturing process and having a custom logic section function is produced as a prototype chip. Then, in a formation area of the memory portion of the prototype chip, a memory chip which is manufactured in advance by another process and has the function of the memory portion is mounted to form a prototype inspection integrated circuit, and the operation of the prototype inspection integrated circuit is verified. A method of developing and manufacturing an integrated circuit in which a memory unit and a custom logic unit are formed on a single substrate by using a mask layout of the prototype chip satisfying a desired function.