JP2001051025A - Program debugging apparatus for semiconductor test - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a program debugging apparatus which obtains a test result similar to that in a case where a program for semiconductor test is operated with respect to an actual semiconductor device to be inspected and by which the content of the program for semiconductor test can be verified accurately on the basis of the test result. SOLUTION: A test emulation part 140 operates a device test program 112 to be an object to be debugged under the operating system of a general-purpose computer, and a semiconductor testing apparatus is constituted in a pseudo manner. An HDL simulation part 150 simulates a semiconductor device on the basis of a file which is described by a hardware description language. The semiconductor device which is simulated by the HDL simulation part 150 becomes an ideal semiconductor device which is operated completely in the same way as a semiconductor device, to be inspected, which does not contain a defect due to its production. A test signal is supplied to the semiconductor device so as to be tested, the test signal is supplied to the ideal semiconductor device so as to be tested equally, and the accuracy of a debugging operation about whether a program for semiconductor test is operated normally can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor test program debug device for emulating a semiconductor test device to verify a test program.

[0002]

2. Description of the Related Art Conventionally, a semiconductor test apparatus has been known for performing a DC test, a function test, and the like on various semiconductor elements such as a logic IC and a semiconductor memory before shipment. The tests performed by the semiconductor test apparatus are roughly classified into a function test and a DC test. In the functional test, a predetermined test pattern signal is given to the semiconductor device under test, and whether or not the semiconductor device under test has performed an expected operation on the test pattern signal is inspected. The DC test is to check whether the DC characteristics of each terminal of the semiconductor device to be tested satisfy predetermined characteristics. For example,
A voltage application current measurement test that tests whether the expected current can be extracted from the terminal when a known voltage is applied, or when a known current flows or is extracted, the expected voltage is generated at the terminal. There is a current application voltage measurement test for testing whether or not there is. Further, even when performing a functional test, the voltage at the time of the high level is set to a regular voltage value,
A voltage lower than 4 volts may be set to 4 volts, or a voltage at a low level may be set to a normal voltage value, for example, 0.5 volts higher than 0 volts, or may be applied to the semiconductor device under test. Voltage conditions, current conditions, and the like are often changed.

[0003] When performing a functional test or a DC test, various conditions for performing what kind of test and under what conditions are preliminarily incorporated in a semiconductor test program.
By operating the semiconductor test program, various tests of the semiconductor device under test can be performed. However, a semiconductor test program has to control a wide variety of operations such as setting of test items, setting of test conditions, execution of a test, judgment of a test result, and the like, and is constructed by a program of enormous steps. . When the type of the semiconductor device to be inspected is changed or its logic is changed, the semiconductor test program must be variously changed in accordance with the change. When a semiconductor test program is newly created or changed, it must be evaluated whether the program itself operates properly or not. As one such method, a semiconductor test program is operated on a semiconductor device to be inspected whose quality is known in advance using an actual semiconductor test apparatus, and the program is evaluated. However, since the semiconductor test equipment itself is expensive and the number of installed semiconductor test equipment is small, evaluating whether or not the semiconductor test program normally operates using the actual semiconductor test equipment requires a semiconductor test line. Stopping is not preferable. Therefore, conventionally, instead of using a real semiconductor test device to evaluate a semiconductor test program, the semiconductor test device is emulated using a general-purpose computer such as a workstation, and the semiconductor test program is normally used. It was verified whether or not it was operating.

[0004] As a device for emulating a semiconductor test apparatus in this way, there is one described in, for example, Japanese Patent Application Laid-Open No. 9-185519. This relates to a debugging device for testing whether or not a semiconductor test program operates normally. This configures a pseudo semiconductor test apparatus by operating a semiconductor test program to be debugged under an operating system of a general-purpose computer. A virtual device under test, a test condition setting unit, a test item setting unit, a test result storage unit, and the like are connected to the pseudo semiconductor test device via an interface unit, and virtual data set in the virtual device under test is connected. Is read in accordance with the test conditions set in the test condition setting unit, thereby performing a pseudo functional test and a DC test.

[0005]

The conventional debugging apparatus described above does not use an actual semiconductor device under test but performs a functional test using a semiconductor test program using the actual semiconductor device under test. Couldn't do as well. For this reason, when trying to debug a semiconductor test program, it is not possible to sufficiently determine a logic transition according to the function of the semiconductor device under test and a match / mismatch with an expected value. The contents of the test program could not be verified accurately.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide the same test results as when a semiconductor test program is operated on an actual semiconductor device under test. It is another object of the present invention to provide a semiconductor test program debug device capable of accurately verifying the contents of a semiconductor test program based on the test results.

[0007]

According to a first aspect of the present invention, there is provided a semiconductor test program debugging apparatus for testing a semiconductor device to be inspected based on a semiconductor test program. Tester emulation means for generating a signal in a pseudo manner to emulate the operation of the semiconductor test apparatus, and simulating the semiconductor device under test based on a hardware description language, and simulating the semiconductor device under test Supplying the test signal output from the tester emulation means to
A hardware description language simulating unit for simulating and outputting a signal output from the semiconductor device under test in response to the supply of the test signal; and a hardware description language simulated by the hardware description language simulating unit. Debugging means for debugging the semiconductor test program based on a signal output from the test semiconductor device.

The tester emulation means operates a semiconductor test program to be debugged under an operating system of a general-purpose computer, and simulates a semiconductor test apparatus. The hardware description language simulating means is Verilog-HDL or V
This simulates a semiconductor device based on a file described in a hardware description language such as HDL. Therefore, the semiconductor device simulated by the hardware description language simulating means is an ideal semiconductor device that operates in exactly the same manner as the semiconductor device to be inspected which does not include a defect due to manufacturing. Supplying and testing a signal is equivalent to supplying and testing a test signal for an ideal semiconductor device, and increasing the debugging accuracy of whether or not a semiconductor test program operates normally. Becomes possible.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor test program debug device according to the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing the overall configuration of a semiconductor test program debug device. The debug device 100 is for emulating the operation of the semiconductor test device and simulating the operation of the semiconductor device under test to verify whether the semiconductor test program operates normally. And a general-purpose computer such as a workstation.

[0010] A debugging device 100 according to this embodiment.
Simulates the operation of the actual semiconductor test apparatus and the semiconductor device under test, and therefore, before giving a detailed description, the configuration of the simulated semiconductor test apparatus will be described.

FIG. 2 is a diagram showing the entire configuration of an actual semiconductor test apparatus. FIG. 3 shows a state in which an actual semiconductor device under test 250 is connected to the semiconductor test apparatus 200. The semiconductor test apparatus 200 performs various direct current tests (DC parametric tests) and functional tests on the semiconductor device 250 to be inspected. The semiconductor test apparatus 200 includes a tester control unit 210, a tester bus 23,
0, tester body 240, semiconductor device under test 250
And a socket portion (not shown) for mounting the same.

The tester control section 210 includes a tester main body 240
And a semiconductor test program (device test program) 212, an application program 214, a language analysis execution unit 216, a tester library 218, and a tester bus driver 220.

The device test program 212 describes the procedure and method for performing a test on the semiconductor device under test 250 by the user using the semiconductor test apparatus 200. Generally, this device test program is developed and created by a user of the semiconductor test apparatus 200. Therefore, the user verifies whether or not the device test program 212 created by himself / herself operates normally without using the actual semiconductor test apparatus 200 by using the debug apparatus 100 according to the present embodiment. Device test program with high performance. Language analysis execution unit 216
Plays a central role in performing a syntax analysis of the device test program 212 and faithfully operating the semiconductor test apparatus 200 according to the device test program 212. The application program 214
Device test program 212 and language analysis execution unit 2
16 in cooperation with the semiconductor device under test 250. The test signals and the like corresponding to the functional test and the DC test are applied to the semiconductor device under test 250, and the output signals are taken in to determine the quality of the semiconductor device under test 250. Judgment and analysis of characteristics. The tester library 218 converts the instruction of the device test program 212 after the syntax analysis is performed by the language analysis execution unit 216 into a register-level instruction (a data write instruction to a register 242 and a data read instruction from the register 242 described later). ) To create and set data necessary for the operation of the semiconductor test apparatus 200,
A measurement operation is instructed for 0. Tester bus driver 2
20 transfers the data created by the tester library 218 to the register 242 in the tester main body 240 via the tester bus 230.

The tester main body 240 performs various tests on the semiconductor device under test 250 based on the data from the tester control section 210 taken in via the tester bus 230. The tester main body 240 includes a register 242, a memory 244, and a test execution unit 246.
The register 242 stores data from the tester library 218 fetched via the tester bus 230.
The data stored in the register 242 is output to the test execution unit 246 directly or via the memory 244. Further, the register 242 and the memory 244 have a test result storage area (not shown) for storing data relating to the test result from the test execution unit 246.

The test execution unit 246 includes the function test execution unit 24
7 and a DC parametric test execution unit 248. The test execution unit 246 includes the register 242 and the memory 2
A functional test or a DC parametric test is performed on the semiconductor device under test 250 based on the data from the tester library 218 stored in the tester library 44, and the test result data is stored in the test result storage area of the register 242 or the memory 244. Store. The test result data stored in the register 242 and the memory 244 is directly taken into the tester library 218 by the tester driver 220 via the tester bus 230. The test result data stored in the memory 244 is taken into the tester library 218 via the register 242.

The debug apparatus 100 shown in FIG. 1 emulates the entire operation of the semiconductor test apparatus 200 and simulates the operation of the semiconductor device under test 250. Therefore, when the device test program 112 created for the semiconductor test apparatus 200 is executed by using the debug apparatus 100 of FIG. 1, it is checked whether or not the operation of the device test program 112 matches the one intended by the user. Can be. Next, the configuration of the debugging device 100 according to this embodiment will be described.

The emulator control unit 110 shown in FIG.
It includes a device test program 112, an application program 114, a language analysis execution unit 116, a tester library 118, and a tester bus emulator 120. The emulator control unit 110 is for controlling the operation of the tester emulation unit 140, and basically performs the same operation as the tester control unit 210 included in the semiconductor test apparatus 200 shown in FIG.

The device test program 112 uses the semiconductor test apparatus 200 to read the semiconductor device 25 to be inspected.
This describes a procedure and a method of what kind of test is to be performed on 0, and is a program to be debugged by the debug device 100. Therefore, the device test program 212 in FIG. 2 is directly ported as the device test program 112 and configured to perform the same operation. Application program 114, language analysis execution unit 116, and tester library 1
Similarly, the application program 214, the language analysis execution unit 216, and the test library 218 of FIG. 2 are ported as they are and configured to perform the same operation. The tester bus emulator 120 drives a virtual tester bus 130 that virtually connects the emulator control unit 110 and the tester emulation unit 140,
The tester library 1 via the virtual tester bus 130
18 and the tester emulator 140 are controlled.

The tester emulation unit 140 realizes the operation of the tester main unit 240 shown in FIG. 2 by software, and responds to an operation instruction of the tester library 118 in the emulator control unit 110 by using a hardware description language (HD).
L) A simulated test for the simulator 150 is performed.
The tester emulation unit 140 includes a virtual register 142, a virtual memory 144, and a virtual test execution unit 146. The virtual register 142 stores data from the tester library 118. This virtual register 14
2 is stored directly or in the virtual memory 14.
4 to the virtual test execution unit 146. Further, the virtual register 142 and the virtual memory 144 have a test result storage area (not shown) for storing virtual test result data output from the virtual test execution unit 146.

The virtual test execution unit 146 includes a function test execution unit 147 and a DC parametric test execution unit 148. This virtual test execution unit 146 stores the virtual register 1
A predetermined signal is output to the HDL simulation unit 150 based on the data from the tester library 118 stored in the storage unit 42, and a function test by the function test execution unit 147 and a DC parametric test by the DC parametric test execution unit 148 are performed. And stores the virtual test result data in the test result storage area of the virtual register 142 or the virtual memory 144. Virtual register 142 and virtual memory 14
4 is output to the tester library 118 via the virtual tester bus 130.
The test result analysis determination unit 160 compares the virtual test result data stored in the virtual register 142, the virtual memory 144, or the tester library 118 with the expected value of the expected test result, and
Verifies whether is operating normally and displays the result to the user. For example, if an erroneous test result is obtained by executing the device test program 112, the line number of the program causing the erroneous test result is displayed on a monitor (not shown), or a printer (FIG. (Not shown).

Next, the operation of the tester emulation section 140 will be described. When an access to the virtual register 142 is input from the virtual tester bus 130, the tester emulation unit 140 calculates which part of the virtual register 142 the access is based on the address of the virtual register 142, and Write data and read data from that location. Further, when an access to the virtual memory 144 occurs through the access of the virtual register 142, the tester emulation unit 140 writes data to and reads data from the unique virtual memory 144. In this case, generally, only one virtual register 142 cannot obtain enough information to read / write data from / to the virtual memory 144. Therefore, in this embodiment, the tester emulation unit 140 reads and writes data from and to the virtual memory 144 by referring to the contents of the associated virtual register 142. The semiconductor test apparatus 200 shown in FIG.
When the same processing as that described above is performed, the virtual test result data stored in the virtual memory 144 is output to the tester library 118 via the virtual register 142 and the virtual tester bus 130. May be configured to directly output the virtual test results stored in the virtual memory 144 to the tester library 118.

When a register for starting generation of a waveform (functional test) is accessed with respect to the tester emulation unit 140, the virtual test execution unit 146 is executed in the first task.
Performs waveform generation processing. At this time, since the data necessary for waveform generation is stored in the virtual register 142 and the virtual memory 144 in advance, the virtual test execution unit 14
6 generates a waveform with reference to it. The waveform generated by the virtual test execution unit 146 is stored in a programming language interface (PLI: Programming Language In).
terface) 149, 151 to the HDL simulation unit 150. The HDL simulation unit 150 simulates exactly the same operation as the actual semiconductor device under test 250 based on the input waveform. The output pin data simulated by the HDL simulating unit 150 is fed back to the virtual test executing unit 146, where it is compared with an expected value, and the result is stored in a predetermined virtual register 142 and virtual memory 144. The above-described series of operations is executed and executed in each operation cycle of the tester emulation unit 140.

The HDL simulation unit 150 is a
It simulates a semiconductor device based on a file described in a hardware description language such as log-HDL or VHDL. In other words, the HDL simulation unit 150 performs the Verilog-HD at the time of designing the actual semiconductor device under test 250 shown in FIG.
Since the semiconductor device of the product itself is simulated based on the L file or the VHDL file, the simulated semiconductor device operates exactly the same as the semiconductor device under test 250 without any defects due to manufacturing. It becomes an ideal semiconductor device. Therefore, the tester emulation unit 140 performs a test on such an ideal semiconductor device. The HDL simulation unit 150 and the virtual test execution unit 14
6, the programming language interface 14
9 and 151 for exchanging test signals and test results.

The tester emulation section 140 does not simulate the logic components constituting the tester one by one, but focuses on the properties of the tester and converts the waveform data mainly with the timing data and the waveform format. One cycle of the event format is created and supplied to the HDL simulation unit 150. HDL simulator 150
Simulates the logic components that constitute it one by one in an event-driven manner and executes until one tester cycle is completed. When one tester cycle is completed, the simulation is terminated while the internal state is maintained, and the output change during the cycle is transferred to the tester emulator 140 in the form of an event. The tester emulation unit 140 analyzes the output change for one cycle from the HDL simulation unit 150 again, compares it with the expected value, and determines the pass / fail judgment result in the virtual register 142.
Or in the virtual memory 144. By performing such an operation, the efficiency of waveform generation by the tester emulation unit 140 is improved. Further, since data is processed for each cycle, data transfer efficiency is improved. In some cases, a plurality of cycles may be processed collectively.

The above-described emulator control unit 110 and tester emulation unit 140 serve as tester emulation means, and the hardware description language simulation unit 150 serves as an HD.
The test result analysis / judgment unit 160 corresponds to the L simulation unit and the debugging unit, respectively.

The operation of the debugging device 100 shown in FIG. 1 will be described with reference to the drawings. FIG. 3 shows a device test program 1 for a DC test (DC parametric test) or a function test.
12 is a flowchart showing an operation procedure of the debugging device 100 when Step 12 is executed. This flow starts when a user instructs a debugging operation of the device test program 112. First, in step 100, the device test program 1 to be debugged
12 is executed. Next, at step 101, the language analysis execution unit 116 in the emulator control unit 110 analyzes the syntax of the device test program 112. After the syntax analysis is performed by the language analysis execution unit 116,
The tester library 118 converts the instructions of the device test program 112 into register-level instructions, creates data necessary for the operation of the debugger 100 based on the instructions, and uses these data as virtual registers 142 in the tester emulator 140. To be stored. Virtual register 142
When the data has been stored in the emulator, the emulator controller 110 instructs the tester emulator 140 to perform a measurement operation in step 103.

The tester emulator 140, which has received a measurement operation instruction from the emulator controller 110, performs a pseudo functional test on the HDL simulator 150 in response to an operation instruction of the tester library 118 in the emulator controller 110. Alternatively, a direct current test (DC parametric test) is performed. Specifically, in step 104, the function test execution unit 147 or the DC parametric test execution unit 148 in the virtual test execution unit 146 stores the data in the virtual register 142 according to the operation instruction of the tester library 118 in the emulator control unit 110. A predetermined test signal based on the obtained data is output to HDL simulation section 150. Step 1
05, the HDL simulation unit 150
A test signal is applied to the semiconductor device under test simulated based on the g-HDL file or the VHDL file, a functional test or a direct current test (DC parametric test) is performed, and a measured value corresponding to the test result is output. . When the measurement value is output from the HDL simulation unit 150, in step 106, the function test execution unit 147 or D
The C parametric test execution unit 148 stores the measured value in the virtual register 142 or the virtual memory 148 as virtual test result data. The virtual test result data stored in the virtual register 142 or the virtual memory 148 is output to the tester library 118 in the emulator control unit 110 in step 107, and the tester library 118 executes a predetermined process corresponding to the virtual test result data. Do.

Since the device test program 112 describes in advance what operations to perform in response to various measurement results, the processing performed by the tester library 118 in response to the virtual test result data is as follows. If it is intended by the program creator, it is verified that there is no error in the corresponding portion of the device test program 112. Conversely, if the processing performed by the tester library 118 in response to the virtual test result data is not the one intended by the program creator, it is verified that there is an error in the corresponding portion of the device test program 112. Thus, the debugging operation of the device test program 112 is performed.

As described above, the HDL simulation unit 150
Simulates a semiconductor device based on a Verilog-HDL file or a VHDL file at the time of designing the actual semiconductor device under test 250, and performs a test on an ideal semiconductor device having no manufacturing error or manufacturing defect. Therefore, there is less variation than when a non-defective semiconductor device actually manufactured is used, the operation at the time of testing can be accurately emulated, and the debugging accuracy of the device test program 112 can be improved. Can be increased.

Further, in the above-described embodiment, the debug apparatus 100 for debugging a device test program for testing the semiconductor device under test 250 has been considered, but the type of the semiconductor device to be tested is Ver.
Various devices such as a semiconductor memory specified by an ilog-HDL file or a VHDL file, various processors, and an IC for logic can be considered.

In the above-described embodiment, the Verilog-time at the time of designing the actual semiconductor device under test is described.
The case where the semiconductor device is simulated based on the HDL file or the VHDL file has been described.
The semiconductor device may be simulated using a Verilog-HDL file or a VHDL file specially created for debugging a semiconductor test program.

Further, in the above-described embodiment, the case where the semiconductor test program is debugged has been described.
Verilog using official semiconductor test program
-Verilog-HDL or VHDL files may be debugged by testing simulated semiconductor devices based on HDL or VHDL files.

[0033]

As described above, according to the present invention, the same test result as when a semiconductor test program is operated on an actual semiconductor device under test is obtained, and based on this test result, This has the effect that the contents of the test program can be verified accurately.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an overall configuration of a debugging device according to an embodiment.

FIG. 2 is a diagram illustrating an overall configuration of a semiconductor test apparatus.

FIG. 3 is a flowchart showing an operation procedure of the debug device when a device test program is executed.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 debug device 110 emulator control unit 112 device test program 140 tester emulation unit 146 virtual test execution unit 147 functional test execution unit 148 DC parametric test execution unit 150 HDL simulation unit 149, 151 programming language interface 160 test result analysis determination unit

Continuation of the front page F term (reference) 2G032 AA01 AA07 AB01 AC08 AD02 AE12 AL00 5B042 HH07 5B048 AA20 BB05 DD04 DD15

Claims (3)

[Claims] 1. A tester emulation means for generating a test signal applied to a semiconductor device under test based on a semiconductor test program to emulate the operation of a semiconductor test apparatus, and a hardware description language. Simulates the semiconductor device under test based on the test signal output from the tester emulation means to the simulated semiconductor device under test, and supplies the test target device according to the supply of the test signal. Hardware description language simulating means for simulating and outputting a signal output from a semiconductor device for use, and based on a signal output from the semiconductor device under test simulated by the hardware description language simulating means. Debugging means for debugging the semiconductor test program. In semiconductor test program debugging apparatus characterized by being configured. 2. The semiconductor test device according to claim 1, wherein the hardware description language simulating unit simulates the semiconductor device under test based on Verilog-HDL as the hardware description language. Program debugging device. 3. The semiconductor test program debug according to claim 1, wherein said hardware description language simulation means simulates said semiconductor device under test based on VHDL as said hardware description language. apparatus.