JP2000183051A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Abstract

(57) Abstract: Provided is a semiconductor device having an interlayer insulating film having improved adhesion at an interface between an organic insulating film and an inorganic insulating film. SOLUTION: A porous silica layer is formed over the entire surface 2S of a lower insulating layer 2. A paste-like hydrogenated silsesquioxane (HSQ) is applied on the exposed surface of the porous silica layer by a spin coating method, and is fired in a nitrogen atmosphere at about 400 ° C. Next, a silicon oxide film is formed on the exposed surface of the HSQ film by a plasma CVD method. Then, using photolithography technology, a U-shaped wiring groove 21 is formed from the exposed surface of the silicon oxide film to the connection hole 17 in the surface 2S of the lower insulating layer 2 and a region in the vicinity thereof. Thereby, the porous silica layer 3, the HSQ film 4, and the silicon oxide film 5 are formed. The inside of the U-shaped wiring groove 21 is filled with the wiring layer 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a structure of an interlayer insulating film composed of a multilayer film including an organic low dielectric constant porous film and a method of manufacturing the same.

[0002]

2. Description of the Related Art In a logic device of the sub-quarter micron generation or later, in order to increase the speed of a device or a semiconductor device, it is important to reduce a signal delay in the device. The signal delay of such a device is given by the sum of the signal delay of the element itself such as a transistor constituting the device and the wiring delay of the wiring connecting between the elements. In recent years, as the wiring pitch has been rapidly reduced, the influence of the wiring delay has become dominant over the signal delay of the device rather than the signal delay of the transistor. This is because the wiring delay is the product of RC (resistance ×
This is because the increase in the interlayer capacitance becomes remarkable as the wiring pitch decreases. As a countermeasure to reduce wiring delay, reduction of wiring resistance or capacitance of interlayer insulating film is conceivable. As one of such measures, research and development of applying a low dielectric constant material to interlayer insulating film is actively pursued. Is being done.

As a first prior art, FIG. 9 shows a schematic longitudinal sectional view of a multilayer wiring structure using a low dielectric constant interlayer film. FIG. 9 shows the structure of the Proceedings of the International
Interconnect Technology Conference 1998, pp146-148
Based on the multilayer wiring structure disclosed in FIG. As shown in FIG. 9, each of the adjacent first metal wirings 111 is electrically separated by a first interlayer insulating film 101 made of a silicon oxide film. The first metal wiring 111 is connected to the second metal wiring 112 via the third metal wiring 113 filled in the connection hole 113H. At this time, the adjacent third metal wires 113 are connected to the first interlayer insulating film 101.
Second interlayer insulating film 1 made of a low dielectric constant material disposed thereon
02 and a third interlayer insulating film 103 made of a silicon oxide film disposed on the second interlayer insulating film 102. Further, each second metal wiring 112 is insulated by a fourth insulating film 104 made of a low dielectric constant film.
Then, the second metal wiring 112 and the fourth interlayer insulating film 104
A fifth interlayer insulating film made of a silicon oxide film. As described above, the second and fourth interlayer insulating films 1 among the first to fifth interlayer insulating films 101 to 105 are formed.
02 and 104 are low dielectric constant interlayer films.
Note that a silicon nitride film may be used as an inorganic insulating film instead of the silicon oxide film.

Next, a semiconductor device 251 according to a second prior art will be described with reference to FIG.

[0005] As shown in FIG.
The gate insulating films 212a and 212b of the MOSFET are arranged at predetermined positions on the surface 201S of the gate insulating film 212a.
11a and 211b are arranged. Further, a MOSF is formed in a region within the surface 201S of the silicon substrate 201 and between the two gate insulating films 212a and 212b.
A diffusion layer 213 forming source / drain regions of ET is formed.

Further, the surface 201S of the silicon substrate 201
The insulating layer 202c is arranged so as to cover. However, as shown in FIG. 10, the insulating layer 202c is arranged except for a portion of the contact hole 217 from the surface 202cS to the diffusion layer 213. At this time, the barrier metal film 214 is disposed on the inner surface 217S of the U-shaped wiring groove formed by the side wall surface of the contact hole 217 and the surface 201S, and the barrier metal film 214 is formed.
A metal plug 215 made of a metal material is arranged on the surface 214 </ b> S so as to fill the inside of the contact hole 217. The surfaces at the same height level as the surface 202cS of the insulating layer 202c of the barrier metal film 214 and the metal plug 215 are collectively referred to as “surface 216”.
S ".

[0007] A porous silica layer 203 having a large number of holes 203V therein is formed on the surface 202cS of the insulating layer 202c except for the vicinity of the contact hole 217.
Is arranged. The porous silica layer 203 is an organic low dielectric constant material containing a carbon atom. Porous silica, which is an organic insulating material, does not have a sufficient film quality as an interlayer insulating film by itself, so that the porous silica layer 203 is used to supplement the insulating properties of the porous silica.
A silicon oxide film 205 is arranged on the surface 203S. The silicon oxide film 205 is formed by a plasma CVD method.

The surface 216S and the insulating layer 20
2c composed of the surface 202cS of the 2c and the side walls of the porous silica layer 203 and the silicon oxide film 205.
The barrier metal layer 206 is disposed on the inner surface 221S of the U-shaped wiring groove 221 and the metal wiring 207 is disposed on the surface 206S of the barrier metal layer 206, so that the inside of the U-shaped wiring groove 221 is filled.

[0009]

When a so-called organic low dielectric constant material is applied as an interlayer insulating film, a silicon oxide film, a silicon nitride film or the like formed in contact with the organic (interlayer) insulating film is used. May have low adhesion to so-called inorganic (interlayer) insulating films. Such a decrease in adhesiveness is caused by the fact that the inorganic insulating film such as the silicon oxide film has a plasma C property.
It is remarkable when formed by the VD method, and the mechanism is considered as follows.

When an inorganic insulating film such as a silicon oxide film is formed on the surface of an organic insulating film by a plasma CVD method, (i) the organic insulating film is formed of oxygen such as oxygen ions and oxygen radicals in the plasma. And (ii) the formation temperature of the inorganic insulating film is high (to such an extent that the organic component is decomposed by reacting with the active species of oxygen), and Organic components in the system insulating film are decomposed to generate gases such as CO ₂ and H ₂ O. Then, the gas accumulates at the interface between the organic insulating film and the inorganic insulating film, and as a result, the adhesion between the two insulating films at the interface becomes low. Note that even when the inorganic insulating film is formed by a film forming method other than the plasma CVD method, the above-described decomposition of the organic component can occur if the conditions (i) and (ii) are satisfied.

Here, the film formation temperature when forming a silicon oxide film on the surface of porous silica by the plasma CVD method, and the methyl group (CH ₃ ) in the porous silica before and after the formation of the silicon oxide film. FIG. 11 shows the relationship with the rate of decrease of. In FIG. 11, the reduction rate of the methyl group in the porous silica can be regarded as the amount of generation of the above-mentioned gas such as CO ₂ . As shown in FIG. 11, it can be seen that the reduction rate of the methyl group in the porous silica after the formation of the silicon oxide film, that is, the content of the methyl group strongly depends on the film formation temperature of the silicon oxide film. And plasma CV
Considering that the film forming temperature when forming a silicon oxide film by the method D is generally about 400 ° C., all the methyl groups in the porous silica are decomposed under such film forming conditions. I understand.

Further, when the semiconductor device 251 shown in FIG. 10 is manufactured, the silicon oxide film 20 is directly formed on the surface of the porous film such as the porous silica layer 203 by using the plasma CVD method.
In the case of depositing No. 5 or the like, there are the following problems.
That is, the plasma CVD method cannot sufficiently reduce the surface unevenness due to the pores 203V of the surface 203S of the porous silica layer 203, which is a porous film. The surface shape of the opposite surface 205S reflects the surface unevenness of the surface 203S of the porous silica layer 203.

The same applies to the prior art proposed in Japanese Patent Application Laid-Open No. 9-199490. That is,
In the related art, since an insulator corresponding to the silicon oxide film 205 is formed by a thermal CVD method, when the insulator is formed on the porous film, the surface of the insulator corresponds to the surface unevenness of the porous film. It has a rough surface shape.

When the flatness of the porous silica layer 3 or the silicon oxide film or the like formed on the porous film 3 is not ensured, the semiconductor device 251 shown in FIG. In addition, when a wiring layer and an insulating layer are further formed to form a multilayer wiring structure as shown in FIG. 9, a case may occur in which good insulating characteristics of the interlayer insulating film cannot be obtained.

As described above, when the adhesiveness between the interlayer insulating films is reduced and the interlayer insulating film lacks the flatness in the multilayer wiring structure, the function as the interlayer insulating film in the portion is not sufficiently exhibited, and As a result, a malfunction occurs in the operation of the semiconductor device or device.

Therefore, the present invention has been made to solve such a problem, and the present invention is directed to a method of forming a flat film even on the surface of an organic low-permittivity porous film having a concave-convex shape formed by pores in the film. It is a first object of the present invention to provide a method for manufacturing a semiconductor device capable of forming a simple insulating film.

In addition to the realization of the first object, an interlayer insulating film capable of improving the adhesion at an interface between an interlayer insulating film made of an organic low dielectric constant porous film and an inorganic interlayer insulating film as compared with the conventional one. A second object is to provide a method for manufacturing a film.

It is a third object of the present invention to provide a semiconductor device capable of executing a predetermined operation reliably by realizing the first and second objects.

[0019]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: preparing a substrate having a predetermined element formed on a surface thereof; Forming a first insulating film, which is an organic-based low-dielectric-constant porous film, and a forming method capable of forming a flat film on the film-forming surface without depending on the unevenness of the film-forming surface. Forming a second insulating film on the surface of the first insulating film opposite to the substrate.

(2) The method for manufacturing a semiconductor device according to the invention described in claim 2 is the method for manufacturing a semiconductor device according to claim 1, wherein the second insulating film has an active species of oxygen. In an atmosphere or at a temperature lower than the temperature at which the active species of oxygen and the organic component in the first insulating film can react with each other,
It is characterized by forming.

(3) The method of manufacturing a semiconductor device according to the third aspect of the present invention is the method of manufacturing a semiconductor device according to the first or second aspect, wherein the step of forming the second insulating film includes the step of: A step of applying a paste-like material, which is a raw material of the second insulating film, onto the surface of the first insulating film by a spin coating method.

(4) The method for manufacturing a semiconductor device according to the invention described in claim 4 is the method for manufacturing a semiconductor device according to claim 1 or 2, wherein the second insulating film is formed by self-planarizing C.
It is characterized by being formed by the VD method.

(5) The method for manufacturing a semiconductor device according to the invention described in claim 5 is the method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein The method further includes a step of forming a third insulating film by a plasma CVD method on a surface opposite to the one insulating film.

(6) A semiconductor device according to a sixth aspect of the present invention is manufactured by the method of manufacturing a semiconductor device according to any one of the first to fifth aspects.

[0025]

(First Embodiment) FIG. 1 is a longitudinal sectional view schematically showing a structure of a semiconductor device 51 according to a first embodiment. Here, a structure in which the semiconductor device 51 has a MOSFET as a (semiconductor) element will be described. However, since the semiconductor device 51 is characterized by the structure of an interlayer insulating film, the element is, for example, a bipolar transistor or an integrated circuit including the same. It does not matter.

As shown in FIG. 1, a semiconductor device 51 has a silicon substrate 1, and gate insulating films 12a and 12b made of, for example, a silicon oxide film are formed at predetermined positions on a surface 1S of the silicon substrate 1. ing. Gate electrodes 11a and 11b are formed on the respective surfaces of the gate insulating films 12a and 12b opposite to the surface 1S. Further, a MOSFET having the gate electrode 11a and the gate insulating film 12a and the MOSFET having the gate electrode 11b and the gate A diffusion layer 13 (forming a source region or a drain region) common to the MOSFET having the film 12b is formed.

Then, the gate electrodes 11a and 11b, the gate insulating films 12a and 12b, and the surface 1S of the silicon substrate 1
An insulating layer 2c made of, for example, a silicon oxide film is formed so as to cover. At this time, a connection hole or a contact hole 17 is formed in a predetermined region from the surface 2 cS of the insulating layer 2 c opposite to the silicon substrate 1 to the diffusion layer 13.
Is formed, and the insulating layer 2c is not provided in such a predetermined region. Connection hole 1 formed of a region in contact with connection hole 17 in the side wall surface of connection hole 17 and surface 1S of silicon substrate 1
7, on the inner surface 17S, for example, titanium nitride (TiN),
Titanium (Ti), tantalum (Ta), tantalum nitride (T
aN) or a barrier metal film 14 made of tungsten nitride (WN) or the like. Further, the entire surface of the barrier metal film 14 is not in contact with the inner surface 17S,
In addition, a metal plug 15 made of a metal material such as copper is formed on the surface 14S along the inner surface 17S, and the inside of the connection hole 17 is filled. The barrier metal film 14 and the metal plug 1 filling the connection hole 17 are formed.
5 is also collectively referred to as “wiring layer 16”. Further, in the following description, components in a region from the surface 1S of the silicon substrate 1 to the surface 2cS of the insulating layer 2c, that is, elements (the MOSFET in the semiconductor device 51 of FIG.
The diffusion layer 13 which is formed in the S and forms a part of the MOSFET may be included), the insulating layer 2c and the wiring layer 16 are also collectively referred to as "lower insulating layer 2". At this time, the insulating layer 2
c and the surface 16S of the wiring layer 16 at the same plane level as the surface 2cS.
Surface 2S ".

Further, in the semiconductor device 51, the lower insulating layer 2
The surface of the wiring layer 16 except for the surface 16S of the wiring layer 16 and a region near the surface 2S of the wiring layer 16 is covered with an organic low dielectric constant porous film (first
A porous silica layer (hereinafter, also referred to as “porous silica layer 3”) is formed as the insulating film 3. Hereinafter, the organic low-permittivity porous film is also simply referred to as “porous film”. Note that FIG. 1 schematically illustrates a large number of holes 3V included in the porous silica layer 3. The porous silica layer 3, which is a porous material, has a lower film density than a dielectric material having no vacancies due to the vacancies 3V present in the film, and thus the dielectric material having no vacancies is used. Lower dielectric constant than material.

In particular, on the surface 3S of the porous silica layer 3 opposite to the surface 2S, a barrier film or a decomposition preventing film (second insulating film) 4, which is a hydrogen silsesquioxane (HSQ). Membrane (hereinafter referred to as “H
SQ film 4). The main component of the HSQ film is a silicon oxide, and the HSQ film is an inorganic insulating film containing no organic component. Then, a silicon oxide film (third insulating film) 5 corresponding to the silicon oxide film 205 in the conventional semiconductor device 251 of FIG. 10 is formed on the surface 4S of the barrier film 4 opposite to the surface 3S. The silicon oxide film 5 (formed by a plasma CVD method as described later) has a role of supplementing the insulation between the porous silica layer 3 and the HSQ film 4. The dielectric constant of the HSQ film is
It is higher than porous silica which is an organic low dielectric constant porous film, and lower than silicon oxide film.

The surface 16S of the wiring layer 16 which does not have the porous silica layer 3 and the like in the surface 2S of the lower insulating layer 2 and the region near the surface 16S, and the porous silica layer 3
The porous silica layer 3 and the HSQ film 4 which are in contact with a region (here, a three-dimensional space including a region above the region) having no
The above-described barrier metal film 14 is formed on the inner surface 21S of the U-shaped wiring groove 21 including the silicon oxide film 5 and the respective sidewall surfaces.
A barrier metal film 6 similar to that described above is formed. Further, the entire surface of the barrier metal film 6 is not in contact with the inner surface 21S and the surface 6 along the inner surface 21S.
A metal wiring 7 made of a metal material such as copper is formed on S, and the inside of the U-shaped wiring groove 21 is filled. In addition,
The barrier metal film 6 and the metal wiring 7 filling the inside of the U-shaped wiring groove 21 are collectively referred to as “wiring layer 8”.

Next, the semiconductor device 51 according to the first embodiment
Will be described with reference to FIGS.

(Step of Forming Lower Insulating Layer) First, as shown in FIG.
A silicon substrate 1 on which an SFET is formed is prepared.

Then, as shown in FIG. 3, a lower insulating layer 2 is formed on the semiconductor device in the state of FIG. Specifically, for example, SOG (Spin On Glas) is applied so as to cover the surface 1S of the silicon substrate 1 of the semiconductor device in the state of FIG.
s) A silicon oxide film is formed by the method. Or,
A silicon oxide film is formed by a normal pressure CVD method. In addition, in order to improve flatness, CMP (Chemical Mecha
nical Polishing). Then,
A portion from the exposed surface of the silicon oxide film to a region having the diffusion layer 13 (which may be referred to as a “surface of the diffusion layer 13”) in the surface 1S is opened by photolithography technology. 3 and the insulating layer 2c of FIG. 3 are formed. Next, a sputtering method or a CVD method is performed on the entire exposed surface of the insulating layer 2c, that is, on the surface 2cS and the inner surface 17S of the connection hole 17.
Using a (Chemical Vapor Deposition) method, titanium nitride (TiN) or the like which will later become the barrier metal film 14 is deposited. Further, an aluminum alloy, copper, or the like which will later become the metal plug 15 is deposited on the entire exposed surface of the titanium nitride film or the like by sputtering or CVD so as to fill the connection holes 17. Note that a copper layer (which will later become the metal plug 15) filling the connection holes 17 may be formed on the entire exposed surface of the titanium nitride film or the like by plating. Thereafter, the titanium nitride film and the like and the aluminum alloy film and the like deposited on the surface 2cS of the insulating layer 2c are etched back to the level of the surface 2cS, and the barrier metal film 14 and the metal plug 15 of FIG. Form. It should be noted that the entire exposed surface (including the surface 16S) of the semiconductor device (see FIG. 3) after the above steps is formed on the lower insulating layer 2
Surface 2S.

(Step of Forming Organic Low-Dielectric-Constant Porous Film) Next, as shown in FIG. 4, the organic device over the entire surface 2S of the lower insulating layer 2 is applied to the semiconductor device in the state of FIG. A porous silica layer 3A, which is a porous film having a low dielectric constant, is formed.
Specifically, first, Trimethylsilan
e: SiH (CH ₃ ) ₃ ), tetramethoxysilane (Tetrame
A polymer solution obtained by polymerizing an organic silane such as thoxysilane: Si (OCH ₃ ) ₄ ) or tetraethoxysilane (Tetraethoxysilane: Si (OC ₂ H ₅ ) ₄ ) is applied on the surface 2S. Thereafter, the applied polymer solution is exposed to an atmosphere of ammonia or an amine-based solvent to form silica gel. Next, the silica gel is heated to about 400 ° C.
To form a porous silica layer 3A. The main material of porous silica is silicon oxide, but as mentioned above, raw materials also contain organic components such as methyl groups, so strictly speaking, porous silica is an organic low dielectric constant containing organic components. It is a membrane. Further, since the film has a large number of holes 3V, it is a porous film.

(Step of Forming Barrier Film) In this step, FIG.
As shown in FIG. 5, an HSQ film 4A which is a barrier film or an anti-decomposition film is formed on the semiconductor device in the state described above. Specifically, paste-like hydrogenated silsesquioxane (HSQ) as a raw material is formed on the exposed surface 3AS of the porous silica layer 3A by a spin coating method. Then, the applied paste-like material is reduced to about 400
By baking in a nitrogen atmosphere of ° C, the HSQ film 4
Form A.

As described above, since the HSQ film 4A is formed by applying the above-mentioned paste-like material on the surface 3AS by the spin coating method, such a process can be performed at a temperature of about room temperature. Moreover, at the time of applying the paste-like material, unlike the film forming method by the plasma CVD method, the porous silica layer 3A is not exposed to the active species of oxygen.

Further, in the baking step after coating, the porous silica layer 3A itself is completely covered with the above-mentioned paste-like material.
Contact with nitrogen atmosphere.

Therefore, in the step of forming the HSQ film 4A, the organic components in the porous silica layer 3A are decomposed and CO
_{No second} class gas is generated. Therefore, the porous silica layer 3A which is an organic insulating film and the inorganic insulating film H
The adhesiveness between the two films at the interface with the SQ film 4A can be made higher than the adhesiveness at the interface between the porous silica layer 203 and the silicon oxide film 205 in the conventional semiconductor device 251.

Further, according to the spin coating method, the surface 3A
Even when the porous silica layer 3A has a concave-convex shape formed by holes 3V in the S, the barrier film 4 is formed flat on the surface 3AS.
A can be formed into a film.

(Step of Forming Silicon Oxide Film 5A)
On the exposed surface of the semiconductor device in the state of FIG.
HSQ film 4A on the side not in contact with porous silica layer 3A
A silicon oxide film 5A on the surface 4AS of
It is formed by the D method (see FIG. 6). Here, as the standard film forming conditions for the silicon oxide film 5A, (a) the case of using silane (SiH ₄ ) and (b) TEOS (Tetra Ety
le Ortho Silicate) will be described.

First, when (a) silane (SiH ₄ ) is used, each flow rate is set to SiH ₄ = 100 (scc
m), N ₂ O = 2000 (sccm), N ₂ = 1000
Each material gas adjusted to (sccm) is introduced into a reactor in which the semiconductor device in the state of FIG. 5 is set. Then, the silicon oxide film 5A is formed by setting the gas pressure of the reaction furnace to 1 Torr and setting the RF power supplied to the reaction furnace to 600 W. At this time, the film formation temperature is set to, for example, 400 ° C.

On the other hand, (b) when TEOS is used, the flow rate of each material gas is set to TEOS = 900 (sccm) and O ₂ =
900 (sccm) and the gas pressure is 5 Torr
r, the RF power is set to 600 W, the film formation temperature is set to 400 ° C., and the silicon oxide film 5A is formed.

(Step of Forming Wiring Layer 8) Next, the exposed surface of the semiconductor device in the state of FIG. 6, that is, the HSQ film 4A
A resist is formed on the entire surface 5AS of the silicon oxide film 5A on the side not in contact with the substrate, and the resist is patterned (see the resist 20 in FIG. 7). To expose the region located above. Then, anisotropic etching is performed from the exposed region of the surface 5AS toward the silicon substrate 1 side, and a connection hole is formed in the surface 2S of the lower insulating layer 2 from the exposed region of the surface 5AS. Then, a U-shaped wiring groove 21 reaching the region 17 and its vicinity is formed (see FIG. 7).
At this time, as shown in FIG.
An SQ film 4 and a silicon oxide film 5 are formed. afterwards,
The resist 20 is removed.

Subsequently, the surface 5S of the silicon oxide film 5 on the entire exposed surface of the semiconductor device with the resist 20 removed from the state of FIG. 7, that is, the surface 5S opposite to the surface 4S.
On the inner surface 21S of the U-shaped wiring groove 21 and the inner surface 21S of the U-shaped wiring groove 21, titanium nitride (TiN), tantalum nitride (titanium nitride) which will later become the barrier metal 6 (see FIG. 1) is formed by the same manufacturing method. A metal film 6A such as TaN) or tungsten nitride (WN) is deposited (see FIG. 8). Furthermore, as shown in FIG. 8, the entire exposed surface 6AS of the metal film 6A is covered and the U-shaped wiring groove 2 is formed.
1 to fill the metal wiring 7 (see FIG. 1)
A metal film 7A such as copper is formed by a sputtering method, a CVD method, or a plating method in the same manner as in the method of manufacturing the metal plug 15 described above.

Then, for the semiconductor device in the state of FIG. 8, using the CMP (Chemical Mechanical Polishing) method, the height of the surface 5S of the silicon oxide film 5 in the metal film 6A and the metal film 7A is raised. By removing the portion existing above, the semiconductor device 51 shown in FIG. 1 is completed.

A further wiring layer is formed on the exposed surface (surface 5S including the exposed surface of wiring layer 8) of semiconductor device 51 in FIG. In the case of manufacturing a semiconductor device having a wiring structure, the steps of forming the organic-based low-dielectric-constant porous film and forming the wiring layer are repeatedly applied.

As described above, according to the manufacturing method according to the first embodiment, the adhesiveness between the porous silica layer 3 and the HSQ film 4 at the interface between the two layers is reduced by the conventional semiconductor device 25 shown in FIG.
The adhesiveness at the interface between the first porous silica layer 203 and the silicon oxide film 205 can be improved. Furthermore, without depending on the surface shape of the surface 3S of the porous silica layer 3,
The HSQ film 4 can be formed flat. Therefore, the functions of the insulating films 2 c, 3, 4, and 5 serving as interlayer insulating films are sufficiently exhibited, and a predetermined operation can be reliably performed. In addition, wiring delay (accordingly, semiconductor A semiconductor device with reduced device signal delay) can be manufactured.

(Embodiment 2) In Embodiment 2, the barrier film 4 for preventing the decomposition of organic components in the organic insulating film 3 is used.
As (or 4A), a case where a silicon oxide film formed by a low-temperature CVD method using a chemical vapor reaction between silane (SiH ₄ ) and hydrogen peroxide (H ₂ O ₂ ) will be described. The silicon oxide film is generated by the following chemical reaction.

SiH ₄ + 2H ₂ O ₂ → Si (OH) ₄ + 2H ₂ (1-1) SiH ₄ + 3H ₂ O ₂ → Si (OH) ₄ + 2H ₂ O + H ₂ (1-2) SiH ₄ + 4H ₂ O ₂ → Si (OH) ₄ + 4H ₂ O (1-3) nSi (OH) ₄ → nSiO ₂ + 2nH ₂ O (2) As shown in chemical formulas (1-1) to (1-3), first, silane (SiH _The silanol (Si (OH) ₄ ) is generated by the oxidation reaction between ₄ ) and hydrogen peroxide H ₂ O ₂ . Then, as shown in the chemical formula (2), the generated silanol causes a dehydration polymerization reaction by hydrolysis or thermal energy to generate silicon oxide (SiO ₂ ).

Therefore, according to such a reaction system, the porous silica layer 3A is not exposed to the active species of oxygen, and the barrier film 4 (or 4) of the second embodiment is formed of a silicon oxide film.
A) can be formed. Further, the above chemical formula (1-1)
Since the reaction represented by the chemical formula (2) proceeds spontaneously even at a very low temperature, the barrier film 4 made of the silicon oxide film can be formed even at a film formation temperature of, for example, room temperature or lower.

As described above, in the manufacturing method according to the second embodiment, the barrier film 4 is replaced with the conventional silicon oxide film 20 shown in FIG.
5, the barrier film 4 is not formed in a high-temperature atmosphere having an active species of oxygen (it can be formed even at a temperature lower than room temperature).
No gas such as CO ₂ is generated from the porous silica layer 3A when A is formed.

Further, according to the low-temperature CVD method, a flat barrier film 4 is formed without depending on the surface unevenness of the surface 3S (or 3AS) of the porous silica layer 3 (or 3A).
(Or 4A) can be formed. Therefore, Embodiment 1
The same effect as described above can be obtained.

As a specific example of the standard film forming conditions, the silicon oxide film forming the barrier film 4 (or 4A) according to the second embodiment has a flow rate of SiH ₄ = 100 (scc).
_{m), H 2 O 2 =} 0.75 (g / min), N ₂ = 1000
Each material gas adjusted to (sccm) is introduced into a reactor in which the semiconductor device in the state of FIG. 4 is set, and the gas pressure in the reactor is set to 1 Torr and the film forming temperature is set to 1 ° C. The film is formed by setting.

Thereafter, the surface of the barrier film 4 (or 4A) made of the silicon oxide film (corresponding to the surface 4AS in FIG. 5)
Above, the silicon oxide film 5A is formed as shown in FIG.
It is formed by a film formation method similar to that of the first embodiment. In particular,
According to the manufacturing method of the second embodiment, after the barrier film 4A is formed by the low-temperature CVD method described above, the silicon oxide film 5A is continuously formed without breaking the vacuum by the plasma C.
It can be formed by the VD method. At this time, since unnecessary impurity levels are not formed at the interface between the barrier film 4A and the silicon oxide film 5A, a multi-layered interlayer insulating film having essential insulating properties can be manufactured.

Thereafter, by performing the same manufacturing method as in the first embodiment, the semiconductor device according to the second embodiment is completed.

As described above, according to the manufacturing method of the second embodiment, a semiconductor device capable of exhibiting the same effect as the semiconductor device 51 is manufactured due to the method of forming the barrier film 4 or 4A. be able to.

In particular, as a method for forming the barrier film 4 (or 4A) according to the second embodiment, the self-planarizing CVD method including the low-temperature CVD method described above can be applied. Here, the “self-flattening CVD method” is a CVD method capable of depositing or forming a predetermined film evenly without depending on a minute surface unevenness of a deposition surface or a deposition surface.

As the organic low dielectric constant porous film 3 in the semiconductor device according to the first and second embodiments, instead of the porous silica layer 3, polytetrafluoroethylene (Polytetrafluoroethylene) or the like which can be formed by a spin coating method is used. ,
Fluorinated amorphous carbon or the like that can be formed by a CVD method may be used.

[0059]

(1) According to the first aspect of the present invention, even if the surface of the first insulating film has an uneven shape caused by pores in the porous film, the second insulating film can be formed. It can be formed flat on the surface of the first insulating film. Therefore, even when a multilayer interlayer insulating film is formed by repeatedly applying the manufacturing method according to claim 1, a semiconductor device including an interlayer insulating film having good insulating characteristics can be manufactured. .

(2) According to the second aspect of the present invention, the second
The insulating film is formed at a temperature at which the first insulating film is not exposed to the active species of oxygen and the organic component in the first insulating film does not react with the active species of oxygen. Therefore, it is possible to effectively suppress the decomposition of the organic component in the first insulating film and the generation of a gas such as CO ₂ . Therefore, the gas does not cause a decrease in the adhesiveness at the interface between the first insulating film and the second insulating film. Can be significantly increased. Therefore, it is possible to manufacture a semiconductor device having an interlayer insulating film capable of sufficiently exhibiting its function.

(3) According to the third aspect of the invention, the second
Since the paste-like material, which is a raw material of the insulating film, is applied by a spin coating method, the paste-like material can be applied evenly on the surface of the first insulating film having an uneven surface. Therefore, the same effect as the above (1) can be obtained.

Further, according to the third aspect of the present invention, even when the step of baking the applied paste-like material is performed at a high temperature of, for example, 400 ° C., the first insulating film is made of the paste-like material. Therefore, the first insulating film itself does not come into contact with the high temperature atmosphere and the active species of oxygen. Therefore, the same effect as the above (2) can be obtained.

(4) According to the fourth aspect of the invention, the second
Since the insulating film is formed by the self-flattening CVD method, the second insulating film can be formed flat even on the surface of the first insulating film having the uneven surface. Therefore, the same effect as the above (1) can be obtained.

(5) According to the fifth aspect of the present invention, the third
The insulating property of the first insulating film made of an organic material can be supplemented by the insulating film. Therefore, it is possible to manufacture a semiconductor device provided with an interlayer insulating film having better insulating properties than the interlayer insulating film formed by the manufacturing method according to the first to fourth aspects of the present invention.

Further, according to the fifth aspect of the present invention, the second
When the steps of forming the insulating film and the third insulating film are performed in the same reactor, both films can be formed continuously without breaking the vacuum of the reactor. At this time, since an unnecessary impurity level is not formed at the interface between the two films, good insulating properties can be obtained.

(6) According to the sixth aspect of the invention, the effects of the above (1) to (5) are exhibited, a predetermined operation can be reliably performed, and a low dielectric constant insulating material is used. A semiconductor device in which wiring delay (accordingly, signal delay of the semiconductor device) is reduced by a certain first insulating film can be provided.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view schematically showing a structure of a semiconductor device according to a first embodiment.

FIG. 2 is a longitudinal sectional view in a manufacturing process of the semiconductor device according to the first embodiment.

FIG. 3 is a longitudinal sectional view in a manufacturing process of the semiconductor device according to the first embodiment.

FIG. 4 is a longitudinal sectional view of the semiconductor device according to First Embodiment in a manufacturing step.

FIG. 5 is a longitudinal sectional view of the semiconductor device according to First Embodiment in a manufacturing step.

FIG. 6 is a longitudinal sectional view of the semiconductor device according to First Embodiment in a manufacturing step.

FIG. 7 is a longitudinal sectional view of the semiconductor device according to First Embodiment in a manufacturing step.

FIG. 8 is a longitudinal sectional view of the semiconductor device according to First Embodiment in a manufacturing step.

FIG. 9 is a longitudinal sectional view schematically showing a multilayer wiring structure according to a first conventional technique.

FIG. 10 is a longitudinal sectional view schematically showing a structure of a semiconductor device according to a second conventional technique.

FIG. 11 is a graph showing a relationship between a film forming temperature when a silicon oxide film is formed on porous silica by a plasma CVD method and a reduction rate of methyl groups in the porous silica before and after the formation of the silicon oxide film. It is.

[Explanation of symbols]

Reference Signs List 1 silicon substrate, 2 lower insulating layer, 2c insulating layer, 2
S, 2cS, 3S, 3AS, 4S, 4AS, 5S, 5A
S, 14S, 16S surface, 3,3A organic low dielectric constant porous film (first insulating film), 3V vacancy, 4,4A barrier film (second insulating film), 5,5A silicon oxide film (third
Insulating film), 6,14 barrier metal layer, 6A, 7A metal film, 7 metal wiring, 8,16 wiring layer, 11a, 1
1b Gate electrode, 12a, 12b Gate insulating film, 1
3 diffusion layer, 15 metal plug, 17 connection hole, 17
S, 21S inner surface, 20 resist, 21 U-shaped wiring groove, 51 semiconductor device.

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference) SS12 SS13 SS15 SS22 TT04 XX01 XX12 XX24 XX27 5F058 AA08 AD02 AD05 AD10 AF04 AG01 AH02 BA20 BD04 BF07 BF23 BF25 BF29 BF46 BH01 BJ02

Claims (6)

[Claims] A step of preparing a substrate having a predetermined element formed on a surface thereof; a step of forming a first insulating film, which is an organic low-permittivity porous film, on the substrate; A second insulating film is formed on the surface of the first insulating film on the side opposite to the substrate by a forming method capable of forming a flat film on the surface on which the film is formed without depending on the uneven shape of the film surface. Forming a semiconductor device. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the second insulating film is formed in an atmosphere having no active species of oxygen or in an atmosphere having no active species of oxygen. A method for manufacturing a semiconductor device, wherein the method is performed at a temperature lower than a temperature at which an organic component in a film can react. 3. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of forming the second insulating film, a paste-like material that is a raw material of the second insulating film is formed by a spin coating method. A method for manufacturing a semiconductor device, comprising a step of applying the solution on the surface of the first insulating film. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the second insulating film is formed by a self-planarization CVD method. 5. The method of manufacturing a semiconductor device according to claim 1, wherein a surface of said second insulating film opposite to said first insulating film is formed by a plasma CVD method. (3) A method for manufacturing a semiconductor device, further comprising a step of forming an insulating film. 6. A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 1. Description: