JP2000163308A - Memory device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] All of the unbuffered standard, buffered standard, and registered standard have advantages and disadvantages, and it has been difficult to construct a high-speed memory device in which a large number of memory chips are mounted. SOLUTION: A control signal RA is supplied to a buffer circuit 16c.
By inputting S, CAS and WE signals, SDR
It is possible to maintain the driving capability of the AMs 161 to 164. Further, in order to prevent the delay of the control signal CS, CS is directly input to each of the SDRAMs 161 to 164 and driven. Therefore, the fall of this CS, which is timing based on CLK,
The rise is about 2 ns from the rise of this CLK.
c and a width of about 1 nsec.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a memory device, and more particularly, to a memory device having a memory chip and a buffer for temporarily inputting a signal input to the memory chip.

[0002]

2. Description of the Related Art In recent years, when selecting various peripheral devices at the time of manufacturing a computer, the operating clock frequency of a CPU employed by the computer is used as one index.
At present, this index is based on a computer whose operation clock frequency corresponds to the 100 MHz class and an operation clock frequency of 6
Computers corresponding to the 6 MHz class are classified into two types. Various peripheral devices to be assembled in the computer are also selected according to the classification of the operating clock frequency. Therefore, a memory device mounted on a computer, which is one of the peripheral devices, is appropriately selected according to the operating clock frequency.

Specifically, a memory device standardized according to the index is selected and assembled into a computer. Further, the memory device is standardized according to the use form of the computer, and the maker of the computer, when producing the computer, requires an appropriate memory according to the operating clock frequency of the computer and the use form of the computer. The device standard is selected and mounted on the computer. Here, the above-mentioned standards of the memory device can be roughly classified into three standards: an unbuffered standard, a buffered standard, and a registered standard.

[0004] The unbuffered standard is a standard of a memory device which is mainly employed and mounted in a computer having an operation clock frequency of 66 MHz class and 100 MHz. The memory device is installed in a predetermined socket on a motherboard of a computer, and through this socket, data signals and control signals (RA signals) are transmitted from the motherboard.
S, CAS, CS, etc.) are directly input to the memory chip. The memory chip operates according to the control signal and the data signal. As described above, since the control signal and the data signal are directly input to the memory chip, no signal delay occurs. Therefore, the unbuffered standard is a standard that can provide a memory device that operates at high speed.

[0005] The buffered standard is a standard of a memory device mainly adopted and mounted in a computer having an operation clock frequency of 66 MHz class. This memory device is installed in a predetermined socket on a motherboard of a computer, forms a buffer area immediately before a memory chip, and inputs a control signal to this buffer area once and then to the memory chip. Therefore, the signal level of the control signal input to the memory chip can be emphasized, and "rounding" generated in the signal waveform can be corrected, so that the reliability of the control signal can be improved.

Further, the registered standard is a standard of a memory device which is mainly used in a computer having an operation clock frequency of 100 MHz class and mounted. This memory device is installed in a predetermined socket on a motherboard of a computer, forms a register area immediately before a memory chip, and inputs a control signal to this register area before inputting to the memory chip. Therefore, the signal level of the control signal can be emphasized, and “rounding” occurring in the signal waveform can be corrected, so that the reliability of the control signal can be improved. On the other hand, since the control signal is once input to the register area, the control signal is input to the memory chip with a delay of one clock. This registered standard is adopted especially for computers that require reliability, for example, computers that operate as servers.

[0007]

In the conventional memory device described above, if a large number of memory chips are mounted in order to realize a large capacity of the memory device in the unbuffered standard, these memory chips are connected in a daisy chain. Therefore, there is a problem that the waveform of an input signal becomes rounded, and the ability to drive a memory chip with respect to a control signal is reduced. Further, in the buffered standard, since a control signal is input via a buffer area, the waveform can be corrected before inputting the control signal to the memory chip. Therefore, since a large number of memory chips can be mounted, the capacity of the memory device can be increased. However, when the operation clock frequency is increased to realize a high-speed operation, the delay of the memory chip selection signal included in the control signal generated through the buffer area makes the operation of the memory chip unstable. There is.

Further, in the registered standard, since data signals and control signals are input via the register area, the waveform can be corrected before these signals are input to the memory chip, as in the buffered standard. Therefore, a large number of memory chips can be mounted, and a large capacity memory device can be realized. In the register area, the data signal and the control signal are input to the memory chip with a delay of one clock, so that the output of the control signal can be stabilized even if the operation clock frequency is increased, thereby realizing high-speed operation. Becomes possible. However, this is not only incompatible with motherboards that adopt the above-mentioned unbuffered standard, which is the mainstream of the current standard, but also causes the data signal and control signal input to the register area to be delayed by one clock as described above. There is a problem of doing it. The present invention has been made in view of the above problems, and has a memory capable of realizing a large capacity of a memory device, which is an advantage of the buffered standard, while providing a high-speed operation which is an advantage of the unbuffered standard. The purpose is to provide the device.

[0009]

According to a first aspect of the present invention, there is provided a plurality of memory chips operating on the basis of predetermined control signals and data signals while operating based on the signals. A buffer means for inputting a predetermined control signal and correcting the waveform of the signal while sending the signal to the memory chip, and a direct input for directly inputting a memory chip selection signal of the predetermined control signal to the memory chip Means.

According to a second aspect of the present invention, there are provided a plurality of memory chips operating on the basis of a predetermined control signal and a data signal while receiving the predetermined control signal and the data signal. And a buffer means for sending the signal to the memory chip while correcting the waveform of the memory chip, wherein the memory chip selection signal among the predetermined control signals is directly input to the memory chip.

Further, according to the present invention, in the memory device provided with a memory chip which operates based on a predetermined control signal and a data signal whose waveforms are corrected, Among the signals, the memory chip selection signal is directly input to the memory chip, and the control signals other than the memory chip selection signal are transmitted to the memory chip while modifying the waveform of the signal via a buffer. There is a configuration to do.

[0012] In the invention according to claim 1 configured as described above, the memory device includes a plurality of memory chips, buffer means for correcting a waveform of a predetermined signal, and direct input means. The memory device operates based on a predetermined control signal input from the buffer means and a memory chip selection signal input from the direct input means. In other words, when a large number of memory chips are mounted on a memory device to increase the capacity of the memory device, the waveform of a predetermined control signal input to the memory chip becomes rounded, and the ability to drive the memory chip is reduced. Run short. Therefore, it is necessary to once input a predetermined control signal to the buffer means in order to correct the "rounding". However, among the predetermined control signals, the memory chip selection signal
Once input to the buffer means, the buffer means causes a delay, which affects the operation of the memory device.
Therefore, only the memory chip selection signal is directly input to the memory chip by the direct input means.

The reason why the control signal has to pass through the buffer means but the memory chip select signal does not have to pass through the buffer means is as follows. That is, while the memory chip selection signal is output for each memory chip to be selected, other control signals are output in common to a plurality of memory chips. Therefore, there is a margin as compared with other control signals, and this allows driving even if it is directly supplied to the memory chip by the direct input means. Note that the memory chips referred to here are divided into groups and may be divided into memory modules. Then, the memory device operates based on the memory chip selection signal.

The memory chip only needs to be able to operate based on predetermined signals while inputting and outputting predetermined control signals and data signals, and it goes without saying that other components for realizing this operation are included. . For example, the configuration may include a parity error detection circuit that detects an error of each signal described above, or may include a configuration including an EEPROM. Conventionally, the number of signal lines transmitting the memory chip selection signal was relatively small with respect to the number of memory chips installed, but the number of signal lines transmitting the memory chip selection signal was relatively small with respect to the number of memory chips installed. This also contributes to directly inputting a memory chip selection signal to the memory chip by the direct input means.

Further, in the invention according to claim 2 configured as described above, the memory device includes a plurality of memory chips and buffer means for correcting a signal waveform of a predetermined control signal. The memory device operates based on the memory chip selection signal while directly inputting a memory chip selection signal among the predetermined control signals without passing through the buffer means.

Here, in a conventional memory device mounted on a computer, a plurality of memory chips operate by inputting a control signal whose signal waveform has been corrected. But,
When a large number of memory chips are mounted on a memory device and the capacity of the memory device is increased, "rounding" occurs in a signal waveform of a control signal transmitted between the large number of memory chips, and a driving capability for driving the memory chip. Was sometimes lacking.

Therefore, in the invention according to claim 3 configured as described above, a control signal excluding the memory chip selection signal is once input to the buffer means in order to correct this "rounding". On the other hand, once the memory chip selection signal is input to the buffer means, a delay occurs in timing due to the buffer means, making it impossible to read the memory chip selection signal based on a predetermined clock signal. In order to influence the operation, the data is directly input to the memory chip without being input to the buffer means.

Here, the term "correcting the waveform of a signal by the buffer means" may refer to correcting the signal level of each signal input by the buffer means, or correcting the waveform of the input signal. May be corrected. Of course, it is also possible to correct "rounding" while enhancing the signal level. Further, the memory device may be any device as long as it can mount a predetermined memory chip and can be inserted into a predetermined socket of a motherboard.
A configuration using M may be adopted. Further, the present invention is not limited to these, and it goes without saying that the present invention can also be applied to products constituting a memory device to be developed in the future. Further, the memory chip constituting the memory device may be a DRAM, and may be an SDRAM or an EDO-DRAM. Of course, a normal DRAM may be adopted, and
It goes without saying that the RAM can also be adopted.

[0019]

As described above, the memory device according to the present invention performs the correction of the signal waveform via the buffer means, so that even if a delay occurs, the memory device does not affect the operation of the memory device other than the memory chip selection signal. The signal is corrected through a buffer means, and the memory chip selection signal which affects the operation of the memory device is directly input to each memory chip. Since this memory chip can operate based on this memory chip selection signal, it is possible to provide high speed operation, which is an advantage of the unbuffered standard, and as described above, the memory chip selection signal For signals other than the above, the signal waveform is corrected by the buffer means before being input to the memory chip, so that a drive capability for driving the memory chip can be formed. Therefore, it is possible to realize a large capacity memory device, which is an advantage of the buffered standard.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a claim correspondence diagram of a memory device according to an embodiment of the present invention. In the figure, a memory device C1 inputs a control signal other than a memory chip selection signal associated with a predetermined access by a buffer means C4. Here, the memory chip selection signal is sent to the memory chips C51 to C5n via the direct input means C2.
Input directly to Control signals other than the above-described memory chip selection signal are input to the memory chip C51 via the buffer means C4. As shown in the figure, the memory device C1 includes a plurality of memory chips C51 to C5n, and these memory chips C51 to C5n are sequentially connected via signal lines. Here, when a control signal other than the memory chip selection signal is input from the buffer means C4 to the memory chip C51, it is transmitted through a signal line and sequentially input to the memory chips C52 to C5n.

For this reason, a control signal other than the memory chip selection signal requires a predetermined driving capability at the time when it is output from the buffer means C4. Therefore, the buffer means C
Numeral 4 corrects the signal waveform in order to improve the driving ability of control signals other than the memory chip selection signal input to the memory chip C51. Here, in the buffer means C4, a control signal other than the input memory chip selection signal causes a delay in signal timing due to the action of correcting the signal waveform described above.

However, this delay has no effect on the operation of the memory chip C5. On the other hand, when the delayed memory chip selection signal is input to the memory chip C51 via the buffer means C4, the operation of the memory chips C51 to C5n is affected, so that the direct input means C2 directly supplies the memory chips C51 to C5n. input. And
The memory chips C51 to C5n execute an operation based on the signal timing of the directly input memory chip selection signal while inputting a control signal other than the memory chip selection signal from the buffer means C4 via a signal line.

The effect of the delay of the memory chip selection signal on the operation of the memory chips C51 to C5n is as follows. A memory chip that detects the signal timing of each signal based on a predetermined clock signal has a rising edge. This means that a predetermined signal timing relationship between the fall and the rise of the memory chip select signal cannot be formed. That is, it means that the operation of the memory chip selection signal cannot be grasped, and the function as the memory device cannot be realized.

FIG. 2 is an external view of a computer on which the memory device according to the embodiment of the present invention is mounted, and FIGS. 3 to 5 show a motherboard on which the memory device is mounted and a specific example of the memory device. A typical example of hardware is a DIMM, and the same motherboard is equipped with the DIMM. In the figure, a computer 10
Is a main body 11 and a keyboard 12 for performing a predetermined input operation
And a mouse 13, and a display 14 for displaying a predetermined screen. The main body 14 is provided with a motherboard 15 on which various devices for executing the operation of the computer 10 are mounted. This motherboard 1
Reference numeral 5 denotes a power supply 15a which is connected to a commercial power supply to the computer 10 and supplies operating power to the computer 10, and a CP which executes various processes realized by the computer 10.
U15b, a plurality of slots 15c and 15e for installing a board or the like having a predetermined extended function, and a DIMM socket 1 for inserting a DIMM 16 as a main memory.
5d. And DIMM16 is DIM
Operation becomes possible depending on the state of being inserted into the M socket 15d.

Next, the schematic internal configuration of the DIMM 16 is shown in FIG.
Is shown by the block diagram of FIG. In the figure, DIMM 16
Is a buffer circuit 16c and a memory chip SDRA
M161 to M164. Then, the control signals WE, CAS, and RAS are input to the buffer circuit 16c, and the waveforms of these signals are corrected. The data signal DATA is directly input to the SDRAMs 161 to 164, and the control signal CLK is input to the SDRAMs 161 to 164 via a PLL circuit. Here, the operation of correcting the signal waveform in the buffer circuit 16c will be described with reference to FIGS. FIG.
FIG. 8 shows an example of a signal waveform input to the buffer circuit 16c, and FIG. 8 shows an example of a signal waveform output from the buffer circuit 16c.

The signal input to the buffer circuit 16c is
Although the signal is originally a rectangular signal, "rounding" or wobbling occurs in the waveform as shown in FIG. 7 due to the resistance and noise of the wiring. Such signals are transmitted to the SDRAMs 161 to 161.
When input to 64, operation becomes unstable. Therefore, the buffer circuit 16c performs an operation of turning on the input signal above a predetermined threshold and turning off the input signal below the threshold. Therefore, the signal output from the buffer circuit 16c can form a rectangular signal that rises to a predetermined ON level at time t1 and falls to 0 level at time t2. At this time, the power supply V of the buffer circuit 16c is
The level of this rectangular signal is raised to a predetermined level by cc. As described above, by shaping the data signal DATA and the control signals WE, CAS, and RAS into rectangular signals and setting the signal level to a predetermined level,
S is connected in a rosary without "rounding" in the waveform
The DRAMs 161 to 164 can be driven normally.

Here, DATA is a data signal associated with a predetermined access, and WE indicates a write enable signal. CLK indicates the operating clock frequency of the computer 10. Here, SDRAMs 161 to 164
Is formed in a lattice like a worksheet, and one bit of data is stored in a portion (memory cell) corresponding to a cell of the worksheet. Therefore,
When accessing this data, a row address and a column address are input and specified. Specifically, when inputting a row address, RAS shown in the figure is activated to input a row address, and when inputting a column address, CAS is activated and a column address is input. Here, RAS is RowAddressS
abbreviation for "trobe", CAS is ColumnA
This is an abbreviation for addressStrobe. Also, CS
Means chip select signal, RAS, CA
This signal selects a memory chip having an address specified by S.

The operation of this CS is as shown in FIG.
It is detected at the rise of K. At this time, CS is CL
It is necessary to fall about 2 ns before the rise of K, and about 1 ns from the rise of CLK.
It is necessary to start up after ec. If such time is not formed, the operation of turning off / on the CS cannot be detected, and the operation of the SDRAMs 161 to 164 becomes unstable. Therefore, CS is not input to the buffer circuit 16c but directly to the SDRAMs 161 to 16D.
4 will be input. Also, this CS is SDR
Before input to the AMs 161 to 164, the damper resistance 1
6b, and while performing a predetermined voltage drop,
M161 to M164. The buffer circuit 16c is supplied with operating power from the power supply Vcc, and uses the ground at GND.

In this embodiment, the memory chip is S
Although it is constituted by a DRAM, it may be constituted by an EDO-DRAM or, of course, may be constituted by a normal DRAM. In the present embodiment, four SDRAMs 1
Although the configurations of 61 to 164 are adopted, it is needless to say that the present invention is not limited to the four SDRAMs, and the number can be changed as appropriate. Further, in the present embodiment, as an example of the signal input to the buffer circuit 16c, the data signal DATA and the control signals CLK, WE,
Although CAS and RAS are illustrated, it goes without saying that this signal alone does not indicate that the SDRAMs 161 to 164 are operating.

Next, the operation of the data signal and the control signal of the present embodiment having the above configuration is shown in FIG. In the figure, the detection of ON / OFF of CS is performed with reference to the rising edge of the second pulse in CLK. Where CS
Are directly input to the SDRAMs 161 to 164, so that the drive capacity is maintained and the SDRAMs 161 to 164 are maintained.
4 is input. RAS, CAS, WE or DATA is transferred to the SDRAM via the buffer circuit 16c.
161 to 164, but the rising of the signal or the like is not detected by the CLK.
1 to 164 operate at the timing of turning off / on CS.

As described above, by inputting the control signals RAS, CAS, and WE to the buffer circuit 16c, the driving capability of the SDRAMs 161 to 164 can be maintained. Also, the control signal CS is sent to the SDRA
Since each of M161 to 164 is directly input and driven, there is no delay in CS. Therefore, the falling rise of CS, which is timed based on CLK, is about 2 nsec and about 1 nsec from the rise of CLK. It can be formed with a width. Therefore, the SDRAMs 161 to 164 can operate at the CS operation timing, and the buffer circuits 16c
, And can operate based on CS, so that the DIMM 16 can achieve high-speed operation.

[Brief description of the drawings]

FIG. 1 is a diagram corresponding to claims of a memory device according to an embodiment of the present invention.

FIG. 2 is a schematic external view of a computer to which the memory device according to the present invention is applied.

FIG. 3 is a schematic plan view of a motherboard provided in the computer.

FIG. 4 is a diagram showing DI which is specific hardware of the memory device.
It is an external appearance perspective view of MM.

FIG. 5 is an external perspective view in which the DIMM is installed on the motherboard.

FIG. 6 is a block diagram showing an internal configuration of the DIMM.

FIG. 7 is a time chart illustrating an example of a signal input to a buffer circuit.

FIG. 8 is a time chart illustrating an example of a signal output from the buffer circuit.

FIG. 9 is a timing chart showing a relationship between a CLK signal and a CS signal in the DIMM.

FIG. 10 is a timing chart of each signal when the DIMM is applied.

[Explanation of symbols]

 16 DIMMs 161-164 SDRAM 16b Damper resistance

Claims (3)

[Claims] 1. A plurality of memory chips operating based on predetermined control signals and data signals while inputting the predetermined control signals, and correcting the waveforms of the signals while inputting the predetermined control signals. A memory device comprising: buffer means for sending to a memory chip; and direct input means for directly inputting a memory chip selection signal among the predetermined control signals to the memory chip. 2. A plurality of memory chips that operate based on a predetermined control signal and a data signal while inputting the predetermined control signal and a waveform of the signal while correcting the waveform of the signal. A memory device comprising: buffer means for sending to a memory chip, wherein a memory chip selection signal among the predetermined control signals is directly input to the memory chip. 3. A memory device comprising a memory chip operating on the basis of a predetermined control signal and a data signal whose waveforms have been corrected, and operating on the basis of the signal. Is input directly to the memory chip, and for control signals other than the memory chip selection signal,
A memory device, wherein the signal is sent to the memory chip while correcting the waveform of the signal via a buffer.