JP2000156078A - Semiconductor storage device - Google Patents

Abstract

(57) Abstract: A synchronous DRAM having a multi-bank configuration is provided with a function of writing data read from a specific bank to another bank, thereby shortening a data writing time in a test. A synchronous DRAM having a multi-bank configuration is provided.
, Any one of a plurality of memory banks BK0 to BK3 is designated as a source bank based on a command designating an inter-bank data copy mode, and data read from the source bank is assigned to at least one of the remaining memory banks. And an inter-bank data copy control circuit 20 for controlling the writing to the data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and, more particularly, to a control circuit for enabling data copying between banks of a semiconductor memory having a memory cell array divided into multi-banks. Used for dynamic random access memory (DRAM).

[0002]

2. Description of the Related Art FIG. 7 shows read / write data between four banks BK0 to BK3 and an input / output buffer (not shown) in a synchronous DRAM having a conventional multi-bank configuration (for example, four banks). As for the input / output path, one bit is typically extracted and shown.

In the DRAM shown in FIG. 7, DQ is a data line pair in each bank BK0-BK3, RDQ0-RD.
Q3 is a read data line pair outside the bank connected to the data line pair DQ of each bank BK0 to BK3, WD
Q0 to WDQ3 are write data line pairs outside the banks connected to the data line pairs DQ of the banks BK0 to BK3.

RB01 is the read data line pair RDQ0.
To RDQ3, a read control circuit commonly connected to a pair of read data lines RDQ0 and RDQ1 which are connected corresponding to two adjacent banks.
RB23 is an adjacent two of the read data line pairs.
Read data line pairs R connected corresponding to the
This is a read control circuit commonly connected to DQ2 and RDQ3.

WB0 to WB3 are four write control circuits connected to the respective write data line pairs WDQ0 to WDQ3.

The read control circuits RB01 and RB23 and the write control circuits WB0 to WB3 are commonly connected to an input / output data line pair RWD, and the input / output data line pair RWD is connected to an input / output buffer (not shown). Write / read data is input / output between

The read control circuits RB01 and RB23 are
Each bank can be selected and read independently, and has a function of transferring complementary data read from the selected bank BKkn to the input / output data line pair RWD.

The write control circuits WB0 to WB3 are:
Each bank can be independently selected and written, and complementary write data supplied from the input / output data line pair RWD is transferred to a pair of write data line pairs WDQn corresponding to the selected bank BKkn. It has a function to do.

Conventionally, when testing a synchronous DRAM having a multi-bank configuration, data writing to memory cells is performed for each bank, and the time required to complete data writing to all banks increases. I have.

On the other hand, in recent years, an increase in test time accompanying an increase in the memory capacity of a synchronous DRAM has been regarded as a problem in terms of manufacturing cost. Considering this problem, synchronous DRAM
In this test, it is not necessary to perform data writing for each bank, and there is no problem even if the same data is written to all banks.

However, a conventional synchronous DRAM having a multi-bank configuration does not have a function of writing data to a plurality of banks at the same time.

[0012] A known example slightly related to such a problem will be described below.

(1) Japanese Patent Application Laid-Open No. 5-234364 discloses a transfer bus for each bit line between adjacent arrays in a video RAM for the purpose of high-speed copying of data between memory cell arrays. A technique for providing is disclosed.

However, the size of the memory core portion and, consequently, the size of the memory chip become large, and it is not possible to cope with a synchronous DRAM having a multi-bank configuration.

(2) JP-A-9-35483 discloses that
A technique has been disclosed which provides a data latch circuit for each data line DQ of a memory so that data can be copied between memory cell arrays connected to the same data line DQ.

However, since it is impossible to copy data between different data lines DQ, it is impossible to copy data between multi-banks.

(3) JP-A-10-27489 discloses a technique for equalizing the number of times of rewriting of data in a nonvolatile memory. However, this technique is specialized for adjacent memory cell arrays, and it is unclear whether the technique can be applied to non-adjacent banks.

(4) Japanese Patent Laying-Open No. 6-214871 discloses a technique of providing separate address & I / O pins for each memory cell array of a cache memory. However, this technique cannot cope with copying data between multi-banks in a synchronous DRAM having a multi-bank configuration as a main memory.

[0019]

As described above, the conventional synchronous DRAM having a multi-bank configuration does not have a function of writing data to a plurality of banks at the same time. was there.

The present invention has been made to solve the above-mentioned problems, and has a function of writing data read from a specific bank to another bank, so that the data writing time can be reduced in a test, It is an object of the present invention to provide a semiconductor memory device having a multi-bank configuration suitable for application to a DRAM or the like.

[0021]

According to a first aspect of the present invention, there is provided a semiconductor memory device having a multi-bank configuration, wherein any one of a plurality of memory banks is selected based on a command designating an inter-bank data copy mode. Is designated as a source bank, and an inter-bank data copy control circuit for controlling data read from the source bank to be written into at least one remaining memory bank is provided.

According to a second aspect of the present invention, there is provided a semiconductor memory device, comprising: a plurality of memory banks in each of which a memory cell array and related circuits are divided into a plurality of groups; and a data read control circuit for selectively reading data from each memory bank. A data write control circuit for selectively writing data to each of the memory banks, a data line commonly connected to the plurality of memory banks, and a command specifying a data copy mode between banks. The data read control circuit and the data read control circuit, wherein any one of a plurality of memory banks is designated as a source bank, and data read from the source bank is written to at least one remaining memory bank via the data line. An inter-bank data copy control circuit that controls the data write control circuit Characterized in that it Bei.

[0023]

Embodiments of the present invention will be described below in detail with reference to the drawings.

<First Embodiment> FIG. 1 shows a part of a block configuration of a synchronous DRAM having a multi-bank configuration according to a first embodiment.

In FIG. 1, the memory cell array is divided into a plurality (four in this example) of memory banks BK0 to BK3.

The clock input buffer 11 receives a clock signal CLK and a control signal CKE, outputs a clock signal, and supplies the clock signal to a required circuit.

The address buffer 12 has an address signal A
0 to Am-1, Am and bank address signals BS0 to B
Sn-1 is inputted and buffer-amplified in synchronization with the output signal of the clock input buffer 11.
A bank selection circuit 12a for decoding a BSn-1 input to generate a bank selection signal is included.

The command decoder 13 receives various kinds of external control signals (the C
KE signal, chip select signal / CS, row address strobe signal / RAS, column address strobe signal / CAS, write enable signal / WE,
The most significant bit Am) of the address signal is input and decoded in synchronization with the output signal of the clock input buffer 11.

The control signal generation circuit 14 receives a command decode output signal from the command decoder 13 and generates various internal control signals in synchronization with the output signal of the clock input buffer 11.

Reference numeral 15 denotes a refresh counter, and 16 is a refresh counter.
Is an address latch circuit for latching an output signal (including a bank selection signal) of the address buffer 12 / an output signal (refresh address signal) of the refresh counter 15 according to a normal operation mode / self-refresh mode.

Circuits such as a row decoder, a bit line sense amplifier SA, a column decoder / column switch CDS, and a data line buffer amplifier DBA related to the memory cell array are also divided and provided corresponding to the banks BK0 to BK3. ing. In this case, the bit line sense amplifier SA is divided and provided for each cell block in each of the banks BK0 to BK3.

Each of the row decoders RD0 to RD3 corresponding to each of the banks BK0 to BK3 receives the output signal of the address latch circuit 16, and controls whether or not a decoding operation can be performed by a corresponding bank selection signal. To perform row selection of the banks BK0 to BK3 to be executed.

The column decoder / column switch CDS corresponding to each of the banks BK0 to BK3 decodes a column address signal, and outputs the corresponding bank BK0 to BK3.
The column selection of 3 is performed.

In the following description, each bank BK0 to BK0 to
Banks BK0 to BK3 including related circuits (row decoder, bit line sense amplifier, column decoder / column switch, data line buffer amplifier, etc.) divided corresponding to BK3 are also referred to.

FIG. 2 shows the four banks BK0 to BK in FIG.
Read between K3 and input / output buffer (not shown)
As for the input / output path of the write data, one bit is typically extracted and shown.

In FIG. 2, in each of the banks BK0 to BK3, a memory cell MC is connected to a data line pair DQ via a bit line sense amplifier SA and a column switch CS. Read data line pairs RDQ0-RD are provided outside the banks corresponding to the data line pairs DQ of the banks BK0-BK3.
DQ3 and the write data line pair WDQ0 to WDQ3 are connected.

RB01 is the read data line pair RDQ0.
RDQ3, two adjacent banks BK0, B
Read data line pair RDQ0 connected corresponding to K1
, RDQ1 in common.

Similarly, RB23 is a read data line pair RDQ2, RDQ3 connected to two adjacent banks BK2, BK3 of the read data line pair.
Is a read control circuit commonly connected to the read control circuit.

WB0 to WB3 are four write control circuits connected to the respective write data line pairs WDQ0 to WDQ3.

The read control circuits RB01 and RB23 and the write control circuits WB0 to WB3 are commonly connected to an input / output data line pair RWD, and the input / output data line pair RWD is connected to an input / output buffer (not shown). Write / read data is input / output between

The read control circuits RB01 and RB23 are
Each bank can be selected and read independently, and has a basic function of transferring complementary data read from the selected bank to the input / output data line pair RWD.

The write control circuits WB0 to WB3 are:
Each bank can be independently selected and written, and complementary write data supplied from the input / output data line pair RWD is transferred to a pair of write data line pairs WDQn corresponding to the selected bank BKkn. It has the basic function of

In the multi-bit synchronous DRAM, the read data line pair RDQ0 to RDQ3, the write data line pair WDQ0 to WDQ3, and the input / output data line pair RWD constitute a data bus.

Further, data copy between multi-banks (M
When the BC) mode is designated, an MBC control circuit 20 for realizing a control function of reading data from an arbitrary one of the plurality of memory banks, transferring the data to another memory bank, and writing the data is performed. Is provided.

This MBC control circuit 20 is a column bank selection signal control circuit (see part of FIG. 4) for controlling a column-system bank selection signal corresponding to the banks BK0 to BK3 according to whether the mode is the MBC mode. ) And a first control circuit (MBC read control circuit) added to control the data read control circuits RB01 and RB23 so as to read data from the source bank of the banks BK0 to BK3 in the MBC mode. , See part of FIG. 5)
And a second control circuit section (MBC writing circuit) added so as to control the data write control circuits WB0 to WB3 so as to write data to the write target bank among the banks BK0 to BK3 in the MBC mode. Control circuit, see part of FIG. 6).

FIG. 3 is a timing chart shown to explain an example of the MBC operation in the synchronous DRAM of the first embodiment.

Next, an outline of an example of the MBC operation in the synchronous DRAM of the first embodiment will be described with reference to FIG.

(1) Write Operation Before Entry to MBC Mode Before entering the MBC mode, desired data (for example, test data) is written to any one bank BKkn in the normal operation mode.

(2) Entry into MBC mode As a command to enter into MBC mode,
When the output signal of the clock input buffer 11 rises in a state where a predetermined signal input is set to a predetermined logic level, the command decoder 13 decodes an entry command to generate an MBC by a control signal.
Enter mode.

(3) Bank Selection The row decoder of the data transfer source bank (source bank) and the row decoder of at least one transfer destination bank, which are any one of the banks, are set to the active state. On this occasion,
In this example, all the banks BK0 to BK3 are set to the active state.
.. BK3 are sequentially inputted, and the banks are sequentially activated every time the output signal of the clock input buffer 11 rises.

It should be noted that the order of (2) and (3) is interchanged (after each bank is activated, MB
(Enter C mode).

(4) Input of a column system drive command, input of a source bank selection address signal and input of a transfer destination bank selection address signal A column system drive command, a source bank selection address signal and a transfer destination bank selection address signal are input. At this time, in this example, the column selection lines for all the banks (four banks) are activated.

(5) Initial Read Operation and Data Transfer Operation Data is read only from the source bank specified by the source bank selection address signal, and the read data is transferred to the transfer destination bank.

(6) Data Write Operation in Transfer Destination Bank In the transfer destination bank specified by the transfer destination bank selection address signal, data is written at the timing when the transferred data is determined. At this time, if there is an inactive bank that is not designated as the transfer destination, the row-related bank selection address signal input to the write data buffer circuit corresponding to this bank is controlled to the inactive state.

(7) Exit from MBC Mode When exiting from the MBC mode, an MBC mode exit command is input by setting a predetermined signal input to a predetermined logic level to terminate the MBC mode (normal operation). Return to operation mode).

The synchronous DRA of the first embodiment as described above
According to M, it is possible to designate one of the plurality of memory banks as a source bank, and control to write data read from the source bank to another memory bank via the input / output data line pair RWD. It is possible.

Therefore, by controlling the data read from the source bank to be written to all the memory banks at substantially the same time, the inter-bank copy can be executed at a high speed. For example, the inter-bank copy of the test data is performed. It is very effective when applied to cases.

Hereinafter, a specific configuration example for realizing the above-described operation will be described with reference to FIGS.

FIGS. 4A and 4B are block diagrams showing an example of a column bank selection signal control circuit included in the MBC control circuit 20 in FIG.

As shown in FIG. 4A, the first decoder 41 decodes two-bit bank signals BS0 and BS1 which are a part of a column address signal and their complementary signals to perform four kinds of decoding. An output signal is selectively generated.

These four types of decoded output signals are respectively applied to one input of four two-input NAND gates NG1 to NG4, and the inverted MBC signal obtained by inverting the MBC signal by the inverter circuit IV is output from the four decoded NAND signals. These are the other inputs of the NAND gates NG1 to NG4.

Further, the second decoder 42 is provided as shown in FIG.
As shown in FIG. 7, the bank signals BS0 and BS1 and their complementary signals are decoded to selectively generate four types of decoded output signals. These four types of decoded output signals are correspondingly inverted by four inverters IV1 to IV4.

Thus, when the mode other than the MBC mode (MB
C signal is at “L” level), the inverted MBC signal is at “H”
In the first decoder 41, the signals selectively output from the four NAND gates NG1 to NG4 according to the four types of decode output signals are the first bank select signal Bank0.
Used as ~ Bank3.

On the other hand, when the MBC signal is at the "H" level (MBC mode), the inverted MBC signal is at the "L" level. The output signals Bank0 to Bank3 of the NAND gates NG1 to NG4 become "H", respectively.

Then, in the MBC mode, the second decoder 42 outputs a signal corresponding to four types of decoded output signals.
The signals selectively output from the inverter circuits IV1 to IV4 are used as the second bank selection signals Bank0M to Bank3M.

FIG. 5 shows the read control circuit RB01 in FIG.
And RB23 are representatively extracted and shown.

In the read control circuit shown in FIG. 5, the read buffer circuit 50 connected to the input / output data line pair RWD includes two adjacent banks (for example, BKn,
BKn ') and two read data line pairs (RDQn, / RDQn and RDQn', / RDQn ')
), One of the read data line pairs (RDQn
, / RDQn) via a first transfer gate switching circuit 51 and the other read data line pair (RDQn ', / RDQn') via a second transfer gate switching circuit 52. Have been.

The first transfer gate switching circuit 51
Is a column bank selection signal (Bankn or BanknM).
) Is controlled to be selectively turned on based on the on-state. Similarly, the second transfer gate switching circuit 52 is configured to be selectively turned on based on a column-related bank selection signal (represented by Bankn 'or Bankn'M).

A predetermined bit signal Col Add and a clock signal CLK of a column address for selecting and specifying one of the two banks BKn and BKn ′ corresponding to the read buffer circuit 50 are supplied to a fourth input NAND gate 53. The active state / inactive state of the read buffer circuit 50 is controlled by the output of the NAND gate 53.

Further, the read control circuit of FIG.
An MBC read control circuit for appropriately controlling the two transfer gate switching circuits 51 and 52 according to the BC mode and other operation modes is added.

The MBC read control circuit includes the first
Provided corresponding to the transfer gate switching circuit 51 of FIG.
Clocked inverters 511 and 512 and two clocked inverters 521 and 522 provided corresponding to the second transfer gate switching circuit 52.
And two PMOS transistors P1 and P2 and two CMOS transistors provided on the input side of the NAND gate 53.
It has transfer gates TG1 and TG2.

That is, the operation of the two clocked inverters 511 and 512 provided corresponding to the first transfer gate switching circuit 51 are controlled by complementary MBC signals and inverted MBC signals, respectively. The first bank selection signal Bankn and the second bank selection signal BanknM corresponding to the same bank selectively output from the column bank selection signal control circuit shown in FIG. 4 are inputted, and these two clocked inverters 511 and The output of 512 is supplied as a switching signal to the first transfer gate switching circuit 51 after being wired or connected.

Similarly, the operation of two clocked inverters 521 and 522 provided corresponding to the second transfer gate switching circuit 52 are controlled by complementary MBC signals and inverted MBC signals, respectively. A first bank selection signal Bank corresponding to the same bank selectively output from the column bank selection signal control circuit shown in FIG.
n 'and the second bank selection signal Bankn'M,
These two clocked inverters 521 and 5
22 is wired or connected to the second
Is supplied as a switching signal to the transfer gate switching circuit 52 of FIG.

The source of each of the two PMOS transistors P1 and P2 provided on the input side of the NAND gate 53 is connected to a power supply node (power supply potential Vcc is at "H" level). And MBC
The signal and the inverted MBC signal are input, and the respective drains become the third input and the fourth input of the four-input NAND gate 53.

Further, two CMOS transfer gates TG 1, T 2 provided on the input side of the NAND gate 53 are provided.
G2 receives second bank selection signals BanknM and Bankn'M selectively output from the column bank selection signal control circuit shown in FIG. 4 corresponding to one ends thereof, respectively. Switching is controlled to the same state by the MBC signal.

Here, the operation of the read control circuit of FIG. 5 having the above configuration will be described.

(1) When not in the MBC mode (when the MBC signal is at “L” level), the clocked inverter 51
1 and 521 are activated, and clocked inverters 512 and 522 are inactive.

If the first bank selection signal Bankn supplied from the column bank selection signal control circuit of FIG. 4 corresponding to one of the activated clocked inverters 511 and 521 is active, The first bank selection signal Bankn is supplied to the first transfer gate switching circuit 51.
The first transfer gate switching circuit 51 supplies a read data line pair RDQn,
/ RDQn is connected to the read buffer circuit 50.

Further, the first supplied from the column bank selection signal control circuit of FIG. 4 corresponding to the other 521 of the activated clocked inverters 511 and 521.
Is activated, the first bank selection signal Bankn 'is transferred to the second transfer gate switching circuit 52, and the second transfer gate switching circuit 52 outputs the other bank BKn'. The read data line pair RDQn ′ and / RDQn ′ on the side are connected to the read buffer circuit 50.

Further, as described above, the MBC signal is "L"
Level, two CMOS transfer gates T
G1 and TG2 are each in the off state, but the two PMOS transistors P1 and P2 are in the on state and transfer the power supply potential from the power supply node. Therefore, the third input and the fourth input of the four-input NAND gate 53 are provided. Become "H".

Thus, the four-input NAND gate 53
Is a first input (a predetermined bit signal Col Add of a column address for selecting and specifying one of the two banks BKn and BKn ′ corresponding to the read buffer circuit 50), a second input (clock signal CLK), The logical product of the third input ("H") and the fourth input ("H") is taken, and the output thereof controls the active / inactive state of the read buffer circuit 50.

(2) In the MBC mode (when the MBC signal is at “H” level), the clocked inverter 51
2 and 522 are activated, and clocked inverters 511 and 521 are inactive.

If the second bank selection signal BanknM supplied from the column bank selection signal control circuit of FIG. 4 corresponding to one of the activated clocked inverters 512 and 522 is active, The second bank selection signal BanknM is transferred to the first transfer gate switching circuit 51, and the first transfer gate switching circuit 5
1 is a read data line pair RDQ on one bank BKn side.
n and / RDQn are connected to the read buffer circuit 50.

Further, the second supplied from the column bank selection signal control circuit of FIG. 4 corresponding to the other 522 of the activated clocked inverters 512 and 522.
Is activated, the second bank selection signal Bankn'M is transferred to the second transfer gate switching circuit 52, and the second transfer gate switching circuit 52 is connected to the other bank. The read buffer circuit 50 reads the read data line pair RDQn 'and / RDQn' on the BKn 'side.
Connect to

Further, as described above, the MBC signal is set to "H".
At the time of the level, the two PMOS transistors P1 and P2 are each off, while the two CMOS transfer gates TG1 and TG2 are each on.

Therefore, the two CMOs in the ON state are
The second bank selection signals BanknM and Bankn'M supplied from the column bank selection signal control circuit of FIG. 4 corresponding to the S transfer gates TG1 and TG2 are supplied to the four-input NAND gate 53 at the third input and the fourth input, respectively. Transferred as input.

Thus, a four-input NAND gate 53 is provided.
Is a first input (a predetermined bit signal Col Add of a column address for selecting and specifying one of the two banks BKn and BKn ′ corresponding to the read buffer circuit 50), a second input (clock signal CLK), The logical product of the third input and the fourth input is obtained, and the active state / inactive state of the read buffer circuit 50 is controlled by the output.

As described above, in the normal operation mode other than the MBC mode, the read control circuit shown in FIG. 5 uses the first bank selection signals Bankn and Bankn 'to transfer the gates BKn and BKn' corresponding to the banks BKn and BKn '.
1 and 52 are controlled independently, and the adjacent banks BKn, BK
The read buffer circuit 50 is driven so as to be shared by n ′.

On the other hand, in the MBC mode,
The transfer gate switching circuit corresponding to one source bank is controlled to a selected state by the second bank selection signals BanknM and Bankn'M, and the read buffer circuit 50 is driven so as to be activated only for the source bank.

FIG. 6 shows the write control circuit WB0 in FIG.
FIG. 5 is a block diagram showing one representatively extracted one of .about.WB3.

The write control circuit shown in FIG. 6 includes a CMOS type write data buffer circuit 60 connected to a pair of write data lines WDQn and / WDQn, and a pair of input / output data lines RWDn and / RWDn. Correspond to two first NAND gates (four-input NAND gates in this example) 61 to be the first inputs, and invert the respective outputs of the two NAND gates 61 to complement the write data buffer circuit 60. Input 2
It has the inverters 62.

The two NAND gates 61 receive, as a second input, a signal (a predetermined bit signal Col Add of a column address) for selecting and specifying one corresponding bank BKn.
Further, a logical product of a third input (row-related bank selection signal BSn) and a fourth input (write pulse signal or delayed write pulse signal) to be described later is obtained.

Further, the write control circuit of FIG.
MB for appropriately controlling the inputs of the two NAND gates 61 according to the BC mode and other operation modes
A C write control circuit is added.

This MBC write control circuit comprises a row bank selection signal input circuit 63 and a write pulse input circuit 64 provided corresponding to the third input side and the fourth input side of the four-input NAND gate 61, respectively. Having.

The write pulse input circuit 64 is configured to transfer the clock signal CLK (write pulse signal) directly or via the delay circuit 642.

The row bank selection signal input circuit 63
Is an inverter 631 to which a row bank selection signal BSn is input, and an output signal of the inverter 631 is input, the operation is controlled by a complementary MBC signal and an inverted MBC signal, and the output signal is the four-input NAND gate 6.
Clocked inverter 632 serving as the third input of 1
And a PMOS transistor 633 connected between the Vcc node and the output node of the clocked inverter 632 and having a gate to which the MBC signal is applied.

The write pulse input circuit 64 is switching-controlled by a complementary MBC signal and an inverted MBC signal, and has a CMOS transfer gate 641 for transferring a clock signal CLK (write pulse signal).
A clock delay circuit 642 comprising a plurality of serially connected inverters into which the write pulse signal CLK is branched and inputted, and delays the write pulse signal CLK;
A CMOS transfer gate 643 for controlling the switching by the complementary MBC signal and the inverted MBC signal and transferring the output (delayed write pulse signal) of the clock delay circuit 642;
The outputs of the transfer gates 641 and 643 are wired-OR connected to form the fourth input of the four-input NAND gate 61.

Here, the operation of the write control circuit having the above configuration shown in FIG. 6 will be described.

(1) At times other than the MBC mode (when the MBC signal is at the “L” level), the PMOS transistor 633 of the row-related bank selection signal input circuit 63 is on, and the power supply potential Vcc is transferred from the power supply node. So, said 2
The third input of each of the four input NAND gates 61 is “H”.
become.

When the MBC signal is at "L" level, the CMOS transfer gate 643 is in the ON state and the CMOS transfer gate 641 is in the OFF state in the write pulse input circuit 64. Of the four-input NAND gate 61.

As a result, the two four-input NAND gates 61 are connected to the first input (one of the data of a pair of RWD line pairs) and the second input (one corresponding bank B).
A predetermined bit signal C of a column address that selects and specifies Kn
ol Add) and the third input (row-related bank selection signal BSn) and the fourth input (delayed write pulse signal) described above. The outputs of the two four-input NAND gates 61 are respectively inverted by inverters 62 and become complementary inputs of the write data buffer circuit 60.

(2) In the MBC mode (when the MBC signal is at “H” level), the PMOS transistor 633 of the row bank selection signal input circuit 63 is off, and the clocked inverters 631 and 632 are activated. You. As a result, the row-related bank selection signal BSn
Are connected to the two four-input NAND gates 61 via the activated clocked inverters 631 and 632.
Is the third input.

When the MBC signal is at "H" level, the CMOS transfer gate 643 is off and the CMOS transfer gate 641 is on in the write pulse input circuit 64. The write pulse signal is transferred and the two Fourth input of the four-input NAND gate 61
Input.

In the write control circuit corresponding to the bank selected as the write target (active bank), the two four-input NAND gates 61
The row input bank selection signal BS which is the third input described above.
n is active, a first input (one of a pair of input / output data line pair RWDn, / RWDn data), and
The logical product of the second input (a predetermined bit signal Col Add of a column address for selecting and specifying one corresponding bank BKn) and the above-described fourth input (write pulse signal) is calculated. The outputs of the two four-input NAND gates 61 are respectively inverted by inverters 62 and become complementary inputs of the write data buffer circuit 60.

On the other hand, in a write control circuit corresponding to a bank which is not selected as a write target (inactive bank), the two four-input NAND gates 61 are connected to the above-mentioned third input, ie, a row which is the third input. System bank select signal BSn is inactive, and the output is fixed at "H" level. The output “H” of the two four-input NAND gates 61 corresponding to the respective outputs “H” and inverted by the inverter 62 becomes the input of the write data buffer circuit 60.

As described above, in the normal operation mode other than the MBC mode, the write control circuit shown in FIG. 6 uses the data of the input / output data line pair RWD and / RWD and the column address bit signal Col Add for bank selection designation. Of the input / output data line pair R
Complementary write data is transferred from WD and / RWD to the selected bank (active bank).

On the other hand, in the MBC mode,
The logical product of the data of the pair of input / output data lines RWD, / RWD, the column address bit signal Col Add for bank selection designation, and the write pulse signal is read from the source bank to the input / output data line pairs RWD, / RWD. The output complementary data is transferred as write data to a selected bank (active bank).

[0108]

As described above, according to the semiconductor memory device having the multi-bank configuration of the present invention, the semiconductor memory device has a function of writing data read from a specific bank to another bank. It can be shortened and is suitable for application to a synchronous DRAM or the like.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a part of a synchronous DRAM having a multi-bank configuration according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a typical one bit extracted from four banks and input / output paths of read / write data in FIG. 1;

FIG. 3 is a timing chart illustrating an example of an MBC operation in the synchronous DRAM according to the first embodiment;

FIG. 4 is a block diagram showing an example of a column bank selection signal control circuit included in the MBC control circuit in FIG. 2;

FIG. 5 is a block diagram typically showing one of the read control circuits shown in FIG. 2;

FIG. 6 is a block diagram typically showing one of the write control circuits in FIG. 2;

FIG. 7 shows a conventional synchronous DRAM having a multi-bank configuration.
FIG. 4 is a block diagram showing one representative bit of the four banks BK0 to BK3 and the input / output path of read / write data in FIG.

[Explanation of symbols]

 BK0 to BK3: Bank, RB01, RB23: Data read control circuit, WB0 to WB3: Data write control circuit, 20: MBC control circuit.

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Shigeo Oshima 580-1 Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa F-term in Toshiba Semiconductor System Technology Center (reference) 5B024 AA15 BA15 BA25 CA16 EA02 5L106 AA01 DD01 DD06 GG05

Claims (5)

[Claims] 1. A semiconductor memory device having a multi-bank configuration, wherein an arbitrary one of a plurality of memory banks is designated as a source bank based on a command designating an inter-bank data copy mode, and A semiconductor memory device comprising: an inter-bank data copy control circuit for controlling read data to be written into at least one remaining memory bank. 2. A plurality of memory banks in which a memory cell array and circuits related thereto are divided into a plurality of groups; a data read control circuit for selectively reading data from each of the memory banks; A data write control circuit for periodically writing data, a data line commonly connected to the plurality of memory banks, and an arbitrary one of the plurality of memory banks based on a command designating an inter-bank data copy mode. Is designated as a source bank, and data read from the source bank is transferred to at least one of the remaining data via the data line.
A semiconductor memory device comprising: an inter-bank data copy control circuit that controls the data read control circuit and the data write control circuit so as to write data into one memory bank. 3. The semiconductor memory device according to claim 2, wherein said inter-bank data copy control circuit includes a column bank corresponding to said plurality of memory banks according to whether or not the inter-bank data copy mode is set. A bank selection signal control circuit that controls a selection signal; and a first control circuit unit that controls the data read control circuit to read data from a source bank of the plurality of memory banks in the inter-bank data copy mode. And a second control circuit unit that controls the data write control circuit so as to write data to a write target memory bank of the plurality of memory banks in the inter-bank data copy mode. A semiconductor memory device characterized by the following. 4. The semiconductor memory device according to claim 1, wherein test data is written to said source bank before entering said inter-bank data copy mode. apparatus. 5. The semiconductor memory device according to claim 4, wherein said inter-bank data copy control circuit controls so that data read from said source bank is written to all memory banks substantially simultaneously. Semiconductor storage device.