JP2000036199A - Pattern generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the testing time by providing a pattern holding circuit, which holds a prescribed cycle of the pattern, for a generator that generates the pattern. SOLUTION: A next address program or an erasing pattern is prepared for pipelines FF1 to FFn in a pattern generator 20 after outputting a program or the erasing pattern. Then, the program of a present address and the erasing pattern are stored in a pattern holding circuit 26. If a selector SEL1 selects a 'b' side by a selection signal SLB, the program of the present address or the erasing pattern held in the circuit 26 is outputted. Then, the output of an SEL 3 is returned to a terminal 'b' side of an SEL2, the circuit 26 becomes a loop circuit and same patterns are repeatedly generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a pattern generator of a semiconductor memory test device for testing a flash memory.

[0002]

2. Description of the Related Art An example of the prior art will be described with reference to FIGS. First, the schematic configuration and operation of the semiconductor memory test device will be described. As shown in FIG. 5, a semiconductor memory test apparatus for testing a memory under test 40 includes a timing generator 10, a pattern generator 20, a waveform shaper 3
0, a logical comparator 50 and a failure analysis memory 60.

[0005] A timing generator 10 receives a clock control signal from a pattern generator 20 and generates a reference clock.

[0004] The pattern generator 20 receives the reference clock from the timing generator 10 and outputs an address signal, a test data signal, a control signal, and expected value data.

These address signals, test data signals,
The control signal is provided to the waveform shaper 30, where the control signal is shaped into a waveform necessary for the test and applied to the memory under test 40.

Then, test data is written to the address of the memory under test 40 by a control signal, and read control is performed.

Further, the read data read from the memory under test 40 is given to a logical comparator 50, where it is compared with expected value data output from the pattern generator 20, and a match / mismatch result is obtained. Then, the quality of the memory under test is determined. In addition, the memory under test 4 in which a defect has occurred
The address and data of 0 are stored in the failure analysis memory 60 to perform failure analysis.

Next, a flash memory serving as the memory under test 40 will be described. In recent years, flash memory has
It has attracted attention as a large-capacity, rewritable nonvolatile memory. In general, a flash memory has a variation between memory cells due to its structure. Therefore, it is not always possible to successfully write data to all memory cells by one write operation at each address. Therefore, the write operation is usually repeated a plurality of times. There is a need.

[0009] The number of times until the flash memory is successfully written differs depending on the type of the flash memory, and also differs for each address even in the same flash memory. Similarly, the number of times until the flash memory is successfully erased differs depending on the type of the flash memory, and also differs for each address even in the same flash memory. For example, the prescribed write count of a certain type of flash memory is 25 times, and the prescribed erase count is 1000 times.

Therefore, in the data write (program) test of the flash memory, when the test pattern data can be repeatedly written within a specified number of times in all the memory cells to which the data is to be written, the write (program) of the memory under test is performed. ) Judge the test as a pass.
The same applies to the data erasure test of the flash memory. If all the memory cells whose data is to be erased can be erased repeatedly within a specified number of times, the erasure test of the memory under test is determined to pass. As described above, the flash memory that has passed the write (program) test and the erase test becomes a non-defective product.

Next, the internal structure of the conventional pattern generator 20 will be described with reference to FIG. The conventional pattern generator 20 includes an address generator 21, a data generator 22,
It comprises a control signal generator 23 and a sequence controller 24 for controlling these. However, other parts are omitted for simplicity of the figure.

The address generator 21, the data generator 22, and the control signal generator 23 have a plurality of flip-flops FF1 to FFn.
The pipeline operation is performed by the reference clock generated at 0. The pipeline needs flip-flops of the necessary number of stages for preprocessing the test pattern of the memory under test and operating at high speed, for example, 50 stages. Therefore, when starting the test, the waveform shaper 30
The address, data, and control signals are output after the clocks for the number of flip-flop stages in the pattern generator 20 have been input.

Further, when the memory under test 40 is a device having a fluctuating test flow, such as a flash memory, the above-described preceding processing cannot be performed for the following reason. In the case of a flash memory, the subsequent test flow changes depending on whether the result of the pass / fail judgment of the writing or erasing pass / fail (verify).

In other words, in the case of a flash memory, unlike a device having a standard and uniform test flow, the sequence of pattern generation changes depending on the output result, so that pre-processing cannot be performed. Therefore, the data of the test pattern is repacked in the flip-flops of the pipeline, and
For 0, the following test pattern is applied.

The flow of a program test for writing data into a flash memory by the conventional pattern generator 20 will be described below with reference to FIG.

(1) The initial value N of the number of times of programming is reset to 0 (step 100).

(2) The test target address (A) of the flash memory under test is set (step 200).

(3) Generate and output a program pattern from the pattern generator (step 310).

(4) By adding 1 to the number of program N, N
(Step 410).

(5) The read data and the expected value data are compared by the logical comparator 50. If the data is fail, the process proceeds to step 600, and if the data is pass, the process proceeds to step 7.
Go to 00 (step 500).

(6) If N is equal to or greater than a specified value, a failure (Fa)
il), and if N is less than the specified value, the process proceeds to step 630 (step 600).

(7) It is determined again that the flash memory of the memory under test 40 is to be programmed (step 630).

(8) The pipeline of the pattern generator 20 is repacked, and the process returns to step 310 (step 640).

(9) If the address PASSed in step 500 is the last address, the program test of the flash memory of the memory under test becomes PASS, and if not, the process proceeds to step 730 (step 70).
0).

(10) The pipeline of the pattern generator 20 is repacked, and the process returns to step 100 (step 730).

As described above, the program test of the flash memory as the memory under test 40 is performed. Further, an erase test of the flash memory as the memory under test 40 is performed as shown in FIG.
The description is omitted because it is the same as the program test shown in FIG.

As described in the above flow, in the conventional test, after performing the program or erase operation, if the result of the pass / fail judgment of the address range to be tested is a pass, the test of the next address and the failure If so, the next pattern to be applied to the memory under test is determined based on the reprogramming or reerasing operation and the determination result of the test target address.

At this time, the pattern generator 20 is in a standby state from when a pattern of a program or erase operation is given to the memory under test 40 to when a pass / fail judgment is input to the pattern generator 20. After the input, according to the result, the pattern given to the memory under test is repacked in each flip-flop of the pipeline.

After the repacking is completed, the address, data, and control signals output from the pattern generator are supplied to the memory under test 40 via the waveform shaper 30, as in the normal operation.

For example, as shown schematically in FIG. 4A, the operation of the flash memory program test or erase test has three cycles (1, 2).
2, 3) If necessary, if the clock is 20 MHz, one cycle is 50 ns.

That is, the time to repack the pipeline is
If the number of flip-flops is 50, 2.5 μs is required, and if the waiting time is 1 μs, a total of 3.5 μs is required for one program test or erase test. Therefore, when testing the same pattern a plurality of times, 3.5 times each time
μs is required.

Therefore, when the test is repeatedly performed with the same pattern, the time required from the application of the program or erase operation pattern to the memory under test to the application of the next pattern becomes longer due to the refilling of the pipeline. Becomes longer.

[0033]

As described above, when a test is repeatedly performed with the same pattern, a program or erase operation pattern is applied to the memory under test by refilling the pipeline until the next pattern is applied. And the test time becomes longer as a result, which is inconvenient for practical use. Therefore, the present invention has been made in view of such problems, and the purpose is to
When testing a flash memory, it is an object to provide a pattern generator in which the time from when a program or erase operation pattern is given to a memory under test to when the next identical pattern is given does not become long.

[0034]

The first object of the present invention to achieve the above object is to generate a test pattern by operating a plurality of flip-flops (FF1 to FFn) in a pipeline with a reference clock. The gist of the present invention is a pattern generator characterized by comprising a pattern holding circuit for holding a predetermined cycle of the test pattern.

The second object of the present invention to achieve the above object is to provide a multi-stage flip-flop (FF1 to FF).
In a pattern generator that generates a test pattern by pipeline-operating n) with a reference clock, a pattern holding circuit that holds a predetermined cycle of the test pattern and a pattern of a predetermined cycle of the pattern holding circuit are selected. A third selector (SEL3) for outputting, and the output of the third selector or the flip-flops (FF1 to F
A second selector (SEL2) that selects an output of the pipeline of Fn) and outputs it to the pattern holding circuit, a pipeline output of the flip-flop (FF1 to FFn), or the third selector (SEL3). A) a first selector (SEL1) for selecting and outputting the output of (1), and a control circuit for controlling the reference clock and the first, second and third selectors. The vessel is the gist.

[0036]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in the following examples.

[0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. The configuration of the semiconductor memory test apparatus is the same as the conventional one as shown in FIG. However, since the internal configuration of the pattern generator 20 is different, its configuration and operation will be described below.

Referring to FIG. 1, the internal configuration of the pattern generator 20 of the present invention will be described. The pattern generator 20 of the present invention includes an address generator 21, a data generator 22,
It comprises a control signal generator 23 and a sequence controller 24 for controlling these. The blocks corresponding to the conventional ones are assigned the same numbers as the conventional ones. The address generation unit 21, the data generation unit 22, and the control signal generation unit 23 have a pattern holding circuit 26 and a selector, respectively.
SEL1 is additionally provided, and a flash memory test control circuit 25 is additionally provided in the sequence control unit 24. The pattern holding circuit 26 includes selectors SEL2 and SEL3.
And flip-flops FF1 to FFm.

Hereinafter, each component will be described. However, since the address generator 21, the data generator 22, and the control signal generator 23 have the same configuration, the address generator 21 will be mainly described.

The selector SEL1 selects the side a of the pipeline system in the normal operation and the side b of the pipeline system of the pattern holding circuit used in the flash memory test in accordance with the selection signal SLB.

The selector SEL2 is provided with a pattern holding circuit 26.
Is a selector that selects the input signal of Also, the selector
The selection signal of SEL2 is the same SLB as that of SEL1, and at the time of reprogramming or re-erasing operation, the b side of SEL2 is selected and the output signal of SEL3 returns in the pattern holding circuit 26 and loops. In other cases, the side a is selected and the output signal of the pipeline system of the normal operation is input.

With this control, the program or erase pattern of the next address is prepared in the pipelines FF1 to FFn in the pattern generator 20 after the output of the program or erase pattern, and the current pattern is held in the pattern holding circuit. The address program and erase pattern are stored. Thereafter, control of stopping the reference clock is performed on the timing generator, and a standby state is waited for a result of the pass / fail determination.

The flip-flops FF1 to FFm of the pattern holding circuit 26 are circuits for holding addresses, data, and control signals during a program or erase operation.
The flip props FF1 to FFm are provided with a number of stages equal to or more than the number of cycles required for a flash memory program or erase operation command of the memory under test, for example, eight stages.

When the re-program or re-erase operation is executed when the pass / fail judgment result is FAIL, the selector SEL3 selects the first pattern of the program or re-erase operation from the held addresses, data and control signals. Is a selector for selecting.

Further, the output of the selector SEL3 becomes the input of SEL2 at the time of the reprogramming or reerasing operation. Also,
As for the selection signal SELA of the selector SEL3, the number of flip-flops to be selected is determined by the number of cycles required for a program or erase operation command. For example,
If the number of command cycles required for testing the flash memory under test is three, the output of the flip-flop FF3 is selected by the selection signal SELA and output from the selector SEL3.

Then, when the CKIH signal is 0, the clock CLK1 is output from the gate in the flash memory test control circuit 25, and the normal pipeline FF
1 to FFn, and when the CKIH signal is 1, the output of the clock CLK1 is inhibited from the gate and the pattern holding circuit 26
Output only the pattern held in.

The clock CLK2 is a reference clock, and is an operation clock of the pipeline of the pattern holding circuit 26.

Also, the selector SEL is selected by the selection signal SLB.
When 1 selects the b side, the program or erase pattern of the current address held in the pattern holding circuit 26 is output. Then, according to the selection signals SLA and SLB, the output of the selector SEL3 is returned to the terminal b side of SEL2, and the pattern holding circuit 26 becomes a loop circuit, and the same pattern can be repeatedly generated.

On the other hand, the selector SEL is selected by the selection signal SLB.
When 1 selects the a side, the flip-flops FF1 to FFn are output with a program or erase pattern. And
After all the patterns required for the program or the erasing operation are output, the timing generator is controlled to stop the reference clock, and the system enters a wait state for waiting for the result of the pass / fail judgment.

By this control, the program or erase pattern of the next address is prepared in the normal pipeline system and the pattern holding circuit 26 has the current state as in the case of waiting for the result of the previous pass / fail judgment. At which the program or erase pattern of the address is stored.
Next, a program test for writing data into a flash memory by the pattern generator 20 of the present invention will be described in the following paragraphs with reference to the flowchart of FIG. The steps of the same operation as the conventional flow have the same step number as the conventional.

(1) Set the initial value N of the number of program tests to 0
(Step 100).

(2) The test target address (A) of the flash memory under test is set (step 200).

(3) The program pattern of the address (A) is generated and the next address (A + 1) is set (step 300).

(4) Simultaneously with outputting the program pattern of the address (A) from the pipeline and holding the pattern in the pattern holding circuit, and generating the program pattern of the next address (A + 1) (step 400). .

(5) The read data and the expected value data are compared by the logical comparator 50. If the read data is “Fail”, the procedure proceeds to Step 600, and if the data is “Pass”, Step 7 is performed.
Go to 00 (step 500).

(6) If the number N of program tests is equal to or more than the specified value, it is determined as fail, and if N is less than the specified value, the process proceeds to step 610 (step 600).

(7) N + 1 is substituted for the number N of program tests (step 610).

(8) The program pattern of the current address held in the pattern holding circuit 26 is output, and the process returns to step 500 (step 620).

(9) If the address passed in step 500 is the last address, the program test of the flash memory of the memory under test becomes PASS, and if not, the process proceeds to step 710 (step 70).
0).

(10)) The number N of program tests is reset to 0 (step 710).

(11) Next test target address (A +
2) is substituted for A, and the process returns to step 400 (step 720). As described above, the program test of the flash memory as the memory under test is performed. Further, the erase test of the flash memory as the memory under test is performed according to the flowchart shown in FIG. 3, but the description is omitted because it is the same as the program test shown in FIG.

Therefore, as shown schematically in FIG. 4B, the operation of the flash memory program test or erase test has three cycles (1, 2).
2, 3) If necessary, if the clock is 20 MHz, one cycle is 50 ns.

That is, in the first test, the time for refilling the pipeline is 2.5 μs when the flip-flop is 50 stages, and 1 time when the waiting time is 1 μs.
3.5μ total for the second program test or erase test
s is required. However, since the second and subsequent tests output from the pattern holding circuit 26 side, there is no need to refill the pipeline, and if the flip-flop is 150 ns for three stages and the waiting time is 1 μs, the second test is performed. The subsequent program test or erase test requires only 1.15 μs. Therefore, in the case of performing the test with the same pattern a plurality of times, the test time that conventionally required 3.5 μs each time can be reduced to 1.15 μs each time after the second time.

[0064]

The present invention is embodied in the form described above and has the following effects. That is,
In the pattern generator of the present invention, when the same pattern is tested a plurality of times, the pipeline is refilled for the second and subsequent times, while the pattern given to the flash memory under test is output from the pattern holding circuit. The time from when an operation pattern is given to when the next same pattern is given becomes short, and as a result, there is an effect that the test time can be shortened.

[Brief description of the drawings]

FIG. 1 is a block diagram of a pattern generator according to the present invention.

FIG. 2 is a flowchart of a program test of a semiconductor memory test device using the pattern generator of the present invention.

FIG. 3 is a flowchart of an erase test of a semiconductor memory test device using the pattern generator of the present invention.

FIG. 4 is a schematic diagram of a pattern generation example of a pattern generator.

FIG. 5 is a block diagram of a semiconductor memory test device.

FIG. 6 is a flowchart of a program test of a semiconductor memory test device using a conventional pattern generator.

FIG. 7 is a flowchart of a program test of a conventional semiconductor memory test device using a pattern generator.

FIG. 8 is a flowchart of an erase test of a semiconductor memory test device using a conventional pattern generator.

[Explanation of symbols]

 Reference Signs List 10 timing generator 20 pattern generator 21 address generator 22 data generator 23 control signal generator 25 flash memory test control circuit 26 pattern holding circuit 30 waveform shaper 40 memory under test 50 logical comparator 60 failure analysis memory

Claims (2)

[Claims] 1. A plurality of flip-flops (FF1 to FFn)
A pattern generator for generating a test pattern by pipeline-operating a test pattern with a reference clock, comprising: a pattern holding circuit for holding a predetermined cycle of the test pattern. 2. A plurality of flip-flops (FF1 to FFn)
A pattern generator for generating a test pattern by pipeline-operating a pattern with a reference clock, and a circuit for holding a predetermined cycle of the test pattern, and selectively outputting a pattern of a predetermined cycle of the pattern holding circuit. A third selector (SEL3), and a second selector (SEL2) for selecting an output of the third selector or an output of a pipeline of the flip-flops (FF1 to FFn) and outputting to the pattern holding circuit. )
A first selector (SEL1) for selecting and outputting a pipeline output of the flip-flops (FF1 to FFn) or an output of the third selector (SEL3); the reference clock, the first, second, and And a control circuit for controlling a third selector.