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JP2000031358A - Power semiconductor module - Google Patents

Power semiconductor module

Info

Publication number
JP2000031358A
JP2000031358A JP10208665A JP20866598A JP2000031358A JP 2000031358 A JP2000031358 A JP 2000031358A JP 10208665 A JP10208665 A JP 10208665A JP 20866598 A JP20866598 A JP 20866598A JP 2000031358 A JP2000031358 A JP 2000031358A
Authority
JP
Japan
Prior art keywords
power semiconductor
metal base
semiconductor chip
insulating substrate
semiconductor module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10208665A
Other languages
Japanese (ja)
Inventor
Atsushi Yamamoto
厚志 山本
Yoichi Makimoto
陽一 牧本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sansha Electric Manufacturing Co Ltd
Original Assignee
Sansha Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sansha Electric Manufacturing Co Ltd filed Critical Sansha Electric Manufacturing Co Ltd
Priority to JP10208665A priority Critical patent/JP2000031358A/en
Publication of JP2000031358A publication Critical patent/JP2000031358A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612Auxiliary members for layer connectors, e.g. spacers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385Shape, e.g. interlocking features

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Punching Or Piercing (AREA)

Abstract

PROBLEM TO BE SOLVED: To reduce the number of manufacturing processes and a cost by providing a recessed part at a specified position when stamping a metal base. SOLUTION: A copper plate, for example, of a regular size or band-like shape is stamped out to provide a metal base. At stamping, a specified position of the metal base is applied with a pressure to form a first recessed part 1a on the surface. After formation of the recessed part 1a, a solder foil 5 is inserted in the recess, and an insulating substrate 4 of a ceramic plate, etc., which has a circuit arrangement of silver foil is mounted on the solder foil 5. Further, a power semiconductor chip 8 is mounted at a specified position on one surface of the insulating substrate 4 through a solder foil 7. When they are heated, the power semiconductor chip 8 is soldered to a specified position of the metal base 1 through the insulating substrate 4 by the recessed part 1a provided at the specified position of the metal base 1. Thus, the number of processes is reduced, resulting in a low-cost power semiconductor module.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は,金属ベース上に電
力用半導体チップが搭載する電力用半導体モジュールに
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor module having a power semiconductor chip mounted on a metal base.

【0002】[0002]

【従来の技術】従来,金属ベース上に,銅箔による回路
配置されたセラミックス板等の絶縁基板を搭載し,さら
に,この絶縁基板上に電力用チップを搭載し,それぞれ
半田付けする電力用半導体モジュールがある。この電力
用半導体モジュールは,出力端子板が電力用半導体チッ
プに直接又はワイヤーにより接続される。この電力用半
導体チップ及び出力端子板が正確な位置が得られていな
いと,出力端子が歪んだり,半田付けが不十分になるな
どの品質上の問題を有している。
2. Description of the Related Art Conventionally, a power semiconductor is mounted on a metal base by mounting an insulating substrate such as a ceramic plate on which a circuit is formed by copper foil, and further mounting a power chip on the insulating substrate and soldering each. There is a module. In this power semiconductor module, the output terminal plate is connected to the power semiconductor chip directly or by a wire. If accurate positions of the power semiconductor chip and the output terminal board are not obtained, there are quality problems such as distortion of the output terminals and insufficient soldering.

【0003】このため,電力用半導体チップは正しい位
置に搭載する方法が各種提案されている。例えば,図5
のものは金属ベース51上にレジストを塗布し,半田の
なじまない層52を設け,この半田のなじまない52の
開口部52aに,両面に金属層が形成された絶縁基板5
4が,半田箔55を介して搭載されている。さらに,絶
縁基板54の一方の面には,銅箔及びめっきにより位置
が決められた所定位置に電力用半導体チップ58が半田
箔57を介して搭載されている。これら金属ベース5
1,半田55,絶縁基板54,半田57,電力用半導体
チップ58をリフロー炉に入れ加熱することにより,金
属ベース51と,絶縁基板54と,電力用半導体チップ
58とが半田付けされる。
For this reason, various methods have been proposed for mounting a power semiconductor chip at a correct position. For example, FIG.
Is coated with a resist on a metal base 51 to provide a layer 52 to which solder does not fit. An insulating substrate 5 having a metal layer formed on both surfaces is formed in an opening 52a of the solder to which it does not fit.
4 are mounted via the solder foil 55. Further, on one surface of the insulating substrate 54, a power semiconductor chip 58 is mounted via a solder foil 57 at a predetermined position determined by copper foil and plating. These metal bases 5
1, the metal base 51, the insulating substrate 54, and the power semiconductor chip 58 are soldered by placing the solder 55, the insulating substrate 54, the solder 57, and the power semiconductor chip 58 in a reflow furnace and heating.

【0004】これにより,電力用半導体チップ58は金
属ベース51の所定位置に半田付けされることになる。
As a result, the power semiconductor chip 58 is soldered to a predetermined position on the metal base 51.

【0005】また,図6に示すように電力用半導体チッ
プ62を金属ベース61に直接半田付けする場合,金属
ベース61と,電力用半導体チップ62の上部の半導体
層62aとの間の空間距離Aが小さいため,金属ベース
61と電力用半導体チップ62とを半田付けする半田層
が,金属ベース61と半導体チップ62の上部の半導体
層62aとを短絡し,十分な耐圧を得ることができなく
なることがあった。
When the power semiconductor chip 62 is directly soldered to the metal base 61 as shown in FIG. 6, a spatial distance A between the metal base 61 and the upper semiconductor layer 62a of the power semiconductor chip 62 is obtained. Is small, the solder layer for soldering the metal base 61 and the power semiconductor chip 62 causes a short circuit between the metal base 61 and the semiconductor layer 62a above the semiconductor chip 62, so that a sufficient withstand voltage cannot be obtained. was there.

【0006】[0006]

【発明が解決しようとする課題】図5の電力用半導体モ
ジュールでは,金属ベース上の位置決めのために,レジ
ストを塗布し,そのレジストを乾燥させる作業が必要に
なるなど,工程が多用化する問題がある。また,レジス
トを塗布するための治具,マスクなどが必要になるな
ど,電力用半導体モジュールを高価にする要因となって
いた。
In the power semiconductor module shown in FIG. 5, there is a problem that the process is used frequently, such as the necessity of applying a resist and drying the resist for positioning on the metal base. There is. In addition, a jig, a mask, and the like for applying a resist are required, and this is a factor that makes the power semiconductor module expensive.

【0007】また,図6の電力用半導体モジュールで
は,金属ベース61と半導体層62aとの短絡を防止す
るために,電力用半導体チップ62の下に銅,モリブデ
ン等の金属を予め敷かれて,高温半田により半田付けさ
れている。このため,電力用半導体モジュールの製造工
程において,電力用半導体チップに銅,モリブデン等の
金属を半田付けする工程が増える等,電力用半導体モジ
ュールを高価にする要因となっていた。
In the power semiconductor module of FIG. 6, a metal such as copper or molybdenum is preliminarily spread under the power semiconductor chip 62 in order to prevent a short circuit between the metal base 61 and the semiconductor layer 62a. Soldered with high temperature solder. For this reason, in the manufacturing process of the power semiconductor module, the number of steps of soldering a metal such as copper or molybdenum to the power semiconductor chip has increased, which has caused the power semiconductor module to be expensive.

【0008】[0008]

【課題を解決するための手段】請求項1記載の電力用半
導体モジュールは,金属ベースに電力用半導体チップを
搭載してなる電力用半導体モジュールで,上記金属ベー
スの打ち抜き加工時に,所定位置に凹部が設けられた金
属ベースである。
According to a first aspect of the present invention, there is provided a power semiconductor module comprising a metal base and a power semiconductor chip mounted thereon, wherein the metal base has a concave portion at a predetermined position when the metal base is punched. Is a metal base provided.

【0009】上記金属ベースは,例えば定尺又は帯状の
銅板を打ち抜き加工して形成される。この打ち抜き加工
時に,所定位置に圧力を加えて,例えば0.3〜0.8
mm程度の凹部が設けられる。
The metal base is formed, for example, by stamping a fixed-size or band-shaped copper plate. During this punching process, pressure is applied to a predetermined position, for example, 0.3 to 0.8.
A recess of about mm is provided.

【0010】すなわち,凹部が金属ベースの打ち抜き加
工と同時に行われる。
That is, the recess is formed simultaneously with the punching of the metal base.

【0011】請求項2記載の電力用半導体モジュール
は,上記金属ベースの打ち抜き加工時に,上記電力用半
導体チップが搭載される所定位置に凹部が設けられた金
属ベースである。
According to a second aspect of the present invention, the power semiconductor module is a metal base having a concave portion provided at a predetermined position where the power semiconductor chip is mounted when the metal base is punched.

【0012】上記金属ベースは,例えば定尺又は帯状の
銅板を打ち抜き加工して形成される。この打ち抜き加工
時に,電力用半導体チップが搭載される所定位置に圧力
を加えて,例えば0.3〜0.8mm程度の凹部が設け
られる。この凹部に半田箔を搭載し,この半田箔上に直
接又はセラミックス等の絶縁基板を搭載して,電力用半
導体チップが搭載されて加熱され半田付けされる。
The metal base is formed, for example, by stamping a fixed-length or band-shaped copper plate. During this punching process, a pressure is applied to a predetermined position where the power semiconductor chip is mounted, so that a concave portion of, for example, about 0.3 to 0.8 mm is provided. A solder foil is mounted in the recess, and an insulating substrate such as a ceramic or the like is mounted directly on the solder foil, and a power semiconductor chip is mounted and heated and soldered.

【0013】請求項3記載の電力用半導体モジュール
は,上記金属ベースの打ち抜き加工時に,上記電力用半
導体チップが搭載される位置を指示する位置に凹部が設
けられた金属ベースである。
According to a third aspect of the present invention, the power semiconductor module is a metal base having a concave portion provided at a position indicating a position at which the power semiconductor chip is mounted when the metal base is punched.

【0014】上記金属ベースは,例えば定尺又は帯状の
銅板を打ち抜き加工して形成される。この打ち抜き加工
時に,電力用半導体チップが搭載される位置を指示する
位置に圧力を加えて,例えば0.3〜0.8mm程度の
凹部が設けられる。この凹部に半田箔が搭載され,この
半田箔上に絶縁基板が搭載され,さらに,電力用半導体
チップが搭載されて加熱され半田付けされる。
The metal base is formed, for example, by punching a fixed-size or band-shaped copper plate. During this punching process, pressure is applied to a position indicating the position where the power semiconductor chip is to be mounted, so that a concave portion of, for example, about 0.3 to 0.8 mm is provided. A solder foil is mounted in the recess, an insulating substrate is mounted on the solder foil, and a power semiconductor chip is mounted, heated and soldered.

【0015】請求項4記載の電力用半導体モジュール
は,上記金属ベースの打ち抜き加工時に,上記電力用半
導体チップが搭載される所定位置を囲むように凹部が設
けられた金属ベースである。
According to a fourth aspect of the present invention, the power semiconductor module is a metal base having a concave portion surrounding a predetermined position where the power semiconductor chip is mounted when the metal base is punched.

【0016】上記金属ベースは,例えば定尺又は帯状の
銅板を打ち抜き加工して形成される。この打ち抜き加工
時に,電力用半導体チップが搭載される所定位置を囲む
ように圧力を加えて,例えば0.3〜0.8mm程度の
凹部が設けられる。この凹部に囲まれる砲台に半田箔を
介して電力用半導体チップが搭載されて加熱され半田付
けされる。
The metal base is formed, for example, by punching a fixed-size or band-shaped copper plate. During this punching process, a pressure is applied so as to surround a predetermined position on which the power semiconductor chip is mounted, so that a concave portion of, for example, about 0.3 to 0.8 mm is provided. A power semiconductor chip is mounted on a turret surrounded by the concave portion via a solder foil, heated and soldered.

【0017】請求項5記載の電力用半導体モジュール
は,金属ベースと,上記金属ベース上に搭載された絶縁
基板と,上記絶縁基板上に搭載された出力端子と,上記
出力端子上に搭載された電力用半導体チップとを備え,
上記出力端子が打ち抜き加工され,その打ち抜き加工時
に所定位置に凹部が設けられた出力端子である。
According to a fifth aspect of the present invention, there is provided a power semiconductor module having a metal base, an insulating substrate mounted on the metal base, an output terminal mounted on the insulating substrate, and mounted on the output terminal. Power semiconductor chip,
The output terminal is an output terminal in which a punching process is performed on the output terminal, and a concave portion is provided at a predetermined position during the punching process.

【0018】出力端子は,例えば定尺又は帯状の銅板を
打ち抜き加工して形成される。この打ち抜き加工時に,
電力用半導体チップが搭載される所定位置に圧力を加え
て,例えば0.3〜0.8mm程度の凹部が設けられ
る。この凹部が出力端子の打ち抜き加工と同時に行われ
る。
The output terminal is formed, for example, by stamping a fixed-size or band-shaped copper plate. During this punching process,
A pressure is applied to a predetermined position on which the power semiconductor chip is mounted, so that a recess of, for example, about 0.3 to 0.8 mm is provided. This recess is formed simultaneously with the punching of the output terminal.

【0019】[0019]

【発明の実施の形態】本発明の第1の実施の形態を,図
1に基づいて説明する。図1において1は金属ベースで
あり,例えば定尺又は帯状の銅板を打ち抜き加工し,金
属ベースを得る。この打ち抜き加工時,金属ベースの所
定位置に圧力を加え,表面が0.3〜0.8mm程度の
第1の凹部1aを形成する。この凹部1aの形成後,凹
みに半田箔5を挿入し,この半田箔5上に銅箔により回
路配置されたセラミックス板等の絶縁基板4を搭載し,
さらにこの絶縁基板4の一方の面の所定位置に半田箔7
を介して電力用半導体チップ8を搭載している。これら
金属ベース1,半田5,絶縁基板4,半田7,電力用半
導体チップ8をフリロー炉に入れて加熱すると,金属ベ
ース1と絶縁基板4と電力用半導体チップ8とが半田付
けされる。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIG. In FIG. 1, reference numeral 1 denotes a metal base, for example, a standard-size or band-shaped copper plate is punched to obtain a metal base. During this punching process, pressure is applied to a predetermined position of the metal base to form a first concave portion 1a having a surface of about 0.3 to 0.8 mm. After the formation of the concave portion 1a, the solder foil 5 is inserted into the concave portion, and the insulating substrate 4 such as a ceramic plate or the like arranged by copper foil on the solder foil 5 is mounted.
Further, a solder foil 7 is provided at a predetermined position on one surface of the insulating substrate 4.
The power semiconductor chip 8 is mounted via the power supply. When the metal base 1, the solder 5, the insulating substrate 4, the solder 7, and the power semiconductor chip 8 are heated in a freezing furnace, the metal base 1, the insulating substrate 4, and the power semiconductor chip 8 are soldered.

【0020】そして,金属ベース1の所定位置に設けら
れた凹部によって,電力用半導体チップ8は絶縁基板4
を介して金属ベース1の所定位置に半田付けされること
になる。これにより,従来のようにレジストを塗布し乾
燥する等の製造工程を設ける必要もない。また,レジス
トを塗布するための治具,マスク等を必要としない。
The power semiconductor chip 8 is connected to the insulating substrate 4 by a concave portion provided at a predetermined position of the metal base 1.
Is soldered to a predetermined position of the metal base 1 through the metal. Thus, there is no need to provide a manufacturing process such as applying and drying a resist as in the related art. Further, a jig, a mask, and the like for applying the resist are not required.

【0021】つぎに,第2の実施の形態を図2に基づい
て説明する。図2において11は金属ベースであり,例
えば定尺又は帯状の銅板を打ち抜き加工し,金属ベース
11を得る。この打ち抜き加工時,金属ベース11の所
定位置に圧力を加え,表面が0.3〜0.8mm程度の
第2の凹部11aを形成する。
Next, a second embodiment will be described with reference to FIG. In FIG. 2, reference numeral 11 denotes a metal base. For example, a metal plate 11 is obtained by punching a fixed-size or band-shaped copper plate. During this punching, pressure is applied to a predetermined position of the metal base 11 to form a second concave portion 11a having a surface of about 0.3 to 0.8 mm.

【0022】この凹部11aは鈎括弧状のもので少なく
とも2ケ所設けられ,この鈎括弧状の凹部の内側に半田
箔を介して絶縁基板14が搭載され,さらに,その絶縁
基板14上に電力用半導体チップ15が搭載され,リフ
ロー炉に入れられて加熱され,金属ベース11と電力用
半導体チップ15とが半田付けされている。これによ
り,従来のようにレジストを塗布し乾燥する等の製造工
程を設ける必要もない。また,レジストを塗布するため
の治具,マスク等を必要としない。
At least two concave portions 11a are provided in the shape of brackets, and an insulating substrate 14 is mounted on the inside of the concave portions of the brackets via solder foil. The semiconductor chip 15 is mounted, placed in a reflow furnace and heated, and the metal base 11 and the power semiconductor chip 15 are soldered. Thus, there is no need to provide a manufacturing process such as applying and drying a resist as in the related art. Further, a jig, a mask, and the like for applying the resist are not required.

【0023】つぎに,第3の実施の形態を図3に基づい
て説明する。図3において21は金属ベースであり,例
えば定尺又は帯状の銅板を打ち抜き加工し,金属ベース
21を得る。この打ち抜き加工時,金属ベース21の所
定位置に圧力を加え,表面が0.3〜0.8mm程度の
第3の凹部21aを形成する。この凹部21aは金属ベ
ースの一部を囲むように設けられ,その中央が凹部21
aから見て凸部21bをもった砲台を形成している。
Next, a third embodiment will be described with reference to FIG. In FIG. 3, reference numeral 21 denotes a metal base, for example, a standard-size or band-shaped copper plate is punched to obtain a metal base 21. During this punching process, pressure is applied to a predetermined position of the metal base 21 to form a third recess 21a having a surface of about 0.3 to 0.8 mm. The concave portion 21a is provided so as to surround a part of the metal base, and the center thereof is
As seen from a, a turret having a convex portion 21b is formed.

【0024】この凸部の砲台21b上に半田箔23を介
して電力用半導体チップ22を搭載しフリロー炉に入れ
て加熱して,金属ベース21と電力用半導体チップ22
とを半田付けしている。従って,金属ベース21と電力
用半導体チップ22の上部の半導体層とを短絡すること
がないので,従来のように電力用半導体チップ22の下
に予め銅,モリブデン等の金属をはんだ付けする必要も
ない。
The power semiconductor chip 22 is mounted on the projecting turret 21b via the solder foil 23, and is placed in a freezer furnace and heated, so that the metal base 21 and the power semiconductor chip 22 are heated.
And are soldered. Therefore, there is no short circuit between the metal base 21 and the upper semiconductor layer of the power semiconductor chip 22, so that it is also necessary to solder a metal such as copper or molybdenum under the power semiconductor chip 22 in advance as in the prior art. Absent.

【0025】つぎに,第4の実施の形態を図4に基づい
て説明する。図4において31は金属ベースであり,こ
の金属ベース31の上に銅箔により回路配置された絶縁
基板32が搭載されている。さらに,この絶縁基板32
の上に出力端子33が搭載されている。この出力端子3
3は.例えば定尺又は帯状の銅板を打ち抜き加工して得
られている。この打ち抜き加工時,出力端子33の所定
位置に圧力を加え,表面が0.3〜0.8mm程度の第
4及び第5の凹部33a,33bを形成する。
Next, a fourth embodiment will be described with reference to FIG. In FIG. 4, reference numeral 31 denotes a metal base, on which an insulating substrate 32 in which circuits are arranged by copper foil is mounted. Further, the insulating substrate 32
The output terminal 33 is mounted on. This output terminal 3
3 is. For example, it is obtained by punching a fixed-size or band-shaped copper plate. At the time of this punching, pressure is applied to a predetermined position of the output terminal 33 to form fourth and fifth recesses 33a and 33b having a surface of about 0.3 to 0.8 mm.

【0026】この第4の凹部33aには半田箔34aが
挿入され,この半田箔34a上に電力用半導体チップ3
5aが搭載されている。
A solder foil 34a is inserted into the fourth recess 33a, and the power semiconductor chip 3 is placed on the solder foil 34a.
5a is mounted.

【0027】さらに,第5の凹部33bは出力端子の一
部を囲むように設けられ,その中央が,凹部33bから
見て凸部33cをもった砲台を形成している。
Further, the fifth concave portion 33b is provided so as to surround a part of the output terminal, and the center thereof forms a turret having a convex portion 33c as viewed from the concave portion 33b.

【0028】この凸部の砲台33c上に半田箔34bを
介して電力用半導体チップ35bを搭載しフリロー炉に
入れて加熱して,金属ベース31と電力用半導体チップ
35a,35bとを半田付けしている。
The power semiconductor chip 35b is mounted on the projecting turret 33c via the solder foil 34b, placed in a freezing furnace and heated to solder the metal base 31 and the power semiconductor chips 35a and 35b. ing.

【0029】従って,第4の凹部33aでは,レジスト
を塗布し乾燥する等の製造工程を設ける必要もない。ま
た,レジストを塗布するための治具,マスク等を必要と
しない。さらに,第5の凹部33bでは金属ベース31
と電力用半導体チップ35bの上部の半導体層とが短絡
することがないので,従来のように電力用半導体チップ
35bの下に予め銅,モリブデン等の金属をはんだ付け
する必要もない。
Therefore, it is not necessary to provide a manufacturing process such as applying and drying a resist in the fourth concave portion 33a. Further, a jig, a mask, and the like for applying the resist are not required. Further, in the fifth concave portion 33b, the metal base 31 is formed.
There is no short circuit between the power semiconductor chip 35b and the semiconductor layer above the power semiconductor chip 35b, so that it is not necessary to solder a metal such as copper or molybdenum under the power semiconductor chip 35b in advance as in the related art.

【0030】[0030]

【発明の効果】請求項1乃至第3及び5記載の電力用半
導体モジュールによれば,従来のようにレジストの塗布
がなく乾燥する等の製造工程を設ける必要もない。ま
た,レジストを塗布する治具マスク等も必要としない。
従って,安価な電力用半導体モジュールを提供できる。
According to the power semiconductor module according to the first to third and fifth aspects, there is no need to provide a manufacturing process such as drying without applying a resist as in the prior art. Also, a jig mask or the like for applying a resist is not required.
Therefore, an inexpensive power semiconductor module can be provided.

【0031】また,請求項1,4及び5記載の電力用半
導体モジュールによれば,従来のように電力用半導体チ
ップの下に銅,モリブデン等の金属を予め設ける必要が
なく,電力用半導体モジュールの製造工程の工数を削減
でき,電力用半導体モジュールを安価に提供することが
できる。
According to the power semiconductor module of the first, fourth and fifth aspects, it is not necessary to previously provide a metal such as copper or molybdenum under the power semiconductor chip as in the prior art. Thus, the number of steps in the manufacturing process can be reduced, and the power semiconductor module can be provided at low cost.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の電力用半導体モジュールの第1の実施
の形態を示す組立時の断面図である。
FIG. 1 is a sectional view of a power semiconductor module according to a first embodiment of the present invention at the time of assembly.

【図2】本発明の電力用半導体モジュールの第2の実施
の形態を示す組立時の平面図である。
FIG. 2 is a plan view of a power semiconductor module according to a second embodiment of the present invention at the time of assembly.

【図3】本発明の電力用半導体モジュールの第3の実施
の形態を示す組立時の断面図である。
FIG. 3 is a sectional view of a power semiconductor module according to a third embodiment of the present invention at the time of assembly.

【図4】本発明の電力用半導体モジュールの第4の実施
の形態を示す組立時の断面図である。
FIG. 4 is a sectional view of a power semiconductor module according to a fourth embodiment of the present invention at the time of assembly.

【図5】従来の電力用半導体モジュールの組立時の断面
図である。
FIG. 5 is a cross-sectional view of a conventional power semiconductor module during assembly.

【図6】従来の他の電力用半導体モジュールの組立時の
断面図である。
FIG. 6 is a cross-sectional view of another conventional power semiconductor module during assembly.

【符号の説明】[Explanation of symbols]

1,11,21,31 金属ベース 1a,11a,21a,33a,33b 凹部 11b,33c 凸部(砲台) 4,14,32 絶縁基板 5,7,23,34a,34b 半田箔 8,15,22.35a,35b 電力用半導体チップ 1, 11, 21, 31 Metal base 1a, 11a, 21a, 33a, 33b Concave portion 11b, 33c Convex portion (battery) 4, 14, 32 Insulating substrate 5, 7, 23, 34a, 34b Solder foil 8, 15, 22 .35a, 35b Power semiconductor chips

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 金属ベースに電力用半導体チップを搭載
してなる電力用半導体モジュールにおいて,上記金属ベ
ースが打ち抜き加工時に所定位置に凹部が設けられた金
属ベースであることを特徴とする電力用半導体モジュー
ル。
1. A power semiconductor module having a power semiconductor chip mounted on a metal base, wherein the metal base is a metal base having a concave portion provided at a predetermined position during punching. module.
【請求項2】 上記金属ベースが打ち抜き加工時に上記
電力用半導体チップが搭載される所定位置に凹部が設け
られた金属ベースであることを特徴とする請求項1記載
の電力用半導体モジュール。
2. The power semiconductor module according to claim 1, wherein the metal base is a metal base having a recess at a predetermined position where the power semiconductor chip is mounted at the time of punching.
【請求項3】 上記金属ベースが打ち抜き加工時に上記
電力用半導体チップが搭載される位置を指示する位置に
凹部が設けられた金属ベースであることを特徴とする請
求項1記載の電力用半導体モジュール。
3. The power semiconductor module according to claim 1, wherein the metal base is a metal base provided with a concave portion at a position indicating a position where the power semiconductor chip is mounted at the time of punching. .
【請求項4】 上記金属ベースが打ち抜き加工時に上記
電力用半導体チップが搭載される所定位置を囲むように
凹部が設けられた金属ベースであることを特徴とする請
求項1記載の電力用半導体モジュール。
4. The power semiconductor module according to claim 1, wherein the metal base is a metal base provided with a concave portion so as to surround a predetermined position where the power semiconductor chip is mounted at the time of punching. .
【請求項5】 金属ベースと,上記金属ベース上に搭載
された絶縁基板と,上記絶縁基板上に搭載された出力端
子と,上記出力端子上に搭載された電力用半導体チップ
とを備えた電力用半導体モジュールにおいて,上記出力
端子が打ち抜き加工時に所定位置に凹部が設けられた出
力端子であることを特徴とする電力用半導体モジュー
ル。
5. A power supply comprising: a metal base; an insulating substrate mounted on the metal base; an output terminal mounted on the insulating substrate; and a power semiconductor chip mounted on the output terminal. A power semiconductor module according to claim 1, wherein said output terminal is an output terminal provided with a recess at a predetermined position during punching.
JP10208665A 1998-07-08 1998-07-08 Power semiconductor module Pending JP2000031358A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10208665A JP2000031358A (en) 1998-07-08 1998-07-08 Power semiconductor module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10208665A JP2000031358A (en) 1998-07-08 1998-07-08 Power semiconductor module

Publications (1)

Publication Number Publication Date
JP2000031358A true JP2000031358A (en) 2000-01-28

Family

ID=16560031

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10208665A Pending JP2000031358A (en) 1998-07-08 1998-07-08 Power semiconductor module

Country Status (1)

Country Link
JP (1) JP2000031358A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10064979C1 (en) * 2000-12-18 2002-02-28 Dieter Loewer Semiconductor circuit device has base plate mounted on heat sink provided with stamped-out sections supporting mounting substrates for semiconductor components
DE102006009978A1 (en) * 2006-03-03 2007-10-31 Infineon Technologies Ag Power semiconductor module, has base plate serving as support, where semiconductor unit is attached with bottom side of the substrate on upper side of base plate, and base plate is made of composite material with metallic material
US8237260B2 (en) 2008-11-26 2012-08-07 Infineon Technologies Ag Power semiconductor module with segmented base plate
JP2013098450A (en) * 2011-11-04 2013-05-20 Sumitomo Electric Ind Ltd Semiconductor module and method of manufacturing semiconductor module
US8466548B2 (en) * 2011-05-31 2013-06-18 Infineon Technologies Ag Semiconductor device including excess solder
DE102014218389A1 (en) 2013-10-31 2015-04-30 Mitsubishi Electric Corporation Semiconductor module
JP2022026902A (en) * 2020-07-31 2022-02-10 富士電機株式会社 Semiconductor device and method for manufacturing semiconductor device
US12009310B2 (en) 2020-01-07 2024-06-11 Fuji Electric Co., Ltd. Semiconductor device
JP7753631B2 (en) 2020-07-31 2025-10-15 富士電機株式会社 Semiconductor device and manufacturing method thereof

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10064979C1 (en) * 2000-12-18 2002-02-28 Dieter Loewer Semiconductor circuit device has base plate mounted on heat sink provided with stamped-out sections supporting mounting substrates for semiconductor components
DE102006009978A1 (en) * 2006-03-03 2007-10-31 Infineon Technologies Ag Power semiconductor module, has base plate serving as support, where semiconductor unit is attached with bottom side of the substrate on upper side of base plate, and base plate is made of composite material with metallic material
DE102006009978B4 (en) * 2006-03-03 2008-12-18 Infineon Technologies Ag The power semiconductor module
US8237260B2 (en) 2008-11-26 2012-08-07 Infineon Technologies Ag Power semiconductor module with segmented base plate
US8466548B2 (en) * 2011-05-31 2013-06-18 Infineon Technologies Ag Semiconductor device including excess solder
JP2013098450A (en) * 2011-11-04 2013-05-20 Sumitomo Electric Ind Ltd Semiconductor module and method of manufacturing semiconductor module
DE102014218389A1 (en) 2013-10-31 2015-04-30 Mitsubishi Electric Corporation Semiconductor module
US9159676B2 (en) 2013-10-31 2015-10-13 Mitsubishi Electric Corporation Semiconductor module
DE102014218389B4 (en) * 2013-10-31 2021-06-17 Mitsubishi Electric Corporation Semiconductor module
US12009310B2 (en) 2020-01-07 2024-06-11 Fuji Electric Co., Ltd. Semiconductor device
JP2022026902A (en) * 2020-07-31 2022-02-10 富士電機株式会社 Semiconductor device and method for manufacturing semiconductor device
JP7753631B2 (en) 2020-07-31 2025-10-15 富士電機株式会社 Semiconductor device and manufacturing method thereof

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