JP2000091575A - Manufacture of insulated-gate field-effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to manufacture an insulated-gate field-effect transistor, which can be miniaturized and enables enlargement of an ASO (safety operating region), with good productivity. SOLUTION: An insulated-gate field-effect transistor of a structure, wherein a groove 17 penetrating the source region 15 is formed, the source electrode 20 is arranged in this groove 17 and the side surfaces of the region 15 are brought into contact with the electrode 20, is manufactured. Before the groove 17 is formed, the groove 17 is formed in such a way as to penetrate a shallow impurity distribution region for the source region by an ion implantation method and after that, a contact region 16 is formed in a body region 14 and at the same time, impurity diffusion in an N+ impurity distribution region is proceeded to obtain the source region 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing an insulated gate transistor having a structure in which a source electrode or an emitter electrode is arranged in a groove of a semiconductor substrate.

[0002]

2. Description of the Related Art As shown in FIG. 1, an insulated gate field effect transistor (hereinafter referred to as a MOSFET) in which a source contact portion has a U-groove structure and a source contact is formed on a side surface of the U-groove is known. . The MOSFET shown in FIG. 1 has a low-resistance drain region 1 composed of an n ⁺ -type semiconductor region, a high-resistance drain region 2 composed of an n-type semiconductor region, a body region (base region or channel forming region) 3 composed of a p ^{+ -type} semiconductor region, and a semiconductor substrate 5 having a source region 4 formed of an n ^{+ type} semiconductor region; a gate insulating film 6 formed on the upper surface of the semiconductor substrate 5; a gate electrode 7 disposed on the upper surface of the gate insulating film 6; 4 and a source electrode 8 electrically connected to the base region 3;
It comprises an interlayer insulating film 9 for insulating between the gate electrode 7 and the source electrode 8, and a drain electrode 10 formed on the lower surface of the semiconductor substrate 5. Although this MOSFET has a plurality of body regions 3 and source regions 4 formed in an annular shape, FIG. 1 shows only one (one cell). In the MOSFET of FIG. 1, a groove 4 a having a concave cross section is formed on the upper surface of a semiconductor substrate 5, and a source electrode 8 penetrates the groove 4 a and is electrically connected to the source region 4 exposed on the side surface of the groove 4 a. It is connected. The groove 4a is the source region 4.
The bottom surface of the groove 4 a reaches the base region 3. Therefore, the source electrode 8 is also electrically connected to the base region 8. MOSFET of Figure 1
According to the method, the planar dimension (area or length in the horizontal direction) of the source contact can be reduced, so that the cell dimension (area or length) can be reduced (cell size can be reduced), and the ON resistance (cell size) can be reduced. Operating resistance) can be reduced.

[0003]

By the way, in the conventional method, the groove 4a is formed so as to penetrate the source region 4 after the source region 4 is formed. Therefore, the groove 4a is formed so that the groove 4a penetrates the source region 4 without fail. Has to be formed relatively deep. That is, considering the variation in the depth of the source region 4 and the variation in the depth of the groove 4a,
It is necessary to form the groove a deeper, and the time required for forming the groove 4a becomes longer, which hinders an improvement in productivity. Also, for insulated gate field effect transistors, the resistance of the body region is reduced, and the latching ASO (Area
(Safety operation area), that is, it is required to expand a safe operation area for an inductive load.
The above-described problem also occurs in the IGBT (insulated gate bipolar transistor).

Therefore, an object of the present invention is to reduce the size and AS
An object of the present invention is to provide a method for manufacturing an insulated gate transistor capable of increasing O with high productivity.

[0005]

In order to achieve the above object, the present invention provides a semiconductor substrate having first and second main surfaces, an insulating film, a source electrode, a drain electrode, and a gate electrode. A drain region disposed so as to be exposed on both the first main surface and the second main surface; and a first region of the substrate disposed adjacent to the drain region. A body region having a portion exposed to the main surface of the base region; a source region disposed adjacent to the body region and having a portion exposed to the first main surface of the base; A contact region disposed adjacent to and having the same conductivity type as the body region, wherein a groove having a depth greater than the source region is formed in the first main surface of the semiconductor substrate; Exposes the sides of the source region The source electrode is formed so as to expose the contact region, the source electrode is formed so as to penetrate into the groove, contact the side surface of the source region, and contact the contact region. An insulated gate electric field which is arranged on the second main surface of the semiconductor device and wherein the gate electrode is arranged to face a portion of the body region exposed on the first main surface via the insulating film. A method of manufacturing an effect transistor, wherein a first impurity for determining a conductivity type of the source region is implanted into the body region by an ion implantation method, and the impurity distribution region is shallower than a final depth of the source region. Forming the trench so as to penetrate the shallow impurity distribution region; and forming a second impurity for determining the conductivity type of the contact region. Forming the contact region by introducing the contact region into the body region through a groove; and obtaining the source region by deeply diffusing the impurities in the shallow impurity distribution region by heating at the same time or independently of the formation of the contact region. The present invention relates to a method for manufacturing an insulated gate field effect transistor, comprising: Preferably, the contact region is formed based on ion implantation. In addition, the present invention provides an IGB
It is also applicable to T.

[0006]

According to the present invention, since the groove is formed in a state where the impurity distribution region for the source region or the emitter region is formed relatively shallow, the groove having a depth penetrating the impurity distribution region is formed. Can be formed reliably and easily. That is, even if there is variation in the depth (thickness) of the shallow impurity distribution region for the source region or the emitter region, the amount of the variation is small because the depth of the impurity distribution region is small. Therefore, when forming the groove, it is not necessary to consider the variation in the depth of the impurity distribution region due to the ion implantation, and the depth of the groove can be set shallower. When the groove becomes shallow, the time for forming the groove can be shortened, and the productivity is improved. Also, according to the present invention,
Since a region having a small resistance is provided, ASO can be expanded. Further, the forward voltage of the diode between the source and the drain or between the emitter and the collector can be reduced.

[0007]

Embodiments and Examples Next, a method of manufacturing a MOSFET according to an embodiment of the present invention will be described with reference to FIGS. FIG. 2 shows a part of the surface of the semiconductor substrate 11 of the MOSFET according to the present embodiment, and FIG.
FIG. 3 is a cross-sectional view showing a part of T at a portion corresponding to line AA in FIG. 2. The silicon semiconductor substrate 11 of the MOSFET according to the present embodiment includes a low-resistance drain region 12 made of an n ⁺ -type semiconductor region, an n-type high-resistance drain region 13, a p-type body region 14, and an n ^{+ -type} source region. 15 and p ⁺
And a contact region 16 having the shape. A gate insulating film 18, a gate electrode 19, a source electrode 20, and an interlayer insulating film 21 are provided on one main surface of the semiconductor substrate 11 in which the annular groove 17 is formed, and a drain electrode 22 is provided on the other main surface. Is provided.

The n ⁺ -type low-resistance drain region 12 is
1 and is connected to the drain electrode. n
The high-resistance drain region 13 is adjacent to the n ⁺ -type low-resistance drain region 12, and a part thereof is exposed on the upper surface of the base 11.

A body region (main region) 14 is a region which can also be called a base region or a channel formation region, is disposed adjacent to the n-type drain region 13, and a part thereof is formed on one main surface (upper surface) of the base 11. ) Is exposed. In addition,
The body region 14 is arranged in an island shape in the n-type drain region 13 and has an annular pattern when viewed in plan. Therefore,
On one main surface of the base 11, the n-type drain region 13 is exposed inside and outside the body region 14.

The n ^{+ -type} source region 15 is arranged in the body region 14, is annularly arranged concentrically in the body region 14 in plan view, and has an inner source region 15 a and an outer source region 15 b by a groove 17. And is divided into:
The outer peripheral side surface of the inner source region 15a is exposed to the groove 17 and contacts the source electrode 20, and the outer source region 15b
Are also exposed to the grooves 17 and are in contact with the source electrode 20.

The p ^{+ -type} contact region 16 can be called a body (base) connection region, and has a groove 17.
And a portion thereof also extends below the source regions 15a and 15b.

FIGS. 2 and 3 show one body region 14.
And one cell including the source region 15 disposed therein, an actual MOSFET includes a number of cells having the same configuration, and the cells are connected in parallel with each other.

The gate insulating film 18 is formed on one main surface of the substrate 11 except for the groove 17. This gate insulating film 18 must be formed so as to cover at least the surface of the base 11 between the source region 15 and the drain region 13. The gate electrode 19 is arranged on the gate insulating film 18 so as to face the channel forming portion of the body region 14 exposed on the surface of the base 11. Source electrode 20
Are formed so as to penetrate the groove 17 and are formed in the interlayer insulating film 21.
It is also formed on. Since the interlayer insulating film 21 has a tapered inclined wall surface 21a in a region surrounding the groove 17, the groove 17
The material for forming the source electrode 20 is satisfactorily filled.

The MOSFET having the structure shown in FIG. 3 is in contact with the source electrode 20 by the side surfaces of the source regions 15a and 15b as in FIG. The contact area can be reduced, and the size of the MOSFET can be reduced. Further, since trench 17 is formed so as to cut into body region 14 and n-type contact region 16 is provided, ohmic contact between source electrode 20 and body region 14 is improved, and Resistance decreases and latching ASO improves. Further, the forward resistance of the built-in diode formed between the source electrode 20 and the drain electrode 22 is reduced.

When manufacturing the MOSFET shown in FIG. 3, first, a semiconductor substrate 23 shown in FIG. 4 is prepared. The semiconductor substrate 23 has a low-resistance drain region 12 made of an n ^{+ -type} semiconductor region having a relatively high impurity concentration and a high-resistance drain region 13 made of an n-type semiconductor region having a relatively low impurity concentration. The low-resistance drain region 12 can be formed by introducing an n-type impurity (for example, phosphorus) into the high-resistance drain region 13 by a known thermal diffusion method. On one main surface (upper surface) of the semiconductor substrate 23, that is, on the upper surface of the high-resistance drain region 13, a first insulating film 24 made of, for example, a silicon oxide film by a well-known thermal oxidation method or the like, and a well-known vapor deposition method or the like Thereby, for example, a polycrystalline silicon film 25 is sequentially formed. Here, the first insulating film 2
4 is a film for obtaining a gate insulating film 19 later, and the polycrystalline silicon film 25 is a film for forming a gate electrode 25 later.

Next, as shown in FIG. 5, an opening 25a is formed in the polycrystalline silicon film 25 by using a well-known dry etching method. The opening 25a is formed in the first insulating film 2
4 is formed. The opening 25a functions as a window for impurity diffusion for forming the body region 14 and the source region 15, and is formed in a ring shape in the first insulating film 24 in plan view. Note that this opening 25a is
A plurality of ET cells are provided corresponding to the number of ET cells. Subsequently, using the polycrystalline silicon film 25 as a diffusion mask,
P-type impurities (for example, boron) are selectively ion-implanted into the high-resistance drain region 13 through 5a. The p-type impurity passes through the first insulating film 24 and is introduced to the upper surface side of the drain region 13. Next, a heat treatment is performed on the semiconductor substrate 23 at about 1100 ° C. for about 220 minutes to diffuse the implanted p-type impurity deeply into the high-resistance drain region 13 so that the p-type impurity is removed from the p-type semiconductor region shown in FIG. Body region 14
To form The body region 14 has an opening 25a in plan view.
Are formed in an annular shape corresponding to the region where the pattern is formed, and are surrounded by the high-resistance drain region 13 in an island shape.

Next, as shown in FIG.
Using the opening 25a used for forming the second region again as a diffusion window, an n-type impurity (eg, arsenic) as a first impurity is selectively ion-implanted into the body region 14. The n-type impurity is introduced into the upper surface side of the body region 14 through the first insulating film 24, and may be referred to as an n-type diffusion region or an n ^{+ -type} ion implantation region for obtaining the source region 15. An impurity distribution region 26 is obtained. The depth of the first impurity distribution region 26 is smaller than the final depth of the source region 15. This n-type impurity is introduced into polycrystalline silicon film 25 in this implantation step. As a result, the polycrystalline silicon film 25 is converted into an n-type conductive film, which becomes the gate electrode 19. Conventionally, the semiconductor substrate 23 is subjected to a heat treatment after the ion implantation in order to diffuse the implanted n-type impurity deeply. However, in the present embodiment, the heat treatment is not immediately performed after the ion implantation, but the groove 17 is formed and the contact is formed. After performing ion implantation of a p-type impurity for forming the region 16, heat treatment is performed.

Next, as shown in FIG. 7, a second silicon oxide film formed by sequentially stacking a silicon oxide film and a silicon oxide film into which boron and phosphorus are introduced is formed on the upper surface of the semiconductor substrate 23 by a known vapor deposition method or the like. Is formed. This second
The insulating film 27 covers the upper surface of the gate electrode 19 and the upper surface of the first insulating film 24 exposed from the opening 25a. The second insulating film 27 is a film for forming an insulating film for electrically separating the gate electrode 19 and the source electrode 20 shown in FIG.

Next, as shown in FIG. 8, the second insulating film 2
7 is coated with a resist film 28 by a well-known spinner type coating method or the like. The resist film 28 corresponds to the portion where the gate electrode 19 is not provided.
7 has a flattened surface with almost no depression corresponding to the depression 29 formed.

Next, the resist film 28 is etched by using a well-known photolithography method to remove a region shown by a dotted line in the resist film 28 in FIG. 8 to form an opening 30 shown in FIG. A mask 31 is formed. The opening 30 is arranged substantially at the center of the n ^{+ -type} first impurity distribution region 26 in plan view. Subsequently, the first and second insulating films 2 are passed through the openings 30 of the mask 31.
The well-known dry etching is performed on the upper surfaces 4 and 27 and the silicon semiconductor substrate 23. As a result, as shown in FIG. 9, the first and second insulating films 2 in a portion corresponding to the opening 30 are formed.
4 and 27 are selectively removed, and a groove 17 is obtained on the upper surface of the semiconductor substrate 23 at a portion corresponding to the opening 30. This groove 17
Is the same as that shown in FIG. 3, and this wall surface stands substantially perpendicularly to this bottom surface. In the state of FIG. 9, trench 17 is formed deeper than first impurity distribution region 26 and shallower than body region 14, and body region 14 is exposed in trench 17. The groove 17 has a substantially circular planar shape, and the first impurity distribution region 26 and the body region 14 are exposed on the side surface. Further, the first insulating film 24 is separated by the dry etching and the gate insulating film 18 is formed.
Is formed.

Next, as shown in FIG. 9, well-known ion implantation is performed from above the mask 31, and the groove 17 is formed through the opening 30.
Is formed as a second impurity in the body region 14
A form of impurity (eg, boron) is introduced. This allows
The p-type impurity concentration of the body region 14 exposed at the bottom of the trench 17 increases, and the p-type impurity concentration is higher than that of the body region 14.
^A second impurity distribution region 32, which can also be referred to as a ^{+ type} diffusion region or a p ^{+ type} ion implantation region, is formed. In addition,
The ion implantation for the second impurity distribution region 32 is performed to such an extent that the conductivity type of the first impurity distribution region 26 is not inverted. Therefore, the n ^{+ -type} first impurity distribution region 26 is exposed above the groove 17 as shown in FIG.
A p ^{+ -type} second impurity distribution region 32 is exposed below the region.

Next, the resist film 31 is removed.
The semiconductor substrate 23 of FIG. 10 is subjected to a heat treatment (annealing) at about 950 ° C. for about 30 minutes to remove the impurities in the n ^{+ -type} first impurity distribution region 26 and the p ^{+ -type} second impurity distribution region 32. Impurities are diffused deeply into body region 14 so that n
^{The +} source region 15 and the p ⁺ contact region 16 are shown in FIG.
1 to complete the same semiconductor substrate 11 as in FIG. Note that the bottom surface of the source region 15 reaches near the bottom surface of the groove 17 but is located at a position shallower than the bottom surface of the groove 17. Further, the contact layer 16 exposed from the bottom of the groove 17 is formed.
Is adjacent to the source region 15. As a result, the source region 15 and the contact region 1
6 is exposed. Further, an interlayer insulating film 21 based on the second insulating film 27 is obtained as shown in FIG. The wall surface of the opening 21a of the interlayer insulating film 21 becomes gentle by heat treatment (annealing), and the step becomes small. A silicon oxide film is formed on the wall surface of the groove 17 of the semiconductor substrate 11 by the heat treatment, and this oxide film is removed by well-known dry etching. At this time, a part of the source region 15 and the contact region 16 on the side of the groove 17 is also removed by etching. However, this is desirable because a surface damage layer that cannot be completely removed by annealing can be removed.

Next, a source electrode 20 made of Al or the like is formed on the upper surface of the semiconductor substrate 11 by using a known vacuum deposition method or the like, as shown in FIG. The source electrode 20 penetrates into the groove 17 and is electrically connected to the source region 15 and the contact region 16 exposed in the groove 17. Also,
An interconnect conductor layer (not shown) for the gate electrode 19 is provided. Similarly, Ti, Ni, Pd, and Ag are continuously vacuum-deposited on the lower surface of the semiconductor substrate 11 to form the drain electrode 22. As described above, the MOSFET shown in FIG.
Is completed.

According to the manufacturing method of this embodiment, the following effects can be obtained. (1) Since the formation of the groove 17 is performed before the heat treatment for forming the source region 15, the depth of the groove 17 can be set shallow as described in the section of the effect of the invention, and the productivity can be improved. Improvement can be achieved. (2) Since the body region 14 is connected to the source electrode 20 via the contact region 16 having a relatively high impurity concentration, the resistance of the body region decreases, and the latching ASO improves. (3) Since the wall surface of the second insulating film 27 becomes smooth by annealing for forming the contact region 16,
The source electrode 29 can be favorably filled in the openings 17 and 21a.

[0025]

[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) The first impurity distribution region 26 can be formed as a region in which ions are implanted and then slightly diffused. Even in this case, the depth of the regions 26 and 32 is
If the depth is smaller than 5, the effect of the present invention can be obtained. (2) The contact region 16 can be formed by a thermal diffusion method without ion implantation. (3) Either one of the two drain regions 12 and 13 can be omitted. Further, the n ⁺ -type drain region can be formed in a state of being divided into a plurality. (4) Although an n-channel MOSFET is manufactured in the embodiment, the present invention can be applied to a p-channel MOSFET. (5) The groove 17 can be formed in a planar quadrilateral. (6) The present invention can be applied to an IGBT (insulated gate bipolar transistor). 12 and 13 show two IGBTs to which the present invention is applied. In FIGS. 12 and 13, substantially the same parts as those in FIGS. 2 to 11 are denoted by the same reference numerals, and description thereof will be omitted. IGBT of FIG.
3, an n ^{+ -type} semiconductor region 12a and a p-type semiconductor region 12b functioning as first and second collectors are provided instead of the low-resistance drain region 12 of the MOSFET shown in FIG. N in the IGBT of FIGS. 12 and 13
The region 13 functions as a drift region, and the n ⁺ region 1
5a functions as an emitter region. IGBT of FIG.
Provided n ^{+ -type} regions 12a, p-type regions 12b and p ^{+ -type} regions 12c, which can be called first, second and third collector regions, instead of the n ⁺ -type drain region 12 in FIG. Things. As is well known, the IGBTs of FIGS. 12 and 13 can reduce the on-state voltage by using conduction modulation. Emitter region (source region) 1 also in IGBT
5a, body region 14, contact region 16, etc. are MOS
Since it can be configured similarly to the FET, it has the same effect as the MOSFET.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a conventional MOSFET.

FIG. 2 is a plan view showing a part of the surface of the semiconductor substrate of the MOSFET according to the embodiment of the present invention.

FIG. 3 is a cross-sectional view showing the MOSFET of the embodiment at a portion corresponding to AA in FIG. 2;

FIG. 4 is a cross-sectional view showing a method for manufacturing the MOSFET of FIG. 3, in which an insulating film and a polycrystalline silicon film are provided on a semiconductor substrate.

FIG. 5 is a cross-sectional view showing the semiconductor substrate of FIG. 4 in which a body region is formed.

6 is a cross-sectional view showing a semiconductor substrate of FIG. 5 in which a first impurity distribution region is formed by ion implantation.

FIG. 7 is a cross-sectional view showing a structure in which a second insulating film is formed on the structure shown in FIG.

FIG. 8 is a cross-sectional view showing a structure in which a resist film is formed on the structure shown in FIG. 7;

FIG. 9 is a cross-sectional view showing a structure in which a groove is formed in the structure shown in FIG.

FIG. 10 is a cross-sectional view showing a semiconductor substrate of FIG. 9 in which a second impurity distribution region is formed by ion implantation.

FIG. 11 is a cross-sectional view showing a state in which the resist film is removed from that in FIG. 10 and heat treatment is performed.

FIG. 12 is a cross-sectional view showing an IGBT of a modified example, similarly to FIG.

FIG. 13 is a cross-sectional view showing an IGBT of another modified example, similarly to FIG.

[Explanation of symbols]

 Reference Signs List 11 semiconductor substrate 12 low-resistance drain region 13 high-resistance drain region 14 body region (base region) 15, 15a, 15b source region 16 contact region 17 groove 18 gate insulating film 19 gate electrode 20 source electrode 21 interlayer insulating film 22 drain electrode

Claims (4)

[Claims] 1. A semiconductor substrate having first and second main surfaces, an insulating film, a source electrode, a drain electrode, and a gate electrode, wherein the semiconductor substrate has a first main surface and a second main surface. A drain region disposed so as to be exposed to both the second main surface, and a first region of the base which is disposed adjacent to the drain region and is located adjacent to the drain region.
A body region having a portion exposed to the main surface of the base region; a source region disposed adjacent to the body region and having a portion exposed to the first main surface of the base; A contact region disposed adjacent to and having the same conductivity type as the body region, a groove having a depth equal to or greater than the source region is formed in the first main surface of the semiconductor substrate; Is disposed so as to expose a side surface of the source region and to expose the contact region. The source electrode penetrates into the groove and contacts the side surface of the source region and contacts the contact region. The drain electrode is formed on the second main surface of the base, and the gate electrode is opposed to a portion of the body region exposed on the first main surface via the insulating film. A method of manufacturing an insulated gate transistor, wherein a first impurity for determining a conductivity type of the source region is implanted into the body region by an ion implantation method. Forming an impurity distribution region shallower than a typical depth; forming the groove so as to penetrate the shallow impurity distribution region; and forming a second impurity for determining a conductivity type of the contact region into the groove. Forming the contact region by introducing the same into the body region through; and performing a heat treatment simultaneously or independently with the formation of the contact region to deeply diffuse the impurities in the shallow impurity distribution region to obtain the source region. A method for manufacturing an insulated gate transistor, comprising: 2. The method of manufacturing an insulated gate transistor according to claim 1, wherein the contact region is formed by ion implantation and heat treatment, and the heat treatment deeply diffuses the impurities in the shallow impurity distribution region. . 3. A semiconductor substrate having first and second main surfaces, an insulating film, an emitter electrode, a collector electrode, and a gate electrode, wherein the semiconductor substrate has a first main surface and a second main surface. A drift region disposed so as to be exposed to both the second main surface, and a first region of the base which is disposed adjacent to the drift region and is adjacent to the drift region.
A body region having a portion exposed to the main surface of the base region; an emitter region disposed adjacent to the body region and having a portion exposed to the first main surface of the base; A collector region of a first conductivity type disposed between the drift region and a second main surface of the semiconductor substrate, the contact region being adjacently disposed and having the same conductivity type as the body region; And a collector region having a depth equal to or greater than the emitter region is formed in the first main surface of the semiconductor substrate, the groove exposing a side surface of the emitter region and the contact The emitter electrode is formed so as to expose a region, and the emitter electrode is formed to penetrate into the groove to contact a side surface of the emitter region and to contact the contact region; A pole is arranged on the second main surface of the base, and the gate electrode is arranged to face a portion of the body region exposed on the first main surface via the insulating film. A method of manufacturing an insulated gate transistor, wherein a first impurity for determining a conductivity type of the emitter region is implanted into the body region by an ion implantation method, the impurity being shallower than a final depth of the emitter region. Forming a distribution region; forming the groove so as to penetrate the shallow impurity distribution region; and introducing a second impurity into the body region through the groove to determine a conductivity type of the contact region. Forming the contact region by heat treatment simultaneously with or independently of the formation of the contact region. Method of manufacturing an insulated gate transistor, characterized in that it comprises the step of obtaining a. 4. The method of manufacturing an insulated gate transistor according to claim 3, wherein the contact region is formed by ion implantation and heat treatment, and the heat treatment causes the impurity in the shallow impurity distribution region to diffuse deeply. .