JP2000091319A - Dry etching method and thin film pattern - Google Patents

Abstract

PROBLEM TO BE SOLVED: To uniformly etch a thin film by reducing the in-plane rate distribution of the etching by using a pattern that contains openings which are not coated with a resist in a specific range over the whole surface of a substrate. SOLUTION: After a protective film is formed on a glass substrate, an amorphous Si film is formed on the protective film. After the amorphous Si is grown in a slide phase, the amorphous Si is patterned into an island-like state. Then a silicon oxide film is formed as a gate insulating film, and a gate electrode and an MoW film are formed through sputtering. After the MoW is formed, a resist pattern in which an extra pattern having a representative size of 50 μm is embedded without gaps within 300 μm or less is formed between a pixel section and a peripheral circuit section. Because of the resist pattern, the etching rate uniformity of the dry-etching performed on the MoW film can be secured within ±10% over the whole surface of the glass substrate. Thereafter, the MoW film is subjected to dry etching. Therefore, the MoW film can be dry- etched with sufficient uniformity.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to dry etching of a thin film formed on a substrate, and more particularly to a method for improving an in-plane distribution of an etching rate.

[0002]

2. Description of the Related Art Polycrystalline silicon thin film semiconductors (TFTs) used in small liquid crystal televisions and image sensors have both electron and hole mobilities of several tens of cm ² / Vs or more, and are used to construct a drive circuit on an array substrate. Is advantageous.

In this case, the structure of the TFT is often a top gate type, and the introduction of impurities into the semiconductor film at the source and drain portions is usually carried out by ion implantation or ion doping by self-alignment using the gate electrode as a mask. And so on. In this case, it is preferable that the gate line be processed vertically. Further, it is necessary to have a high selectivity with respect to the underlying gate insulating film, and therefore, it is desired that the in-plane velocity distribution of the etching is also very small.

In the prior art, the in-plane velocity distribution of etching is usually of a down-flow type using CF ₄ / O ₂ gas, and is adjusted by adjusting the gas supply distribution and gas ratio. The distribution of the gas supply is closely related to the exhaust speed, in addition to the distribution and shape of the gas discharge nozzles and showerheads, and has been reduced to about ± 10% by optimizing the process pressure.

As described above, in the conventional dry etching, adjustment of the gas composition and the like is performed only on the etching apparatus side in order to improve the in-plane velocity distribution of the etching.

In a liquid crystal display of the active matrix drive system using the TFT as an element as described above, a MoW thin film is used as a gate line of a transistor using amorphous silicon. Mo
W is an alloy having a specific resistance of about 15 μΩcm.

In dry etching of MoW among thin films, an SF ₆ / Cl ₂ / O ₂ gas system is used. Oxygen radicals generated by plasma oxidize the MoW surface and accelerate etching by fluorine radicals and fluorine ions. It is said that.

However, on the other hand, oxygen radicals are consumed by carbon and hydrogen of the resist, and this acceleration effect may be lost. In particular, when the processing area is large and the supply of radicals and ions is not sufficient, the etching rate is governed not only by the so-called etching loading effect depending on the MoW area but also by the area of the resist.
FIG. 6 schematically shows this state. With the consumption of oxygen, the etching rate of a portion having a large resist area decreases.

Here, a conventional problem will be described in detail by taking as an example a process of manufacturing a coplanar TFT. For example, if the etching of the gate electrode is performed twice and the ashing of the resist is performed three times, the underground gate insulating film is removed each time. Therefore, the selectivity with respect to the base in the etching requires a high value of about several tens of times.

Conventionally, when the gate insulating film is a silicon oxide film, SF ₆ / Cl obtained by adding Cl ₂ to an etching gas is used.
Improvements in selectivity have been attempted using the ₂ / O ₂ system. However, in the etching using an O ₂ system, there is a large difference in the etching rate between a region where a fine pattern such as a drive circuit is densely packed and a region such as a periphery thereof which is almost covered with a resist and has no processed portion. As a result, the rate distribution is reduced, and as a result, there is a problem that a large amount of the underlying oxide film is shaved to obtain a large overetch.

[0011]

As described above, in the conventional dry etching, there is a problem that the etching speed varies depending on the shape of the resist pattern, so that the etching varies.

Accordingly, the present invention provides a dry etching method and a thin film pattern which can uniformly etch the thin film by reducing the in-plane velocity distribution in the dry etching of the thin film formed on the semiconductor device substrate. The purpose is to provide.

[0013]

According to the present invention, in dry etching of a thin film formed on a substrate, a pattern is used in which at least an opening not covered with a resist exists within 300 μm over the entire surface of the substrate. Is provided.

That is, when a thin film having undergone a lithography process is dry-etched with an SF ₆ / Cl ₂ / O ₂ gas system, a pattern having at least an opening not covered with a resist within 300 μm over the entire surface of a substrate is used. Dry etching method.

The present invention also provides a thin film pattern formed on a substrate, wherein at least an opening exists in the thin film within 300 μm over the entire surface of the substrate.

The gas used in the dry etching contains at least one of F, Cl ₂ and O ₂ .

As such a gas, for example, SF ₆
/ Cl ₂ / O ₂ , CF ₄ / O ₂ , CF ₄ / O ₂ / N ₂ ,
CCl ₂ , CHF ₃ / O ₂ , and CF ₄ / H ₂ are mentioned. The mixing ratio may be appropriately adjusted.

The size of the opening which is not covered with the resist of the pattern used in the dry etching method of the present invention is at least a representative dimension of 10 μm or more. The representative dimension is the length of the longest line segment among the line segments between two points existing in the opening. The thin film formed on the semiconductor device to which the dry etching method of the present invention is applied is, for example, a MoW thin film. The MoW thin film mainly used for the gate electrode tends to have a particularly easy variation in the etching rate as compared with polysilicon, silicide, aluminum or the like.

The wafer size of the semiconductor substrate targeted by the dry etching method of the present invention is not particularly limited.
Further, the material of the resist for forming the thin film pattern of the present invention is not particularly limited.

According to the dry etching method using the thin film pattern of the present invention, a thin film such as a MoW gate line can be etched with a sufficiently uniform speed distribution.

[0021]

[Embodiment 1] An example in which the present invention is applied to a top gate type TFT having a low concentration drain (LDD) which is an electric field relaxation region will be described with reference to FIG.

First, after a protective film (not shown) is formed on a glass substrate, 500A of amorphous Si is formed by a CVD method (FIG. 2A).

Next, after heating at 600 ° C. for 48 hours to grow the amorphous silicon in a solid phase, it is patterned into an island shape by photolithography (FIG. 2B).

Next, a silicon oxide film having a thickness of 1000 A is formed as a gate insulating film by a CVD method. Next, MoW is deposited as a gate electrode by sputtering at 2500 A (FIG. 2).
(C)). Here, for the next step of dry etching, between the pixel portion and the peripheral circuit portion, 3
A resist pattern in which a discard pattern having a representative dimension of 50 μm is buried without a gap within 00 μm is formed on a substrate. With this resist pattern, uniformity of etching rate within ± 10% can be secured over the entire surface of the substrate.

Thereafter, the MoW film is dry-etched. This etching process is performed using SF ₆ / Cl ₂ as a gas.
Using / O ₂ , the conditions of the reactive ion etching (RIE) mode are set, and the holding temperature of the processing substrate is set to 25 ° C.

As the etching conditions in this case, for example, the supply gas flow ratio is SF ₆ / O ₂ / Cl ₂ = 56.
0/240 / 200sccm, discharge time is 30sec,
The pressure is 65 mTorr, the apparatus to be used is inductively coupled plasma (ICP), and the distance between the electrodes is preferably about 300 mm. After the etching, a p ⁺ layer is formed by ion doping in this state (FIG. 2).
(D)).

Similarly, an n ^- layer is formed through another photolithography step. Finally, coat with resist only
^{A +} layer is formed (FIG. 2F).

[Embodiment 2] An example in which the dry etching method of the present invention is applied to another LDD formation will be described with reference to FIG.

This embodiment is similar to the first embodiment except that the undercut is performed in the steps shown in FIGS. 2 (e) and 2 (f).
Is the same as

After p ⁺ is ion-doped on the p-channel side of the p-Si using a MoW gate as a mask to form p ^{+, the} entire p ⁺ side is covered with a resist in another lithography step, and the MoW gate is on the n-channel side. The MoW is processed using a mask capable of forming a pattern about 0.3 μm thicker.

After processing MoW vertically with the resist on the n-channel side, the bias voltage at the time of etching is further reduced to zero, and MoW is reduced to 0.3 on one side in the downflow mode.
A μm undercut is made, and in this state, p ⁺ is ion-doped using a resist as a mask to form n ^{+ in} p-Si. Thereafter, the resist is peeled off, and then p ⁺ is lightly doped using MoW with an undercut as a mask to form an n ⁻ region.

Example 3 The relationship between the distance between resist patterns and the etching rate was examined, and the in-plane uniformity of the etching was examined.

FIG. 3 is a circuit diagram showing a circuit between the pixel section and the peripheral circuit section.
FIG. 9 shows comparison between the etching rate distributions of Examples 1 and 2 using a pattern having an opening not covered with a resist within μm and the etching rate distribution when the opening exceeds 300 μm. .

When the distance of the discarded pattern exceeds 300 μm, the etching rate in the circuit portion, which is a fine pattern, is slow, and a large-sized test pattern placed around the substrate shows a considerably large rate. It can be seen that the distribution extends to ± 56.8%.

On the other hand, when the discard pattern is provided within 300 μm, the distribution is improved to ± 26.1% under exactly the same etching conditions. As a result of examining detailed conditions, the etching rate distribution was ± 10
%.

[Embodiment 4] A mask and etching conditions will be examined.

[0037] Figure 4 is the pattern interval and the LDD length and discarded, the results obtained for the wear amount of the g-SiO _x base (base gate oxide film).

As the discard pattern interval becomes shorter, the LD
It can be seen that although the D length is longer, the distribution of the LDD length is also smaller, reflecting that the etching distribution is improved.

[0039] Along with this, was not shaved deeply g-SiO _x underlying part of a fast etching rate, the upper limit of the abrasion amount according to the discard pattern interval is shortened to decrease the effective selectivity of It can be seen that is improved.

[Embodiment 5] The relationship between the gas ratio and the etching rate distribution will be examined.

As shown in FIG. 5, when the oxygen partial pressure of the gas supplied to form the plasma is reduced, the overall etching rate is reduced. This is because the reaction acceleration effect of MoW due to oxygen decreases.

On the other hand, it can be seen that the influence of the decrease in the etching rate due to the consumption of oxygen by the resist can be reduced as shown in the figure by providing a discard pattern.

That is, by providing at least one discard pattern at intervals of 200 microns, the etching speed distribution can be kept at ± 6% or less.

As is clear from the results shown in FIGS. 4 and 5, the thin film transistor in which the LDD is formed by the method shown in FIG. It has been found that drive for display can be provided.

[0045]

According to the dry etching method and the thin film pattern of the present invention, the MoW film can be etched with sufficient uniformity, and the transistor can be manufactured without processing the underlying gate oxide film. And the yield has improved.

[Brief description of the drawings]

FIG. 1 is a plan view of a thin film pattern of the present invention.

FIG. 2 is a diagram showing an LDD forming process of a coplanar TFT.

FIG. 3 is a graph showing a relationship between a MoW etching rate and a distance between patterns.

FIG. 4 is a graph showing a relationship between a discard pattern and an LDD length distribution.

FIG. 5 is a graph showing a relationship between a gas ratio and an etching rate distribution.

FIG. 6 is a schematic diagram showing the relationship between resist coverage and etching rate in MoW etching.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Glass substrate 2 ... a-Si 3 ... SiOx 4 ... MoW 5, 6 ... Photoresist

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) 4K057 DA20 DB01 DD01 DE01 DE06 DE08 DE20 DN01 DN02 5F004 AA01 DA00 DA01 DA04 DA16 DA18 DA24 DA25 DA26 DB12 EA00 EA21 EB02

Claims (7)

[Claims] 1. A dry etching method for dry etching a thin film formed on a substrate, comprising using a pattern having at least an opening not covered with a resist within 300 μm over the entire surface of the substrate. 2. The dry etching method according to claim 1, wherein the gas used in the dry etching contains at least one of F, Cl ₂ and O ₂ . 3. The dry etching method according to claim 1, wherein the size of the opening not covered with the resist is at least a representative dimension of 10 μm or more. 4. The dry etching method according to claim 1, wherein said thin film is made of a MoW thin film. 5. A thin film pattern formed on a substrate, wherein at least an opening is present in the thin film within 300 μm over the entire surface of the substrate. 6. The thin film pattern according to claim 5, wherein the size of the opening is at least a representative dimension of 10 μm or more. 7. The thin film pattern according to claim 5, wherein said thin film is made of a MoW thin film.