JP2000068992A - Frame synchronization detection method for inverted data and its device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To process continuously received inverted data from confirmation of synchronization till decode processing. SOLUTION: The frame synchronization device has a synchronization code detection section 1 that detects each data frame based on a synchronization code whose bits are inverted in a received signal, a data bit inversion section 2 that inverts bit sequence of the detected data frame to restore noninverted data, a format processing section 3 that decodes output data from the data bit inversion section 2 and a control section 4 that sets and control the operation of the code detection section 1 to the format processing section 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization system for multiplexed digital data transmission, and more particularly to a method for detecting a frame synchronization of inverted data transmitted by inverting the order of bit strings, such as in satellite communication. Regarding the device.

[0002]

2. Description of the Related Art In a frame synchronization system in digital data transmission, a predetermined bit pattern for synchronizing a transmission side and a reception side is arranged for each frame of data to be transmitted and transmitted. , The received data is processed while confirming the synchronization of the received data for each frame.

A data signal with a frame synchronization signal transmitted via a communication satellite is used in a ground station to avoid scrambling / descrambling for avoiding concentration of consecutive same codes and facilitating clock synchronization maintenance. In addition to performing code / decoding processing for adding an error correction code such as a Reed-Solomon code, in a satellite, processing such as amplification and frequency conversion of radio waves received from a ground station is performed and transmitted to the ground station.

At this time, the satellite station inverts the arrangement order of the input data bits of one frame as one means for preventing interference between input and output and transmits the inverted data to the ground station as inverted data. The receiving ground station first confirms the synchronization of the received data, and then processes the data by returning the data bits to the original arrangement order.

[0005]

Conventionally, in order for a frame synchronizer to confirm synchronization using a bit-reversed synchronization code and to perform processing subsequent to the detection of synchronization, the inverted data is temporarily recorded in a data recorder or the like. Until the data is reversely reproduced and converted into forward data, subsequent processes such as scramble decoding and Reed-Solomon decoding cannot be performed.

Therefore, extra time of recording / reverse reproduction after synchronization detection is required, and real-time processing cannot be performed. In addition, a device for always recording data and performing reverse reproduction is necessary, which has led to a decrease in the reliability of the system.

An object of the present invention is to solve the above-mentioned problems,
It is an object of the present invention to provide a method and an apparatus for detecting frame synchronization of inverted data, which can process the inverted data in real time by performing processing from synchronization confirmation to decoding processing of the received inverted data consistently.

[0008]

According to the method for detecting frame synchronization of inverted data of the present invention, a synchronization detection code in which the bit sequence of a frame synchronization code is inverted is set in advance, and when the inverted data is input, the set synchronization detection code is set. The frame synchronization code of the inverted data input by the detection code is detected, and every time the frame synchronization code is detected, the inverted data is stored in the buffer in the order of the input bit by frame, and the inverted data stored in the buffer is opposite to the input. , And the data of one frame read from the buffer is decoded by a predetermined decoding method and output.

The frame synchronization detecting apparatus according to the present invention comprises a synchronization code detecting section for preliminarily setting a synchronization detection code in which the bit sequence of the frame synchronization code is inverted, detecting the synchronization of the inverted data received and each frame. Done 1
A data bit inverting unit for inverting the inverted data of the frame to the data in the forward direction by inverting the bit order of the input, a format processing unit for decoding the output data of the data bit inverting unit, and setting and controlling operations of these units. And a control unit for performing the control.

It is desirable that the format processing unit has at least decoding processing means of a scramble coding method and decoding processing means of a Reed-Solomon method.

The data bit inverting section includes at least two buffers for storing input data and switching means for switching between the buffers one by one. The input data is buffered by one frame each time a synchronization code is detected. It is desirable to switch and store the data, and to perform inversion processing of the data bit order of the input data stored for each buffer.

When the data of one frame detected by the synchronization code detection unit is not the inverted data but the forward data, the data bit inversion unit transfers the input data directly to the format processing unit without sending the input data to the buffer. By providing a selection means, the present invention can be applied to received data in which inverted data and non-inverted data are mixed.

[0013] Further, a frame length discriminating means may be provided to discriminate the frame length of the inverted data to be transmitted for each frame so as to cope with variable length frame data.

[0014]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a system configuration diagram showing a basic configuration of an embodiment of the present invention, and FIG. 2 is a block diagram of a first embodiment of the present invention.

As shown in FIG. 1, a frame synchronization detection system for inverted data according to the present invention detects a synchronization code whose bit has been inverted and finds one frame, and an inversion of the found frame. A data bit inverting unit 2 for inverting the bit order of the data to return to the forward data (frame), and performing scramble decoding and Reed-Solomon decoding processing on the output data from the data bit inverting unit 2 to convert the data into digital data It comprises a format processing unit 3 for converting into a format that can be easily processed, and a control unit 4 for setting and controlling the operation of each unit.

In FIG. 2, a synchronization code detection section 1 of the first embodiment is a programmable one in which a synchronization detection code is set, detects a synchronization code in an input signal by the set synchronization detection code, and You can find the data for the frame.

The data bit inverting unit 2 comprises two buffers A and B, a buffer switching control unit 21 and a buffer address control unit 22. Each of the buffers A and B stores data for one frame, and when writing data to one buffer (for example, buffer A), the other buffer (buffer B) is controlled by the buffer switching control unit 21 to perform reading. . Further, since the data written in each buffer is read in the reverse direction to the order input by the buffer address control unit 22, the inverted data is returned to the forward frame data in frame units.

The format processing unit 3 includes a scramble decoding unit 31, a Reed-Solomon decoding unit 32,
/ 16-bit conversion unit 33. The scramble decoding unit 31 decodes the scrambled frame data to obtain the original data. The Reed-Solomon decoding unit 32 performs a decoding process on the data on which the Reed-Solomon process has been performed, and performs an error correction. The 8 / 16-bit conversion unit 33 converts the frame data into 8 bits.
The data is converted into data in units of bits or 16 bits.

The control section 4 sets predetermined data in each section from the synchronous code detection section 1 to the format processing section 3 and controls the operation.

Next, the operation of the first embodiment will be described with reference to FIG.

Here, the frame length of the data to be processed is 100 bits, and the frame synchronization code is (1ACFFC).
1D).

Before processing this data, the control section 4 inverts the bit order of the frame synchronization code to the synchronization code detection section 1 as a synchronization detection code (B83FF35).
8) Set. Further, the control unit 4 sets 100 as the frame length to be processed in the buffer address control unit 22 of the data bit inversion unit 2 and the scramble decoding determination / conversion formula and the Reed-Solomon decoding in the format processing unit 3. And the procedure of the 8 / 16-bit conversion unit are set.

When the inverted data is input, the synchronization code detection unit 1 searches for a code that matches the synchronization detection code (B83FF358) set for the input data. The buffer switching control unit 21 of the inversion unit 2 is notified. Upon obtaining the information, the buffer switching control unit 21 of the data bit inversion unit 2 switches the buffer A to the input and the buffer B to the output. And when the next sync code is detected,
The buffer B is switched to the input, and the buffer A is switched to the output. As a result, the buffer is switched every time the synchronization code is detected, so that one buffer always stores data for one frame.

When the next synchronization code is detected, the frame data input to any one of the buffers
The data bit length of 10 set in the address control unit 22
By reading from 0 until the address becomes 31 (before the frame synchronization code) until the address becomes 31, the written data is read in reverse, and the output from the buffer is the forward frame data (frame synchronization code Excluded). With such forward data (a sequence of regular data), the next processing can be performed.

The format processing unit 3 performs scramble decoding, Reed-Solomon decoding, and bit conversion, and outputs the result to a computer or the like for processing.

Next, a second embodiment of the present invention will be described with reference to the drawings.

In FIG. 3, the selector 23 is provided before the buffer so that inverted data can be processed via the buffer and non-inverted forward data can be processed without passing through the buffer. . Switching of the selector 23 is set by the control unit 4.

In the third embodiment shown in FIG. 4, the read / write address control sections 24A, 24A, which store the address written in the buffer and control data read from that address.
4B is provided for each buffer so as to correspond to variable-length frame data. Since the data length can be determined from the address written in the data, the inverted data can be returned in the forward direction by controlling to subtract from the address and read out the synchronization code.

[0030]

As described above, according to the present invention, a synchronization detection code in which the bit sequence of the frame synchronization code is inverted is set in advance, the frame synchronization code of the input inverted data is detected, and the inverted data of one frame is detected. Is temporarily stored in the buffer in the order of the input bits, then read out in the bit order opposite to the input, decoded by a predetermined decoding method and output, and the process from the synchronization confirmation of the received inverted data to the decoding process is performed consistently By doing so, there is an effect that the inverted data can be processed in real time and the data can be promptly provided. Further, since an external device for recording the inverted data, and performing the reverse playback and inputting the inverted data is not required, there is an effect that the availability (reliability) of the system can be improved.

Further, by providing at least two buffers and switching between the buffers for each data frame to perform writing and reading, the synchronization detection of the data frame and the data inversion processing can be continuously performed.

Further, by providing the data bit inverting section with a selection means for transferring the non-inverted data in the forward direction directly to the format processing section, the data bit inverting section can be applied to received data in which inverted data and non-inverted data are mixed. .

Further, the provision of the frame length determining means has an effect that the frame of the inverted data can be of variable length.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a data bit inversion unit 2 and a format processing unit 3 of FIG.

FIG. 3 is a block diagram of a second embodiment.

FIG. 4 is a block diagram of a third embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Synchronization code detection part 2 Data bit inversion part 3 Format processing part 4 Control part A, B buffer 21 Buffer switching control part 22 Buffer address control part 23 Selector 24A, 24B Address control part 31 Scramble decoding part 32 Reed-Solomon decoding part 338 / 16 bit conversion unit

Claims (7)

[Claims] 1. A method for detecting a frame synchronization of inverted data to which a plurality of bits of a frame synchronization code are added and transmitted by inverting the order of a bit string, comprising the steps of: When the inverted data is input, a frame synchronization code of the input inverted data is detected by the set synchronization detection code, and the inverted data is input one frame at a time every time the frame synchronization code is detected. Storing the inverted data stored in the buffer in a bit order, reading the inverted data stored in the buffer one frame at a time in the bit order opposite to the input, decoding the data of one frame read from the buffer by a predetermined decoding method, and outputting the decoded data. A method for detecting frame synchronization of inverted data as a feature. 2. A frame synchronization detecting apparatus for inverted data to which a plurality of bits of a frame synchronization code are added and transmitted by reversing the order of a bit sequence, wherein a synchronization detection code in which the sequence of the bit sequence of the frame synchronization code is reversed in advance is set. When the inverted data is input,
A synchronization code detection unit that detects a frame synchronization code of input data whose bit order is inverted by the synchronization detection code, and stores the inverted data in a buffer in the order of input bits one frame at a time every time the frame synchronization code is detected. And
A data bit inverting unit that reads data in an order opposite to the stored bit order; a format processing unit that decodes the data inverted in the data bit inverting unit and returned in the forward direction by a predetermined decoding method for each frame; A frame synchronization detecting device for inverted data, comprising: a control unit for controlling the operation of each unit. 3. The data bit inverting unit includes at least two buffers for storing input data and switching means for switching between the buffers one by one, and buffers the input data by one frame each time a synchronization code is detected. 3. The frame synchronization detecting apparatus according to claim 2, wherein the frame synchronization detecting apparatus switches and stores the data and performs inversion processing of the data bit order of the input data stored for each buffer. 4. The frame synchronization detecting device according to claim 2, wherein the format processing unit has a decoding processing unit of a scramble coding system and a decoding processing unit of a Reed-Solomon system. 5. The data bit inverting section transfers input data directly to a format processing section without sending the input data to a buffer when data of one frame detected by the synchronization code detecting section is forward data that is not inverted data. 5. The frame synchronization detecting device according to claim 2, further comprising a selection unit. 6. The frame synchronization detecting apparatus according to claim 5, further comprising a frame length determining means for determining a frame length of the inverted data to be transmitted for each frame, and capable of handling variable-length frame data. 7. The frame length judging means according to claim 6, further comprising: a read / write address control section for storing an address of the data written for each buffer and controlling the reading of data for each frame based on the address. Frame synchronization detection device.