HK40080674A - Integrated measurement systems and methods for synchronous, accurate materials property measurement - Google Patents

Description

Integrated measurement system and method for synchronized, accurate measurement of material properties

Cross Reference to Related Applications

U.S. provisional patent application No.63/057,745, entitled "SYNCHRONOUS SOURCE MEASURE SYSTEMS AND METHODS", filed on 28.7.2020, to Fortney; U.S. provisional patent application No.63/016,747 TO Fortney, entitled "ADVANCED ANALOG-TO-DIGITAL CONVERSION SYSTEMS AND METHODS", filed on 28.4.2020; AND U.S. provisional patent application No.63/034,052 TO Fortney, entitled "altered DIGITAL-TO-ANALOG SIGNAL Generation System AND METHODS", filed on 3.6.2020, each of which is incorporated herein by reference in its entirety.

Technical Field

The present disclosure relates to electronics, analytical instruments, software and facilities for signal sources and signal measurements. More particularly, the present disclosure relates to systems capable of measuring signals for material and device characterization and other applications under challenging experimental conditions that can cause high levels of noise and interference.

Background

Material and device property measurements (e.g., electron transport properties such as hall properties, mobility, and carrier concentration, etc.) are typically highly sensitive to noise, interference, and stray signals. For example, superconducting properties are typically measured at extremely low temperatures (e.g., below 4K) necessary to observe these properties without excessive noise. These measurements may also require very high field strengths (e.g., in excess of 5T), which may complicate the experimental setup. Processing noise, interference and spurious signals under these adverse conditions is critical to obtaining reliable, accurate data.

Experimental devices for measuring these characteristics currently require several different types of equipment (e.g., lock-in amplifiers, other amplifiers, current sources, voltmeters, ammeters, analog-to-digital (a/D) converters, and other devices). For example, lock-in amplifiers are critical for measuring signals under high interference/noise conditions. They extract the measured signal with a known carrier, thereby screening out extraneous or interfering signals. The lock is typically sold as a separate component designed to be mounted in the laboratory frame with the other devices mentioned above. In fact, each piece of equipment is housed in the laboratory apparatus as a single, self-contained unit. Researchers create experimental devices by physically and electrically connecting units.

The user creates experimental equipment from different equipment units, making noise reduction within the system-wide difficult, if not impossible. Each unit independently generates noise. Each cell has a unique and often unpredictable susceptibility to interference. Each cell has a different settling or transient effect. These different contributions and sensitivities have to be addressed independently. The calibration must be performed independently. Thus, the complexity of the interference/noise mitigation and calibration depends on the number of devices involved in the measurement. This number may easily grow rapidly even for relatively modest material property experiments. It places a hard limit on the accuracy of such measurement systems.

Since the equipment units are often from different commercial vendors, compatibility issues limit noise and interference mitigation within the system-wide. Mitigation techniques involving the cooperative operation of one or more units may not be possible or practical. For example, even if digital interference confuses sensitive measurements, it may not be possible to shield or shut down digital electronics in a system-wide. Since each unit typically has its own clock, accurate synchronization may be difficult or impossible. Standard connections (e.g., through BNC connectors and cables and using traditional instrument racks) introduce problems. Each connection may introduce additional impedance and/or noise. The wires add interference. Stray capacitances from any number of sources prevent measurement.

These problems degrade the repeatability and accuracy of the measurements. Different experimental devices can produce different results for the same measurement on the same sample. Thus, there is an unmet need for an accurate, consistent, and reliable material measurement system that provides noise mitigation, interference suppression, source/measurement synchronization, and calibration within the overall system. There is also an unmet need to reduce the number of noise and interference sources, including those due to excessive connector, wire and digital electronics interference.

Disclosure of Invention

Aspects of the present disclosure include a measurement system including a source unit configured to provide a source signal to a sample. The source unit includes at least one of a voltage source, a current source, and a memory configured to store a source calibration. The system includes a measurement unit configured to obtain a measurement signal from the sample that may be responsive to the source signal. The measurement unit includes at least one of a voltage measurement unit, a current measurement unit, and a capacitance measurement unit, and a memory configured to store a measurement calibration. The system includes a control unit comprising: a digital signal processing unit; a source converter connected between the digital signal processing unit and the source unit. The system comprises: a measurement converter connected between the digital signal processing unit and the measurement unit; a synchronization unit configured to synchronize clocks of the digital signal processing unit, the source converter, and the measurement converter; a calibration unit for calibrating a system comprising the control unit; and a reference voltage source configured to supply a common reference voltage for the control units.

The control unit may be configured to obtain at least one of: calibration data from a self-calibration performed by the source unit and the measurement unit; calibration data from a stored factory calibration; calibration data from a remote source via the internet; calibration data from user input; source calibration data from the source unit; and measurement calibration data from the measurement unit. The control unit may be configured to periodically obtain the source calibration and the measurement calibration. The control unit may be configured to obtain at least one of: a source calibration from a memory of the source unit when the source unit is unable to provide the source signal to the sample; and a measurement calibration from the memory of the measurement unit when the measurement unit is unable to acquire a measurement signal from the sample. The control unit may be configured to obtain the source calibration and the measurement calibration simultaneously. The digital signal processing unit may store calibration data of at least one of the control unit, the source unit and the measurement unit. The current source unit may be configured to measure a source current associated with the source signal via a sense resistance and vary a resistance range of the sense resistance according to a magnitude of the source current. The system may include a current source protection unit configured to determine whether the source current exceeds a threshold current, and when the source current exceeds the threshold current, change a feedback element of at least one of the source unit and the measurement unit such that the source current falls below the threshold current.

The synchronization unit may be configured to synchronize the digital signal processing unit, the source converter and the measurement converter with respect to an internal clock signal. The digital signal processing unit may be configured to provide a time stamp of data originating from at least one of the measurement unit and the source unit. The data from the measurement unit may comprise the measurement signal. The data from the source unit may comprise the source signal. The source unit may be configured to deactivate non-analog circuitry when providing the source signal. The measurement unit may be configured to deactivate non-analog circuitry when measuring the measurement signal.

The digital signal processing unit may be configured to perform at least one of the following with respect to at least one of the measurement signal and the source signal: lock-in analysis, alternating current/direct current (AC/DC) measurement, inductance L, capacitance C and resistance R (LCR) measurement, time/range domain rendering, frequency domain analysis, noise analysis, AC/DC sources, control loops, and providing source signals from more than one source.

The interface between the source unit and the control unit may comprise an interface between a low impedance buffered analog signal and the measurement unit. The control unit may comprise at least one of: a voltage-mode analog signal interface having low-impedance transmit and high-impedance receive circuits, and a current-mode analog signal interface having high-output-impedance transmit and low-impedance receive circuits. The interface signals between at least one of the source unit, the measurement unit and the control unit may comprise a differential method for transmitting or receiving circuits.

At least one of the interfaces between the source unit and the control unit may comprise a low impedance buffered analog signal, and the interface between the measurement unit and the control unit may comprise a low impedance buffered analog signal. The measurement unit and the source unit may be remotely located with respect to the control unit and the digital signal processing unit. The system may comprise a power supply filter to at least one of the measurement unit and the source unit. The system may comprise a first cable connecting the control unit to the measurement unit and a second cable connecting the control unit to the source unit.

The digital signal in at least one of the measurement unit and the source unit may be isolated from the control unit. At least one of the source converter and the measurement converter may include: a gain chain configured to amplify an analog input signal; a range selector configured to select a gain between the analog input signal and an output of a plurality of analog-to-digital converters (ADCs), wherein the output of each ADC has a path and the gain of each output path may consist of a gain stage in the gain chain; and a mixer configured to combine the outputs of the plurality of ADCs into a single mixed output.

The ADC output path may include: two ADC output paths that can be independently configured as either a high-range or a low-range path, the low-range path having a first gain for converting the analog input signal, the high-range path having a second gain for converting the analog input signal, the second gain being lower than the first gain; a mixing device configured to combine the output of the lower range with the output of the higher range; and means configured to vary an amount of gain combined by the high-range path and the low-range path.

The source converter may include two or more digital-to-analog converters (DACs) that are combined to generate two or more frequency components. The source converter may comprise a first path for generating a substantially low frequency signal, the first path comprising a first one of the DACs. The source converter may comprise a second path for generating a substantially high frequency signal, the second path comprising a second one of the DACs. The source converter may include: a data processor for processing an input signal; a combining circuit configured to combine outputs of the first path and the second path into a source signal; a feedback section configured to sense the source signal; and a servo loop configured to employ the feedback section to substantially maintain the source signal in accordance with the input signal.

The system may include at least one of a plurality of source units and a plurality of measurement units. The digital signal processing unit may be configured to perform lock signal processing. The lock signal processing may be synchronized with the synchronization unit. The lock signal processing may process at least one of a fundamental frequency and a harmonic frequency. The control unit may be configured to set a phase relationship between the source unit and the measurement unit. The lock signal processing may comprise providing a lock reference for communication between the control unit and at least one of the source unit and the measurement unit. The source unit may be configured to provide DC feedback to the control unit via an analog signal. The digital signal processing unit may be configured to convert the DC feedback to digital and set a DC measurement signal according to the digital DC feedback value.

The control unit may be configured to measure a parameter of the source signal using a DC signal. The DC feedback signal may be a low frequency AC signal. The control unit may be configured to evaluate a type of at least one of the measurement unit and the source unit and configure the digital signal processing unit according to the type. The control unit may be configured to output a DC offset as part of the measurement signal. The source unit may be configured to at least one of: the method further includes limiting a voltage of the source signal below a voltage threshold and limiting a current of the source signal below a current threshold. The system may include a housing for at least one of the source unit and the measurement unit, the housing including at least one of an electrostatic shield and a magnetic shield.

The control unit may comprise a single interface which conveys the source and measurement signals and control information. The control unit may be configured to perform at least one of: channel calibration, seamless varying range, spectrum analyzer noise analysis, and square wave or arbitrary wave demodulation for harmonic acquisition. The system may include a configurable display. The control unit may be configured to display real-time oscilloscope readings. The control unit may be configured to display the spectrum reading. The control unit may be configured to perform at least one of a factory calibration and a self calibration by: applying a signal to a more accurate resistance range; measuring the applied signal over the more accurate range; applying a signal to a less accurate resistance range; measuring the applied signal over the less accurate range; and calibrating the less accurate resistance range using the applied signal measured in the more accurate range and the applied signal measured in the less accurate range.

The control unit may be configured to perform a voltage measurement mode calibration on the measurement unit by: measuring an offset error at the measurement unit; storing the offset error in the memory of the measurement unit; connecting an amplifier associated with the measurement cell to a reference voltage; measuring, via the control unit, a gain error from applying the reference voltage to the amplifier; storing the measured gain error in the memory of the measurement unit; reading, via the control unit, at least one of the stored gain errors from the memory of the measurement unit; and applying at least one of the offset error and the stored gain error to correct the voltage measurement.

The control unit may be configured to perform a current measurement mode calibration on the measurement unit by: disconnecting the input connector of the control unit; connecting the input connector of the measurement unit to ground; configuring the measurement unit in a voltage measurement mode; measuring a voltage offset error of an amplifier via the measurement unit in the voltage measurement mode; applying an analog correction to reduce the measured voltage offset to approximately zero; switching the measurement cell to a current measurement mode and floating an input to the measurement cell; determining, via the control unit, a voltage offset error between the measurement unit and the control unit by configuring the measurement unit in a high current range and measuring the resulting voltage at the control unit; adjusting the leakage current until the current measurement value of the measurement unit is approximately zero; storing, via the control unit, the adjusted at least one of the leakage current and the voltage offset error in the memory of the measurement unit; reading, via the control unit, the adjusted at least one of the leakage current and the voltage offset error; and applying the adjusted at least one of the leakage current and the voltage offset error to correct a current measurement of the measurement cell.

The source unit may be configured to acquire the measurement signal, and the measurement unit may be configured to provide the source signal. The system may include a matrix switch control unit configured to provide a set of switches for scanning the source signal and the measurement signal. The power supply may be configured to supply power to the control unit, the source unit, and the measurement unit with reference to a common ground.

Aspects of the present disclosure include a method including providing a source signal to a sample via a source unit including at least one of a voltage source and a current source. The source unit includes a memory configured to store a source calibration. The method includes acquiring, via a measurement unit, a measurement signal from the sample in response to the source signal. The measurement unit includes at least one of a voltage measurement unit, a current measurement unit, and a capacitance measurement unit, and a memory configured to store a measurement calibration. The method comprises receiving, by a control unit, the measurement signal from the measurement unit. The control unit comprises a digital signal processing unit, a source converter connected between the digital signal processing unit and the source unit, and a measurement converter connected between the digital signal processing unit and the measurement unit. The control unit includes a synchronization unit configured to synchronize clocks of the digital signal processing unit, the source converter, and the measurement converter. The control unit comprises a calibration unit for calibrating aspects of the system comprising the control unit and a reference voltage source configured to supply a common reference voltage for the control unit.

Drawings

Fig. 1 illustrates one exemplary M81 platform or system 100 within the context of the present disclosure.

Fig. 2 illustrates another variation of an M81 platform or system 200 within the context of the present disclosure.

Fig. 3A illustrates another of the M81 platforms or systems 300 within the context of the present disclosure.

Fig. 3B is a first portion of a flow chart 330 showing how the head 102 and the cartridge (pod) 104 may work together to calibrate a measurement unit or cartridge configured to measure voltage.

Fig. 3C is a continuation of the flow chart 330 of fig. 3B.

Fig. 3D is a first portion of a flow chart 340 showing how the head 102 and the cartridge 104 may work together to calibrate a measurement cell or cartridge configured to measure current.

Fig. 3E is a continuation of the flow diagram 340 of fig. 3D.

Fig. 3F is a first portion of a flowchart 360 illustrating an exemplary calibration routine 360 for a source cartridge 104 (or a cartridge 104 in source mode) driven by the head 102.

Fig. 3G is a second portion of the flow diagram 360 of fig. 3F.

Fig. 4 illustrates several exemplary features of the source cartridge 104 within the context of the present disclosure.

Fig. 5A shows a direct comparison of the noise of the 1 mua current source in systems 100, 200, and 300 with the noise in a more conventional device.

Fig. 5B shows an enlarged view of signal a from box 104 within the context of the present disclosure.

Fig. 5C shows the amplified signal B in fig. 5A.

Fig. 6A illustrates the effect of mismatched timing in a conventional instrument rack, which can be avoided by using the shared synchronous clock 302 of the present disclosure.

Fig. 6B illustrates other effects of mismatched timing in a conventional instrument rack.

Fig. 7 illustrates a source signal chain 700 between an exemplary head unit 102 and an exemplary source cartridge 104 in a variation of systems 100, 200, and 300.

Fig. 8 illustrates an exemplary source signal chain 800 in which Alternating Current (AC) 802 and Direct Current (DC) 804 inputs are digitally added together by a mixer 806 in variations of the systems 100, 200, and 300.

Fig. 9 illustrates an exemplary source signal chain 900 in which AC 902 and DC 904 inputs are separately converted by DACs 906 and 908, respectively, in a variation of systems 100, 200, and 300.

Fig. 10 illustrates another exemplary source signal chain 1000 that prevents an AC circuit ("AC configuration") from affecting the accuracy of a DC circuit in variations of systems 100, 200, and 300.

Fig. 11 illustrates another exemplary source signal chain 1100 with a DC feedback loop within the context of the present disclosure.

Fig. 12 illustrates another exemplary source signal chain 1200 with digitized feedback within the context of the present disclosure.

Fig. 13 illustrates one exemplary variation of a digitally synthesized source channel 1300 within the context of the present disclosure.

Fig. 14 illustrates an exemplary variation of a source wave table 1400 that may be used in conjunction with a digital source 1300 within the context of the present disclosure.

Fig. 15 is a waveform 1500 generated within the context of the present disclosure by drawing a source wave table 1400 that may be used in conjunction with a digital source 1300.

Fig. 16A shows a step waveform obtained by low-pass filtering the waveform in fig. 15.

Fig. 16B shows a smoothed version of the waveform in fig. 16A.

Fig. 17 illustrates exemplary features of measurement box 104 within the context of the present disclosure.

Fig. 18 illustrates a measurement signal chain between an exemplary head unit and an exemplary measurement box 104.

Fig. 19 compares a voltage measurement with a seamless (continuous) varying range 1902 to the same measurement made by a conventional device 1904 within the context of the present disclosure.

Fig. 20 is a block diagram of one variation of implementing seamless range change 2000 via a dual amplification chain within the context of the present disclosure.

Fig. 21 illustrates a block diagram of another exemplary amplification chain 2100 for seamless rangeability within the context of the present disclosure.

Fig. 22A provides a schematic example of an automatic rangefinding algorithm 2200 that may be used in conjunction with seamless rangefinding within the context of the present disclosure.

Fig. 22B shows exemplary experimental data for use by the automatic ranging algorithm 2200.

FIG. 22C is a first portion of a flowchart detailing the auto ranging algorithm 2220.

FIG. 22D is a second portion of the flowchart detailing the auto ranging algorithm 2220.

Fig. 23 illustrates a locking technique within the context of the present disclosure for multiplying 2304 a measurement signal 2302 with a known reference source 2306 to form a demodulated signal 2308.

Fig. 24 shows the phase difference (θ) between the multiplied signals.

Fig. 25 shows how variations of M81100, 200 and 300 may also utilize a Phase Locked Loop (PLL) 2500.

Fig. 26 illustrates an exemplary reference output 2600 within the context of the present disclosure.

Fig. 27 shows how a variation of M81100, 200 and 300 utilizes a measurement Digital Signal Processor (DSP) 2700.

Fig. 28A illustrates a housing for the source/measurement cartridge 104.

Fig. 28B illustrates a housing for the source/measurement cartridge 104.

Fig. 29A illustrates an exemplary display for the head 102.

Fig. 29B illustrates another exemplary display for the head 102.

Detailed Description

The platform or system referred to as "M81" disclosed herein enables systematic noise and interference mitigation that is not possible with conventional ad hoc, rack-based systems. It provides an all-in-one experimental platform with time synchronized operation and advanced sourcing and measurement, incorporating source and/or measurement amplifier cartridges, lock-in amplifier functionality, digital multimeters (DMMs), DC/AC and other signal generators, etc.

The term "M81" is used interchangeably with the term "system". Thus, the phrase "systems 100, 200, and 300" with reference to the systems shown in fig. 1,2, and 3 is synonymous with the term "M81 100, 200, and 300". The term "M81" will be used generally to describe the various systems disclosed herein or encompassed by the general inventive concept.

M81 integrates numerous innovative solutions to reduce noise and interference in material measurement systems. It includes remote, automatic and periodic calibration of the entire system for noise reduction. It calibrates the entire system-wide measurement and signal chain, rather than individually calibrating each of its individual components. This provides a much more accurate calibration than can be achieved with conventional gantry-based systems. Its system-wide control of the digital electronics during the measurement prevents interference. Its system-wide clock synchronizes the source, measurement and analysis. This provides the excitation/input signal from the stored digital signal model. It feeds these analog signals to the samples via a mixed signal chain comprising both AC and DC components, each with a separately configured gain. The signal chain may be stabilized for output based on feedback from the sample stage. The system includes a balanced current source for matching input and output currents into/out of the sample to protect the sample and system from large fluctuations. Its "seamless ranging" technique protects the measurements from glitches and transients as they change across orders of magnitude. These and other solutions are detailed below. Features and functions described in the context of one M81 variant apply to other variants of M81, whether explicitly discussed or implied by the present disclosure.

Survey system overview

Fig. 1 shows one exemplary M81 platform or system 100 including an instrument "head" or control unit 102 and several exemplary remote "cartridges" 104. As shown in fig. 1, the cartridge 104 may include source units 104a-104c that may provide a detection signal to a sample (not shown) on the sample stage 106. Note that the words "cartridge" and "unit" are used interchangeably herein, such that reference to "source cartridge" is synonymous with reference to "source unit" and reference to "measurement cartridge" is synonymous with reference to "measurement unit". Similarly, the words "head" and "control unit" are used synonymously. The sample stage 106 may include various components 107, such as a cryostat, peltier cooler, power supply, heat sink, auxiliary electronics and/or mechanical positioning system, balance system, pneumatic stage, weights, and the like.

The cartridge 104 may include a measurement unit 104d configured to measure a signal from the sample. In this variation, system 100 includes three remote boxes 104a-c that serve as signal sources and one remote box 104d that serves as signal measurements. It is to be understood that this configuration is merely exemplary. In fact, source cartridges 104a-c may be used as measurement cartridges (e.g., 104 d), and vice versa. In a variation, each cartridge 104 may be of a certain type or configuration (e.g., measurement, source, and/or a particular set of features shown in fig. 4 and 17 below). In these variations, the head 102 may detect the type of cartridge 104 when connected. Upon cartridge 104 type detection, the head 102 may then configure itself and the rest of the system in a manner appropriate for the type of cartridge detected. For example, the head 102 may self-calibrate and/or perform a system-wide calibration of the cartridge type suitable for detection. The head 102 may perform other configurations depending on the detected cartridge type (e.g., it may configure the digital signal processing unit 326, etc.).

The system 100 may include any suitable number of sources and measurement cartridges 104. In other variations, M81 may include head unit 102 without cartridge 104. Note that system 100 may include any of the features described in the other variations below (e.g., variations 200 and 300). These include, for example, the shared synchronous clock 302 described in the context of fig. 3A below.

Although fig. 1 shows a head 102 with multiple connections (e.g., four connections 102a and multiple front panel connections 102b for a cassette 104), in a variation, it may have only one interface with the outside world. For example, the head 102 may have a single Universal Serial Bus (USB) connection that enables the head to send and receive data and control information to and from the cartridge 104. The data may include data related to providing source signals via the cartridge 104, acquiring measurement signals from the cartridge 104, processing those signals, obtaining other feedback from measurements, providing processed data including processed feedback to the cartridge 104. The control information may include any of the calibration, diagnostic, and configuration information disclosed herein. For example, the control information may include instructions to provide a particular input signal to the sample, extract a particular output, calibrate equipment in the system 100, and/or control an aspect of the sample stage 106, including the cryogenic characteristics of the stage 106. It may include calibration information from any unit in the system 100.

Fig. 1 also shows that the head 102 includes a display 102c. The display 102c may be a touch screen. It may be configured to display any of the data, signals, processed information, and control functions described herein. For example, the display 102c may be configured to display oscilloscope functionality when an aspect of the system 100 is used as an oscilloscope. The readings of these oscilloscopes can be displayed in real time. For example, the display 102c may also display a frequency spectrum. The display 102c may be configured to display other data including any data collected by the measurement box 104. The display 102c may also be configured to display the status of any unit in the system 100, the status of any communication into/out of any unit in the system 100, and any measured or signal derived diagnostic information about the in/out of the sample 106. The display may be configured to simultaneously display a plurality of parameters that may be configured by a user or through a remote interface. The display 102c may also be configured to display signal noise, interference, and/or spectral analysis, among others. The display 102c may also be configured to display any feature of a Graphical User Interface (GUI) for interacting with any aspect of the system 100.

Fig. 1 shows that the head 102 may include a housing or casing 102d. The housing or enclosure 102d may comprise a material (e.g., plastic or rubber) that provides electrostatic shielding. It may also include a metallic material for electromagnetic shielding. The housing may be made of any suitable material. It may include any mechanical or electrical interface as desired. For example, the housing 102d may include hooks, fasteners, or recesses such that it is compatible with a laboratory rack. It may include feet, posts or brackets so that it stands independently on a table or desktop. It may comprise a wall mount or ceiling mount or the like.

Other variations include any suitable number of heads, source cartridges, and measurement cartridges 104. For example, fig. 2 shows that the head unit 102 may have another exemplary variation 200 of six channels that may support three measurement type cartridges 104e and three source type cartridges 104 f. In this variation, M81 is also shown connected to an optional computer 108 and three exemplary Devices Under Test (DUTs) 110 in sample stage 106. Again, this configuration is merely exemplary. The number of measurement cassettes 104e and source cassettes 104f need not be equal. For example, one source 104f may provide stimulus signals for all three DUTs 110.

Herein, the abbreviation "DUT" will be used interchangeably with "sample". It is understood that the DUT or "sample" may be a device or material sample. In general, in the context of material measurement disclosed herein, devices (e.g., transistors) are created for the express purpose of testing materials (e.g., semiconductor materials) in the resulting devices.

Fig. 3A shows another variation 300 of M81 as a high level graph. Fig. 3A illustrates information sharing between components of the variant 300. For example, fig. 3A shows how the head or control unit 102 may handle analog-to-digital signal conversion (and vice versa). The source and measurement box 104 shown in fig. 3A are not unique. They can be used for different applications.

FIG. 3A also shows a shared synchronous clock 302 connected to each of a source channel 304 and a measurement channel 306. The clock 302 may provide shared synchronization to each of the signals derived from the measurement and source boxes 104, any converters or other electronics in the source channel 304 and measurement channel 306, and the head 102 itself. Having a shared clock enables all components in system 300 to synchronize automatically, thereby avoiding problems resulting from synchronization glitches or failures between any of these components. The shared synchronous clock 302 may be synchronized to an external or internal clock of the head 102. The source channel 304 and the measurement channel 206 may also include an interface between the cassette 104 and the head 102 with analog signals that are unaffected by cable length and external RF noise. All of these functions of the shared synchronous clock 302, source channel 304, and measurement channel 306 are discussed in further detail below.

Also as shown in FIG. 3A, the head 102 may have ports (e.g., monitor output, reference input and reference output ports 308, digital I/O ports 310, and auxiliary I/O ports 312) that enable the head 102 to connect to other hardware 314. The other hardware 314 may include any hardware suitable for collecting and analyzing data and/or supplying input from the system 300. Examples of other hardware 314 enabled by these connections include a laboratory oscilloscope, a Programmable Logic Controller (PLC), a laptop or other computer, a monitor, a switch matrix, a reference signal input, and so forth. Fig. 3A also shows how the head 102 may be connected to the external computer 108 through suitable connection mechanisms 316 including USB, ethernet, general Purpose Interface Bus (GPIB), cellular data, and wireless networking technologies (Wi-Fi). A suitable distance 318 may be maintained between the head 102 and the cassette 104 so that operation of the head 102 (and in particular its digital circuitry) causes little or no interference to measurements at the location of the DUT 110.

Fig. 3A also shows that the head has a calibration memory 320 and the cartridge has a calibration memory 322 for storing any aspect of the system. For example, the calibration memories 320 and 322 may store calibration information for each of the head 102 itself and/or the cartridge 104. Calibration memories 320 and 322 may include the following information: the actual voltage of the main reference, the gain compensation factor (measurement source), the offset compensation factor (measurement and source), the bias current compensation factor, the voltage compensation, and the common mode reduction factor.

The calibration information may be entered in any suitable manner. For example, calibration information may be installed on the calibration memories 320 and 322 by the manufacturer. It may be downloaded from the internet and/or provided via user input. Each of the components including the head 102 and the cartridge 104 may provide information from performing a self-calibration process. The head 102 may provide calibration to the cassette 104 and vice versa. The calibration information may also be stored in other devices (e.g., diagnostic devices, external computers, multimeters, etc.) connected to the system 300 but not shown. Calibration information regarding either of the calibration memories 320 and 322 may be periodically updated. Calibration information stored on the memory of any device (e.g., head 102 or cartridge 104) may be updated (e.g., via calibration) when the device is not in use. The calibration for the head 102 and the cassette 104 may be stored by the digital signal processing unit 324. Calibration may include a number of methods and components for calibrating different ranges. For example, the advantage of resistors with highly different resistance accuracies and temperature dependencies can be exploited to calibrate ranges that use less accurate resistors or that drift more with temperature and time. Since the G Ω resistor provides very low current noise, it can be advantageously used in some calibration aspects. However, the resistance value of the G Ω resistor is not always precisely known, and may be somewhat unstable over time. The M Ω range resistor is more stable over time even though its calibration suffers from more noise associated with larger currents. Thus, with the low noise advantage of G Ω and the high stability advantage of M Ω, the range of G Ω can be calibrated using an M Ω range resistor (100M Ω) and vice versa. The same may be true for lower values of resistance. For example, a typical 10 Ω resistor has better accuracy and drift than a 1 Ω resistor. In general, it is advantageous to use a 1 Ω resistance when measuring large currents, whether as an external sensing element or as part of the source or measurement circuit.

As discussed above, the systems 100, 200, and 300 may be calibrated in a number of different ways. Although not shown in fig. 1, each cartridge 104 has inputs/outputs that allow connection to precise signal sources and measurement devices (e.g., external voltmeters, ammeters, current sources, voltage sources). These inputs/outputs enable local calibration at the cassette 104 itself, just like individual components on a conventional rack system.

However, the M81 systems 100, 200 and 300 also provide total internal calibration. This enables the use of sensitive electronics in the head 102 to calibrate for measurement drift/error/fluctuation in the in/out cartridge 104 throughout the systems 100, 200 and 300. That is, the overall internal calibration is to calibrate for all the features in the entire signal chain from the measurement/source to the analysis electronics and from the analysis electronics to the measurement/source. This provides much higher accuracy. It is also much easier to implement. The calibration function of the entire system may be initiated via a GUI on the screen 102c and/or a button on the housing 102d. They may be set to run automatically and periodically. More specific functions of the overall internal calibration are discussed below.

Fig. 3B and 3C are a flow chart 330 showing how the head 102 and the cartridge 104 may work together to calibrate, where both measurements are taken, updates are taken, and calibrations are stored in the memories 320 and 322. In particular, a flowchart, algorithm, or routine (used interchangeably herein) 330 calibrates measurements received at the head 102 from the measurement box 104 when the box 104 is configured to measure voltage signals from the sample 110. The routine 330 is primarily driven by the head 102.

Turning to fig. 3B, in step 333, an offset error is measured at the box 104 for at least one hardware input configuration of the box 104. The hardware configuration is typically related to the type of measurement box being used and its associated features (see, e.g., the list of features in fig. 17). Typically, different hardware input configurations contain different components that affect the error being calibrated. For example, different hardware configurations may require the use of different feedback resistors, gain/amplifier configurations, or other components (e.g., DACs) to process the signal. The offset error for a particular hardware configuration is the difference between the voltage measured by the hardware configuration and the actual (known) input voltage. In step 333, the input to the box 104 may be disconnected from external measurements and connected to ground to ensure that the actual, known input voltage is zero. Other known input voltages (e.g., a known, stable voltage reference such as the main reference MR) may be used. The offset error is the voltage measured under these conditions. The offset error is stored as a calibration correction in the memory of the box 104. In step 334, the head 102 reads the offset error calibration from the memory of the cartridge 104. In step 335, the head 102 may apply an offset correction for the hardware configured voltage measurement based on the offset error measured in step 334. Alternatively, step 334 may be skipped and the correction applied until step 339. In step 336, the head 102 connects a reference voltage from the main reference MR to the amplifier input. The main reference MR may be, for example, a stable and reliable voltage reference, which may be anywhere in the system, for example, in the head 102. For example, the reference voltage may be a positive full-scale, negative full-scale, positive mid-scale, and negative mid-scale voltage. The selected reference voltage is appropriate for the hardware configuration of the box 104.

Turning to fig. 3C, in step 337 the head 102 measures the gain error of the hardware configuration by applying a reference voltage to the amplifier input in step 336. The gain error is measured, for example, by taking the difference between the expected, or desired gain and the measured gain. Many factors may cause gain errors and variations in gain errors. For example, the feedback resistance in an instrumentation amplifier topology may vary slightly over time and temperature. If the amplifier changes for reasons described below, the new amplifier will have a different gain error that should be compensated for by routine 330.

In step 338, the head 102 stores the gain error as a calibration in the memory of the cartridge 104. In step 339, the head 102 reads the gain error stored in the memory of the cartridge 104 and applies a gain correction for the voltage measurement of the at least one hardware configuration of the cartridge 104. One common technique for applying gain correction is to multiply the voltage measurement estimate by the inverse of the gain error. Any other suitable method of using gain error correction is contemplated. After this gain correction or calibration is completed, the input is reconnected to the external signal and the measurement can begin. In this phase, the head 102 may also apply the offset error calibration of step 334 as a correction for the voltage measurement. Gain correction and offset error correction may be applied by the box 104 for all voltage measurements until the head 102 restarts calibration by re-running the algorithm 330.

Fig. 3D and 3E are another flow chart 340 showing how the head 102 and the cartridge 104 may work together to calibrate the cartridge 104 configured to measure the current signal from the sample 110. The routine 340 is primarily driven by the head 102.

Turning to fig. 3D, in step 341, the input of the box 104 is disconnected from the front-end amplifier and connected to ground to protect the outer samples from possible switching transients. In step 343, measurement box 104 is configured into a voltage measurement mode with gain (e.g., voltage amplifier topology) to read the voltage offset error of the front-end amplifier when the input of the front-end amplifier is grounded. This is similar to the voltage offset error measurement detailed in step 333. The voltage offset error is the difference between the measured voltage and zero (since the amplifier input is set to ground). This is the voltage offset of the "front end" amplifier or amplifiers that will be connected to the sample. The first amplifier stage or front-end amplifier is connected to the device under test and is often the main cause of offset and leakage currents. Exemplary "front-end" amplifiers are amplifiers 720 and 810, 912, 1018, and 1114 (fig. 7, 8, 9, 10, 11, and 18). The front-end amplifier may comprise one or more amplifiers.

In step 344, the head 102 applies analog correction to reduce the voltage offset error of the front-end amplifier measured in step 343 until the box 104 measures substantially zero voltage (e.g., only a few tenths of volts, a few millivolts, or a few microvolts). Analog offset correction may include, for example, applying equal and opposite voltages to reduce, minimize, or eliminate voltage offset errors. In step 345, the head 102 switches the measurement box 104 to the current measurement mode. In step 345, the input of the box 104 may be disconnected from ground and left floating. In step 346, the head 102 determines a voltage offset error between the measurement box 104 and the head 102 by configuring the measurement box 104 in a high current range or even a highest current range (e.g., by switching to a lower feedback resistance) and measuring the resulting voltage at the head 102. The voltage offset error due to the front-end amplifier is pre-zeroed in step 344 and the front-end amplifier is set to give the lowest offset current. The measured residual offset is due to a voltage offset in the gain component between the front-end amplifier and the measurement transducer. Setting the front-end amplifier to a high current range results in a small gain in current offset due to the offset current flowing through the feedback resistor, resulting in a small voltage at the output of the front-end amplifier. When large gain or filtering is required to amplify the measured signal, a multi-stage amplifier configuration is typically used. These include, for example, amplifiers dedicated to the head 102 in the system 700 of fig. 7 or any of the amplifiers in fig. 20 and 21. In step 346, the voltage offset error between the front end amplifier of the measurement box 104 and the head 102 measured in step 346 is determined. This voltage offset error will be used to calibrate the error due to the transmission of the measured signal from the cartridge 104 to the head 102.

Turning now to fig. 3E, in step 347, the head 102 adjusts the leakage current (e.g., through a feedback resistance of a front-end amplifier) for one or more of the current ranges until the box 104 measures approximately zero current (e.g., only a few tenths of amperes (a), a few milliamperes, or a few microamps). For one or more of the ranges, the leakage current compensation is a current applied in the opposite direction of the measured current to reduce, minimize, or zero the measured current when no current flows into the box 104. The head 102 may use analog techniques to adjust the leakage current (e.g., routing a converter that connects a compensation current into the circuit) until the net current measured is zero. Leakage current adjustment may be performed for hardware input configurations. In step 348, the head 102 stores the leakage current of step 347 and/or the voltage offset error of step 343 as calibration corrections in a memory on the cartridge 104. In step 349, the head 102 reads the calibration corrections stored to the memory of the cartridge 104 in step 348 and applies at least one of the calibration corrections for the measurements of each hardware configuration of the cartridge 104. Note that the current measurement gain error can also be calibrated out by using an accurate current source derived from the main voltage reference MR or from a regulated current source located in the box 104. The calibration correction of step 349 may be applied by the box 104 for all current measurements until the head 102 restarts the calibration by re-running the algorithm 340.

Fig. 3F and 3G are another flow diagram illustrating an exemplary calibration routine 360 for a source cartridge 104 (or a cartridge 104 in source mode) driven by the head 102. Unlike the calibration routine 350, the calibration compares the source signal measured by the head 102 via a fully calibrated measurement channel to the actual source signal.

In step 361, the head 102 calibrates the measurement channel against the primary reference 351 a. This is an internal calibration of the head 102 for calibrating its own measurement capabilities.

In step 362, the head 102 commands the source cartridge 104 to apply a purely positive source signal. The high amplitude signal will be used to calibrate the source accuracy. In step 363, the head 102 measures the fully positive source signal generated in step 362 using the measurement channel calibrated in step 361. In step 364, the head 102 commands the source cartridge 104 to apply a negative full-scale source signal. In step 365, the head 102 measures the negative full-scale source signal generated in step 364 using the measurement channel calibrated in step 361. In step 366, the head 102 commands the source cartridge 104 to apply a source signal of zero. The signal is then measured by the head 102 in step 367 using the measurement channel calibrated in step 361.

In step 368, the head 102 compares the measured values of the fully positive, fully negative, and zero source signals (i.e., the values measured in steps 363, 365, and 367) with the command values of the corresponding fully positive, fully negative, and zero source signals (in steps 362, 364, and 366, respectively) to determine an error. Finally, in step 369, the head 102 uses the error determined in step 368 to generate and store a signal calibration measured for the cartridge 104. Calibration may be used to accurately supply signals to the sample.

Returning to fig. 3A, the figure shows how the head 102 has a digital signal processing unit 324. Although the digital signal processing unit 324 is not shown in fig. 3A as being connected to other aspects of the system 300, it may have multiple variable connections. For example, it may be connected to and synchronized with the shared synchronous clock 302. It may further accept and process signals from digital I/O310, source channel 304 and measurement channel 306, auxiliary I/O, interface 316. In general, the digital signal processing unit 324 may process signals from any of these components and provide the processed signals to any of these components. The digital signal processing unit 324 may use synchronization with the shared synchronous clock 302 to provide time stamps for data originating from the cartridge 104 and/or the head 102.

The digital signal processing unit 324 may provide various functions for the system 300. For example, it may provide any of lock-in analysis, alternating current/direct current (AC/DC) measurement, inductance (L), capacitance (C), and resistance (R) (LCR) measurement, time/range domain representation, frequency domain analysis, and noise analysis for the sample 110 measurement signal. Details of some of these operations will be described below. The digital signal processing unit 324 may also provide a source signal with respect to the sample 110: an AC/DC source, a control loop, and providing source signals from more than one source.

Fig. 3A also shows the head 102 with a power source 326. The power source 326 may supply other components of the system, not just the head 102. In some applications, for example, it may be advantageous for each of the cartridge 104 and the head 102, and possibly some of the other hardware 314, to share the power source 326. This may be advantageous for noise and interference mitigation and glitch prevention. The power source 326 may include a common ground in a reference system (not shown), such as the common ground of the head 102 and the cartridge 104. It may also include a power filter to at least one of the boxes 104.

Although not explicitly shown in fig. 3A, the head 102 may supply a single voltage reference for use by all components in the systems 100, 200, and 300. The reference voltage may be used to measure measurements in calibration as described herein, in noise determination and mitigation, and for other suitable applications explicitly described or implied by the present disclosure. Other system-wide references may also be provided for similar purposes.

Any feature described in the context of one of the M81 platforms/systems 100, 200 and 300 should be understood to apply to and/or be compatible with any of the other features. These features confer several advantages over conventional laboratory devices, including conventional instrument rack aspects, for the M81 platform/systems 100, 200, and 300. For example, they may exhibit very low noise. This is because the sensitive analog circuitry in the cartridge 104 is separated from the noise-containing digital circuitry in the head (see, e.g., separation distance 318 in fig. 3A). The M81 platforms/systems 100, 200, and 300 may be highly configurable/reconfigurable. In variations, the combination of cartridges 104 connected to the head 102 may be configured for a wide variety of experiments. The system is designed such that the digital and power circuits are separate from the sensitive analog circuits, and wherein the digital functions in the sensitive analog circuits are paused or turned off while the cassette 104 is taking measurements in order to minimize noise and interference.

The M81 systems 100, 200, and 300 may also support multiple ways of communicating between the cartridge 104, the head 102, and any other devices included in the system. These communication methods include the use of programmable instrument Standard Commands (SCPI) and queries. In various variations, a method of communication may include: a serial USB; TCP or Wi-Fi over Ethernet; general Purpose Interface Bus (GPIB); and so on. With respect to the data streaming buffer, information may be read from various variations of M81, for example, up to 10,000 samples per second. In various variations, for any channel, the buffer may include any combination of: a source amplitude; a source offset; a source frequency; a source range; source compliance; a source sensing error; (ii) a DC reading; an RMS reading; a peak; low peak; peak-to-peak; in-phase reading (I); out-of-phase readings (Q); locking the amplitude; locking the phase difference; measuring range; an overload state; a stable state; locking; lock to the reference frequency, etc.

The M81 systems 100, 200, and 300 described herein may be utilized in various applications. For example, in solid state electronic devices: DC and AC resistivities, I/V curves of the diode and transistor, operating scheme of the PIN (P-type, intrinsic and N-type materials) diode, subthreshold MOSFET characterization, capacitor dielectric absorption, deep transient spectroscopy, etc. In quantum and superconducting materials: I/V of superconducting materials, thin film dynamic inductance, spin hall magnetoresistance, abnormal hall effect, field and angle dependence in magnetic tunnel junctions, spin torque ferroresonance, and the like.

Variations of the M81, 200 and 300 systems have cassettes 104 that enable mixed sources. This means that in a variant, the output of the source box 104 may combine a signal chain of a DC configuration with a signal chain of an AC configuration. The signal chains may be independent, enabling the combination of high precision AC signals with DC offsets. Variations of M81100, 200 and 300 also enable seamless ranging in measurement mode. This means that in a variant, the measurement box 104 may have two or more variable range amplifiers and two analog-to-digital converters. This arrangement can suppress glitches that would otherwise affect the measured values when the measured signal spans a measurement range of many orders of magnitude. The variations of M81, 200 and 300 may also support flexible locking in the sense that each source and measurement box 104 may be referenced to each other or to the outside. Variations of M81100, 200 and 300 may also support external phase relationships. This means that, in a variation, the phase shift of each source capsule 104 can be configured independently while using the same reference. Each of these advantages will be described in more detail below.

Signal source

Summary of the features

The M81 platforms/systems 100, 200, and 300 may utilize any type of capsule 104 described herein. Fig. 4 illustrates several exemplary capsule configurations with exemplary features. For example, the ability of a combination source/measurement cartridge to combine a source cartridge and a measurement cartridge by using a channel for each is enhanced. The precision source capsule may include an I (current) or V (voltage) source with built-in current or voltage readback. This may help to reduce ambient noise that would otherwise confound a low temperature experiment with tight power limits. The source capsule 104 may also include a Balanced Current Source (BCS), as described further below, which may ensure that the same amount of current returns as provided. This helps protect sensitive equipment from surges.

It is to be understood that fig. 4 illustrates a combination of features that may be practical for certain applications. In some cases, it may be advantageous to include more or fewer features than shown in FIG. 4. For example, in some cases it may be advantageous to provide common mode noise rejection for enhanced combination source/measurement boxes and precision source boxes. In some cases, it may be advantageous to balance the current source box to accommodate the hybrid AD/DC source. All such variations should be considered within the context of the present disclosure.

Noise reduction of source signals

Fig. 5A shows a direct comparison of signal noise for M81 (e.g., systems 100, 200, and 300) to a more conventional device. More specifically, fig. 5A is a screen shot of noise for an exemplary M81 current source box 104 (labeled "a" in fig. 5A) and a more conventional laboratory current source (a conventional commercial current source labeled "B" in fig. 5A). Both sources are delivering currents in the range of 1 μ Α. Fig. 5B shows an enlarged view of signal a from the M81 box 104. Fig. 5C shows an enlarged view of signal B from the same cross section of fig. 5A. A comparison of fig. 5B with fig. 5C shows the advantageous signal-to-noise ratio of box 104 signal a. In particular, the 1 μ A signal amplitude 502 of signal A is several times greater than the exemplary noise amplitude 504 of signal A. In contrast, the 1 μ A signal amplitude of signal B is essentially buried in its noise amplitude 506, the noise amplitude 506 being several times greater than the signal amplitude 502 of signal A. It is also more than the noise amplitude 504 of signal a.

Synchronization

The M81 systems 100, 200 and 300 are inherently synchronized via a shared synchronous clock 302 (fig. 3A). In particular, synchronization enables signals sent from the source cartridge 104 to the sample 110 to be synchronized with the measurement cartridge 104 and analysis hardware (e.g., digital signal processor 322) in the head 102 itself.

Fig. 6A and 6B depict the effects of mismatched timebases in conventional instrument racks, which can be avoided by using a shared synchronous clock 302. For a conventional instrument rack, the clocks and timestamps of the source signal 602 and the sample measurement signal clock 1604 and the sample measurement signal clock 2 606 may be misaligned, as shown in fig. 6A.

Furthermore, the skew between clocks 604 and 606 may evolve over time. For example, different misalignments 610, 612, and 614 and different times t1, t3, and t3 are compared. These misalignments result in differences in the measured signal 608 shown in fig. 6B at 616, 618, and 620 at t1, t3, and t3. These frequency and phase differences can create significant problems in data analysis. They cause inaccuracies and errors. This problem can be potential and difficult to correct as time variations can make the problem appear non-systematic. Although fig. 6A and 6B present synchronization issues in the context of measurement signals and source signals, it is to be understood that this is merely exemplary. Lack of synchronization may cause trouble other than experimentally measured values. It may also obscure and confuse system-wide instructions, calibrations, and data analysis.

Synchronization issues are avoided by the M81, 200, and 300 system sharing one clock sampling clock (e.g., clock 302) among all of the source and measurement boxes 104 and the head 102. This inherently and automatically synchronizes all instruments, thereby avoiding inconsistencies between the source and measurement signals shown in fig. 6A and 6B.

Hybrid source

The "mixed source" forms an analog output source signal from both the AC and DC components. This technique can take advantage of both AC and DC source electronics by creating separate gain paths for the AC and DC signals. It also allows the construction of a source signal with a lower noise level, higher resolution and greater flexibility than a conventional single converter source. Variations of M81100, 200 and 300 have mixed source capability, as discussed below and in more detail in co-pending U.S. provisional patent application No.63/034,052, incorporated herein by reference.

FIG. 7 illustrates a source signal chain between an exemplary head unit 102 and an exemplary source cartridge 104 in variations of systems 100, 200, and 300 ¹ 700. The components shown as part of the head 102 in fig. 7 (i.e., the components 702, 706-714, 722, and 726-730) may be part of the digital signal processing unit 324 shown in fig. 3A.

As shown in fig. 7, M81 includes a source channel 702. In the exemplary case shown in fig. 7, there are three source channels 702, however it is understood that any suitable number of source channels is possible. The source channel 702 is fed a reference signal 704 via a Phase Locked Loop (PLL) 706. The source channel 702 may also include signals from other source channels 708 and measurement channels 710 from other cartridges 104. Input signals 708, 710, and 704 may then be selected as sources by reference to selection 712. The selected aspects of the signal, including waveform shape, amplitude, frequency, and phase, may then be sent to an AC configuration digital-to-analog converter (DAC) 714. The operation of the AC configuration DAC 714 will be discussed further below. The AC configured source signal and the DC configured signal may be combined to the sample 110 via suitable amplification.

Both AC and DC configuration signals may have independent configurations and separate amplifications by their respective DACs. A DC configuration signal is derived from DC feedback from the combined signal to adjust the sample source signal. Combining feedback and independent AC and DC configurations in a mixed source can improve the resolution and update rate of the source signal. Real-time feedback and independent configuration can avoid or minimize error sources such as offset error, gain error, differential non-linearity error, integral non-linearity error, calibration error, output noise, dynamic range, output bandwidth, source impedance, output drive capability, switching noise, phase error, drift and time, drift and temperature, etc.

Fig. 7 illustrates an exemplary hybrid source 700 configuration. The sample source signal (i.e., the signal sent by chain 700 to DUT 110) is a combination of an AC signal ("AC configured signal") and a DC signal ("DC configured signal"). These signals are combined to produce a sample source signal via variable gain 720, variable gain 720 may be dynamically varied to avoid glitches in the signal. The DC configuration signal is generated based on DC feedback from a combination of the signal of the AC configuration and the signal of the DC configuration.

More specifically, the AC configured DAC 714 provides an AC configured source signal to an amplifier 716 in the source box 104, where it is combined with a DC configured source signal via 718 and provided to a variable range amplifier 720, and then to the sample (DUT) 110. The waveform shape, amplitude, frequency, and phase of the source provided to the AC-configured DAC 714 may be preprogrammed, selected by the user, and/or selected from among options by the head 102 according to user preferences and/or protocols (e.g., measurement or diagnostics). The output of 718 is also provided as DC feedback via an amplifier 724 to a DC configured ADC 726 of the head 102. The DC feedback signal is then sent via bias 728 to DC configured DAC 730, which is then routed to 718 via amplifier 732.

As shown in fig. 7, the range of the variable range amplifier 720 along with other settings may be selected by means of a "range and other settings" signal sent via the range and other settings element 722 of the head 102. The ranges and other settings may be preprogrammed, selected by the user, and/or selected from among options by the head 102 according to user preferences and/or protocols (e.g., measurement or diagnostics).

The capsule 104 may also include digital (non-analog) circuitry capable of performing various functions including analysis, data communication, command information, power regulation, timing, and communication with external devices. In a variation, the source cartridge 104 has the ability to deactivate the non-analog circuitry when providing its source signal or performing a measurement. Doing so reduces the amount of interference and noise in the signal or measurement. For the same reason, the digital signals in the source cartridge 104 may be isolated from the measurement cartridge 104 and the head 102.

Before delving into mixed sources in more detail, it is useful to consider more conventional non-mixed sources. Fig. 8 illustrates one such unmixed source signal chain 800 where the inputs of AC 802 and DC 804 are digitally added together by 806. The chain 800 is suitable when the inputs of the AC 802 and DC 804 are generally in the same or similar range. In this configuration, small AC signals relative to DC signals have a resolution of only a few bits. DAC 808 converts the AC/DC combined signal to an analog signal, which is provided to variable amplifier 720, amplifier 810, and then to sample 110. Although fig. 8 does not explicitly show a DC feedback mechanism as shown in fig. 7, it is to be understood that it may include such feedback, for example, through the DC input 804.

Although chain 800 may be included in systems 100, 200, and 300, it has some disadvantages. The chain 800 must provide gain to both AC and DC input signals. Thus, there is no opportunity to configure the AC and DC signal chains independently. In addition, the degree of freedom in selection of the gain configuration is extremely small. The only flexibility of the chain 800 comes from the variable gain 720 that must be configured for both AC and DC simultaneously.

In contrast, fig. 9-12 illustrate an exemplary alternative approach to providing a more flexible and accurate hybrid source. Each of these systems may independently configure the DC and AC signal paths. They may be used in conjunction with the source signal chain 700 and systems 100, 200, and 300. Other methods that may be used to mix the sources are set forth in U.S. provisional patent application No.63/034,052.

Fig. 9 illustrates an exemplary source signal chain 900 for separately converting AC 902 and DC 904 inputs by DACs 906 and 908, respectively, in a combined configuration ("both must be configured") when the AC and DC configurations occur in parallel. This enables the AC 902 and DC 904 inputs to be individually and independently configured and varied, providing greater flexibility in defining the range of contributions of the AC 902 and DC 904 to the signal ultimately sent to the sample 110. Each AC 902 and DC 904 input is also applied individually to variable gains 720a and 720b, respectively. The variable gains 720a and 720b may be set by range and other settings 722 (fig. 7), or by user preference, protocol, or may be preset. The DC gain 720b may or may not depend on the output to the samples 110, as disclosed in the context of the system 700 and fig. 7. After variable amplification, both AC and DC signals are added 910, sent to an amplifier 912 and sent to the sample 110.

Fig. 10 illustrates another exemplary source signal chain 1000 in which the AC and DC configurations are separate and parallel. In the chain 1000, the AC circuit ("AC configuration") is prevented from affecting the accuracy of the DC circuit. In this case, it is advantageous that the bandwidths of the AC and DC paths are substantially different from the transition frequency to obtain a flat frequency response when they are summed and transmitted to the sample 110.

As shown in fig. 10, first, the sum of the AC 1002 and DC 1004 inputs is sent to the DAC 1008 in the DC configuration path at 1006. The AC 1002 input is sent to the DAC 1010 in the AC configuration path. Both the AC and DC signals are then amplified by variable amplifiers (720 a and 720b, respectively). The gains 720a and 720b of the DC and AC configuration circuits are different and may be configured for each. Within the context of fig. 9, they may be set in the same manner as described above for gains 720a and 720b. Next, the AC configuration signal is high pass filtered 1012 to remove low frequency components. The DC configuration signal is low pass filtered 1014 to remove high frequency components. The filtered AC and DC signals are then summed 1016. The summed signal is amplified at 1018 and sent to sample 110.

Fig. 11 illustrates another exemplary source signal chain 1100 with a DC feedback loop. The AC input 1102 and the DC input 1104 are summed 1106 and sent to the DC configuration path via a DAC 1108. The AC input 1102 is fed to the AC configuration path via a DAC 1110. The AC configuration path then passes through a variable amplifier 720a before summing 1112 with the signal from the DC configuration path after amplification by 720b. Gains 720a and 720b may be set as discussed above in the context of fig. 9 and 10. Then, sum 1112 is fed to sample 110 via amplifier 1114.

DC feedback is implemented as follows. The DC configuration path from DAC 1108 is summed 1116 with the DC input signal after processing by DAC 1108 and then to variable amplifier 720c via 1118. The gain 720c may be set as discussed above for 720a and 720b. Subsequently, at 1112, the DC configuration signal is summed with the AC configuration signal. The feedback loop essentially treats the AC path as interference to the DC path, enabling a flat frequency output to the sample 110.

Fig. 12 illustrates another exemplary source signal chain 1200 in which DC feedback is digitized feedback using an ADC. It introduces less DC inaccuracy, enhancing the DC DAC resolution. Chain 1200 also takes advantage of the fact that: ADCs are generally more accurate and provide better control than DACs.

The AC configuration path in chain 1200 is the same as the AC configuration path in chain 1100 in fig. 11. The DC configuration path of chain 1200 differs from the DC configuration path of chain 1100 primarily in that ADC 1202 is included in the DC feedback. However, there are some other subtle differences. Specifically, the DC feedback from the sample 110 is fed to the ADC 1202 via the variable amplifier 720c, where it is converted to an analog signal. This signal is then DC added 1204 to the combined DC input/AC input signal from 1106. The combined signal is then fed to DAC 1108, via 1206, amplifier 720b, and then summed with the AC configuration signal at 1112. Gains 720a, 720b, and 720c may all be set as described above with respect to fig. 11.

Balanced current source

Turning back to fig. 7, the capsule 104 may also include a Balanced Current Source (BCS) capability 732. BCS 732 is described in more detail in U.S. Pat. No.6,501,255 entitled DIFFERENTIAL CURRENT SOURCE WITH ACTIVE COMMON MODE REDUCTION, filed on 4.10.2001, to Pomeroy (the' 255 patent), the entire contents of which are incorporated herein by reference.

In short, measurement systems (e.g., systems 100, 200, and 300) may be susceptible to inconsistent loads, resulting in current spikes and/or asymmetries between inputs/outputs. These spikes can damage the components of these systems. Another problem with single-ended current sources is that if the load is grounded to the source return, the output current return is not controlled. Single-ended current sources also generate a common mode voltage across the load. In such a current source, the output and return have different impedances, which creates an unbalanced load. Common mode noise coupled into leads having different impedances reacts to produce normal mode noise, which can negatively impact the desired current excitation. There is a need to achieve current balancing in the context of material measurements that account for both floating and grounded loads without substantially changing and rewiring the circuit. BCS 732 addresses this need.

As discussed in the' 255 patent, the BCS 732 drives the load with two modified Howland current sources that deliver equal currents in opposite directions to each side of the load. In the context of systems 100, 200, and 300, the BCS 732 uses sense resistance to measure a source current associated with a source signal sent from the source cartridge 104 to the sample ("sample source signal" in fig. 7). It then changes the resistance range of the sense resistor according to the magnitude of the measured source current. The BCS 732 may also balance the load by changing the resistance of either (or both) of the source and measurement boxes 104 based on the source signal measurement. For example, when the measured source current exceeds a threshold, the BCS 732 may increase or decrease the resistance of one or both of the cartridges 104 to reduce the current below the threshold. The threshold current may represent, for example, a current beyond which damage to one or more components of the systems 100, 200, and 300 would result.

Digital source synthesis

Variations of M81, 200 and 300 may use direct digital synthesis to generate the source signal. Direct digital signals provide greater consistency and control over the source signal. Digital signals also tend to have less variability and drift. Since these problems ultimately lead to noise or ambiguity in the output signal, the use of direct digital synthesis can improve the accuracy and reproducibility of the measurement. Although certain specific examples are described below, it is to be understood that any suitable mechanism for providing a digital source signal may be used in conjunction with any of the variations described herein.

Fig. 13 illustrates one exemplary variation of a digitally synthesized source channel 1300. The digitally synthesized source channel 1300 may be part of the digital signal processing unit 324 shown in fig. 3A.

The source may be derived primarily from waveform table 1302. The table 1302 may be an algorithm (software or firmware) that generates a waveform based on a plurality of inputs 1304. Input 1304 may direct table 1302 to select a particular waveform to the source. Input 1304 may select frequency, phase shift, and hysteresis, among others. Each of these inputs 1304 need not be used in every variation. Input 1304 may be stored locally, may be input directly by a user, may be generated by other software, and/or according to a measurement or diagnostic protocol.

Reference signal 1306 may also be incorporated as an input into table 1302. Reference 1306 includes a source reference from a lock-in amplifier (e.g., a source lock-in reference from channels 1-3) and a phase-locked loop (PLL) reference. References 1306 may be selected by multiplexer 1308 and sent to multiplexer (mux) 1310 where they are combined with waveform settings 1304 and additional references 1316. The reference 1306 may be selected by a user, other software, and/or according to a measurement or diagnostic protocol. They are then sent to table 1302 to select the particular waveform to be output as the source signal. The output waveform from table 1302 may then be further processed 1302 by any of the signal processing methods described herein and provided to source box 104. The channel 1300 may also use a phase-locked reference with a selectable phase shift 1304 instead of being selected directly via the input 1304. In this case, the frequency and phase of the source may be determined by a phase-locked reference signal (e.g., reference 1312). Selectable phase shift 1304 may set a phase relationship with reference 1312. The external phase relationship may be configured differently for each channel.

Fig. 14 and 15 illustrate exemplary variations of a source wavetable 1400 that may be provided by an element 1302 of a digital source 1300. Waveform 1500 in fig. 15 is generated by plotting the data in table 1400. Fig. 15 plots a single cycle of waveform 1500 in relative units.

In one variation, the source signal supply algorithm may repeat increments in the table 1400 representing one or more cycles of the waveform. Table 1400 provides waveform amplitude (output) versus time (position) in normalized units. It is not necessary to use a normalization unit. It is convenient to scale the voltage or time dependence of the waveform based on input 1304. In this manner, table 1400 determines the shape of waveform 1500. An algorithm, called phase increment (element 1304, fig. 13), determines the frequency of waveform 1500 by the rate at which table 1400 cycles.

The "position" of table 1400 need not be changed by an integer. In certain variations, for example, a higher resolution phase accumulator (element 1304, fig. 13) may be used to track the phase of waveform 1500. Phase accumulator 1304 may increment a non-integer amount to convert the phase to a position in table 1400.

The waveform 1500 in fig. 15 may be smoothed and/or continued through the table 1302 itself or in the source process 1302. For low pass smoothing, at time t _w May replace the values in the table of fig. 14 with discrete output values having a non-zero width. This produces a "stair-step" output waveform 1602, as shown in FIG. 16A. Applying an analog low pass filter to 1602 produces a smoothed waveform 1604 shown in fig. 16B. The AC waveform 1604 may be combined with DC bias settings (not shown) and fed into a closed-loop DC source system in source processing 1302. This may be part of the mixed source variation discussed above in the context of fig. 8-13.

Advanced measurement technique

The M81 platforms/systems 100, 200, and 300 may utilize measurement boxes 104 having many different features. The particular type of cassette 104 used and its measurement characteristics may depend on the application and/or practical considerations. Fig. 17 presents several variations of an exemplary measurement box 104 with its feature set. "enhanced combination source/measurement cartridge" may combine the capabilities of a source cartridge and a measurement cartridge by using the channels of each. The "voltage measurement box" may be single ended, or may have differential voltage measurements with continuity over multiple orders of magnitude. The "current measurement box" may include a transimpedance amplifier that measures the current into a virtual ground. It is to be understood that while fig. 17 illustrates a combination of features that may be practical for certain applications, in certain circumstances it may be advantageous to include more features than are shown in fig. 17. For example, in some cases, it may be advantageous to enhance the combined source/measurement cell to measure voltage, current, have lowest noise, analog filters, seamless and seamless ranges. All such variations should be considered within the context of the present disclosure.

Fig. 18 illustrates a measurement signal chain 1800 between the example head unit 102 and the example measurement box 104 in a variation of the systems 100, 200, and 300. A portion of the signal chain 1800 in the header 102 (i.e., 1802, 1806-1816) may be part of the digital signal processing unit 324 shown in fig. 3A.

As shown in fig. 18, the head 102 includes a measurement channel 1802. In the exemplary case, there are two input measurement channels, one for range a and one for range B, each channel having its associated ADC. It is to be understood that any suitable number of measurement channels is possible, depending on the particular measurement and the number of ranges involved, which may be significantly greater than two (e.g., three, four, or more). The measurement channels 1802 may be obtained from the measurement box 104 via a plurality of variable amplifiers 720 and analog filters 1804, as shown in fig. 18. The gain on amplifier 720 may be set as described in the context of gains 720a-720c in fig. 10-12. Channel 1802 may be combined 1806 with range mix 1808 and sent via lock-in for demodulation 1810, as described in more detail below with respect to fig. 23. The demodulation may learn the reference signal (e.g., reference (locked) and reference +90 degrees (locked) 1812) and is subject to signal refinement by a digital filter 1814. The digital filter 1814 may be, for example, a finite impulse response and an infinite impulse response.

As shown in fig. 18, the range mixer 1808 may also provide an output of the range and settings 1816, which is ultimately fed back to the amplifier 720 and the analog filter 1804 to adjust the gain and processing of the measured sample signal specifically for each of the ranges a and B. This process is referred to as continuous measurement ranging and/or range compounding. The purpose is to ensure that glitches or measurement inconsistencies that would otherwise occur when the measurement box 104 has to change its acquisition parameters to adjust for a range change in the measured sample signal are prevented. The operation of range mixer 1808 and the continuously varying ranges between ranges a and B are discussed further below.

The measurement box 104 may also include digital (non-analog) circuitry capable of performing various functions including analysis, data communication, command information, power regulation, timing, and communication with external devices. In a variation, the measurement box 104 has the ability to disable the non-analog circuitry when performing a measurement or providing a source signal. Doing so reduces the amount of interference and noise in the signal or measurement. For the same reason, the digital signals in the measurement box 104 may be isolated from the source box 104 and the head 102.

Continuous measuring range

Material measurements, particularly those performed at low temperatures and involving properties related to electronic structures, can range across tens of times and many orders of magnitude. These wide ranges can subject conventional measurement equipment to stress. Different devices are often required to measure different ranges of values. Switching between different devices to cover multiple ranges in a single experiment can cause glitches in the measured data. These spikes are caused by many factors, such as accuracy and gain differences between different range measurement systems. Additionally, variations in the range can cause the measurements to be discontinuous over time, resulting in gaps in the collected data. Neither of these cases is desirable. Both of which degrade the overall measurement accuracy. To address these issues, variants of M81, 200 and 300 have "seamless rangeability" capabilities, as discussed below and in more detail in co-pending U.S. provisional patent application No.63/016,745.

Fig. 19 compares the voltage measurement with a seamless (continuous) varying range 1902 in M81, 200 and 300 with the same measurement made by a conventional device 1904 that lacks seamless varying range capability. Fig. 19 shows how a conventional variable range 1904 produces a discontinuity D in the measured data 1904 over a range transition Δ t. This is because different sets of devices with different measurement characteristics (e.g., accuracy, gain, etc.) are used to measure the data in ranges r1 and r2. In addition, switching between ranges r1 and r2 may introduce transient signals, noise or glitches caused by "warm-up" or the start of using equipment dedicated to making measurements in the range to which it is transitioned (r 2 in the exemplary case shown in fig. 19).

Fig. 19 also shows how the transition at is smoothed by the seamless rangeability included in the M81 platforms/systems 100, 200, and 300 (continuous variable range measurement data 1902). This smoothing effect is schematically represented in fig. 19 as avoiding discontinuities D by continuously varying range data 1902. Although only two exemplary ranges r1 and r2 are discussed in the context of fig. 19, it is to be understood that the continuously variable range technique may be applied to any suitable number of ranges associated with a particular measurement. For example, in some cases, the number of ranges may be three, four, or more. In each of these cases, the continuously variable range may be configured to ensure a smooth transition between each range change regardless of the direction of the range change (i.e., regardless of whether the range change involves an increase or decrease (not shown) in the measured value as shown in fig. 19).

Continuously variable range processes the two ranges r1 and r2 using separate signal amplification/gain chains that can be applied independently and/or simultaneously. Specific implementations will be discussed below in the context of fig. 20 and 21. Processing each range r1 and r2 separately and/or simultaneously allows configuring the inactive range (i.e., the range not currently employed in the measurement, e.g., when t is<t _TR Range r2 or when t>t _TR The range r 1). Keeping the amplification chain of the inactive range online while measuring the active range can avoid start-up transients when the inactive range is terminated. It also allows "range-mixing" in which the gain chains for each range are applied in combination so that the data within the transition Δ t from the range r1 to r2 (and vice versa) varies smoothly. That is, amplification chains from both ranges may be applied simultaneously to smooth the data within the range transition Δ t. For example, this may beTo be done via a software mixer and/or may then smoothly transition from r1 to r2 and vice versa.

Fig. 20 is a variation 2000 to achieve seamless ranging via a dual amplification chain. The variant 2000 may be implemented by, for example, a range mixer 1808 shown in fig. 18.

As shown in fig. 20, the lower gain chain 2002 and the higher gain chain 2004 are identical except for 1) different ADCs (2008 a and 2008b, respectively) and 2) an additional amplifier 2006 in the higher gain chain 2004 to which it is given a higher gain than the lower gain chain 2002. The outputs from ADCs 2008a and 2008b are combined by mixer 2010 and used in the acquisition routine of measurement box 104 for range measurements. In chain 2000, the combinations may be weighted by a factor α. Alpha may be dynamically selected to ensure a smooth transition within the varying range transition at (e.g., range blending is used to avoid discontinuity D in fig. 19). α can be set by the user, but is often set by a variable range algorithm (e.g., algorithm 2200 shown in FIG. 22A).

Fig. 21 illustrates another exemplary amplification chain 2100 for seamless rangeability. The variation 2100 may be implemented by, for example, the range mixer 1808 shown in fig. 18.

Chain 2100 includes a lower gain section 2102 and a higher gain section 2104 that, in addition to 1), are different ADCs (2108 a and 2108b, respectively); 2) An additional amplifier 2106 in the higher gain section 2104 (to which a higher gain is given than in the lower gain section 2102); and 3) the lower gain section 2102 and the higher gain section 2104 are connected out of the gain stage 2112 via multiplexers 2114a and 2114b, respectively.

As shown in fig. 21, the amplification supplied from the gain stages 2112a and 2112b to the lower gain section 2102 and the higher gain section 2104 may be selected via multiplexers 2114a and 2114b, respectively. In this way, chain 2100 may use fewer dedicated amplifiers than chain 2000 to provide combining to mixer 2110. It is not only more efficient to use the same gain stages 2112a and 2112b (and amplifier) for the lower gain section 2102 and the higher gain section 2104. It may also introduce less noise in the system that may be caused by glitches or incompatibilities between different amplifiers. For example, each amplifier may have transients that can be avoided when they are in constant use, regardless of the range of application.

As in the case of chain 2000, the combinations in chain 2100 may be weighted by a factor α. The factor α may be dynamically selected to ensure a smooth transition within the varying-range transition Δ t (e.g., using distance blending to avoid discontinuity D in fig. 19). α can be set by the user, but is often set by a variable range algorithm (e.g., algorithm 2200 shown in FIG. 22A).

In variations including chains 2000 and 2100, among others, seamless rangeability may include automatic rangeability. Fig. 22A provides a schematic example of an automatic rangefinder algorithm 2200 that may be used in conjunction with seamless rangefinding. Fig. 22C shows algorithm 2200 in flow chart form. It may be implemented by the range mixer 1808 in fig. 18, in addition to other components in the digital signal processing unit 324.

Algorithm 2200 changes range as the measurement signal 2250 shown in fig. 22B increases from ranges r1, r2, and r3. Signal 2250 at t = t _TR(1-2) Transition from range r1 to r2 and at t _TR(3-4) Transitioning from range r2 to r3. Fig. 22A shows the response of algorithm 2200 in these transitions in terms of applying gain chains dedicated to ranges r1, r2, and r3.

As shown in fig. 22A and 22C, at the transition from r1 to r2 (t) _TR(1-2) ) During the previous period 2202, the algorithm 2200 provides the gain configured for 100%r1 (e.g., extracted from the higher gain portion 2004 in the chain 2000 of FIG. 20 to provide the higher gain to the lower of the two ranges). FIGS. 22A and 22C also show that the measured signal approaches the transition t _TR(1-2) Algorithm 2200 blends the gain characteristics for r1 and r2 (e.g., extracted from higher gain section 2004 and lower gain section 2004). The pre-transition r1/r2 mixing period is labeled 2204. As discussed above, blending avoids glitches and/or gaps in the data during r1/r2 range transitions. At t _TR(1-2) After the r1/r2 transition at (a), algorithm 2200 applies the r2 gain without mixing (e.g., extracted from lower gain section 2002 in chain 2000 of fig. 20). 22A, 22B, and 22C show that the algorithms are identicalBy first mixing the gain characteristics for r2 and r3 during period 2208, and then by providing the gain of the r3 configuration only during period 2210 _TR(3-4) From r2 to r3.

Fig. 22A also shows an area of lag 2212 during period 2206 (r 2 only). During lag 2212, there is no expected range change (i.e., only one gain section of the gain chain is active, in this case, the gain chain for r 2). This avoids switching back and forth between ranges due to noise or signal variations. Once the edge of the measurement signal 2250 approaches r3, the lag period 2212 ends. Period 2214 represents a period ranging from r2 to r3 expected by splicing a gain chain (not shown) for r3. The gain chain corresponding to r3 is engaged during 2214, both for calibration purposes and to avoid transients, as discussed above. Although the expectation of a hysteresis or range-up portion is not shown for the r1/r2 transition, it is understood that they may also apply to this transition.

Although fig. 22A shows the operation of the algorithm 2200 as the measured signal increases, it is understood that the algorithm applies the same way as the measured signal decreases (e.g., from the upper range r3 to the lower range r2, and then to the lowest range r 1). This is illustrated via flowchart 2220 in fig. 22D. In this case, algorithm 2200 would have an expected range decrease period, rather than an expected range increase period (e.g., at t) _TR(2-3) Transition from r3 down to r2 (step 2224 in fig. 2220), etc.). While fig. 22A, 22B, and 22C show algorithms 2200 and 2220 that handle range changes between three exemplary ranges r1, r2, and r3, it is understood that it can handle range changes between any number of ranges suitable for experimentation in the same manner. Other variations of algorithms 2200 and 2220 may include many other algorithms and/or range/parameter settings and any suitable number of range transitions.

Lock-in measurement

The M81100, 200, and 300 variants may include a head 102 with lock-in measurement capability to accurately extract measurements from noisy measurement signals, among others. Fig. 23 shows an exemplary variation 2300 that may be implemented by the digital signal processing unit 324. In a variation 2300, the measured signal 2302 may be multiplied 2304 by a known reference source 2306 to produce a demodulated signal 2308. After demodulation, a low pass filter 2310 may remove noise and produce a reading 2312.

In one exemplary implementation, the resistance R1 of the sample 110 may be measured by obtaining an AC current and measuring the voltage 2302. Multiplying 2304 the measured voltage reading 2302 with the output of the current source 104 as the reference signal 2306 may allow the voltage produced only by the current through the resistor R1 to be extracted via the locking technique of fig. 23.

Locking technique 2300 utilizes the following signal processing concept. In this case, signal multiplication helps signal extraction because of the different frequencies (ω) _r ≠ω _m ) The product of two repeated signals of (a) averages to zero:

∫sin(ω _r t）*sin(ω _m t)＝O，ω _r ≠ω _m

however, when the multiplied signals have the same frequency (ω) _r ＝ω _m ) The product of the signals will average to half the signal amplitude:

thus, the lock-in technique 2300 of fig. 23 can be used to isolate the measurement signal 2302 from interference and noise that do not include the reference 2306 signal.

Variations of M81100, 200, and 300 may also demodulate harmonics (i.e., multiples of the reference frequency) for signal extraction. This is particularly useful when there is a phase difference (θ) between the signals, as shown in fig. 24 for signals 1902 and 1904.

If there is a phase difference θ (FIG. 24) between the reference signal and the measured signal, the value of the single lock reading depends on θ:

variations of M81100, 200 and 300 may account for this phase correlation by using demodulation phase shifts that match theta. The demodulation phase shift is performed as follows. First, two-phase measurements determine the amount of phase difference. The measured signal may be multiplied by both the reference and the 90 degree phase shifted reference. This results in-phase (I) and out-of-phase (Q) signal portions:

then, (1) and (2) may be used to calculate the amount of phase difference:

the phase difference calculated through (3) can be used as a demodulation phaseIs applied to the reference signal. This brings readings in phase and zeroes out the out-of-phase component:

variations of M81100, 200 and 300 may automatically calculate and apply the demodulation phase.

Fig. 25 shows how the head 102 can also use a Phase Locked Loop (PLL) 2500 to obtain the reference to be supplied to 2300. The PLL 2500 may be part of the digital signal processing unit 324.

A reference is selected (by a user or by an algorithm) from an external signal 2504, a power line frequency 2506, and/or one of the three measurement channel signals 2508 via a multiplexer 2502. In some variations, the user may bypass 2510 high pass filter 2512 to apply a low frequency signal. The user may choose to invert the input signal (180 ° offset).

In a variation of PLL 2500, one signal may be used to generate a reference at a given time. PLL 2500 can ensure that the frequency and phase of the reference match the frequency and phase of the input signal. Independent frequency (k) _f ) And a phase control loop (k) _p ) Changes in the input signal can be tracked. The high pass filter 2512 may enable locking to a reference square wave or AC signal +/-5V. Multiplexer 2502 may select one of the measurement channels as a reference.

Variations of M81100, 200 and 300 may utilize the reference output. An exemplary reference output 2600 is shown in fig. 26. The reference output 2600 may be implemented by the digital signal processing unit 324.

The user may select one of the output source reference 2602 or the PLL reference 2604 via the multiplexer 2608. A timer peripheral 2610 (e.g., triggered after a certain amount of time or clock period) or other timing device may generate a signal that is synchronized to a sampling clock (e.g., the shared synchronization clock 302 in fig. 3A). In some variations, the user may also choose to invert the signal via an optional inverter 2612. In a variant, one reference signal may be emitted at a time.

Variations of M81, 200 and 300 may utilize a measurement digital signal processor/process (DSP) implemented by digital signal processing unit 324. An exemplary variant 2700 is shown in fig. 27. For example, with respect to signal inputs, the a and B measurement channels may be read by two separate ADCs 2552 and 2554, respectively. The signals sent to the ADCs 2552 and 2554 may be interpolated for seamless range change, as described in detail above in the context of fig. 19-22C.

The larger of the two signal sums B may be sent to a PLL, such as PLL 2500 described in the context of fig. 25. Peak detection may be used to make automatic rangefinding decisions in a seamless rangefinding algorithm, such as algorithm 2200 described in fig. 22A and 22C and/or algorithm 2220 in fig. 22C. An optional/configurable digital filter 2756 may be applied to the measurements. In one variation, the filter is a cascaded biquad filter that may be configured for low pass, high pass, band pass, or notch filtering. In some variations, switches 2758 and 2760 may select their upper signals 2758a and 2760a, respectively, when making AC/DC measurements. This results in the measurement value being multiplied by itself in multiplier 2762 and by 1 (i.e., unchanged) in multiplier 2764. After averaging, top signal 2768 is the RMS measurement readings from a and B. The bottom signal 2770 is a DC reading. The peak detection 2766 may remain the same regardless of the type of measurement being made. The measurement value can be converted into an appropriate unit according to the type of the cartridge and its range.

With regard to variations of PLL 2500, the user can select which reference signal to use and can also set the demodulation harmonics and phase. Two waveforms may be generated from a reference. For example, as shown in FIG. 24, waveforms 1902 and 1904 are 90 ° out of phase. In a variation of the lock measurement, switches 2758 and 2760 select their lower signals, i.e., 2758b and 2760b. After averaging, the top signal 2768 is a Q (quadrature) indication and the bottom signal 2770 is an I (in-phase) indication (equations 2 and 1 above, respectively). The packet generator 2772 may synchronize the timestamp signals, synchronize via the shared synchronization clock 302, and buffer them to the rest of the header 102.

M81100, 200 and 300 System integration

As an integrated system, variations of M81, 200, and 300 may include cartridge mounts, such as mounts 2802 and 2804 shown in fig. 28A and 28B, respectively. Fig. 28A illustrates how mounts 2802 and 2804 may have two halves (e.g., halves 2802a and 2802 b) and fit together in a clamshell configuration. Other configurations are possible and within the context of the present invention. The mounts 2802 and 2804 may include a material for electrostatic shielding (e.g., plastic, resin, rubber, etc.). The mounts 2802 and 2804 may comprise a material for magnetic shielding, such as steel, mu metal, or other magnetic alloys. The cassettes 104 may be stacked together via housings 2802 and 2804 and rack mounted.

These mounts typically include a plurality of through connections, such as BNC connector 2806a in fig. 28B. Although only BNC connector 2806a is shown, it is understood that any number of suitable connectors may be used. Fig. 28B shows a plurality of additional through holes 2806B that can accommodate such connectors. The through hole 2806b may be occupied by a connector. They may also be empty and have a top cover to prevent internal exposure, as shown in fig. 28 b. Suitable connectors include coaxial cable types, triaxial types, etc. As shown in fig. 28B, mounts 2802 and 2804 may also include a sliding mount 2808 for mounting to a fixture, such as a rack or a segment of a sample stage (e.g., sample stage 106 in fig. 1). While a sliding mount 2808 is shown in the figures, it is understood that suitable mounting systems (e.g., bolts, snap fits, rails, screws, etc.) may be used. Fig. 28A and 28B also show feet (2802 c, 2802d, 2804c, and 2804 d) on which mounts 2802 and 2804 can stand.

Fig. 29A and 29B show details of the touch screen 102c in the source configuration (fig. 29A) and the measurement configuration (fig. 29B). It is to be understood that although the source configuration and the measurement configuration are shown in fig. 29A and 29B, respectively, they need not be separate. The source configuration and measurement configuration may be shown on the same screen 102c at the same time as each other, and also with other indicators, diagnostics, or information disclosed herein. As an example, the head 102 may include an oscilloscope function and display waveforms on the same screen 102c as the measurement display and source display of fig. 29A and 29B.

Since 102c is a touch screen, various elements on fig. 29A and 29B can be adjusted by touch input. For example, fig. 29A shows how source mode 2902 can be adjusted by touch (e.g., from I (current) to V (voltage)). Fig. 29A shows how all of the source range 2904, source level 2906, compliance limit 2908, sense line 2910, and measurement mode 2912 can be adjusted by touch. Fig. 29B shows how the measurement pattern 2914, the average time 2916, and the range 2918. In addition, the screen 102c may allow input of current and voltage (shown in fig. 29A and 29B). In general, any of the measurements and settings described herein may be viewed and configured via the front panel touch screen 102c, whether explicitly shown in fig. 29A and 29B or not.

While various inventive aspects, concepts and features of the inventions may be described and illustrated herein as embodied in combination in the exemplary embodiments, these various aspects, concepts and features may be used in many alternative embodiments, either individually or in various combinations and sub-combinations thereof. Unless expressly excluded herein all such combinations and sub-combinations are intended to be within the scope of the present inventions. Further, while various alternative embodiments as to the various aspects, concepts and features of the inventions-such as alternative materials, structures, configurations, methods, circuits, devices and components, software, hardware, control logic, alternatives as to form, fit and function, and so on-may be described herein, such descriptions are not intended to be a complete or exhaustive list of available alternative embodiments, whether presently known or later developed. Those skilled in the art may readily adopt one or more of the aspects, concepts or features of the invention into additional embodiments and uses within the scope of the present invention even if such embodiments are not expressly disclosed herein. Additionally, even though some features, concepts or aspects of the inventions may be described herein as being a preferred arrangement or method, such description is not intended to suggest that such feature is required or necessary unless expressly so stated. In addition, exemplary or representative values and ranges may be included to assist in understanding the present disclosure, however, such values and ranges are not to be construed in a limiting sense and are intended to be critical values or ranges only if so expressly stated. In addition, exemplary or representative values and ranges may be included to assist in understanding the present disclosure, however, such values and ranges are not to be construed in a limiting sense and are intended to be critical values or ranges only if so expressly stated. A parameter identified as "about" or "approximately" a specified value is intended to include both the specified value and values within 10% of the specified value, unless otherwise expressly specified. Further, it is to be understood that the drawings attached hereto may, but are not necessarily, to scale and thus may be understood as teaching the various ratios and proportions apparent in the drawings. Moreover, while various aspects, features and concepts may be expressly identified herein as being inventive or forming part of an invention, such identification is not intended to be exclusive, but rather there may be inventive aspects, concepts and features that are fully described herein without being expressly identified as such or as part of a specific invention, the inventions instead being set forth in the appended claims. Descriptions of exemplary methods or processes are not limited to inclusion of all steps as being required in all cases, nor is the order that the steps are presented to be construed as required or necessary unless expressly so stated.

Claims (22)

1. A measurement system, comprising:

a source unit configured to provide a source signal to a sample, the source unit comprising:

at least one of a voltage source and a current source; and

a memory configured to store a source calibration;

a measurement unit configured to acquire a measurement signal from the sample in response to the source signal, the measurement unit comprising:

at least one of a voltage measuring unit, a current measuring unit, and a capacitance measuring unit; and

a memory configured to store measurement calibrations; and

a control unit, the control unit comprising:

a digital signal processing unit;

a source converter connected between the digital signal processing unit and the source unit;

a measurement converter connected between the digital signal processing unit and the measurement unit;

a synchronization unit configured to synchronize clocks of the digital signal processing unit, the source converter, and the measurement converter;

a calibration unit for calibrating a system comprising a control unit; and

a reference voltage source configured to supply a common reference voltage to the control unit.

2. The system of claim 1, wherein the control unit is configured to obtain at least one of:

calibration data from a self-calibration performed by the source and the measurement unit;

calibration data from a stored factory calibration;

calibration data from a remote source via the internet;

calibration data from user input;

source calibration data from the source unit; and

measurement calibration data from the measurement unit.

3. The system according to any one of claims 1 and 2, wherein the control unit is configured to at least one of:

periodically obtaining the source calibration and the measurement calibration;

obtaining a source calibration from a memory of the source unit when the source unit is not providing the source signal to the sample;

obtaining a measurement calibration from the memory of the measurement unit when the measurement unit is not acquiring measurement signals from the sample; and

the source calibration and the measurement calibration are obtained simultaneously.

4. The system of any one of claims 1 to 3, wherein at least one of:

the digital signal processing unit stores calibration data of at least one of the control unit, the source unit, and the measurement unit;

the measurement unit and the source unit are remotely located relative to the control unit and the digital signal processing unit;

the system comprises a first cable connecting the control unit to the measurement unit and a second cable connecting the control unit to the source unit;

the digital signal in at least one of the measurement unit and the source unit is isolated from the control unit;

the measurement interface between the measurement unit and the control unit and the source interface between the source unit and the control unit are isolated from each other within the cable;

the system comprises a plurality of source units;

the system includes a plurality of measurement units;

the source unit is configured to acquire the measurement signal; and

the measurement unit is configured to provide the source signal.

5. The system of any of claims 1 to 4, wherein the current source unit is configured to measure a source current associated with the source signal via a sense resistance and to vary a resistance range of the sense resistance according to a magnitude of the source current.

6. The system of claim 5, further comprising at least one of:

a current source protection unit configured to determine whether the source current exceeds a threshold current and, when the source current exceeds the threshold current, to change a feedback element of at least one of the source unit and the measurement unit such that the source current falls below the threshold current; and

a voltage source protection unit configured to determine whether a source voltage exceeds a threshold voltage and, when the source voltage exceeds the threshold voltage, change a feedback element of at least one of the source unit and the measurement unit such that the source voltage falls below the threshold voltage.

7. The system of any one of claims 1 to 6, wherein the synchronization unit is configured to synchronize the digital signal processing unit, the source converter, and the measurement converter with respect to an internal clock signal.

8. The system of any one of claims 1 to 7, wherein the digital signal processing unit is configured to provide a time stamp to at least one of the measurement signal and the source signal.

9. The system of any one of claims 1 to 8, wherein at least one of:

the source unit is configured to disable non-analog circuitry when providing the source signal; and

the measurement unit is configured to deactivate non-analog circuitry when measuring the measurement signal.

10. The system of any one of claims 1 to 9, wherein the digital signal processing unit is configured to perform at least one of the following for at least one of the measurement signal and the source signal:

lock-in analysis;

alternating current/direct current measurements, i.e., AC/DC measurements;

measuring inductance L, capacitance C and resistance R, namely LCR measurement;

time/scope domain presentation;

analyzing a frequency domain;

analyzing noise;

an AC/DC source;

controlling circulation; and

a source signal from more than one source is provided.

11. The system of any one of claims 1 to 10, wherein at least one of the interfaces between the source unit and the control unit comprises a low impedance buffered analog signal, and the interface between the measurement unit and the control unit comprises at least one of:

a voltage mode analog signal interface having low impedance transmit and high impedance receive circuits; and

a current-mode analog signal interface with high output impedance transmit and low impedance receive circuits.

12. The system of any one of claims 1 to 11, wherein at least one of:

the power supply is configured to supply power to the control unit, the source unit, and the measurement unit with reference to a common ground;

the system includes a power filter to at least one of the measurement unit and the source unit; and

at least one of the measurement unit and the source unit is supplied with power by at least one of a power converter isolated from the control unit, an isolated external power source, and battery power.

13. The system of any one of claims 1 to 12, wherein at least one of the source converter and the measurement converter comprises:

a gain chain configured to amplify an analog input signal;

a range selector configured to select a gain between the analog input signal and a plurality of analog-to-digital converter (ADC) outputs, wherein each ADC output has a path and the gain of each output path consists of a gain stage in the gain chain; and

a mixer configured to combine the plurality of ADC outputs into a single mixed output.

14. The system of any of claims 1 to 13, wherein the source converter comprises:

two or more digital-to-analog converters (DACs) combined to generate one or more frequency components;

a first path for generating a substantially low frequency signal, the first path comprising a first one of the DACs;

a second path for generating a substantially high frequency signal, the second path comprising a second one of the DACs;

a data processor for processing an input signal;

a combining circuit configured to combine outputs of the first path and the second path into a source signal;

a feedback section configured to sense the source signal; and

a servo loop configured to employ the feedback section to hold the source signal substantially in accordance with the input signal.

15. The system of any one of claims 1 to 14, wherein the digital signal processing unit is configured to perform lock signal processing, and wherein the lock signal processing at least one of:

synchronizing with the synchronization unit;

processing at least one of a fundamental frequency and a harmonic frequency; and

including providing a lock reference for communication between the control unit and at least one of the source unit and the measurement unit.

16. The system of any one of claims 1 to 15, wherein the control unit is configured to measure a parameter of the source signal using a feedback signal that is one of a DC signal and a low frequency AC signal.

17. The system of any one of claims 1 to 16, wherein the control unit is configured to evaluate a type of at least one of the measurement unit and the source unit and configure the digital signal processing unit according to the type.

18. The system of any one of claims 1 to 17, further comprising at least one of:

a housing for at least one of the source unit and the measurement unit, the housing comprising at least one of an electrostatic shield and a magnetic shield; and

a configurable display configured to at least one of:

displaying the real-time oscilloscope readings; and

the spectrum reading is displayed.

19. The system of any one of claims 1 to 18, wherein the control unit is configured to perform at least one of a factory calibration and a self calibration by:

applying a signal to a more accurate resistance range;

measuring the applied signal over the more accurate range;

applying a signal to a less accurate resistance range;

measuring the applied signal over the less accurate range; and

calibrating the less accurate resistance range using the applied signal measured in the more accurate range and the applied signal measured in the less accurate range.

20. The system of any one of claims 1 to 19, wherein the control unit is configured to at least one of:

performing a voltage measurement mode calibration on the measurement cell by:

measuring an offset error at the measurement unit;

storing the offset error in the memory of the measurement unit;

connecting an amplifier associated with the measurement cell to a reference voltage;

measuring, via the control unit, a gain error from applying the reference voltage to the amplifier;

storing the measured gain error in the memory of the measurement unit;

reading, via the control unit, at least one of the stored gain errors from the memory of the measurement unit; and

applying at least one of the offset error and the gain error to correct a voltage measurement;

performing a current measurement mode calibration on the measurement unit by:

disconnecting the input connector of the control unit;

connecting the input connector of the measurement unit to ground;

configuring the measurement unit in a voltage measurement mode;

measuring a voltage offset error of an amplifier via the measurement unit in the voltage measurement mode;

applying an analog correction to reduce the measured voltage offset to approximately zero;

switching the measurement cell to a current measurement mode and floating an input to the measurement cell;

determining, via the control unit, a voltage offset error between the measurement unit and the control unit by configuring the measurement unit in a high current range and measuring the resulting voltage at the control unit;

adjusting the leakage current until the current measurement value of the measurement unit is approximately zero;

storing, via the control unit, the adjusted at least one of the leakage current and the voltage offset error in the memory of the measurement unit;

reading, via the control unit, the adjusted at least one of the leakage current and the voltage offset error; and

applying the adjusted at least one of the leakage current and the voltage offset error to correct a current measurement of the measurement cell.

21. The system of any one of claims 1 to 20, wherein the control unit is configured to:

calibrating the measurement channel against a master voltage reference;

instructing the source unit to apply a positive signal in place of a source signal;

measuring the positive signal of a command via the calibrated measurement channel to produce a measured positive signal;

instructing the source unit to apply a negative signal instead of the source signal;

measuring the applied negative signal via the calibrated measurement channel to produce a measured negative signal; and

instructing the source unit to apply a zero signal instead of the source signal;

measuring an applied null signal via the calibrated measurement channel to produce a measured null signal; and

generating a source unit calibration based on a difference between at least one of the commanded positive signal, the negative signal, and the null signal and the measured positive signal, the negative signal, and the null signal.

22. A method, comprising:

providing a source signal to a sample via a source unit, the source unit comprising:

at least one of a voltage source and a current source; and

a memory configured to store a source calibration;

obtaining a measurement signal from the sample in response to the source signal via a measurement unit comprising:

at least one of a voltage measuring unit, a current measuring unit, and a capacitance measuring unit;

a memory configured to store measurement calibrations; and

receiving, by a control unit, the measurement signal from the measurement unit, the control unit comprising:

a digital signal processing unit;

a source converter connected between the digital signal processing unit and the source unit;

a measurement converter connected between the digital signal processing unit and the measurement unit;

a synchronization unit configured to synchronize clocks of the digital signal processing unit, the source converter, and the measurement converter;

a calibration unit for calibrating an aspect of a system comprising the control unit; and

a reference voltage source configured to supply a common reference voltage for the control units.