HK40033951B - Configurable modal amplifier system - Google Patents

Description

Configurable Modal Amplifier System

Cross-reference to related applications

This patent application claims priority to U.S. Provisional Patent Application No. 62/608,465, filed December 20, 2017; and European Patent Application No. 18156223.2, filed February 12, 2018, each of which is incorporated herein by reference in its entirety.

Technical Field

This application relates to amplifiers. More specifically, embodiments of the invention relate to the modulation of power rails for linear amplifiers.

Background Technology

Various amplifier topologies can be used to amplify audio signals for driving monitors or speakers. Linear topologies (especially Class A topologies) are characterized by high fidelity (high-quality reproduction of the audio input signal). However, Class A amplifiers can be inefficient, especially at low signal levels. On the other hand, switching topologies (such as Class D topologies) can achieve high efficiency levels over a wide range of signal levels, but are generally characterized by lower fidelity sound reproduction.

Attempts to improve the efficiency of certain linear topologies (such as Class A, Class B, and Class AB) involve manipulating the track voltage between discrete (Class G) and continuous (Class H) levels based on the input signal level.

Attached Figure Description

Figure 1 is a block diagram of the amplifier system.

Figure 2 is a schematic diagram of the switching amplifier.

Figure 3 is a block diagram of a multi-channel amplifier system.

Figure 4 is a block diagram of the amplifier system.

Figure 5A is a schematic diagram of the bias control circuit.

Figure 5B is another schematic diagram of the bias control circuit.

Figure 6 is a simplified schematic diagram of the amplifier output stage used to demonstrate amplifier efficiency calculation.

Figure 7 is a graph comparing the amplifier efficiency of a Class A amplifier with the output signal level.

Figure 8 is a graph comparing the amplifier efficiency of a Class B amplifier with the output signal level.

Detailed Implementation

Reference will now be made in detail to specific embodiments. Examples of these embodiments are shown in the accompanying drawings. It should be noted that these examples are described for illustrative purposes and are not intended to limit the scope of this disclosure. Rather, alternatives, modifications, and equivalents of the described embodiments are included within the scope of this disclosure as defined by the appended claims. Specific details may be provided to facilitate a thorough understanding of the described embodiments. Some embodiments within the scope of this disclosure may be practiced without some or all of these details. Furthermore, well-known features may not have been described in detail for clarity.

This disclosure describes a configurable amplifier system in which the power rails of a linear amplifier (e.g., a Class A amplifier) are modulated by a switching amplifier (e.g., a Class D amplifier), which can also be configured to operate independently of the linear amplifier. Certain types of such amplifier systems are designed for amplifying audio signals. Systems implemented by this disclosure comprise configurable multi-channel systems, some of which can be configured to use switching amplifiers to drive loads, such as speakers, while other channels can be configured to use linear amplifiers to drive loads, the power rails of which are modulated by one or more switching amplifiers. This disclosure also describes various improvements that can enhance the efficiency of various amplifier operations.

Figure 1 is a block diagram of an example of a configurable amplifier system implemented according to a specific embodiment. The amplifier system 100 includes a linear amplifier 102 and switching amplifiers 104 and 106. The linear amplifier 102 (e.g., a Class A amplifier) is configured to amplify an input signal and drive a load (represented by speaker 108). The switching amplifiers 104 and 106 are dual-mode amplifiers that can be configured (via the depicted configuration/communication link) in a first mode (referred to herein as track modulation mode) to modulate the positive power rail V+ and negative power rail V- of the linear amplifier 102, respectively. In a second mode (referred to herein as signal amplification mode), the switching amplifiers 104 and 106 can each be configured to operate independently of the linear amplifier 102. For example, each switching amplifier can be configured to drive its own load, as shown by speakers 110 and 112 in dashed lines. In another example, the same load is driven in both modes; for example, when the switching amplifier is in signal amplification mode, speaker 108 is driven by the switching amplifier, and when the switching amplifier is in track modulation mode, speaker 108 is driven by the linear amplifier.

In one example, when the switching amplifier operates in track modulation mode, the input signal is amplified by a linear amplifier, where the power rails of the linear amplifier are modulated by the switching amplifier. In another example, when the switching amplifier operates in signal amplification mode, the input signal is amplified by the switching amplifier, and the linear amplifier is not used.

In track modulation mode, switching amplifier 104 receives the same digital audio input signal received by linear amplifier 102 and generates a positive track V+ through positive peak rectification. Switching amplifier 106 generates a negative track V- based on the same input signal through negative peak rectification. In this mode, both switching amplifiers are subjected to a non-zero DC bias at their outputs and may also have a minimum allowable voltage below which the corresponding track is not permitted to pass (in absolute terms). Thus, the power supply track for linear amplifier 102 tracks the input signal, providing sufficient power supply voltage to handle large transient signal levels with low clipping risk, while significantly reducing power consumption at low signal levels compared to a design with fixed tracks.

Linear amplifier 102 includes a delay circuit 114 (or preceding it) that delays the input signal before it is amplified by linear amplifier 102 to ensure proper synchronization with the modulation of the power supply track. The delay introduced by delay circuit 114 ensures that points in the input signal amplified by the output stage of linear amplifier 102 (after conversion by digital-to-analog (D/A) converter 116) are adequately aligned with corresponding points in the modulation track voltages V+ and V-. Because appropriate bias voltage levels are available, the appropriate delay ensures the desired efficiency gain while also reducing the likelihood of clipping events that may occur if the signal is not properly aligned. A signal indicating the amount of delay for synchronization with other audio channels or accompanying video can be provided from linear amplifier 102.

According to some embodiments, the delay represented by delay circuit 114 can be characterized at design time and is therefore fixed. Alternatively, the delay represented by delay circuit 114 can be programmable. This allows, for example, system designers and/or installers to test and set the optimal delay for a given system configuration. For example, during the setup of an audio system, the tone can be used as the input to a channel amplifier, and the delay can be adjusted until the amplified tone is correct. Embodiments that do not require delaying the input signal to a linear amplifier are envisioned. In such cases, delay circuit 114 can be configured or programmed to introduce a delay greater than or equal to zero. Alternatively, delay circuit 114 can have accompanying switching circuitry (not shown) that allows delay circuit 114 to be bypassed.

Additionally, an implementation scheme for a switching amplifier (not shown) for an independently programmable delay circuit is envisioned. This would provide additional flexibility in manipulating the relative delay between the two signal paths to ensure proper alignment between the track voltage and the amplified signal. In either of these cases, a signal indicating the current delay for synchronization with other audio channels or accompanying video could be provided from the linear amplifier 102 and/or the switching amplifier 104 (e.g., via their respective configuration/communication links). It is understood that the delay circuit may also need to be equipped with such other audio channels and/or accompanying video to support synchronization.

The start-up and decay times characterizing the operation of switching amplifiers 104 and 106 in track modulation mode can be varied depending on the implementation. In track modulation mode, the start-up time should be fast enough to ensure proper alignment of the track voltage and the amplified signal. On the other hand, it is desirable for the track voltage to move as slowly as possible to avoid unacceptable switching artifacts in the output of the linear amplifier.

There is greater flexibility in decay time, which can be slower but at the cost of efficiency. That is, if the signal level drops faster than the rail voltage can keep up, the rail voltage (and therefore the power dissipated) will be higher than required until the rail voltage catches up. Each system can be designed to achieve the desired balance between efficiency and fidelity. In addition, some implementations allow these parameters to be programmed by the system installer or end user.

In the example shown in Figure 1, linear amplifier 102 is a Class A amplifier, and its output stage is implemented by output transistors 118 and 120 in a push-pull configuration between positive and negative power supply rails. However, it should be noted that embodiments using other linear amplifier types and configurations are contemplated. For example, linear amplifier 102 could be implemented as a Class A, B, or AB amplifier. In another example, the output stage could be a single-ended configuration instead of a push-pull configuration. In yet another example, the output stage could be powered by a single power supply rail (positive or negative) with AC-coupled outputs referenced to ground. Therefore, the scope of this disclosure should not be limited to the specific amplifier configuration depicted.

In the example shown in Figure 1, the modulation scheme employed by switching amplifiers 104 and 106 results in the track voltage of the input signal being tracked in a continuous manner, similar to, for example, a Class H amplifier topology. Examples of Class H topologies are described in U.S. Patents 6,373,335, 6,166,605, 4,445,095, and 4,218,660, the entire disclosure of each of which is incorporated herein by reference for all purposes. However, it should be noted that embodiments employing other modulation schemes are conceivable. For example, the switching amplifier may use some form of stepped or quantized voltage track to drive the power rails of a linear amplifier to multiple discrete voltage levels. These discrete levels may be coarsely quantized, for example, like a Class G topology, an early example of which is the Hitachi Dynaharmony HMA 8300 high-power audio amplifier (1977). Alternatively, the discrete levels may be quantized more finely. Therefore, the scope of this disclosure should not be limited to a particular track modulation scheme.

As described above, the linear amplifier 102 can be a Class A amplifier, in which case the bias circuit 122 is configured to cause both output transistors to be on 100% of the time. In some embodiments, the stabilizing current or bias current of the output stage is fixed by the bias circuit 122 at approximately half of the expected peak current. Alternatively, and depending on the specific type of embodiment, the stabilizing current of the output stage set by the bias circuit 122 can also be modulated in response to an input signal, as represented by bias control blocks 124 and 126, which receive modulated rail voltages V+ and V- as inputs, respectively. This allows for an additional increase in power efficiency beyond that provided by the modulation of the power rails. Examples of embodiments of this bias control circuit are illustrated with reference to Figures 4 and 5.

Figure 2 is a block diagram of an example of a dual-mode switching amplifier 200 that can be used in some embodiments. The depicted amplifier topology has the same characteristics as some conventional Class D amplifiers. A digital input signal (e.g., an N-bit audio stream) is converted to the analog domain by a digital-to-analog (D/A) converter 202, the output of which is integrated by an integrator 204. A sync signal is injected into the output of the integrator 204 for comparison by a comparator 206. The output of the comparator 206 drives an output stage 208, which drives a load (not shown) via an output LC filter. Feedback is provided via one or more feedback elements 210 and 212, depicted in this example as having corresponding transfer functions _H1 and _H2 .

Amplifier 200 also includes loop configuration logic 214, which is configured to set or control various loop parameters and aspects of the operation of amplifier 200. Logic 214 may be programmable and may be implemented using any of a variety of programmable logic devices (e.g., field-programmable gate arrays or FPGAs), firmware-controlled devices, discrete circuits, and software. Logic 214 monitors aspects of loop operation (as shown by the dummy input lines), which may include, for example, digital input signals, the 1-bit output of comparator 206, the gate drive of the power transistors of output stage 208, the output signal after the LC filter, load characteristics, etc. Logic 214 uses these inputs to control aspects of loop operation (as shown by the dummy output lines), including, for example, synchronization control (via a synchronization signal), duty cycle monitoring and level control, dead-time timing, dynamic loop delay control (e.g., using a programmable delay line (not shown)), controlling the transfer characteristics of integrator 204, manipulating the transfer functions of feedback elements 210 and 212, etc.

Logic 214 can be configurable (e.g., via a configuration/communication link) to cause amplifier 200 to operate differently in different operating modes (e.g., track modulation mode and signal amplification mode as described herein). The way logic 214 uses its various inputs to control various aspects of loop operation can be optimized for the desired efficiency and fidelity associated with each mode. For example, at least some of the stringent requirements associated with high-fidelity amplification of the audio signal in signal amplification mode can be relaxed in track modulation mode to achieve further efficiency gains beyond those achieved by track modulation.

For example, Class D amplifiers are characterized by switching losses that are related to the switching frequency. Fidelity is also related to the switching frequency, meaning there is a trade-off between efficiency and fidelity. For track modulation mode, logic 214 can optimize the switching characteristics of switching amplifier 200 to achieve maximum power conversion rather than high fidelity. This may involve implementing so-called “soft switching”; selecting the optimal time to switch the power transistors of the output stage to minimize their switching losses. That is, in track modulation mode, the power transistors can be switched such that they transition at or near the “ideal” time in terms of the instantaneous voltage and current across each transistor, determined by monitoring the LC output filter. Other examples of loop operating parameters that can be optimized by logic 214 for a given operating mode include switching frequency (lower frequencies improve efficiency), start-up time, decay time, and soft switching (e.g., zero-voltage switching (ZVS) and zero-current switching (ZCS)).

In another instance, logic 214 can, for example, impose a non-zero DC bias on the modulator output in track modulation mode by switching appropriate signal processing within the amplifier signal chain (e.g., imposing a minimum duty cycle that generates a net DC output potential, or injecting a DC offset into the front end of the closed-loop servo system).

For example, the switching amplifier can be configured to have a lower switching frequency in track modulation mode than in signal amplification mode. In another example, alternatively or additionally, the switching amplifier can be configured to have a shorter decay time in track modulation mode than in signal amplification mode. In another example, alternatively or additionally, the switching amplifier can be configured to apply soft switching of its output stage to track modulation mode, but not to signal amplification mode. In another example, alternatively or additionally, the switching amplifier can be configured to impose a non-zero DC bias at its output stage in track modulation mode, but not in signal amplification mode.

The embodiments implemented in this disclosure include systems that provide only a single amplification channel, and systems that provide multiple channels and maintain at least some level of synchronization between the channels. Examples of such multi-channel systems include home and theater systems.

The technology used to create content for film involves mixing digital audio signals to produce digital audio tracks for playback in conjunction with the visual components of the entire film projection. Portions of the mixed audio signals are assigned to and played on a specific number of predetermined channels across all industry standards, for example, six in the case of Dolby Digital 5.1, eight in the case of Dolby Surround 7.1, and up to 64 in the case of Dolby Atmos.

Figure 3 illustrates an example (from a top view) of a cinematic environment 300 in which a particular implementation scheme can be practiced. A projector 302, a sound processor 304, and an audio power amplifier assembly 306 work together to provide video and audio components for a cinematic projection, wherein the power amplifier 306 drives loudspeakers and subwoofers deployed around the environment (connections not shown for clarity). The sound processor 304 can be any of a variety of computing devices or sound processors, including, for example, one or more personal computers or one or more servers, or one or more cinema processors, such as the Dolby Atmos Cinema Processor CP850 from Dolby Laboratories, Inc. Interaction between the sound engineer and the sound processor 304 can be accomplished via, for example, a browser-based HTML connection through a laptop computer 308, tablet computer, smartphone, etc. Audio measurements and sound processing will typically be performed using the sound processor, which includes analog or digital inputs to receive microphone feeds and outputs to the power amplifiers driving the loudspeakers.

The depicted environment can be configured via sound processor 304 and amplifier configuration interface 310 to play audio tracks with different numbers of audio channels (e.g., 6, 8, 10, 14, etc.), where different subsets of amplifiers and speakers correspond to different channels. Configuration interface 310 (with inputs, for example, from laptop computer 308) and appropriate interconnect cabling (not shown for clarity) can configure subsets of power amplifier 306 to drive each subset or array of speakers with audio for the corresponding channel according to any of a variety of digital audio formats (e.g., Dolby 5.1, 7.1, or Atmos).

Power amplifier 306 includes a switching amplifier 312 and a linear amplifier 314. The switching amplifier 312 may be implemented in a separate chassis and housing (e.g., for rack mounting) or contained within a single chassis and housing (as shown in dashed box 316). Each linear amplifier 314 may have its own chassis and housing (as shown in dashed box 318). Such a configuration allows, for example, existing amplifier products to be modified to provide track modulation to an external linear amplifier. Alternatively, each linear amplifier 314 may be integrated with a corresponding loudspeaker in the cinema environment 300, represented by shadow blocks distributed throughout the environment. As another alternative, each linear amplifier 314 may be integrated with one or more switching amplifiers 312. Other suitable variations of this subject matter will be apparent to those skilled in the art.

With appropriate interconnect cable wiring and configuration via interface 310, one or more switching amplifiers 312 can be configured as the power supply track for one of the modulation linear amplifiers 314, which themselves can be configured to drive one of the speakers in the cinema environment 300, such as one of the screen monitors 320. Since these monitors tend to dominate the sound experience in such an environment, the selection of a linear amplifier for higher fidelity sound reproduction can be guaranteed at the expense of power efficiency.

This configuration can include a switching amplifier (operating in track modulation mode) modulating the positive power rail of the linear amplifier and another switching amplifier (also operating in track modulation mode) modulating the negative rail, as described, for example, with reference to Figure 1. For example, as described with reference to Figure 2, the configuration of each switching amplifier operating in the optimized track modulation mode can be achieved through a configuration interface 310 and a configuration/communication link associated with each amplifier.

Compared to screen monitor channels, surround channels, such as those represented by top (322), left (324), right (326), and rear (328) monitors or subwoofers (330), can guarantee different balances between power efficiency and fidelity, resulting in the use of switching amplifiers 312 to directly drive the respective monitors. For example, as described with reference to Figure 2, each switching amplifier 312 can be configured to operate in an optimized signal amplification mode via a configuration interface 310 and a configuration/communication link associated with each amplifier. As will be understood, the implementation scheme that optimizes the operation of each switching amplifier for each of the different operating modes of each switching amplifier provides considerable flexibility when configuring a multi-channel amplifier system, such as that shown in Figure 3.

According to various embodiments, the system shown in Figure 3 can be configured such that one or more speakers correspond to specific audio channels. Furthermore, amplifiers 306 can be combined in various ways (via appropriate interconnect cable wiring and configuration interface 310) to support specific audio channels. For example, when operating in signal amplification mode, switching amplifiers 312 can each be configured to amplify the audio signal of the corresponding channel. Alternatively, switching amplifiers 312 can be configured to operate in a parallel, half-bridge, or full-bridge configuration for a given audio channel. Similarly, linear amplifiers 314 (having power tracks modulated by one or more switching amplifiers 312) can be configured to operate in a parallel, half-bridge, or full-bridge configuration for a given audio channel. Additionally, switching amplifiers 312 can be configured to operate in a parallel, half-bridge, or full-bridge configuration in track modulation mode to modulate one track of one of the linear amplifiers 314. This configuration, for example, can provide greater power handling flexibility or higher efficiency operation.

Various embodiments implemented by this disclosure allow designers and/or system installers to achieve an appropriate balance between amplifier distortion and power efficiency for a particular application. In the case of audio amplification, a linear output stage is used to achieve a balance that favors higher fidelity sound reproduction. However, even with the best linear amplifier fidelity, other factors in the system can still be sources of undesirable artifacts. For example, the transducers in a monitor driven by an audio amplifier are mechanical systems made of paper, rubber, plastic, polyimide (kapton), aluminum, and various other materials, each with its own resonance and the potential to produce undesirable artifacts. Furthermore, the generation of such artifacts is generally more pronounced at higher power levels.

According to a particular embodiment, a linear amplifier (e.g., amplifier 102 of FIG. 1 or amplifier 314 of FIG. 3) may have an associated feedback terminal for receiving transducer feedback, such that undesirable artifacts from such a transducer can be reduced as part of the linearization of the entire system loop comprising the amplifier and the loudspeaker. As those skilled in the art will appreciate, there are various ways in which such transducer feedback can be introduced. For example, according to some embodiments, feedback can be introduced using a nested loop local to the output stage. Such transducer feedback can be obtained via any of a variety of mechanical, electrical, acoustic, or other mechanisms. Examples include a separate winding adjacent to the voice coil, a capacitor or other transducer tracking the movement of the loudspeaker cone, a pressure sensor on a diaphragm adjacent to the cone, etc.

Implementations that integrate the switching amplifier and the linear amplifier with separate racks offer the opportunity to place the linear amplifier near the speaker it is driving. That is, if the linear amplifier housing is separate from the switching amplifier that modulates its power rails, the linear amplifier housing can be placed much closer, even adjacent, to the speaker it is driving. Therefore, the transducer feedback terminals on the exterior of its housing can be connected to the transducer feedback mechanism associated with the speaker via a very short cable. This can be advantageous in applications such as those in cinema environments, as shown in Figure 3, where there may be tens (or even hundreds) feet of cable between the equipment rack and some speakers. Proximity means a shorter loop to be linearized, and therefore better performance. It is also impossible for the speaker to contain active electronics to power any transducer feedback sensor or send transducer feedback over any effective distance.

According to some implementations, the linear amplifier can be implemented in the same housing as the loudspeaker; that is, the motorized loudspeaker being powered by an externally switched amplifier. This eliminates the need to bring the transducer feedback terminals of the loudspeaker and the linear amplifier outside the housing, thereby allowing for a wider variety of methods to use feedback and potentially improving the linearization of transducer artifacts.

Figure 4 illustrates an example of an embodiment of amplifier 400, in which the supply rail voltage and bias current of the output stage are modulated. As described above, modulating the rail voltage results in a supply voltage just large enough to support the swing of the amplified signal. Modulation of the stabilizing current of the output stage further reduces power loss.

In the example shown in Figure 4, the output stage of amplifier 400 is implemented using output transistors 418 and 420 in a push-pull configuration between the positive power rail V+ and the negative power rail V-, and is configured for Class A operation in driving load 408. However, it should be noted that embodiments with other configurations and biasing schemes are contemplated. For example, the output stage of amplifier 400 may be configured for Class A, B, or AB operation. In another example, the output stage may be a single-ended configuration instead of a push-pull configuration. In yet another example, the output stage may be powered by a single power rail (positive or negative) referenced to ground. Therefore, the scope of this disclosure should not be limited to the specific amplifier configuration depicted.

Amplifier 400 includes rail modulation circuits 404 and 406, which can be configured to modulate their respective power rails according to any of a variety of modulation schemes. For example, a suitable rail modulation scheme may result in the rail voltages tracking the input signal in a continuous manner, similar to, for example, a Class H amplifier topology. In another instance, the rail modulation circuitry may use some form of quantization circuitry to drive the power rails of the linear output stage to multiple discrete voltage levels. These discrete levels, or stepped rails, may be coarsely quantized, as in, for example, a Class G topology, or more finely quantized. Therefore, the scope of this disclosure should not be limited to a particular rail modulation scheme.

Depending on a specific subset of the implementation, track modulation circuits 404 and 406 can be implemented using switched amplifiers (e.g., Class D amplifiers). These amplifiers can be configurable, as described elsewhere herein, but can also be specifically built for track modulation. Alternatively, the track modulation circuitry can be any of a variety of conventional circuits used to modulate the tracks of a linear amplifier. Amplifier 400 may include a delay circuit 414 (or preceding it) that delays the input signal before it is amplified by the linear output stage to ensure proper synchronization with the modulation of the powered tracks.

Depending on a specific subset of the implementation, the output stage bias current comprises a static component and a dynamic component. The static component is set based on the minimum load amplifier 400 to be driven. For example, if amplifier 400 is an audio amplifier, it is expected to drive a speaker load of 2 to 8 ohms. If it is known that amplifier 400 will not see loads below 8 ohms, the static component of the bias current can be set to support a maximum bias current based on 8 ohms, rather than the much higher maximum value required to drive 2 ohms. The dynamic component of the output stage bias current can be based on a modulated power rail, thereby modulating a steady current near the level corresponding to the static component. Alternatively, the dynamic component of the output stage bias current can be based on a feedforward signal corresponding to or based on the input signal (as shown by the dashed line). Furthermore, both the static and dynamic components controlling the output stage bias current can be configurable, allowing one or both to be turned on or off during setup time.

A specific embodiment of the bias circuit 422 is shown in Figure 5A. In the depicted embodiment, R4 represents the speaker load (8 ohms in this example), and Q1, Q2, and Q3 form a triple Darlington (e.g., replacing the output transistor 418 of Figure 4), where Q3 is the output device that supplies current to the load on the positive cycle. Q4, Q5, and Q6 form another triple Darlington (e.g., replacing the output transistor 420 of Figure 4), where Q4 is the output device that draws current from the load on the negative cycle. V1 and V2 are the positive and negative power supply rails for the output stage, which can be, for example, modulation rails from a Class D stage in the modulator mode described above (e.g., V+ and V- of Figure 4). R1 and R2, combined with the bias setting network, determine the bias current in the output stage. The voltage across R3 modulates the voltage across resistors R1 and R2. This, in turn, modulates the bias current in the output stage. Diodes D1-D6 are designed to offset the _VBE voltage drop of the output devices Q1-Q6.

The active component within the dashed box contains the current source that allows R3 to float relative to circuit ground. When the positive and negative rails of the output stage are modulated, the current through the branch formed by Q8, Q10, and R5 determines the current reflected through the current mirrors (to Q7, Q9 and Q11, Q12). This is then converted into a voltage across R3. Because R3 is in parallel with R1 and R2, the same voltage modulates the output stage bias current. Note that the circuit shown in Figure 5A can be designed to operate in Class A, Class B, or Class A/B.

When switch S1 is closed, the static control of the bias current is set by R5 connected in parallel with R7. Multiple switches and resistors can be used to support multiple load impedances (e.g., 2, 4, 8 ohms, etc.). Given the amplifier's maximum output power and the impedance of the loads connected to it, the output bias can be selected to avoid wasting excessive energy. The dynamic control of the bias current is set by the gain through the current mirror and the design of the current source, the gain being a factor of R5 (and R7).

Figure 5B shows a modified version of the circuit in Figure 5A, where (optionally) operational amplifiers U1 and U2 are used as buffers to ensure that the output stage is not loaded with a modulated bias voltage. These may not be necessary for some implementations. In some implementations, U1 and U2 can be replaced with simpler circuitry, such as emitter followers.

Figure 6 is the circuit diagram that forms the basis for the following amplifier output stage efficiency calculations. V2 and V3 are the positive and negative voltage rails, respectively, and are typically equal in magnitude but opposite in sign. Q1 and Q2 are the output stage devices used to transfer power from the power supply (V2, V3) to the load R3 (also called RL). In the following example: V2 = -V3 = 30V; and RL = 8 ohms. The combination of V1, R1, and R2 determines the bias current of the output stage. V1 determines the operating class of the output stage. V4 is the AC input signal source. For the calculations below, efficiency is determined by the ratio of the RMS power consumed by the load to the average power delivered by the power supply (which comprises two rails for a bipolar design).

Definition of efficiency:

The following calculations are for the conventional static (unmodulated) track case (Class A and Class B) using the push-pull output stage for sine waves as shown in Figure 6. These calculations provide the basis for the modulated track case and will show that the maximum efficiency achievable with the static track at maximum output voltage is true for all signal levels in the modulated case.

Calculation of Class A push-pull efficiency of _VOUT = VCC

Power supply voltage rail

V_{_CC} = 30V

_VCC = _-VEE

Peak output voltage of the load

V _{o_pk} = V _CC

(Maximum efficiency is set to equal the rail voltage)

Load impedance

R _L = 8Ω

Average current drawn from the power source

Power supplied by the power source (the modified subscript "A" indicates Class A operation):

_PSA = _VCC · _ICC = 112.5W

RMS-Crest Factor (Crest Factor) of a normal signal: Square wave = 1 (see, for example, the Wikipedia entries on Crest Factor https://en.wikipedia.org/wiki/Crest_factor and Root Mean Square https://en.wikipedia.org/wiki/Root_mean_square).

RMS power delivered to the load (modified subscript "A" indicates Class A operation):

Class A maximum efficiency

Note that efficiency increases with increasing RMS-peak ratio. Figure 7 is a graph showing the efficiency of the Class A output stage as a function of the output levels for triangular, sine, and square waves.

_VOUT = VCC's Class B push-pull efficiency calculation (assuming the following variables are the same as those in the Class A instance above).

Power supply voltage rail

V_{_CC} = 30V

_VCC = _-VEE

Peak output voltage of the load

V _{o_pk} = V _CC

(Maximum efficiency is set to equal the rail voltage)

Load impedance

R _L = 8Ω

When Vout,pk = Vcc: Average-to-peak ratio of ordinary signals: Triangular wave = 0.5; Sine wave = 2/π; Square wave = 1

Average current drawn from the power source

Power supplied by the power source (the modified subscript "B" indicates a Class B operation):

RMS power delivered to the load (the modified subscript "B" indicates a Class B operation)

Class B maximum efficiency

Note again that efficiency increases with increasing RMS-peak ratio and average-peak ratio. Figure 8 is a graph showing the efficiency of the Class B output stage as a function of the output levels for triangular, sine, and square waves.

Regarding the power supply current during Class A operation, the current drawn from the power supply is constant and determined by a bias network designed to account for the expected worst-case load. The output device controls the current required by the load based on the input signal. However, the power supply has a constant current. In Class B operation, the power supply primarily has load current flowing through the power supply filter capacitor.

The above analysis of the static voltage rail conditions for Class A and Class B output stages reveals two important points. First, efficiency is a function of the output signal level, and efficiency is maximized when the output level equals the rail voltage (Vcc, Vee). Second, efficiency is proportional to the RMS-peak ratio (inverse peak factor) of the amplified signal (e.g., square wave = 1; pink noise ~4 (or higher, depending on the distribution).

In theory, regardless of the input signal level, the modulation path strives to achieve maximum efficiency for all time allowed by these linear push-pull topologies. Further losses then depend on the signal crest factor (e.g., see the "k" factor shown in the calculation above).

For example, to understand this improvement, if the input signal RMS level is 10% of 90% of the track voltage all the time, the overall efficiency will not exceed 10%. However, if the track voltage is modulated, then the peak level of the signal is almost equal to the track voltage for 100% of the time. The resulting efficiency will then depend on the crest factor of the input signal. Since audio typically has a crest factor of 3dB or greater, this means that when biased for Class A operation, the efficiency for all signal levels will approach 50%.

Furthermore, and as described elsewhere in this document, further efficiency improvements can be achieved by modifying the bias current in one or both of the following ways: (1) by adjusting the static bias current based on a known load impedance; and/or (2) by modulating the bias current based on rail modulation. Higher efficiency can be obtained depending on the precision of the bias current modulation and the lower limit that allows the modulated voltage rail to keep the output device on.

The implementation schemes disclosed in this document include the following:

Implementation 1 is an amplifier system including a linear amplifier. The linear amplifier has power rails. The amplifier system further includes a first switching amplifier. The first switching amplifier is configurable to modulate the power rails of the linear amplifier based on the input signal of the linear amplifier in a first mode. The first switching amplifier is configurable to operate independently of the linear amplifier in a second mode.

Implementation scheme 2 is the amplifier system of implementation scheme 1, wherein the first switching amplifier is a Class D amplifier.

Implementation scheme 3 is an amplifier system of implementation scheme 1 or 2, wherein the linear amplifier is a Class A amplifier, a Class B amplifier, or a Class AB amplifier.

Implementation scheme 4 is an amplifier system of any one of implementation schemes 1 to 3, wherein the first switching amplifier is configured to operate with a first average power efficiency in a first mode and with a second average power efficiency lower than the first average power efficiency in a second mode.

Implementation scheme 5 is an amplifier system of any one of implementation schemes 1 to 4, wherein the first switching amplifier is configured to operate at a first switching frequency in a first mode and at a second switching frequency higher than the first switching frequency in a second mode.

Implementation scheme 6 is an amplifier system of any one of implementation schemes 1 to 5, wherein the first switching amplifier is configured to operate at a first distortion level in a first mode and at a second distortion level lower than the first distortion level in a second mode.

Implementation scheme 7 is an amplifier system of any one of implementation schemes 1 to 6, wherein the first mode of the first switching amplifier is characterized by soft switching of the output stage of the first switching amplifier.

Implementation scheme 8 is an amplifier system of any one of implementation schemes 1 to 7, wherein the first mode of the first switching amplifier is characterized by imposing a non-zero DC bias at the output of the first switching amplifier.

Implementation scheme 9 is an amplifier system of any one of implementation schemes 1 to 8, further comprising a first delay circuit configured to delay the input signal before it is amplified by the linear amplifier.

Implementation 10 is an amplifier system of Implementation 9, wherein the first delay circuit is programmable to introduce a delay greater than or equal to zero, or wherein the first delay circuit is configurable to be bypassed.

Implementation 11 is an amplifier system of implementation 9 or 10, which further includes a second delay circuit configured to delay the input signal before it is amplified by the first switching amplifier, wherein both the first delay circuit and the second delay circuit are independently programmable.

Implementation scheme 12 is an amplifier system of any of implementation schemes 1 to 11, further comprising a first chassis and a second chassis, a linear amplifier integrated with the first chassis, and a first switching amplifier integrated with the second chassis.

Implementation 13 is an amplifier system of implementation 12, which further includes one or more sensing terminals integrated with a first chassis and configured to provide feedback to the linear amplifier from a load driven by the linear amplifier.

Implementation scheme 14 is an amplifier system of implementation scheme 12, wherein the load driven by the linear amplifier is integrated with the first base frame.

Implementation 15 is an amplifier system of any one of Implementations 1 to 14, further comprising a bias modulation circuit configured to modulate the steady current of the linear amplifier based on the input signal to the linear amplifier or based on the modulation of the power rail.

Implementation 16 is an amplifier system of Implementation 15, wherein the bias modulation circuitry can be configured to modulate the steady current of the linear amplifier based on a specified load impedance.

Implementation 17 is an amplifier system of any one of Implementations 1 to 16, wherein the power rail is a positive power rail and the linear amplifier also has a negative power rail, the amplifier system further comprising a second switching amplifier configured to modulate the negative power rail of the linear amplifier based on the input signal to the linear amplifier in a first mode, the second switching amplifier being configured to operate independently of the linear amplifier in a second mode.

Implementation scheme 18 is an amplifier system of any of implementation schemes 1 to 17, wherein the first switching amplifier is configured to modulate the power rails of the linear amplifier in a generally continuous manner.

Implementation 19 is an amplifier system of any one of Implementations 1 to 17, wherein a first switching amplifier is configured to drive the power rails of a linear amplifier to multiple discrete voltages.

Implementation 20 is an amplifier system comprising multiple linear amplifiers. Each linear amplifier has one or more power rails. The amplifier system further comprises multiple switching amplifiers. Each switching amplifier is configured to modulate one of the power rails of one of the corresponding linear amplifiers based on an input signal to the corresponding linear amplifier in a first mode. Each switching amplifier is configured to operate independently of the linear amplifiers and other switching amplifiers in a second mode. A control interface is configured to enable the amplifier system to be configured as multiple channels. Each of a first subset of channels includes one of the switching amplifiers configured to operate in the second mode. Each of a second subset of channels includes one of the linear amplifiers and one or more of the switching amplifiers configured to operate in the first mode.

Implementation scheme 21 is the amplifier system of implementation scheme 20, wherein the linear amplifier is a Class A amplifier, a Class B amplifier, or a Class AB amplifier, and the switching amplifier is a Class D amplifier.

Implementation scheme 22 is an amplifier system of implementation scheme 20 or 21, wherein each switching amplifier can be configured via a control interface to operate in a first mode with a first average power efficiency and a first distortion level, and in a second mode with a second average power efficiency and a second distortion level, wherein the first average power efficiency is higher than the second average power efficiency and the first distortion level is higher than the second distortion level.

Implementation scheme 23 is an amplifier system of any one of implementation schemes 20 to 22, wherein the first mode of each switching amplifier is characterized by soft switching of the output stage of the switching amplifier.

Implementation scheme 24 is an amplifier system of any of implementation schemes 20 to 23, wherein the first mode of each switching amplifier is characterized by imposing a non-zero DC bias at the output of the switching amplifier.

Implementation 25 is an amplifier system of any of Implementations 20 to 24, which further includes a delay circuit associated with each linear amplifier, the delay circuit being configured to delay the corresponding input signal.

Implementation 26 is an amplifier system of implementation 25, wherein the delay circuit can be programmed via a control interface to introduce a delay greater than or equal to zero, or wherein the delay circuit can be configured via a control interface to be bypassed.

Implementation scheme 27 is an amplifier system of any of Implementation schemes 20 to 26, which further includes multiple chassis, each linear amplifier being integrated with a corresponding chassis, and all switching amplifiers being integrated with a chassis.

Implementation 28 is an amplifier system of implementation 27, wherein each chassis integrated with a corresponding linear amplifier includes one or more sensing terminals configured to provide feedback from a load driven by the linear amplifier to the corresponding linear amplifier.

Implementation scheme 29 is an amplifier system of any of Implementation schemes 20 to 28, wherein the control interface is configured such that the two channels of the amplifier system can operate in parallel, in half-bridge mode or in full-bridge mode.

Implementation scheme 30 is an amplifier system of any of implementation schemes 20 to 29, wherein the control interface is configured such that a configuration of two or more switching amplifiers can modulate one of the power rails of one of the linear amplifiers, the two or more switching amplifiers being connected in parallel, in a half-bridge configuration or a full-bridge configuration.

Embodiment 31 is an amplifier system including a linear amplifier. The linear amplifier has a power rail. The amplifier system further includes a first rail modulation circuit configured to modulate the power rail of the linear amplifier based on an input signal to the linear amplifier. The amplifier system further includes a bias modulation circuit configured to modulate a steady current of the linear amplifier based on the input signal to the linear amplifier or based on the modulation of the power rail.

Implementation scheme 32 is an amplifier system of implementation scheme 31, wherein the bias modulation circuitry can be configured to modulate the steady current of the linear amplifier based on a specified load impedance.

Implementation scheme 33 is an amplifier system of implementation scheme 31 or 32, wherein the first track modulation circuit is configured to modulate the power rails of the linear amplifier in a generally continuous manner.

Implementation scheme 34 is an amplifier system of implementation scheme 31 or 32, wherein a first track modulation circuit is configured to drive the power rails of the linear amplifier to multiple discrete voltages.

Implementation scheme 35 is the amplifier system of implementation schemes 31 to 34, wherein the first track modulation circuit is a switching amplifier.

Implementation scheme 36 is the amplifier system of implementation scheme 35, wherein the linear amplifier is a Class A amplifier, a Class B amplifier, or a Class AB amplifier, and the switching amplifier is a Class D amplifier.

Implementation 37 is an amplifier system of implementation 35 or 36, wherein the switching amplifier is configurable to modulate the power rails of the linear amplifier based on the input signal in a first mode, and is configurable to operate independently of the linear amplifier in a second mode.

Implementation scheme 38 is an amplifier system of implementation scheme 37, wherein the switching amplifier is configured to operate with a first average power efficiency in a first mode and with a second average power efficiency lower than the first average power efficiency in a second mode.

Implementation scheme 39 is an amplifier system of implementation scheme 37 or 38, wherein the switching amplifier is configured to operate at a first switching frequency in a first mode and at a second switching frequency higher than the first switching frequency in a second mode.

Implementation scheme 40 is an amplifier system of any of implementation schemes 37 to 39, wherein the switching amplifier is configured to operate at a first distortion level in a first mode and at a second distortion level below the first distortion level in a second mode.

Implementation scheme 41 is an amplifier system of any one of implementation schemes 37 to 40, wherein the first mode of switching amplifier is characterized by soft switching of the output stage of switching amplifier.

Implementation scheme 42 is an amplifier system of any of Implementation schemes 37 to 41, wherein the first mode of the switching amplifier is characterized by applying a positive DC bias at the output of the switching amplifier.

Implementation scheme 43 is an amplifier system of any of implementation schemes 31 to 42, which further includes a first delay circuit configured to delay the input signal before it is amplified by the linear amplifier.

Implementation scheme 44 is an amplifier system of implementation scheme 43, wherein the first delay circuit is programmable to introduce a delay greater than or equal to zero, or wherein the first delay circuit is configurable to be bypassed.

Implementation 45 is an amplifier system of implementation 43 or 44, further comprising a second delay circuit configured to delay the input signal before the input signal is used by the first track modulation circuit to modulate the power rail of the linear amplifier, wherein the first delay circuit and the second delay circuit are independently programmable.

Implementation scheme 46 is an amplifier system of any one of implementation schemes 31 to 45, further comprising a first chassis and a second chassis, a linear amplifier integrated with the first chassis, and a first track modulation circuit integrated with the second chassis.

Implementation 47 is an amplifier system of implementation 46, which further includes one or more sensing terminals integrated with a first base and configured to provide feedback to the linear amplifier from a load driven by the linear amplifier.

Implementation scheme 48 is an amplifier system of implementation scheme 46, wherein the load driven by the linear amplifier is integrated with the first base frame.

Implementation scheme 49 is an amplifier system of any one of implementation schemes 31 to 48, wherein the power rail is a positive power rail and the linear amplifier also has a negative power rail, the amplifier system further includes a second rail modulation circuit configured to modulate the negative power rail of the linear amplifier based on the input signal to the linear amplifier, and wherein a bias modulation circuit is configured to modulate the steady current of the linear amplifier based on the modulation of the positive power rail and the negative power rail.

Implementation 50 is an amplifier system including a first amplifier. The first amplifier is a linear amplifier with power rails. The amplifier system further includes a second amplifier. The second amplifier is configured to modulate the power rails of the first amplifier based on an input signal to the first amplifier in a first mode. The second amplifier is configured to operate independently of the first amplifier in a second mode.

Implementation scheme 51 is the amplifier system of implementation scheme 50, wherein the second amplifier is a switching amplifier.

Implementation scheme 52 is an amplifier system of implementation scheme 50 or 51, wherein the first amplifier is a Class A amplifier, a Class B amplifier, or a Class AB amplifier.

Implementation scheme 53 is an amplifier system of any one of implementation schemes 50 to 52, wherein the second amplifier is configured to operate with a first average power efficiency in a first mode and with a second average power efficiency lower than the first average power efficiency in a second mode.

Implementation 54 is an amplifier system of any one of Implementations 50 to 53, wherein the second amplifier is a switching amplifier and is configured to operate at a first switching frequency in a first mode and at a second switching frequency higher than the first switching frequency in a second mode.

Implementation scheme 55 is an amplifier system of any one of implementation schemes 50 to 54, wherein the second amplifier is configured to operate at a first distortion level in a first mode and at a second distortion level below the first distortion level in a second mode.

Implementation scheme 56 is an amplifier system of any one of implementation schemes 50 to 55, wherein the second amplifier is a switching amplifier, and the first mode is characterized by soft switching of the output stage of the switching amplifier.

Implementation scheme 57 is an amplifier system of any one of implementation schemes 50 to 56, wherein the second amplifier is a switching amplifier, and the first mode is characterized by imposing a non-zero DC bias at the output of the switching amplifier.

Implementation 58 is an amplifier system of any of Implementations 50 to 57, further comprising a first delay circuit configured to delay the input signal before it is amplified by the first amplifier.

Implementation scheme 59 is an amplifier system of implementation scheme 58, wherein the first delay circuit is programmable to introduce a delay greater than or equal to zero, or wherein the first delay circuit is configurable to be bypassed.

Implementation 60 is an amplifier system of implementation 58 or 59, which further includes a second delay circuit configured to delay the input signal before it is amplified by the second amplifier, wherein both the first delay circuit and the second delay circuit are independently programmable.

Implementation scheme 61 is an amplifier system of any of implementation schemes 50 to 60, further comprising a first base and a second base, wherein the first amplifier is integrated with the first base and the second amplifier is integrated with the second base.

Implementation 62 is an amplifier system of implementation 61, which further includes one or more sensing terminals integrated with a first chassis and configured to provide feedback to the first amplifier from a load driven by the first amplifier.

Implementation scheme 63 is an amplifier system of implementation scheme 61, wherein the load driven by the first amplifier is integrated with the first base frame.

Implementation 64 is an amplifier system of any of Implementations 50 to 63, further comprising a bias modulation circuit configured to modulate the stable current of the first amplifier based on the input signal to the first amplifier or based on the modulation of the power rail.

Implementation scheme 65 is an amplifier system of implementation scheme 64, wherein the bias modulation circuitry can be configured to modulate the steady current of the first amplifier based on a specified load impedance.

Implementation 66 is an amplifier system of any of Implementations 50 to 65, wherein the power rail is a positive power rail and the first amplifier also has a negative power rail, the amplifier system further comprising a third amplifier configured to modulate the negative power rail of the first amplifier based on the input signal to the first amplifier in a first mode, and the third amplifier configured to operate independently of the first amplifier in a second mode.

Implementation scheme 67 is an amplifier system of any of implementation schemes 50 to 66, wherein the second amplifier is configured to modulate the power rails of the first amplifier in a generally continuous manner.

Implementation 68 is an amplifier system of any of Implementations 50 to 66, wherein the second amplifier is configured to drive the power rails of the first amplifier to multiple discrete voltages.

Those skilled in the art will understand that changes may be made to the form and details of the embodiments described herein without departing from the scope of this disclosure. Furthermore, although various advantages, aspects, and objectives have been described with reference to various embodiments, the scope of this disclosure should not be limited to reference to such advantages, aspects, and objectives. Rather, the scope of this disclosure should be determined by reference to the appended claims.

Claims (19)

1. An amplifier system comprising: A linear amplifier for amplifying an input signal, the linear amplifier having power rails; and A first switching amplifier is configured to modulate the power rail of the linear amplifier based on the input signal to the linear amplifier in a first mode, and the first switching amplifier is configured to amplify the signal in a second mode, wherein the first switching amplifier is configured to modulate the power rail of the linear amplifier only in its first mode. 2. The amplifier system according to claim 1, wherein the first switching amplifier is a Class D amplifier. 3. The amplifier system according to claim 1 or claim 2, wherein the linear amplifier is a Class A amplifier, a Class B amplifier, or a Class AB amplifier. 4. The amplifier system of claim 1 or claim 2, wherein the first switching amplifier is configured to operate with a first average power efficiency in the first mode and with a second average power efficiency lower than the first average power efficiency in the second mode. 5. The amplifier system of claim 1 or claim 2, wherein the first switching amplifier is configured to operate at a first switching frequency in the first mode and at a second switching frequency higher than the first switching frequency in the second mode. 6. The amplifier system of claim 1 or claim 2, wherein the first switching amplifier is configured to operate at a first distortion level in the first mode and at a second distortion level lower than the first distortion level in the second mode. 7. The amplifier system according to claim 1 or claim 2, wherein the first mode of the first switching amplifier is characterized by soft switching of the output stage of the first switching amplifier. 8. The amplifier system according to claim 1 or claim 2, wherein the first mode of the first switching amplifier is characterized by imposing a non-zero DC bias at the output of the first switching amplifier. 9. The amplifier system of claim 1 or claim 2, further comprising a first delay circuit configured to delay the input signal before it is amplified by the linear amplifier. 10. The amplifier system of claim 9, wherein the first delay circuit is programmable to introduce a delay greater than or equal to zero, or wherein the first delay circuit is configurable to be bypassed. 11. The amplifier system of claim 9, further comprising a second delay circuit configured to delay the input signal before it is amplified by the first switching amplifier, wherein both the first delay circuit and the second delay circuit are independently programmable. 12. The amplifier system of claim 1 or claim 2, further comprising a first chassis and a second chassis, wherein the linear amplifier is integrated with the first chassis and the first switching amplifier is integrated with the second chassis. 13. The amplifier system of claim 12, wherein the amplifier system further includes one or more sensing terminals integrated with the first chassis and configured to provide feedback to the linear amplifier from a load driven by the linear amplifier. 14. The amplifier system of claim 12, wherein the load driven by the linear amplifier is integrated with the first chassis. 15. The amplifier system of claim 1 or claim 2, further comprising a bias modulation circuit configured to modulate the steady current of the linear amplifier based on the input signal to the linear amplifier or based on modulation of the power rail. 16. The amplifier system of claim 15, wherein the bias modulation circuitry is configured to modulate the steady current of the linear amplifier based on a specified load impedance. 17. The amplifier system of claim 1 or claim 2, wherein the power rail is a positive power rail and the linear amplifier further has a negative power rail, the amplifier system further comprising a second switching amplifier configured to modulate the negative power rail of the linear amplifier based on the input signal to the linear amplifier in a first mode, the second switching amplifier configured to be used for signal amplification in a second mode, wherein the second switching amplifier is configured to modulate the negative power rail of the linear amplifier only in its first mode. 18. The amplifier system of claim 1 or claim 2, wherein the first switching amplifier is configured to modulate the power rail of the linear amplifier in a continuous manner. 19. The amplifier system of claim 1 or claim 2, wherein the first switching amplifier is configured to drive the power rails of the linear amplifier to a plurality of discrete voltages.