HK1233766A1 - Hybrid heterostructure light-emitting devices - Google Patents

Description

Hybrid heterostructure light emitting device

Cross Reference to Related Applications

This application claims priority to U.S. patent application No.14/506,975, filed on 6/10/2014, which is incorporated herein by reference in its entirety.

Relating to government rights

The invention was made with the help of the government of FA9550-09-1-0482 awarded by USAF/AFOSR. The government has certain rights in this invention.

Background

Conventionally, epitaxially grown heterostructures are used to produce certain light emitting devices, which include pin diodes (pindiodes) having a multiple quantum well structure in their active region. For devices fabricated from III-V semiconductor materials (e.g., GaN), the limitations of the highest achievable doping concentration in the p-type semiconductor of the hole injection layer limit the hole injection efficiency and thus the internal quantum efficiency of the device. In addition, the low mobility of holes in p-type doped III-V semiconductor materials results in the need for high bias voltages to operate the device. These problems are particularly serious for nitride semiconductor-based devices for blue light generation and UV light generation, because the hole mobility and concentration of the activated p-type dopant tend to be particularly low in p-type doped GaN-based semiconductors.

SUMMARY

Light emitting devices having a Multiple Quantum Well (MQW) pin diode structure and methods of making and using the same are provided.

One embodiment of a light emitting device comprises: a hole injection layer comprising a single crystal p-type doped semiconductor material; an electron injection layer comprising a monocrystalline n-type doped semiconductor material; a light emitting active region comprising an intrinsic semiconductor material disposed between the hole injection layer and the electron injection layer, the light emitting active region comprising a multiple quantum well structure comprising alternating barrier layers and quantum well layers; and a current tunneling layer disposed between and in contact with the hole injection layer and the light emitting active region or disposed between and in contact with the electron injection layer and the light emitting active region. The current tunneling layer comprises an inorganic material having a bandgap that is wider than the bandgaps of the intrinsic semiconductor material and the doped semiconductor material in contact therewith. The interface between the current tunneling layer and the doped semiconductor material and the interface between the current tunneling layer and the intrinsic semiconductor material do not have epitaxial structures.

One embodiment of a method of making a light emitting device includes providing a multilayer semiconductor heterostructure comprising: an electron injection layer comprising a monocrystalline n-type doped semiconductor material; and a light emitting active region including an intrinsic semiconductor material on the electron injection layer, the light emitting active region including a multiple quantum well structure including alternating barrier layers and quantum well layers. Then, depositing a current tunneling layer on the light emitting active region; transferring a hole injection layer comprising a single crystalline p-type doped semiconductor material onto the current tunneling layer; and bonding the hole injection layer to the current tunneling layer. The current tunneling layer comprises an inorganic material having a bandgap that is wider than the bandgaps of the intrinsic semiconductor material and the p-type doped semiconductor material in contact therewith. The interface between the current tunneling layer and the p-type doped semiconductor material and the interface between the current tunneling layer and the intrinsic semiconductor material do not have epitaxial structures. The transfer and bonding of the hole injection layer to the current tunneling layer may be performed using a thin film detachment and transfer method or by wafer bonding followed by thin film detachment (clean).

Other principal features and advantages of the invention will become apparent to those skilled in the art upon review of the following drawings, the detailed description, and the appended claims.

Brief description of the drawings

Illustrative embodiments of the invention will hereinafter be described with reference to the accompanying drawings, wherein like numerals denote like elements.

Fig. 1 is a schematic diagram of a light emitting diode.

Fig. 2 is a schematic diagram of an edge-emitting (edge-emitting) laser.

Fig. 3 is a schematic diagram of a vertical cavity surface emitting laser including a lower distributed bragg reflector and an upper distributed bragg reflector.

FIG. 4 is a schematic diagram of a vertical cavity surface emitting laser including a lower photonic crystal reflector and an upper photonic crystal reflector.

Fig. 5 is a schematic diagram showing the processing steps of a transfer and bonding method for making a light emitting diode of the type shown in fig. 1.

Fig. 6 is a schematic diagram showing a method for transferring a single crystal doped semiconductor layer onto a current tunneling layer of a heterostructure using a thin film detachment and transfer method.

Fig. 7 is a schematic diagram showing a method for transferring a single crystal doped semiconductor layer onto a current tunneling layer of a heterostructure using a wafer bonding and separation method.

Fig. 8 is a schematic diagram showing the processing steps of the transfer and bonding method for making a pin diode heterojunction comprising two current tunneling layers.

Detailed Description

Light emitting devices having a Multiple Quantum Well (MQW) pin diode structure and methods of making and using the same are provided.

The device is fabricated using a thin film transfer and bonding process or an interfacial bonding process in combination with the introduction of one or more interfacial current tunneling layers to produce a high performance light emitting device wherein the doped semiconductor materials of the p-type and n-type layers of the pin heterojunction can be selected independently of the intrinsic semiconductor material of the intrinsic active region.

The device is composed of a multilayer semiconductor heterostructure in which a layer of material that tunnels current through a lattice-mismatched heterojunction is provided at the interface between the intrinsic active region and the p-type and/or n-type doped charge injection layer. Using this design, many materials can be put together to form a hybrid heterostructure despite their lattice mismatch and/or thermal mismatch.

Because the transfer and bonding process does not rely on epitaxial growth or wafer bonding, the material in the charge injection layer does not need to be lattice matched to the semiconductor material of the active region. In addition, unlike wafer bonding techniques, the transfer and bonding process and the interfacial wafer bonding process require atomically smooth surfaces for bonding and can tolerate relatively large differences in thermal expansion coefficients for doped and undoped semiconductor materials in a heterojunction. Finally, because the p-type and/or n-type doped injection layers are physically separated from the intrinsic active region by the current tunneling layer, chemical reactions between the materials are avoided and the surfaces of the materials can be passivated. As a result, the light emitting device can be manufactured with a wider range of semiconductor materials than those made by epitaxial growth or wafer bonding techniques.

The pin diode of the light emitting device includes: a hole injection layer comprising a single crystalline p-type doped semiconductor material, such as a p-type doped narrow bandgap group IV semiconductor or a narrow bandgap group III-V semiconductor; an electron injection layer comprising a single crystal n-type doped semiconductor material; and a light emitting active region disposed between the hole injection layer and the electron injection layer. A current tunneling layer is disposed between one or both of the charge injection layers and the intrinsic active region.

The intrinsic active region includes a MQW structure comprising alternating barrier layers and quantum well layers made of different semiconductor materials. In the MQW structure, carriers are confined by quantum confinement in a thin layer of one semiconductor "well" material sandwiched between layers of other semiconductor "barrier" materials. The active region may further comprise a lower spacer layer and an upper spacer layer with the MQW structure disposed therebetween. Spacer layers are used to increase the thickness of the intrinsic active region and because they form part of the intrinsic active region, they comprise undoped single crystal semiconductor material. In embodiments of the device that include a spacer layer in the active region, the current tunneling layer will be disposed between and in contact with the spacer layer and its adjacent charge injection layer. In the absence of a spacer layer, the current tunneling layer would be adjacent to and in contact with the outermost barrier layer of the MQW structure. The barrier layer, quantum well layer, and spacer layer may comprise group III-V or group II-VI semiconductor materials.

The current tunneling layer is formed of an inorganic material having a bandgap wider than the bandgap of the intrinsic semiconductor material of the active region in contact therewith and the bandgap of the doped semiconductor material of the charge injection layer. In this structure, the single crystalline p-type or n-type doped semiconductor material has a different chemical composition and a different lattice constant than the intrinsic semiconductor material.

The term "current tunneling layer" as used herein refers to a layer characterized by: made of a suitable material and sufficiently thin to be able to act as a tunneling layer for electrons and/or holes. That is, unlike typical dielectrics, the current tunneling layer allows both electrons and holes to pass therethrough (from the first layer to the second layer of single crystalline semiconductor material) by means of quantum tunneling. Thus, metal is not a suitable material for the current tunneling layer because it will block the passage of holes. However, a wide range of non-metallic inorganic materials can meet these criteria. The inorganic material of the current tunneling layer may be a material that will act as a dielectric in its bulk form, but is thin enough that it no longer acts as an electrical insulator. The current tunneling layer provides a kind of "glue" between the layers of monocrystalline semiconductor material. It is capable of conforming to the surface topography of a layer of semiconductor material without introducing voids at the interface. In addition, the current tunneling layer may prevent interdiffusion of semiconductor material from adjacent single crystal semiconductor material layers. This avoids the formation of an undesirable intervening cross-contaminated semiconductor interfacial layer between the monocrystalline semiconductor layers.

An additional advantage provided by such an inorganic material layer is that it can passivate the surface of the semiconductor material layer in contact therewith, such that dangling bonds and interface states are minimized or eliminated. This property is useful because when directly bonding two amorphous lattice matched single crystal materials, the chemical bonds formed between the two materials can produce a large number of interface states. These interface states prevent the two materials from forming an ideal rectifying junction. However, the two materials are physically separated when the inorganic material is embedded. If the layer is thin enough and has the ability to chemically passivate the material, the number of interface states can be reduced to a level such that both electrons and holes can tunnel efficiently through the layer.

Other components that may be part of the light emitting device are those that are typically incorporated into such devices, including substrates, buffer layers, cladding layers, reflectors, electrically conductive contact layers, electrodes, and interconnects. For example, the device can also include electrodes in electrical communication with the p-type and n-type doped semiconductor materials and a voltage source configured to apply a voltage across the pin junction.

Light Emitting Diodes (LEDs) are examples of light emitting devices that may include the MQW pin diode structure. A schematic diagram of an LED is provided in fig. 1. The LED includes a substrate 102 and an electron injection layer 104 comprising an n-type doped semiconductor material. In this embodiment, the substrate 102 is a growth substrate on which the electron injection layer 104 is epitaxially grown, and thus the substrate 102 also includes a buffer layer 106 to facilitate epitaxial growth of the semiconductor material of the electron injection layer over the substrate material, since those materials do not have a perfect lattice match. An active region 108 comprising a MQW structure is disposed on electron injection layer 104 and a layer of current tunneling material 110 is disposed on active region 108. The layer of p-type doped semiconductor material provides the hole injection layer 112 and completes the pin diode structure. An anode 114 and a cathode 116 are placed in electrical communication with the hole injection layer and the electron injection layer, respectively.

The MQW pin diode structure may also be incorporated in an edge-emitting laser as schematically shown in fig. 2. The edge-emitting laser comprises a substrate 202 and an electron injection layer 204 comprising an n-type doped semiconductor material. An active region 208 comprising a MQW structure is disposed on electron injection layer 204 and a layer of current tunneling material 210 is disposed on active region 208. A layer of p-type doped semiconductor material provides the hole injection layer 212 and completes the pin diode structure. An anode 214 and a cathode 216 are placed in electrical communication with the hole injection layer and the electron injection layer, respectively.

The light emitting device may also be a Vertical Cavity Surface Emitting Laser (VCSEL). One embodiment of a VCSEL incorporating an MQW pin diode structure is depicted in fig. 3. The VCSEL comprises a substrate 302 and an electron injection layer 304 comprising an n-type doped semiconductor material. An active region 308 comprising a MQW structure is disposed on electron injection layer 304 and a layer of current tunneling material 310 is disposed on active region 308. The layer of p-type doped semiconductor material provides the hole injection layer 312 and completes the pin diode structure. An anode 314 and a cathode 316 are placed in electrical communication with the hole injection layer and the electron injection layer, respectively. The VCSEL also includes a lower Distributed Bragg Reflector (DBR)318 sandwiched between the substrate and the cathode and an upper DBR320 disposed above the p-type doped hole injection layer 312.

Another embodiment of a VCSEL is depicted in figure 4. As shown in fig. 3, the VCSEL includes a substrate 402 and an electron injection layer 404 comprising an n-type doped semiconductor material. An active region 408 comprising a MQW structure is disposed on electron injection layer 404 and a layer of current tunneling material 410 is disposed on active region 408. The layer of p-type doped semiconductor material provides the hole injection layer 412 and completes the pin diode structure. An anode 414 and a cathode 416 are placed in electrical communication with the hole injection layer and the electron injection layer, respectively. The VCSEL also includes a lower photonic crystal reflector 418 sandwiched between the substrate and the cathode and an upper photonic crystal reflector 420 disposed over the p-type doped hole injection layer 412.

Although the upper and lower reflectors in the VCSELs in fig. 3 and 4 are of the same type, different types of reflectors may be used in the same device. For example, a photonic crystal type reflector may be used as the lower reflector and a DBR may be used as the upper reflector, or vice versa. The reflector in the VSCEL can be formed by epitaxial growth or by transfer and bonding. A method for transferring and bonding a photonic crystal type reflector to the active region of a VCSEL is described in U.S. patent No. 8,217,410.

A thin film transfer and bonding process and a current tunneling layer deposition process for forming the MQW pin diode structure in the LED are illustrated in fig. 5. Panel (a) of fig. 5 shows a heterostructure comprising a substrate 102, a buffer layer 106, an n-type doped semiconductor layer 104, an active region 108 and a current tunneling layer 110. The semiconductor layer 104-108 may be epitaxially grown on the growth substrate 102 using known methods, such as Molecular Beam Epitaxy (MBE). The current tunneling layer 110 may be deposited on the upper surface of the active region 108 using, for example, Atomic Layer Deposition (ALD).

The thickness of the current tunneling layer typically needs to be only on the order of the root mean square (rms) roughness at the surface of the layer of semiconductor material to which it is bonded. By way of illustration, in some embodiments, the current tunneling layer has a thickness in a range from about 0.5 to about 10 nm. This includes the following embodiments: it has a thickness in the range of from about 0.5 to about 10, from about 0.5 to about 5nm, or from about 0.5 to about 3 nm. Because the thickness of the current tunneling layer may not be uniform on an atomic scale, the thickness of the layer corresponds to the average thickness of the layer across the bonding interface of the heterostructure.

As shown in picture (b), once the current tunneling layer is formed, a pre-formed single crystalline p-type doped semiconductor material layer 112 may be placed on its upper surface to provide the p-layer of the pin diode structure. The junction between the transferred layer of single crystal p-type doped semiconductor material and the current tunneling layer may be enhanced by annealing (panel (c)). Next, mesas (mesas) are etched into the pin diode structure (picture (d)) and the anode 114 and cathode 116 are deposited using, for example, metallization (picture (e)).

Fig. 6 illustrates in more detail a method of transferring a pre-formed single crystal p-type doped semiconductor material onto the current tunneling layer. The method begins with a semiconductor-on-insulator substrate comprising a handle wafer 601 (e.g., a Si handle wafer), a buried oxide layer 603 and a thin layer 112 of p-type doped monocrystalline semiconductor (e.g., a thin layer of monocrystalline p-type Si, Ge, GaAs or InGaAs) (panel (a)). The buried oxide layer 603 is selectively removed from the structure using, for example, a selective chemical etchant. As a result, the layer 112 settles down on the underlying handle wafer 601 as shown in panel (b). A body material 605, such as a rubber stamp (rubber stamp), is then pressed onto the upper surface of the layer 112. Layer 112 adheres to host material 605 and is lifted away from handle wafer 601 (panel (c)). In a subsequent step (panel (d)), the detached layer 112 is brought into contact with the current tunneling layer 110 and transferred onto the current tunneling layer. The single crystal layer may be doped before or after transfer and bonding. The host material 605 is then removed (panel (e)) leaving the MQW pin structure.

Fig. 7 illustrates an alternative method, sometimes referred to as Smart Cut (Smart Cut), of using wafer bonding followed by hydrogen implantation to transfer a single crystalline p-type doped semiconductor layer onto a current tunneling layer to create a split plane in the semiconductor material. A description of this smart cut process can be found in Bruel et al Proceedings 1995IEEE International SOI Conference,178 (1995). In this technique, as shown in panel (a), a buried hydrogen implant layer 702 is formed in a p-type doped semiconductor substrate 700 (e.g., a semiconductor wafer). The depth of the hydrogen implant layer 702 will determine the thickness of the single crystal p-type doped semiconductor layer 712 to be transferred. Once the splitting plane is formed by means of hydrogen implantation, the surface of the substrate 700 is in contact with the current tunneling layer 110 (panels (b) and (c)). The substrate 700 is then cleaved at the hydrogen implant layer 702 and most of the substrate 700 is removed (panel (d)) to form the MQW pin diode structure (panel (e)). If light from the active layer is emitted through the single crystal p-type doped semiconductor layer 712, the layer can be thinned using chemical mechanical polishing after transfer.

Fig. 1-5 illustrate embodiments of light emitting devices having a single current tunneling layer sandwiched between a p-type doped hole injection layer and an active region of a pin heterojunction structure. However, in other devices a single current tunneling layer may be provided between the active region and the n-type doped electron injection layer. Alternatively, the device may include a first current tunneling layer between the active region and the p-type doped hole injection layer and a second current tunneling layer between the active region and the n-type doped electron injection layer. Fig. 8 is a schematic diagram illustrating a method of forming an MQW pin diode structure having two current tunneling layers.

Panel (a) in fig. 8 shows a heterostructure comprising a substrate 802, an active region 808, and a current tunneling layer 810. A buffer layer 801 is present between the substrate 802 and the active region 808. The active region and any buffer layer may be epitaxially grown on growth substrate 802 using known methods, such as Molecular Beam Epitaxy (MBE). The current tunneling layer 810 can be deposited on the upper surface of the active region 808 using, for example, Atomic Layer Deposition (ALD). Once the current tunneling layer 810 is formed, a pre-formed layer 812 of single crystalline p-type semiconductor material may be placed on its upper surface to provide a p-layer of the pin diode structure, as shown in picture (b). The junction between the transferred single crystal p-type doped semiconductor material layer and the current tunneling layer 812 can be enhanced by annealing (panel (c)). The substrate 802 is then removed using, for example, chemical mechanical polishing and/or selective etching (panel (d)). A second current tunneling layer 820 is then deposited on the surface of the active region 808 (opposite the first current tunneling layer 810) and a pre-formed single crystal n-type doped semiconductor material layer 822 is placed on its upper surface to provide the n-layer of the pin diode structure (panel (e)). The junction between the transferred single crystal n-type doped semiconductor material layer and the current tunneling layer 822 may be enhanced by annealing (panel (f)).

In some embodiments, the inorganic material of the current tunneling layer is an oxide. In such embodiments, the oxide may comprise, consist of, or consist essentially of: a metal oxide, an oxide of a semiconductor element, or an oxide of a metalloid element. Examples of oxides that may be used in the metal oxide current tunneling layer include, but are not limited to, those that may be deposited by Atomic Layer Deposition (ALD). Examples of such metal oxides include aluminum oxide (Al)₂O₃) Oxygen, oxygenTitanium (TiO)₂) Hafnium oxide (HfO)₂) Tantalum oxide (Ta)₂O₅) And silicon dioxide (SiO)₂). In some embodiments, the metal, semiconductor, or metalloid elements present in the oxide are different from any metal, semiconductor, or metalloid elements in other semiconductor layers that are in contact therewith and disposed therebetween. In existing heterostructures, the inorganic oxide of the current tunneling layer is not a native oxide of either of the two semiconductor materials in the layers they separate. (As used herein, the term native oxide refers to an oxide that is integrally formed on a semiconductor material as a result of oxidation of the material in an oxygen-containing environment₂Is a natural oxide of Si. )

In other embodiments, the inorganic material of the current tunneling layer is a nitride. In such embodiments, the nitride may comprise, consist of, or consist essentially of: a metal nitride, a nitride of a semiconductor element, or a nitride of a metalloid element. Examples of nitrides that may be used in the nitride current tunneling layer include, but are not limited to, those that may be deposited by Atomic Layer Deposition (ALD). Examples of such nitrides include aluminum nitride, silicon nitride, and titanium nitride. In some embodiments, the metal, semiconductor, or metalloid elements present in the nitride are different from any metal, semiconductor, or metalloid elements in the semiconductor layer in contact therewith and disposed therebetween.

In some embodiments, the current tunneling layer comprises two or more sublayers, each comprising an inorganic material, provided however that the total combined thickness of the sublayers is still low enough to allow tunneling of electrons and holes through the layer. For example, in a current tunneling layer comprising a plurality of inorganic oxide sublayers, the inorganic oxides can be selected such that one oxide passivates one of two adjacent semiconductor materials, while the other oxide passivates the other of the two adjacent semiconductor materials.

The single crystal semiconductor material of the hole injection layer, the electron injection layer, the MQW structure and any spacer layer is an inorganic semiconductor. The semiconductor materials in adjacent layers (i.e., layers separated by an intervening current tunneling layer) are dissimilar such that there is a band offset in the electronic band diagram of the heterojunction formed by the two materials. The semiconductor material may be independently selected from a wide range of semiconductors including: (a) a group IV semiconductor; (b) a group III-V semiconductor; and (c) a II-VI semiconductor. The semiconductor materials of adjacent layers may be selected from the same group or may be selected from different groups. For example, in embodiments where the p-type doped semiconductor material is a group IV semiconductor layer, the layers of intrinsic semiconductor material and the layers of n-type doped semiconductor material that make up the electron injection layer of the active region (e.g., the well and barrier layers and spacer layers of the MQW structure) may be group III-V or group II-VI semiconductor layers. Similarly, in embodiments where the p-type doped semiconductor material layer is a group III-V semiconductor layer, the intrinsic semiconductor material layer can be a group IV or group II-VI semiconductor layer. The group IV semiconductors include elemental semiconductors (e.g., Si, Ge, and C, which include diamond) as well as alloy and compound semiconductors (e.g., SiGe: C, SiGe, SiGeSn, and SiC). The group III-V and group II-VI semiconductors include binary, ternary, and higher compound semiconductors. Examples of group III-V semiconductors include GaAs, AlGaAs, InGaAs, AlAs, InAlAs, InP, GaInP, GaP, GaN, InGaN, InAlN, AlN, and AlGaN. Examples of II-VI semiconductors include oxides such as ZnO.

Each layer of semiconductor material may have the following characteristics: the upper, lower, and peripheral edge surfaces (the terms "upper" and "lower" are not used to designate any absolute orientation-rather they are merely intended to refer to oppositely facing surfaces that are parallel (including substantially parallel) to a plane that transversely slices the layer) -in some embodiments, the root mean square (rms) roughness of the upper and/or lower surfaces may be significantly higher than what is considered acceptable for void-free wafer bonding. Thus, in some embodiments, the upper and/or lower surface has an rms roughness of greater than 1 nm. This includes embodiments in which the upper and/or lower surface has an rms roughness of at least 1nm (e.g., in the range of from 1nm to 5 nm) and also includes embodiments in which the upper and/or lower surface has an rms roughness of at least 5nm (e.g., in the range of from 5nm to 10 nm). For the purpose of determining the rms roughness of the surface, it can be determined from an AFM image over a region of the interface between the layer of single-crystal semiconductor material and the current tunneling layer.

Adjacent layers of the heterojunction fabricated using the transfer and junction process do not have an epitaxial structure. The term "epitaxial structure" as used herein refers to a structure in which the crystallographic orientation of an overlying layer is determined by the crystallographic orientation of its underlying layer (the crystallographic orientation of the overlying layer matches the crystallographic orientation of its underlying layer) such that the two layers have the same crystallographic orientation at least in the region of their interface. Such epitaxial structures may include strain and stress at the interface caused by lattice mismatch between the two materials and may even include misfit dislocations. In contrast to such epitaxial structures, the non-epitaxial layers in the present structure have a crystallographic orientation that is independent of (e.g., different from) the crystallographic orientation of their adjacent layers. As such, the layer without the epitaxial structure is free of lattice mismatch induced strain or stress and lattice mismatch induced misfit dislocations. In fact, the semiconductor material selected for one or both of the charge injection layers and the intrinsic semiconductor material selected for the active region may have a lattice constant mismatch-even in the presence of an intermediate buffer layer-that would make them unsuitable for epitaxial growth. For example, in some embodiments the lattice constant mismatch between the semiconductor material of one or both of the charge injection layers and the semiconductor material of the active region is greater than about 15%.

The semiconductor material selected for one or both of the charge injection layers and the semiconductor material of the active region may have a coefficient of thermal expansion mismatch that would make them unsuitable for wafer bonding, which is typically performed at very high temperatures. This is caused at least in part by the presence of the current tunneling layer. The current tunneling layer can act as a buffer for thermal expansion differences between the two single-crystal semiconductor materials and can be used to bond the two single-crystal semiconductor materials at a lower processing temperature than that used in wafer bonding processing techniques.

The thickness of the layer of monocrystalline semiconductor material will depend on the intended light emitting device application. By way of illustration, however, in some embodiments of the device, some or all of the layers of single crystal material have a thickness of no greater than about 1000 nm. If the semiconductor material of the charge injection layer absorbs radiation in the emission wavelength range of the active region, it is advantageous to use a very thin layer of this material. For example, the p-type and/or n-type doped semiconductor layer may be thinned to a thickness of 10nm or less, including a thickness of 5nm or less.

The wavelength of the radiation emitted by the light emitting device will depend on the semiconductor material used in the active region. Thus, with appropriate material selection, the light emitting device can be configured to emit ultraviolet (UV, from-100 to 400nm, including 220nm to 240nm), visible (vis, from 400nm to 780nm), and/or infrared (IR, from 780nm to 1mm, e.g., 1.55 μm) light in the electromagnetic spectrum. By way of illustration, a light emitting device designed to emit light in the wavelength range from about 220 to 240nm may employ an active region having a MQW structure comprising alternating layers of single crystal AlGaN quantum well layers and single crystal AlN barrier layers. The active region may be epitaxially grown over the n-type AlGaN electron injection layer. Alternatively, a light emitting device designed to emit light at a wavelength of about 1.55 μm may employ an active region having a MQW structure comprising alternating layers of single crystal InGaP quantum well layers and single crystal InGaP barrier layers, wherein the quantum well layers and barrier layers have different elemental ratios. The active region may be epitaxially grown over the n-type InP electron injection layer. A light emitting device designed to emit blue light may employ an active region having a MQW structure comprising alternating layers of single crystal InGaN quantum well layers and single crystal GaN barrier layers. The active region may be epitaxially grown over the n-type GaN electron injection layer. Other combinations of materials that can be used for the active region and the electron injection layer are listed in table 1.

TABLE 1Example materials for quantum well, barrier, and electron injection layers

Suitable doped semiconductors for the charge injection layer of the light emitting device include doped Si, Ge, GaAs, and InP.

Examples

Example 1: fabrication of Si/GaN hybrid blue LED

The fabrication process for the Si-GaN hybrid LED starts with the growth of an n-layer of GaN and an undoped InGaN/GaN Multiple Quantum Well (MQW) layer on a sapphire substrate the InGaN/GaN i-n layer structure is grown using a Metal Organic Chemical Vapor Deposition (MOCVD) system, the structure consists of a 1.0 μm thick undoped GaN buffer layer, a 2 μm thick Si doped n-GaN (n-3 × 10)¹⁸cm^-3) And five pairs of In_0.2Ga_0.8N/GaN (2nm/8nm) MQW active layer. The MQW structure is designed to achieve a desired emission wavelength between 450nm and 470 nm. A thin aluminum oxide layer is then deposited on top of the MQW as a current tunneling layer using an Atomic Layer Deposition (ALD) system. The InGaN/GaN structure is immersed in a dilute ammonium hydroxide acid solution (DI water: NH) prior to oxide deposition₄OH ═ 10:1) for 10 minutes and then rinsed in Deionized (DI) water rinse to obtain a surface free of native oxide.

As the p-type layer, a heavily doped Si layer (doped by ion implantation and diffused to achieve high boron concentration) is prepared from the top silicon layer of a silicon-on-insulator (silicon-on-insulator) substrate using photolithography and reactive ion etching (RIE 790) to etch holes through the doped silicon layer. The doped Si layer is then detached from the substrate by undercutting the substrate with concentrated hydrofluoric acid (HF, 49%). The detached Si layer, which acts as a p-type layer in this pin structure, is transfer printed onto a current tunneling layer coated InGaN/GaN substrate. As a result, very clean Si-alumina-I is achievedAn nGaN interface. In order to enhance the bonding between the transfer printed Si layer and the InGaN/GaN substrate, in N₂The annealing process is performed using a Rapid Thermal Annealing (RTA) system in ambient. A ring-shaped anode consisting of a Ti/Au layer stack for the p + Si layer was deposited by electron beam evaporation. The interior (active area) of the ring is covered with a photoresist (through which light will be emitted) to protect it during the entire etching process. The Si layer is then etched by Reactive Ion Etching (RIE) until the oxide tunneling layer is exposed, while the ring-shaped active region remains intact due to the photoresist. After the Si layer is completely etched, the current tunneling layer serving as an etch stop layer is removed by wet etching with diluted hydrogen fluoride (HF, 1:20 ═ HF: DI water) for a short time of several seconds. Then, InGaN/GaN MQW and n-type GaN were etched to a depth of 800nm using inductively coupled plasma reactive ion etching (ICP-RIE, plasma therm770ICP) to expose the n-GaN layer. After etching the n-GaN layer, a Ni/Au stack for n-GaN was deposited to provide ohmic contact, and then the sample was annealed at 500 ℃ for 1 minute using RTA to enhance ohmic properties.

The electrical (I-V) and optical (EL) properties were measured by a 4155B Agilent semiconductor parametric analyzer and spectrometer (USB2000, Ocean Optics), respectively.

Example 2: fabrication of Si/AlN hybrid UV LED

The fabrication process for the Si-AlN hybrid LED starts with the growth of an n-layer of AlGaN and an undoped AlGaN/AlN Multiple Quantum Well (MQW) layer on an AlN substrate. All c-plane InGaN/GaN i-n layer structures were grown using a Metal Organic Chemical Vapor Deposition (MOCVD) system. The MQW structure consists of a 400nm thick AlN undoped homoepitaxial (homoepi) layer and 600nm thick n-type Al_0.8Ga_0.2N layer (with 2nm thick Al)_0.65Ga_0.35N QW and 3nm thick AlN barrier). A thin aluminum oxide layer is deposited on top of the MQW of AlGaN/AlN as a current tunneling layer using an Atomic Layer Deposition (ALD) system before transfer printing the p-type Si layer onto the MQW top layer. The AlGaN/AlN is deposited prior to oxide depositionThe structure is immersed in a dilute ammonium hydroxide acid solution (DI water: NH)₄OH ═ 10:1) for 10 minutes and then rinsed in Deionized (DI) water rinse to obtain a surface free of native oxide.

As a p-type layer, a heavily doped Si layer (doped by ion implantation and diffused to achieve high boron concentration) is prepared from the top silicon layer of a silicon-on-insulator substrate using photolithography and reactive ion etching (RIE, Unaxis790) to etch holes through the doped silicon layer. The doped Si layer is then detached from the substrate by undercutting the substrate with concentrated hydrofluoric acid (HF, 49%). The detached Si layer, which acts as a p-type layer in this pin structure, was transfer printed using an elastomeric stamp (PDMS) without any adhesive onto a current tunneling layer coated AlGaN/AlN substrate. As a result, a very clean Si-alumina-AlN interface is achieved. In order to enhance the junction between the transfer printed Si layer and the AlGaN/AlN substrate, in N₂The annealing process is performed using a Rapid Thermal Annealing (RTA) system in ambient. An annular anode consisting of a Ti/Au layer stack for the p + Si layer was deposited by electron beam evaporation. The interior (active area) of the ring is covered with a photoresist (through which light will be emitted) to protect it during the entire etching process. The Si layer is then etched by Reactive Ion Etching (RIE) until the tunneling layer is exposed, while the ring-shaped active region remains intact due to the photoresist. After the Si layer is completely etched, the current tunneling layer serving as an etch stop layer is removed by wet etching with diluted hydrogen fluoride (HF, 1:20 ═ HF: DI water) for a short time of several seconds. Then, AlGaN/AlN MQW and n-type AlN were etched to a depth of 260nm using inductively coupled plasma reactive ion etching (ICP-RIE, plasma therm770ICP) to expose the n-AlGaN layer. After etching the n-AlGaN layer, a Ni/Au stack for n-AlGaN was deposited to provide ohmic contact, and then the sample was annealed at 500 ℃ for 1 minute using an RTA system to enhance ohmic properties.

The electrical (I-V) and optical (EL) properties were measured by a 4155B Agilent semiconductor parametric analyzer and spectrometer (USB2000, Ocean Optics), respectively.

Example 3: fabrication of Si/InGaAsP hybrid NIR LEDs

The fabrication process for the Si-InGaAsP hybrid LED starts with the growth of an undoped InGaAsP Multiple Quantum Well (MQW) layer on an InP substrate. The InGaAsP MQW (consisting of 8 pairs of In undoped 7.5nm thick) was grown using a Metal Organic Chemical Vapor Deposition (MOCVD) system_0.485Ga_0.515As_0.83P_0.17Quantum well and In_0.76Ga_0.24As_0.83P_0.17Barrier formation) and an InP/InGaAs n-type layer below the MQW layer. The MQW structure is designed to achieve a desired emission wavelength between 1550nm and 1560 nm. Before transfer printing a heavily doped p-type Si layer on top of the MQW of InGaAsP, a thin aluminum oxide layer was deposited as a current tunneling layer using an Atomic Layer Deposition (ALD) system. Prior to oxide deposition, the sample was immersed in a Buffered Oxide Etch (BOE) solution for 1 minute and then rinsed in a Deionized (DI) water rinse to obtain a surface free of native oxide.

As a p-type layer, a heavily doped Si layer (doped by ion implantation and diffused to achieve high boron concentration) is prepared from the top silicon layer of a silicon-on-insulator substrate using photolithography and reactive ion etching (RIE, Unaxis790) to etch holes through the doped silicon layer. The doped Si layer is then detached from the substrate by undercutting the substrate with concentrated hydrofluoric acid (HF, 49%). The detached Si layer, which acts as a p-type layer in the pin structure, was transfer printed onto a current tunneling layer coated InGaAsP/InGaAs/InP substrate. As a result, a very clean Si-alumina-InGaAsP interface is achieved. In order to enhance the bonding between the transfer printed Si layer and the InGaAsP/InGaAs/InP substrate, in N₂The annealing process is performed using a Rapid Thermal Annealing (RTA) system in ambient. A ring-shaped anode consisting of a Ti/Au layer stack for the p + Si layer was deposited by electron beam evaporation. The interior (active area) of the ring is covered with a photoresist (through which light will be emitted) to protect it during the entire etching process. The Si layer is then etched by Reactive Ion Etching (RIE) until the tunneling layer is exposedAnd the ring-shaped active region remains intact due to the photoresist. After the Si layer is completely etched, the current tunneling layer serving as an etch stop layer is removed by wet etching with diluted hydrogen fluoride (HF, 1:20 ═ HF: DI water) for a short time of several seconds. Then, the i-nInGaAsP/InP/InGaAs layer was etched to a depth of 250nm by inductively coupled plasma reactive ion etching (ICP-RIE, plasma therm770ICP) to expose the n-InGaAs layer. The Ti/Pd/Ti/Au metal stack was deposited and annealed at 350 ℃ for 30 seconds using a Rapid Thermal Annealing (RTA) system to achieve ohmic contact.

The electrical (I-V) and optical (EL) properties were measured by a 4155B Agilent semiconductor parametric analyzer and spectrometer (USB2000, Ocean Optics), respectively.

The word "illustrative" is used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as "illustrative" is not necessarily to be construed as preferred or advantageous over other aspects or designs. Further, for the purposes of this disclosure and unless otherwise stated, "a" or "an" means "one or more.

The foregoing description of illustrative embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and modifications and variations are possible in light of the above teachings or may be acquired from practice of the invention. The embodiments were chosen and described in order to explain the principles of the invention and as a practical application of the invention to enable one skilled in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.

Claims (20)

1. A light emitting device, comprising:

a hole injection layer comprising a single crystal p-type doped semiconductor material;

an electron injection layer comprising a monocrystalline n-type doped semiconductor material;

a light emitting active region comprising an intrinsic semiconductor material disposed between the hole injection layer and the electron injection layer, the light emitting active region comprising a multiple quantum well structure comprising alternating barrier layers and quantum well layers; and

a current tunneling layer disposed between and in contact with the hole injection layer and the light emitting active region or disposed between and in contact with the electron injection layer and the light emitting active region, the current tunneling layer comprising an inorganic material having a wider band gap than the band gap of the intrinsic semiconductor material and the doped semiconductor material in contact therewith;

wherein an interface between the current tunneling layer and the doped semiconductor material and an interface between the current tunneling layer and the intrinsic semiconductor material do not have an epitaxial structure.

2. The device of claim 1, wherein the inorganic material is an oxide that is not a native oxide of the intrinsic semiconductor material or a native oxide of the doped semiconductor material with which it is in contact.

3. The apparatus of claim 2, wherein the inorganic material is alumina.

4. The device of claim 1, wherein the inorganic material is a nitride.

5. The device of claim 1, wherein the current tunneling layer is disposed between and in contact with the hole injection layer and the light-emitting active region.

6. The device of claim 5, wherein the p-type doped semiconductor material is a p-type group IV semiconductor or a group III-V semiconductor.

7. The device of claim 6, wherein the p-type group IV semiconductor is p-type silicon.

8. The device of claim 7, wherein the current tunneling layer is an aluminum oxide layer.

9. The device of claim 6, wherein the p-type group IV semiconductor is p-type germanium.

10. The device of claim 9, wherein the current tunneling layer is an aluminum oxide layer.

11. The device of claim 6, wherein the intrinsic semiconductor material is a group III-V semiconductor material.

12. The device of claim 1, wherein the barrier layer is an AlN layer and the quantum well layer is an AlGaN layer.

13. The device of claim 1, wherein the barrier layers are InP layers and the quantum well layers are InGaAs layers.

14. The device of claim 1, wherein the barrier layer is a GaN layer and the quantum well layer is an InGaN layer.

15. The apparatus of claim 1, wherein the apparatus comprises:

a first current tunneling layer disposed between the hole injection layer and the light emitting active region, the first current tunneling layer comprising an inorganic material having a wider bandgap than the bandgap of the intrinsic semiconductor material and the p-type doped semiconductor material in contact therewith, wherein an interface between the first current tunneling layer and the p-type doped semiconductor material and an interface between the first current tunneling layer and the intrinsic semiconductor material do not have an epitaxial structure; and

a second current tunneling layer disposed between and in contact with the electron injection layer and the light emitting active region, the second current tunneling layer comprising an inorganic material having a wider bandgap than the bandgap of the intrinsic semiconductor material and the n-type doped semiconductor material in contact therewith, wherein an interface between the second current tunneling layer and the n-type doped semiconductor material and an interface between the second current tunneling layer and the intrinsic semiconductor material do not have an epitaxial structure.

16. The device of claim 15, wherein the p-type doped semiconductor material is a p-type doped group IV semiconductor, the n-type doped semiconductor material is an n-type doped group IV semiconductor and the intrinsic semiconductor material is an intrinsic group III-V semiconductor.

17. The device of claim 16, wherein the inorganic material is an oxide that is not a native oxide of the intrinsic semiconductor material or a native oxide of the doped semiconductor material with which it is in contact.

18. The apparatus of claim 17, wherein the inorganic material is alumina.

19. The device of claim 17, wherein the inorganic material is a nitride.

20. A method of making a light emitting device, the method comprising:

providing a multilayer semiconductor heterostructure comprising:

an electron injection layer comprising a monocrystalline n-type doped semiconductor material; and

a light emitting active region comprising an intrinsic semiconductor material on the electron injection layer, the light emitting active region comprising a multiple quantum well structure comprising alternating barrier layers and quantum well layers;

depositing a current tunneling layer on the light emitting active region;

transferring a hole injection layer comprising a single crystalline p-type doped semiconductor material onto the current tunneling layer; and

bonding the hole injection layer to the current tunneling layer;

wherein the current tunneling layer comprises an inorganic material having a bandgap that is wider than the bandgaps of the intrinsic semiconductor material and the p-type doped semiconductor material in contact therewith;

and further wherein an interface between the current tunneling layer and the p-type doped semiconductor material and an interface between the current tunneling layer and the intrinsic semiconductor material are free of epitaxial structures.