HK1232667A1 - Semiconductor device with stacked terminals - Google Patents

Abstract

A semiconductor device includes: a housing; a substrate inside the housing; first and second semiconductor circuits on the substrate; and first and second planar terminals electrically connected to the first and second semiconductor circuits, respectively, the first and second planar terminals stacked on top of each other, wherein each of the first and second planar terminals extends away from the housing.

Description

Semiconductor device with stacked terminals

Technical Field

The present disclosure relates to the field of semiconductors, and in particular to a semiconductor device having stacked terminals.

Background

Many conventional semiconductor devices have a substantially similar shape: a housing having a thin lead extending therefrom. The housing may be in the form of a solid rectangle that is used to enclose and protect the internal circuit devices. Leads protrude through the housing for electrically connecting the device to other components or circuits. For example, this form factor is used for certain types of Insulated Gate Bipolar Transistors (IGBTs).

Since semiconductor devices are used to control current, their efficiency in controlling current plays an important role in the efficiency of the overall device to which they are applied. For example, the performance and efficiency of a power inverter-a Direct Current (DC) to Alternating Current (AC) converter-depends on the efficiency of the semiconductor devices in its circuit. The efficiency of the device may in turn affect the performance of some larger systems. For example, in an electric vehicle (e.g., a plug-in electric vehicle or a hybrid vehicle), a stroke provided by electric power before the battery must be recharged is an important characteristic. Accordingly, the improved semiconductor devices may improve the performance and efficiency of electric vehicles and other systems.

Disclosure of Invention

In a first aspect, a semiconductor device includes: a housing; a substrate within the housing; first and second semiconductor circuits on a substrate; and first and second planar terminals electrically connected to the first and second semiconductor circuits, respectively, the first and second planar terminals being stacked on top of each other, wherein each of the first and second planar terminals extends away from the housing.

Implementations may include any or all of the following features. The first and second semiconductor circuits are positioned in a common plane on top of the substrate, wherein the first planar terminal abuts the first semiconductor circuit, wherein the second planar terminal is positioned on an opposite side of the first planar terminal from the first and second semiconductor circuits, wherein the second planar terminal includes a contact portion offset from a main portion of the second planar terminal by an offset portion, and wherein the contact portion abuts the second semiconductor circuit. The housing has a common opening through which the first and second planar terminals extend away from the housing. The semiconductor device further includes an electrically insulating layer between the first planar terminal and at least a major portion of the second planar terminal. The first and second semiconductor circuits are positioned in a common plane on top of the substrate, and the semiconductor device further comprises: a first bus bar adjoining the first semiconductor circuit, wherein the first planar terminal adjoins the first bus bar; and a second bus bar adjoining the second semiconductor circuit, wherein the second planar terminal adjoins the second bus bar. The first busbar is planar and extends out through the housing, and wherein the first planar terminal abuts the first busbar outside the housing. The second busbar is planar and has a portion exposed through an opening in the housing. A second planar terminal is positioned on an opposite side of the first planar terminal from the first and second bus bars, wherein the second planar terminal includes a contact portion offset from a main portion of the second planar terminal by an offset portion, and wherein the contact portion abuts a portion of the second bus bar. The first and second planar terminals overlap each other for a majority of their respective surface areas. Each of the first and second planar terminals has a width that is at least 70% of a width of the semiconductor device.

In a second aspect, an apparatus comprises: a plurality of semiconductor devices, each semiconductor device including a substrate, first and second semiconductor circuits on the substrate, and first and second bus bars adjoining the first and second semiconductor circuits, respectively; a capacitor; and a first planar terminal and a second planar terminal electrically connected to the capacitor, the first and second planar terminals being stacked on each other, wherein the first planar terminal abuts the first busbar of each of the plurality of semiconductor devices, and wherein the second planar terminal abuts the second busbar of each of the plurality of semiconductor devices.

Implementations may include any or all of the following features. The apparatus further includes a plurality of capacitors, wherein the first and second planar terminals are electrically connected to each of the plurality of capacitors. Each of the first and second planar terminals includes a respective sheet extending between the capacitor and the plurality of semiconductor devices. At least one of the sheets has a step shape to provide a first contact plane at the distal side of the capacitor. The other of the sheets also has a step shape to provide a second plane of contact at the proximal side of the capacitor.

In a third aspect, a method comprises: positioning a plurality of semiconductor devices in a row, each of the plurality of semiconductor devices including a substrate, first and second semiconductor circuits on the substrate, and first and second bus bars adjoining the first and second semiconductor circuits, respectively; forming an assembly by placing a first planar terminal in contact with a first busbar of each of the plurality of semiconductor devices and a second planar terminal in contact with a second busbar of each of the plurality of semiconductor devices, the first and second planar terminals being stacked on each other; soldering the first planar terminal to the first bus bar of each of the plurality of semiconductor devices, the soldering being performed from one side of the assembly; and soldering the second planar terminal to the second bus bar of each of the plurality of semiconductor devices, the soldering being performed from the opposite side of the assembly.

Implementations may include any or all of the following features. The method further comprises the following steps: an electrically insulating layer is included between the first and second planar terminals. The method further includes electrically connecting each of the first and second planar terminals to a plurality of capacitors. The welding comprises laser welding.

Drawings

Fig. 1 shows a cross-section of an example of a semiconductor device with stacked planar terminals.

Fig. 2 shows a top view of the semiconductor device of fig. 1.

Fig. 3 shows a cross-section of another example of a semiconductor device with stacked planar terminals.

Fig. 4 shows a perspective view of an assembly of a semiconductor device and a capacitor.

Fig. 5 shows a cross-section of the assembly in fig. 4.

Detailed Description

Examples of systems and techniques related to improved semiconductor devices are described herein. In some embodiments, the semiconductor device has relatively large and planar high voltage terminals stacked on top of each other. These planar terminals and their arrangement relative to the device as a whole may allow for more efficient semiconductor operation and provide for a convenient manufacturing process. For example, some components of a system that are conventionally arranged around a device may instead be integrated into the same package as the device. This can improve the electrical and thermal performance of the device, reduce its inductance, and reduce manufacturing and assembly costs.

Some examples herein relate to IGBTs or power inverters. This is merely exemplary and other embodiments include transistors other than IGBTs and/or devices other than inverters.

In a conventional IGBT, the module consists essentially of a substrate, with four semiconductor circuits (also referred to as silicon dies) positioned on the surface of the substrate in a generally rectangular arrangement. The module then has two bus bars that are soldered to the silicon die such that the two bus bars extend away from the module. That is, each of the bus bars is positioned on top of two of the silicon die such that one bus bar end is located on the substrate and the other end extends beyond the edge of the substrate. These busbars are generally parallel to each other and spaced apart by a distance that substantially corresponds to the positioning of the silicon die on the substrate. In operation, current flows into the semiconductor device through one of the bus bars, through the silicon die, and out of the device through the other bus bar.

One electrical characteristic that negatively impacts semiconductor device performance is its inductance. It is therefore desirable to reduce the inductance of the device without reducing its ability to conduct and convert current. In the above IGBT, the inductance is proportional to the area between the bus bars. Looking at the IGBT at a higher level, the individual silicon dies are connected to each other by bonding wires that also connect the individual silicon dies to one or more of the three leads extending from the housing. Bond wires typically form a loop between two silicon dies, or between a die and a lead. In this context, the inductance is proportional to the area under the loop of the bond wire. In this way, the efficiency of the semiconductor device can be improved by reducing the area between the bus bars or the area under the loop of the bonding wire.

Fig. 1 shows a cross-section of an example of a semiconductor device 100 having stacked planar terminals 120A-B. The device is implemented using a substrate 104. The substrate may be used to direct heat away from the device while at the same time electrically insulating the high voltage components. In some embodiments, the substrate comprises a Direct Bonded Copper (DBC) structure. For example, a DBC structure may include a ceramic layer sandwiched between copper layers as shown.

The semiconductor circuit is implemented on top of the substrate. Here, silicon dies 160A-B are shown. These silicon dies contain circuit devices that define a particular mode of operation for the overall semiconductor assembly. In some embodiments, the silicon die defines an IGBT device. For example, a silicon die may be fabricated as a chip (sometimes also referred to as a silicon chip) that is then mounted onto the top surface of a substrate.

In this example, the semiconductor device has stacked planar terminals 102A-B that abut silicon dies 106A-B, respectively. The stacked planar terminals have any length extending toward the left in the figure. Each terminal forms a complete plane, can be made of any conductive material, and can be soldered to its respective silicon die. The planar terminal 102A here abuts the silicon die 106A and is labeled positive (+) for reference. The planar terminal 102B here abuts the silicon die 106B and is marked negative (-) for reference. That is, the terminals are stacked on top of each other and the negative terminal overlaps the positive terminal in this example. A space 108 is formed here between the planar terminals.

In particular, because the silicon dies 106A-B lie in a common plane (on top of the substrate), the planar terminal 102B has an offset portion 110 along the entire width of the plane in order to provide a contact portion 112 that abuts the silicon die 106B. In some embodiments, the contact portion forms a plane that is parallel to and offset from a major portion of the planar terminal 102B. The offset portion may be formed using any suitable technique, such as by stamping or bending.

The housing 114 encloses at least a portion of the semiconductor device. The housing may have one or more openings. In some embodiments, the housings have a common opening 116 through which the planar terminals 102A-B extend. For example, after the substrate, the silicon die and planar terminals are assembled, and the housing may be injection molded over the assembly such that the terminals extend from the encapsulated structure.

An electrical insulator 118 may be disposed in the space between the planar terminals. The insulator provides electrical insulation across the entire width of the conductive sheets forming the respective planar terminals. In some embodiments, insulating paper is used.

That is, the semiconductor device 100 of the above example includes a housing 114, a substrate 104 within the housing, semiconductor circuits 106A-B on the substrate, and planar terminals 102A-B extending away from the housing and electrically connected to the first and second semiconductor circuits, respectively. Specifically, the planar terminals are stacked on each other.

Thus, inductance is currently proportional to the area between planar terminals 102A-B plus the area between terminal 102B and substrate 104, where the negative terminal overlaps the positive terminal. This may allow for a significant reduction in inductance compared to conventional device designs. For example, because the planar terminals abut the silicon die and also extend out of the housing, it is contemplated that the bus bar structure may be (at least partially) integrated within the housing. Some of the present embodiments may avoid attaching IGBT leads to an external bus bar layer and thus eliminate the need to form holes in the bus bar layer that increase inductance.

Fig. 2 shows a top view of the semiconductor device 100 in fig. 1. This shows how the planar terminals 102A abut the silicon die 106A and how the planar terminals 102B abut the silicon die 106B. Because the planar terminals are stacked on top of each other and one partially overlaps the other, the terminals 102A and the silicon dies 106A-B are shown in phantom. Terminal 102A is shown here as being narrower than terminal 102B merely to clarify the illustration. This arrangement provides increased bus bar width per die area, which improves performance. In some embodiments, the planar terminals overlap each other for a majority of their respective surface areas. Additional semiconductor circuits are also shown. In some embodiments, these additional semiconductor circuits include additional silicon dies 200A-B, which are also part of the semiconductor device. The planar terminals are attached to the respective silicon dies 106A-B and 200A-B by any suitable technique, including but not limited to soldering.

Fig. 3 illustrates a cross-section of another example of a semiconductor device 300 having stacked planar terminals 302A-B. The silicon die and the substrate may be substantially the same as above. However, the bus bars 304A-B that adjoin the respective silicon dies extend here in a common plane, rather than being stacked on top of each other. The bus bars 304A-B are substantially planar conductors that provide high voltage connections to the silicon die. Some or all of the bus bar 304A is exposed through an opening 306 in a housing 308, which housing 308 encloses at least a portion of the semiconductor device. Also, some or all of the bus bars 304B are exposed through openings 310 in the housing. For example, the opening may be formed as part of an injection molding process that encapsulates the device into an encapsulated structure.

Here, the planar terminal 302A abuts the bus bar 304A outside the housing. Likewise, planar terminal 302B abuts bus bar 304B, at least a portion of bus bar 304B being exposed through opening 310. For example, the planar terminal and the bus bar may be welded together. In some embodiments, the method may enable a simplified manufacturing process in which planar terminals-which may be sheets wide enough to span several IGBTs-may be easily aligned with and attached to bus bars of the device. In some embodiments, both bus bars may be exposed through the aperture in a similar manner as shown for bus bar 304B.

Similar to the previous example, the planar terminal 302B may have an offset portion that provides a contact portion-parallel to and offset from the main portion of the planar terminal-to touch at least a portion of its bus.

Electrical insulation 312 may be provided in the spaces between the planar terminals 302A-B. In some embodiments, the stacked structure of these planar terminals (with insulation) may be pre-assembled and then the assembly may be routed to the rest of the semiconductor device for electrical connection. As such, the present example may be considered to have the stack completed outside of the semiconductor package, rather than inside, which may simplify manufacturing.

Fig. 4 shows a perspective view of an assembly 400 of a semiconductor device 402 and a capacitor 404. Fig. 5 shows a cross-section of the assembly in fig. 4. In some embodiments, a capacitor is coupled to the semiconductor device to protect against transients and to help maintain the voltage on the DC bus. For example, a capacitor may be used as the dc link capacitor. Any form of capacitor conductor may be used, including, but not limited to, a film or foil (e.g., folded or rolled into a compact configuration).

Here, a set of six semiconductor devices 402 is shown, but more or fewer may be used in other embodiments. The semiconductor housing is omitted here for clarity. The semiconductor devices are arranged adjacent to each other in a row. Each device has a substrate 406 and bus bars 408A-B. The busbars are connected to corresponding semiconductor circuitry (e.g., a silicon die) on a substrate, which is not visible in this illustration. In particular, silicon dies may be positioned between respective bus bars 408A-B and the substrate 406.

The planar terminals 410A-B here comprise conductive strips that connect the capacitor 404 to each of the semiconductor devices through a bus bar. The planar terminals are stacked on each other such that planar terminal 410A abuts busbar 408A and planar terminal 410B abuts busbar 408B. At the other end of the planar terminals they are connected to the corresponding conductors of the capacitor. That is, each planar terminal connects a plurality of semiconductor devices to each of several capacitors. Fig. 4 also shows that the bus bars have a significant width compared to the semiconductor device as a whole (essentially the width of the substrate). For example, each of the bus bars may be at least 70% of the width of the semiconductor device.

One or more of the planar terminals 410A-B may have a stepped shape when viewed in profile. Here, the region of the planar terminal near the semiconductor device is substantially a flat plane. To accommodate the relative positions of the capacitor and the semiconductor device, planar terminal 410B (the "lower" portion of the terminal in this example) creates corners 412A-B to provide a contact plane 414B (in this example) for the bottom conductor of the capacitor. The planar terminal 410A may generate a corresponding corner to form a contact plane 414A for the opposing capacitor conductor.

The planar terminals provide a continuous conductive plane for current transfer to and from the capacitor. That is, because the edges of these sheets or pins that are electrically connected to the semiconductor device do not have holes, there is little or no "bottleneck" that impedes the flow of current.

The assembly 400 may form part of a power inverter. In some embodiments, the inverter may include two (or more) assemblies 400 in which semiconductor devices (e.g., IGBTs) are commonly controlled to perform dc-to-ac conversion. For example, two such assemblies may be oriented such that their respective semiconductor devices are in close proximity to each other, which may simplify the operation of arranging and cooling systems (e.g., liquid heat sinks).

An example of an assembly device will now be described. For illustrative purposes, the description will refer to some examples of the components described above. However, other components may be used instead of or in addition to these components.

The semiconductor devices (e.g., 402) are positioned in a row. Each of the semiconductor devices includes a substrate (e.g., 406), first and second semiconductor circuits (e.g., 106A-B) located on the substrate, and first and second bus bars (e.g., 408A-B) adjoining the first and second semiconductor circuits, respectively.

An assembly is formed by placing a first planar terminal (e.g., 410A) in contact with a first busbar (e.g., 408A) of each of the plurality of semiconductor devices and a second planar terminal (e.g., 410B) in contact with a second busbar (e.g., 408B) of each of the plurality of semiconductor devices. The first and second planar terminals are stacked on each other. For example, the terminals may be first stacked and then (as an assembled stack) placed in contact with the respective bus bars.

The first planar terminal is soldered to a first bus bar of each of the plurality of semiconductor devices. The welding is performed from one side of the assembly. The weld 416A from above the assembly is shown schematically here. Similarly, a second planar terminal is soldered to a second bus bar of each of the plurality of semiconductor devices. The welding is performed from the opposite side of the assembly. The weld 416B from below the assembly is shown schematically here. For example, laser welding may be used.

An electrically insulating layer (e.g., 118) may be included between the first and second planar terminals. For example, the insulating paper may be inserted before the terminals are stacked on each other.

Each of the first and second planar terminals may be electrically connected to a plurality of capacitors (e.g., 404). For example, respective contact planes of the terminals may be connected (e.g., soldered) to respective capacitor terminals.

More or fewer steps may be performed in some assembly processes. Also, two or more of the multiple steps may be performed in a different order.

Various embodiments have been described as examples. However, other embodiments may be covered by the following claims.

Claims (19)

1. A semiconductor device, comprising:

a housing;

a substrate within the housing;

a first semiconductor circuit and a second semiconductor circuit on the substrate; and

first and second planar terminals electrically connected to the first and second semiconductor circuits, respectively, the first and second planar terminals being stacked on one another with each of the first and second planar terminals extending away from the housing.

2. The semiconductor device of claim 1, wherein the first and second semiconductor circuits are positioned in a common plane on top of the substrate, wherein the first planar terminal abuts the first semiconductor circuit, wherein the second planar terminal is positioned on an opposite side of the first planar terminal from the first and second semiconductor circuits, wherein the second planar terminal includes a contact portion offset from a main portion of the second planar terminal by an offset portion, and wherein the contact portion abuts the second semiconductor circuit.

3. The semiconductor device of claim 2, wherein the housing has a common opening through which the first and second planar terminals extend away from the housing.

4. The semiconductor device of claim 2, further comprising an electrically insulating layer between the first planar terminal and at least the main portion of the second planar terminal.

5. The semiconductor device of claim 1, wherein the first and second semiconductor circuits are positioned in a common plane on top of the substrate, the semiconductor device further comprising:

a first bus bar abutting the first semiconductor circuit, wherein the first planar terminal abuts the first bus bar; and

a second bus bar abutting the second semiconductor circuit, wherein the second planar terminal abuts the second bus bar.

6. The semiconductor device of claim 5, wherein the first bus bar is planar and extends out through the housing, and wherein the first planar terminal abuts the first bus bar outside of the housing.

7. The semiconductor device of claim 5, wherein the second bus bar is planar and has a portion exposed through an opening in the housing.

8. The semiconductor device of claim 7, wherein the second planar terminal is positioned on an opposite side of the first planar terminal from the first and second bus bars, wherein the second planar terminal includes a contact portion offset from a major portion of the second planar terminal by an offset portion, and wherein the contact portion abuts the portion of the second bus bar.

9. The semiconductor device of claim 1, wherein the first and second planar terminals overlap each other for a majority of their respective surface areas.

10. The semiconductor device of claim 1, wherein each of the first and second planar terminals has a width that is at least 70% of a width of the semiconductor device.

11. An apparatus, comprising:

a plurality of semiconductor devices, each semiconductor device including a substrate, a first semiconductor circuit and a second semiconductor circuit on the substrate, and a first bus bar and a second bus bar adjoining the first semiconductor circuit and the second semiconductor circuit, respectively;

a capacitor; and

a first planar terminal and a second planar terminal electrically connected to the capacitor, the first and second planar terminals being stacked on each other, wherein the first planar terminal abuts the first busbar of each of the plurality of semiconductor devices, and wherein the second planar terminal abuts the second busbar of each of the plurality of semiconductor devices.

12. The apparatus of claim 11, further comprising a plurality of capacitors, wherein the first planar terminal and the second planar terminal are electrically connected to each capacitor of the plurality of capacitors.

13. The apparatus of claim 11, wherein each of the first and second planar terminals comprises a respective sheet extending between the capacitor and the plurality of semiconductor devices.

14. The device of claim 13, wherein at least one of the sheets has a step shape to provide a first contact plane distal to the capacitor.

15. The device of claim 14, wherein others of the sheets also have a step shape to provide a second plane of contact proximal to the capacitor.

16. A method, comprising:

positioning a plurality of semiconductor devices in a row, each of the plurality of semiconductor devices including a substrate, first and second semiconductor circuits on the substrate, and first and second bus bars abutting the first and second semiconductor circuits, respectively;

forming an assembly by placing a first planar terminal in contact with the first busbar of each of the plurality of semiconductor devices and a second planar terminal in contact with the second busbar of each of the plurality of semiconductor devices, the first and second planar terminals being stacked on each other;

soldering the first planar terminal to the first bus bar of each of the plurality of semiconductor devices, the soldering being performed from one side of the assembly; and

soldering the second planar terminal to the second bus bar of each of the plurality of semiconductor devices, the soldering being performed from an opposite side of the assembly.

17. The method of claim 16, further comprising: an electrically insulating layer is included between the first planar terminal and the second planar terminal.

18. The method of claim 16, further comprising electrically connecting each of the first and second planar terminals to a plurality of capacitors.

19. The method of claim 16, wherein the welding comprises laser welding.