HK1229065B - Split thin film capacitor for multiple voltages - Google Patents

Description

Split film capacitors for multiple voltages

Technical Field

Various embodiments described herein relate to capacitor designs, generally including thin film capacitors, for use with electronic devices such as integrated circuits.

Background Art

Many electronic devices have localized, transient current demands that cannot always be adequately supplied by the power supply, resulting in local voltage level shifts and potentially erroneous signal propagation. The use of capacitors in local power filtering applications within electrical and electronic devices is well known. However, as clock cycle rates in electronic devices continue to increase as devices become smaller, particularly in integrated circuits such as microprocessors and memory devices, the need for tightly coupled capacitors increases. Furthermore, as electronic devices become smaller, operating voltages need to be reduced in certain parts of the device to keep the electric field below critical levels that degrade device reliability. One approach to maintaining electronic device performance while reducing operating voltages in critical reliability areas is to operate with two power supplies of different supply voltage levels. For example, the internal logic of an integrated circuit (IC) may use the smallest transistors to achieve the fastest possible operating speed and, therefore, may require a low-voltage power supply, while the input and output (I/O) drivers at the periphery of the IC may use larger, more powerful transistors that require a high-voltage power supply and can withstand voltage levels higher than the small logic transistors can tolerate without compromising reliability. As a result of the two-supply voltage scenario just discussed, there may be a need for two different tightly coupled capacitors associated with the same integrated circuit chip. Using two different capacitors with different power supply levels may cause space problems for electronic devices such as in IC packages, so there is a need for a single capacitor with multi-voltage level capabilities. There is also a need for a capacitor with two independent power supplies to isolate noise.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a side view of an exemplary embodiment of the present invention;

FIG2 is a top view and a side view of another exemplary embodiment of the present invention;

FIG3 is a top view and a side view of another exemplary embodiment of the present invention;

FIG4 is a side view of a component using an embodiment of the present invention;

FIG5 is a block diagram of a system utilizing an embodiment of the present invention.

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings which form a part of the detailed description, in which, via an explanation of the principles of the present invention, specific embodiments of the means by which the present invention may be best implemented are shown. In the accompanying drawings, identical numerals in all the various views of the embodiments essentially describe similar components. These embodiments are described in sufficient detail to enable those skilled in the art to implement the present invention. Other embodiments of this disclosed principle may be used, and various structural and material changes may be made to the embodiments disclosed herein without departing from the spirit and principles of the present invention.

The terms "high" and "low," as used herein for dielectric constants (i.e., high-k and low-k), are relative terms referring to materials having dielectric constants relative to standard dielectric materials such as silicon dioxide and silicon nitride. When the terms "high" and "low" are used herein for voltages, they refer to relative values of the supply voltage, with the term "ground" referring to a reference voltage supply. The value of the "high" voltage will vary depending on various factors in the electrical system in which these embodiments may be implemented, such as the process and size of the integrated circuits found in the electrical system, as well as other such factors. For example, as ICs become smaller, they become more sensitive to the high voltage drop in the gate oxide of MOSFETs and junction breakdown of bipolar junction transistors, and operating voltages are often reduced to increase device lifetime.

Referring to FIG. 1 , a side view of the internal structure of a thin-film capacitor is shown. The capacitor comprises a substrate 100, typically made of a standard or low-value dielectric material (i.e., low-k), and a second dielectric layer 102 on the top surface. This second dielectric layer 102 is typically made of a low-k material to reduce signal crosstalk in the numerous electrical pathways and signal lines that traverse the substrate in various directions, such as a straight line from the top to the bottom. Side wiring connecting different parts of the device utilizes the top, interior, and bottom surfaces, creating external electrical contacts to other electrical devices and a printed circuit board (i.e., PCB). In this illustrative embodiment, numerous wires and vias 104 forming the top plate of the thin-film capacitor (i.e., TFC) and connecting it to the back side of substrate 100 are shown in cross section. Also shown are numerous wires and vias 106 forming the bottom plate of the TFC, embedded in second dielectric layer 102, and connecting it to the back side of substrate 100. A high-value (i.e., high-k) dielectric material 108 separates the two capacitor plates 104 and 106 to form a high-value capacitor. Any high-k material may be used as layer 108. Illustrative examples of high-k materials include barium strontium titanate, barium titanate, or strontium titanate, which is particularly useful if dielectric material 108 is a tape-cast ceramic. Numerous other high-k dielectric materials are known to those skilled in the art and may be used in the implementation of this embodiment depending on the material and process requirements for a particular application.

The schematic embodiment shown in FIG1 can be clearly extended to include vertical electrical conductors such as 110 to connect the top surface portions to external electronics using contacts on the top or bottom surfaces, and to connect portions of the TFC at one location on substrate 100 to other locations. For example, all upper capacitor electrode plate portions 104 can be connected together to form a large capacitor using horizontal electrical conductors on the bottom, top, or buried in substrate 100, by methods known to those skilled in the art. The combined top plate electrode lines can then be connected to vertical conductors 110 and, thereby, to an external power source via contacts on the top or bottom surfaces. Alternatively, the combined top plate electrode lines can be connected to external electronics via connection pads located on the bottom surface of substrate 100, without the need for vertical connectors 110. In a similar manner, using similar means as those described above, the buried bottom capacitor plates 106 can be connected together to form a large capacitor and connected to external electronics such as an IC or power supply via connections on the top or bottom surfaces.

The exemplary embodiment shown in FIG. 1 can be extended to include an arrangement in which the structures shown on the top surface of the substrate can also be formed on the bottom surface to provide a capacitor with substantially twice the area and capacitance within the same overall usable area of the electronic device to which the capacitor is attached. It should also be understood that vertical electrical conductors 110 are not limited to the single row shown surrounding the periphery of the capacitor, but can include multiple rows of vertical connectors and contacts, and can form an area array of connectors to reduce the resistance and inductance of the output and input currents. Thus, in the exemplary embodiment shown in FIG. 1 , by including electrical conductors such as vertical connectors 110, each of the upper capacitor plates 104 can be connected to a different voltage source, while the lower capacitor plates 106 can both be connected to a reference voltage to provide a reference voltage that can be referred to as ground. Alternatively, for various reasons, such as ground bounce isolation, the lower capacitor plate 106 can be connected to a separate reference voltage source, isolated from the upper capacitor plate 104. With this arrangement, two different supply voltages can be provided to a circuit such as an IC, which is useful when, for example, a low voltage level is provided to the smallest transistor logic components within the IC while a high voltage level is provided to the memory cache or input/output (i.e., I/O) components of the same IC.

FIG2 shows a top view of a thin-film capacitor (TFC) at the top of the diagram, with the upper capacitor plate schematically divided into two separate sections. In this illustrative example, the left side 202 of the capacitor is selected to provide an operating voltage level to the memory cache components of a tightly coupled electronic device, such as an IC mounted directly on top of the TFC. The right side 204 of the illustrative TFC is selected to provide a different operating voltage level to the voltage-sensitive logic core of the IC. Alternatively, due to synchronous switching issues or other design reasons, the two sides 202 and 204 can each provide internal IC signals that require electrical isolation from each other.

The detailed side view below FIG2 illustrates the area surrounding the upper capacitor plate spacer. In this illustrative example, the upper capacitor plate is shown as being divided into only two sections, and the lower capacitor plate 208 is shown as a single piece of electrical conductor. The embodiments described herein are clearly not limited to the illustrative example discussed above with reference to FIG1 , in which the lower capacitor plate is divided. The capacitor is formed on a substrate 210 and covered with a high-k dielectric material 206, which is shown as continuous in this illustrative example for simplicity. The choice of high-k dielectric material 206 will depend on the specific application in which the embodiment is used. For example, in the field of low-temperature co-fired ceramics, the high-k dielectric material may be barium strontium titanate or other similar materials. For simplicity, the high-k dielectric material 206 is shown as a single continuous layer, but the embodiments are not so limited, and the high-k dielectric layer may be broken down into multiple separate sections as is most useful for the specific application being implemented.

FIG3 shows an exemplary embodiment with a top view, which includes a region 302 selected to provide a lower power supply voltage level to the smallest transistor core logic region of an IC, and a region 304 selected to provide a higher, lower, or different power supply voltage level to the memory cache region of the same IC. As seen in the expanded top view, region 302 is arranged in this exemplary embodiment to provide two different lower power supply voltage levels to different regions of the IC's core region, using alternating stripes of capacitor plate conductors, such as stripe 306 having connections to different external power sources compared to stripe 308. For signal isolation purposes, the different power supplies can have the same voltage level and be independent of each other, or, depending on the specific needs of the application, the different power supplies can provide different voltage levels in response to operational differences in the transistors of each region. This same power supply isolation can also occur in region 304 selected for use by the IC's cache components. For example, the high-voltage power supply level region 304 can use two different power supply voltage levels for the cache component and the I/O component. I/O components in what is known as a BiCMOS process, or other I/O type devices, may use bipolar junction transistors as output devices and thus may require different power supply levels than cache MOS transistors.

As can be seen in the side view of the exemplary embodiment, the isolated conductor stripes 306 and 308 of the upper capacitor plate 302 are located on a high-k dielectric layer 310, which is shown as a continuous layer in FIG. 3 for simplicity. This embodiment should not be limited to the above illustration. In this exemplary embodiment, the bottom conductor forming the lower capacitor plate 312 is shown as separated into separate conductor stripes, each associated with a conductor strip of the upper capacitor plate 302. However, in many specific applications, an uninterrupted lower capacitor plate with the addition of a reference voltage supply (e.g., ground) may be a preferred approach. The lower capacitor plate conductor 312 is formed on a substrate 314, as previously disclosed in conjunction with the description of FIG. 1 and 2. The substrate 314 may also have via conductors, internal horizontal conductors, and/or another capacitor structure located on the bottom of the substrate 314, as just described.

With this arrangement, the high supply voltage level capacitors 304 can be provided to the cache area of the IC, while two different low voltage supply levels can be provided to portions of the internal core logic area using portions 306 and 308 of the low supply voltage capacitor region 302. By varying the relative sizes of stripes 306 to stripes 308, the amount of capacitance provided to different portions of the lower portion 302 can be easily adjusted to the needs of a particular application.

An alternative approach to controlling the amount of capacitance provided to different portions of the low voltage power supply region 302 or the high voltage power supply region 304 of the IC is shown in the side view at the bottom of FIG3 , which shows an illustrative embodiment having two different high-k dielectric layers 310 and 311. The amount of capacitance provided to different portions of the IC can still be controlled by varying the relative areas of the conductor stripes 306 and 308 as previously described, but with this illustrative arrangement, the thickness of the two high-k dielectric layers can also be varied, as shown, with layer 311 being shown as thinner than the other high-k dielectric layer 310, or the material used as the high-k dielectric can be different for the two layers, or a combination of both approaches can be used as appropriate for the specific application in which the embodiment is implemented.

In addition to the features already discussed, the stacked capacitor arrangement of the exemplary embodiment shown in FIG3, substrate 314 can have vertical through-hole connectors, internal conductors, and capacitor structures formed on the top and bottom sides as previously discussed with respect to FIG1 and 2 and with respect to the side-by-side stripe embodiment.

FIG4 illustrates an exemplary embodiment of a TFC for use with a direct IC mount. TFC capacitor 402 is shown with an organic substrate 404, which may be a multilayer printed circuit board, and with a top-formed capacitor 406 and a bottom-formed capacitor 408. The capacitors may also be embedded within the substrate. The top and bottom capacitors can be connected in various ways. For example, they can be completely isolated from each other and adapted to different portions of a mounted IC 412, or they can be interconnected to essentially double the available capacitance, or any combination of connections required for the specific application in which the TFC is being used.

The bottom surface of the TFC capacitor 402 has a plurality of connection pads that may be connected to external contacts. For example, the exemplary embodiment shows an area array of pins 410 for connecting to a through-hole printed circuit board. Alternative connections may include gull-wing wires for surface mount applications, ball grid arrays, or connector pins such as the full grid socket (i.e., FGS) shown in the figure.

In this illustrative embodiment, the top surface of TFC capacitor 402 has an area array of connection pads arranged to receive and solder a packaged IC 412 using an array of solder balls 414. Alternative connection methods may include flip-chip mounting of an unpackaged silicon die using plated solder or gold pads, or surface mounting of an IC package with ceramic leads and an attached heat sink.

With this arrangement, IC 412 has short electrical connections from various portions of TFC capacitor 402 to any desired number of different power or reference supply voltage sources. TFC capacitor 402 can also advantageously be used to provide a means for attaching IC 412 to an electronic device using electrical connection pins 410. This arrangement can have the advantage of allowing more complete testing of IC 412 prior to assembly into a complete electronic device due to the proper placement of the capacitance required for full-speed IC testing.

FIG5 is a block diagram of a product 502, such as a communication network, a computer, a memory system, a magnetic or optical disk, some other information storage device, and/or any other type of electronic device or system, according to various embodiments. Product 502 may include a processor 504 coupled to a machine-accessible medium, such as a memory 506 storing relevant information (e.g., computer program instructions 508 and/or other data), and input/output drivers 510 connected to external electrical or electronic devices via various means, such as a bus or cable 512, which, when accessed, cause the machine to perform actions, such as calculating the answer to a mathematical problem. Various components of product 502, such as processor 504, may have transient current issues that could benefit from using this embodiment to mitigate and smooth out current variations using tightly coupled capacitors. As an illustrative example, processor 504 may be advantageously packaged in a ceramic package directly on top of a TFC, as previously discussed and illustrated in FIG4 . This embodiment may be applied to any component of product 502 other than processor 504.

As another illustrative example, product 502 may be a system of communication network elements, such as a communication network element, attached to other network elements (not shown) via bus cable 512. The communication network may include multiple coupled network elements interconnected by a bus, such as cable 512 shown in the figure. The network elements may include dipole antennas, unidirectional antennas, or other forms of wireless interconnection capabilities, used in place of or in addition to wired cable 512. Among the various elements shown in the illustrative communication network may be electronic circuits that can benefit from using the illustrative embodiments of the TFC described above. Electronic circuits in the communication network that can benefit from the described tightly coupled TFC may include a local microprocessor 504 and external line drivers, such as input/output driver 510, shown sending signals along cable 512. Depending on the specific application or use of the system, this embodiment may be advantageous for any individual component of the illustrated system.

As another illustrative example, product 502 may alternatively be a computer system having multiple components, including a computing element 504 such as a microprocessor, a memory element 506 storing program code 508, a communication element, and an input/output driver element 510. The system may be connected to other computer systems via a bus or cable 512 or via a wireless connection (not shown). One or more of these components may benefit from the use of the TFC described above, particularly I/O driver 510 and/or computing element 504, both of which may have transient current issues that a tightly coupled TFC can improve. Depending on the application, this embodiment may be advantageous for any individual component in the system. In various other examples using capacitors, this embodiment may also be useful for more than one, or any number of, such capacitors in each of these components, including components such as charge pumps, filters, RF applications, and differential AC couplers.

The accompanying drawings, which form a part of the detailed description, illustrate, by way of illustration and not limitation, specific embodiments that implement the disclosed subject matter. The illustrated embodiments are described in sufficient detail to enable one skilled in the art to practice the teachings disclosed herein. Other embodiments may be utilized or derived therefrom, allowing for structural and logical substitutions and variations without departing from the spirit of the disclosure. Therefore, this detailed description is not to be construed in a limiting sense, but rather to entitle the invention to the spirit of the various embodiments as defined solely by the appended claims and all equivalents.

For convenience only, embodiments of these inventive subject matters may be referred to herein individually or collectively as the term "invention," and if more than one subject matter is actually disclosed, it is not intended to arbitrarily limit the spirit of this application to any single invention or inventive concept. Thus, although specific embodiments have been illustrated and described herein, it should be understood that any device calculated to achieve the same purpose may be substituted for the specific embodiments shown. This disclosure is intended to cover any and all modifications or variations of the various embodiments. Combinations of the above embodiments, as well as other embodiments, not described individually herein, will be apparent to those skilled in the art upon reviewing the above description.

In compliance with 37 C.F.R. §1.72(b), requiring an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure, an abstract of the disclosure is provided. It is submitted with the understanding that the abstract is not intended to interpret or limit the meaning of the claims. Additionally, in the foregoing Detailed Description, various features may be grouped together in a single embodiment for the purposes of streamlining the disclosure and enhancing its clarity. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than expressly recited in each claim. Rather, as reflected in the following claims, inventive subject matter lies in less than all features of a single disclosed embodiment. Accordingly, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.

Claims (21)

1. An electronic device, comprising: A substrate, the substrate including a top surface, a bottom surface, a plurality of electrical pathways connecting selected portions of the top surface to selected portions of the bottom surface, and a plurality of electrical connections arranged to connect at least one external circuit; and At least one surface includes at least two types of multiple electrodes, each multiple electrode being electrically isolated from the other multiple electrodes by at least one dielectric layer. The multiple electrodes include a first multiple electrode, a second multiple electrode, and a third multiple electrode. The second multiple electrode is located between the first multiple electrode and the third multiple electrode. Multiple contact holes pass through the second multiple electrode through gaps. At least one of the first multiple electrodes is connected to a first contact hole in the multiple contact holes, and at least one of the third multiple electrodes is connected to a second contact hole in the multiple contact holes. 2. The electronic device of claim 1, wherein at least one of the plurality of electrodes comprises at least two portions, each portion being connected to a different power source. 3. The electronic device of claim 1, wherein at least one of the dielectric layers is a high dielectric constant material, the high dielectric constant material comprising one or more materials selected from the group consisting essentially of barium strontium titanate, barium titanate, strontium titanate and mixtures thereof. 4. The electronic device of claim 1, wherein a plurality of electrical connections arranged to connect at least one external circuit are respectively electrically connected to one of a plurality of flip-chip mounting pads on the integrated circuit. 5. The electronic device of claim 1, wherein the electrical connection comprises an array of connectors selected from the group consisting of pins, solder blocks, wires, and mixtures thereof. 6. The electronic device of claim 1, wherein the electrical connection comprises a peripheral array having at least one row of coaxial conductors. 7. The electronic device of claim 1, wherein the substrate is substantially composed of monocrystalline silicon, polycrystalline silicon, glass, monocrystalline oxide, semiconductor material, metal foil, ribbon casting ceramic, inorganic polymer, organic polymer and mixtures thereof. 8. An electronic system comprising: Multiple coupling elements, including dipole antennas and electronic circuitry; The electronic circuit includes a substrate, the substrate including a top surface, a bottom surface, a plurality of electrical pathways connecting selected portions of the top surface to selected portions of the bottom surface, and a plurality of electrical connections arranged to connect at least one external circuit; and At least one surface includes at least two types of multiple electrodes, each multiple electrode being electrically isolated from the other multiple electrodes by at least one dielectric layer. The multiple electrodes include a first multiple electrode, a second multiple electrode, and a third multiple electrode. The second multiple electrode is located between the first multiple electrode and the third multiple electrode. Multiple contact holes pass through the second multiple electrode through gaps. At least one of the first multiple electrodes is connected to a first contact hole in the multiple contact holes, and at least one of the third multiple electrodes is connected to a second contact hole in the multiple contact holes. 9. The electronic system of claim 8, wherein at least one plurality of electrodes comprises at least two parts, each part being connected to a different power source. 10. The electronic system of claim 8, wherein at least one of the dielectric layers is a high dielectric constant material, the high dielectric constant material comprising one or more materials selected from barium strontium titanate, barium titanate, and strontium titanate. 11. The electronic system of claim 8, wherein the plurality of electrical connections arranged to connect at least one external circuit are respectively electrically connected to one of a plurality of flip-chip mounting pads on the integrated circuit. 12. The electronic system of claim 8, wherein the electrical connection comprises an array of connectors selected from the group consisting of pins, solder blocks, wires, and mixtures thereof. 13. The electronic system of claim 8, wherein the electrical connection comprises a peripheral array of wires. 14. The electronic system of claim 8, wherein the substrate comprises monocrystalline silicon, polycrystalline silicon, amorphous silicon, glass, doped glass, monocrystalline metal oxide, semiconductor material, metal foil, ribbon casting ceramic, inorganic polymer, organic polymer, and mixtures thereof. 15. A computer system comprising: A plurality of elements, including at least computing elements, memory elements, communication elements, and input/output elements, at least one of which includes a substrate, the substrate including a top surface, a bottom surface, a plurality of electrical pathways connecting selected portions of the top surface to selected portions of the bottom surface, and a plurality of electrical connections arranged to connect to at least one external circuit; and At least one surface includes at least two types of multiple electrodes, each multiple electrode being electrically isolated from the other multiple electrodes by at least one dielectric layer. The multiple electrodes include a first multiple electrode, a second multiple electrode, and a third multiple electrode. The second multiple electrode is located between the first multiple electrode and the third multiple electrode. Multiple contact holes pass through the second multiple electrode through gaps. At least one of the first multiple electrodes is connected to a first contact hole in the multiple contact holes, and at least one of the third multiple electrodes is connected to a second contact hole in the multiple contact holes. 16. The computer system of claim 15, wherein at least one plurality of electrodes comprises at least two portions, each portion being connected to a different power source. 17. The computer system of claim 15, wherein at least one of the dielectric layers is a high dielectric constant material, the high dielectric constant material comprising one or more materials selected from the group consisting substantially of barium strontium titanate, barium titanate, strontium titanate and mixtures thereof. 18. The computer system of claim 15, wherein a plurality of electrical connections arranged to connect at least one external circuit are respectively electrically connected to one of a plurality of flip-chip mounting pads on an integrated circuit. 19. The computer system of claim 15, wherein the electrical connection comprises an array of connectors selected from the group consisting of pins, solder blocks, wires, and mixtures thereof. 20. The computer system of claim 15, wherein the electrical connection comprises a peripheral array having at least one row of coaxial conductors. 21. The computer system of claim 15, wherein the substrate is substantially composed of monocrystalline silicon, polycrystalline silicon, glass, monocrystalline oxide, semiconductor material, metal foil, ribbon casting ceramic, inorganic polymer, organic polymer, and mixtures thereof.