HK1225545A1 - Compensation for dual conversion gain high dynamic range sensor - Google Patents

Abstract

The subject application is directed to compensation for dual conversion gain high dynamic range sensor. An image sensor, readout circuitry for an image sensor, and a method of operating readout circuitry are disclosed. Readout circuitry includes an analog-to-digital-converter ("ADC") including input stage circuitry with a first selectable input and a second selectable input. The ADC is coupled to sequentially receive a first reset signal, a second reset signal, a high gain image signal, and a low gain image signal, in that order. The input stage circuitry is configured to select the first selectable input when receiving the first reset signal and the low gain image signal and select the second selectable input when receiving the second reset signal and the high gain image signal.

Description

Compensation for dual conversion gain high dynamic range sensor

Technical Field

The present disclosure relates generally to optics, and more particularly to high dynamic range sensors.

Background

Standard image sensors have a limited dynamic range of approximately 60 to 70 dB. However, the real world luminance dynamic range is much larger. Natural scenes typically span a range of 90dB and above. To capture highlights and shadows simultaneously, high dynamic range ("HDR") techniques have been used in image sensors to increase the captured dynamic range. The most common technique for increasing the dynamic range is to merge multiple exposures captured using a standard (low dynamic range) image sensor into a single linear HDR image that has a much larger dynamic range than the single exposure image.

One of the most common HDR sensor solutions would be to have multiple exposures into one single image sensor. With different exposure integration times or different sensitivities (e.g., by inserting neutral density filters), one image sensor may have 2, 3, 4, or even more different exposures in a single image sensor. Multiple exposure images can be obtained in a single shot using this HDR image sensor. However, using this HDR sensor reduces the overall image resolution compared to a normal full resolution image sensor. For example, for an HDR sensor that combines 4 different exposures in one image sensor, each HDR image would only be one-quarter resolution of the full resolution image. Accordingly, improved HDR imaging techniques, including new pixels and readout architectures and techniques, are desired.

Disclosure of Invention

In one aspect, the present application relates to an image sensor. The image sensor includes: an array of pixels; control circuitry coupled to the pixel array for facilitating image acquisition, wherein pixels in the pixel array are configured to sequentially generate a first reset signal at a first conversion gain, a second reset signal at a second conversion gain greater than the first conversion gain, a high-gain image signal at the second conversion gain, and a low-gain image signal at the first conversion gain in the following order; and a successive approximation register ("SAR") analog-to-digital converter ("ADC") including an input stage circuit having a first selectable input and a second selectable input, wherein the SAR ADC is coupled to sequentially receive the first reset signal, the second reset signal, the high-gain image signal, and the low-gain image signal in that order, and wherein the input stage circuit is configured to select the first selectable input when receiving the first reset signal and the low-gain image signal, and is configured to select the second selectable input when receiving the second reset signal and the high-gain image signal.

In another aspect, the present application relates to a readout circuit for an image sensor. The readout circuit includes: a plurality of successive approximation register ("SAR") analog-to-digital converters ("ADC"), including an input stage circuit having a first selectable input and a second selectable input, wherein the SAR ADC is coupled to sequentially receive a first reset signal, a second reset signal, a high gain image signal, and a low gain image signal in that order, and wherein the input stage circuit is configured to select the first selectable input when receiving the first reset signal and the low gain image signal, and is configured to select the second selectable input when receiving the second reset signal and the high gain image signal, wherein an input stage circuit is for coupling to a bitline of a pixel array, and wherein each of the plurality of SAR ADCs includes an output for transmitting a digital conversion of the first reset signal, the second reset signal, the high gain image signal, and the low gain image signal.

In another aspect, the present application relates to a method. The method comprises the following steps: sequentially receiving, at an input stage circuit, a first reset signal, a second reset signal, a high-gain image signal, and a low-gain image signal in the following order, wherein the first reset signal and the low-gain image signal are generated by an image sensor pixel at a first conversion gain, and wherein the second reset signal and the high-gain image signal are generated by the image sensor pixel at a second conversion gain that is greater than the first conversion gain; selecting a first selectable input of the input stage circuit to amplify and output for comparison by an analog-to-digital converter ("ADC") when the first reset signal and the low-gain image signal are received by the input stage circuit; and selecting a second selectable input of the input stage circuit to amplify and output for comparison by the ADC when the second reset signal and the high gain image signal are received by the input stage circuit.

Drawings

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

FIG. 1 is a block diagram schematically illustrating one example of an imaging system including a high dynamic range ("HDR") pixel array and readout circuitry coupled to readout the HDR pixel array, according to an embodiment of the invention.

FIG. 2 is an example schematic of an HDR image pixel according to an embodiment of the present disclosure.

FIG. 3A illustrates an example analog-to-digital converter ("ADC") including an input stage circuit coupled to receive signals from the HDR image pixels of FIG. 2, according to an embodiment of the invention.

FIG. 3B illustrates an example differential amplifier with selectable inputs, according to an embodiment of the invention.

FIG. 3C includes an example regenerative latch for coupling to the differential amplifier of FIG. 3B, according to an embodiment of the invention.

FIG. 4 shows a timing diagram for operating the ADC of FIG. 3A, according to an embodiment of the invention.

Detailed Description

Embodiments of an image sensor and a method of reading out a pixel array of an image sensor are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of embodiments. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases such as "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Fig. 1 is a block diagram schematically illustrating one example of an imaging system 100, the imaging system 100 including a high dynamic range ("HDR") pixel array 102 and readout circuitry 104 coupled to readout the HDR pixel array 102, according to an embodiment of the invention. The imaging system 100 includes an HDR pixel array 102, control circuitry 108, readout circuitry 104, and functional logic 106. As shown in the depicted example, the HDR pixel array 102 is coupled to the control circuitry 108 and the readout circuitry 104. The sensing circuit 104 is coupled to functional logic 106. The control circuitry 108 is coupled to the pixel array 102 to control operating characteristics of the HDR pixel array 102 in order to capture an HDR image produced by image light received by the HDR pixel array 102. For example, the control circuitry 108 may generate a shutter signal or shutter signals for controlling image acquisition. The control circuitry 108 is also coupled to the readout circuitry 104 such that the control circuitry 108 can coordinate image acquisition of the HDR pixel array 102 with readout of the HDR pixel array 102.

In one example, the HDR pixel array 102 is a two-dimensional (2D) array of HDR pixels 110 (e.g., pixels P1, P2 …, Pn). In one example, each HDR pixel 110 is readout with dual conversion gain to achieve HDR imaging. As illustrated, each HDR pixel 110 is arranged in rows (e.g., rows R1-Ry) and columns (e.g., columns C1-Cx) to capture image data of a person, location, object, etc., which can then be used to render an image of the person, location, object, etc.

In one example, after each HDR pixel 110 has acquired its image data or image charge, the image data is read out by readout circuitry 104 through bit lines 112 (which may be column lines) and then transferred to functional logic 106. In various examples, the readout circuitry 104 may include amplification circuitry, analog-to-digital (ADC) conversion circuitry, or others. Function logic 106 may simply store the image data or even manipulate the image data by applying post-image effects (e.g., crop, rotate, remove red-eye, adjust brightness, adjust contrast, or otherwise). In one example, readout circuitry 104 can readout a row of image data at a time along readout column lines.

Fig. 2 is an example schematic diagram of an HDR image pixel 210 employing dual conversion gain readout to achieve HDR imaging, according to the teachings of this disclosure. It should be noted that the pixel 210 of fig. 2 may be one of the examples of the pixel 110 of fig. 1. In fig. 2, pixel 210 includes photodetector PD 205 coupled to transfer transistor 291, transfer transistor 291 being coupled to be controlled by TX signal 281. Transfer transistor 291 is coupled to a Floating Diffusion (FD) node 207.

In the depicted example, the Floating Diffusion (FD) node 207 is coupled to be reset to the RFD signal voltage by a reset transistor 294 and a DFD transistor 292. In the illustrated example, reset transistor 294 is coupled to be controlled in response to RST signal 284, and DFD transistor 292 is coupled to be controlled in response to DFD signal 282. The example illustrated in fig. 2 also illustrates that the in-pixel capacitor C233 is coupled to the Floating Diffusion (FD) node through the DFD transistor 292 in response to the DFD signal 282. In other words, the floating diffusion node 207 has increased capacitance when the DFD signal 282 activates the DFD transistor 292.

Continuing with the example depicted in fig. 2, the floating diffusion node 207 is also coupled to a control terminal of an amplifier transistor 297, which in fig. 2 is a Source Follower (SF) coupled transistor having its gate terminal coupled to the Floating Diffusion (FD) node. In the depicted example, a row select transistor 293 controlled using an RS signal 283 is coupled between a voltage source terminal and a drain terminal of a Source Follower (SF) transistor 297. In the depicted example, the source terminal of the Source Follower (SF) transistor is coupled to VPIX output 299, VPIX output 299 is an output bitline of pixel 210, and the output signal of pixel 210 is read out through the output bitline of pixel 210.

In operation, when the PD 205 accumulates image charge in response to incident image light, the floating diffusion 207 is reset by enabling the transistor DFD 292 and enabling the reset transistor 294. Then, the first reset signal of FD 207 is transferred onto VPIX 299 while transistor DFD 292 is enabled (and transistor RST 294 is disabled). When DFD 292 is enabled, FD 207 is coupled to capacitor 233 and thus reads out the first reset signal at low conversion gain. The transistor DFD 292 is then disabled to decouple the capacitor 233 from the FD 207. With the capacitor 233 decoupled from the FD 207, the second reset signal of the FD 207 is transferred onto VPIX 299. Since the FD 207 is decoupled from the capacitor 233 when the second reset signal is transferred onto VPIX 299, the second reset signal is read out at a high conversion gain.

After readout of the first and second reset signals, the transfer transistor 291 is enabled (pulsed) to transfer image charges accumulated in the PD 205 from the PD 205 to the FD 207. The high-gain image signal associated with the image charge in the FD 207 is transferred onto VPIX 299 while the transistor DFD is disabled, meaning that the high-conversion image signal associated with the image charge in the FD 207 is sampled at a high conversion gain. Then, the transistor DFD 292 is enabled to couple the capacitor 233 to the FD 207. When the capacitor 233 is coupled to the FD 207, the low-gain image signal associated with the image charge in the FD 207 is transferred onto VPIX 299, meaning that the low-gain image signal associated with the image charge in the FD 207 is sampled at a low conversion gain. As described above, the pixel 210 sequentially generates the first reset signal (at a low conversion gain), the second reset signal (at a high conversion gain), the high-gain image signal (at a high conversion gain), and the low-gain image signal (at a low conversion gain) in the following order.

FIG. 3A illustrates an example analog-to-digital converter ("ADC") 300 that includes an input stage circuit 330 coupled to receive signals from HDR image pixels 210, according to an embodiment of this disclosure. At V by ADC 300_IN323 receive a first reset signal, a second reset signal, a high gain image signal and a low gain image signal. VPIX 299 can be directly coupled to V_IN323. Sample and hold switch SHX 325 is opened and closed to sample a signal onto the input of input stage circuit 330. The input stage circuit 330 includes a differential amplifier 335, the differential amplifier 335 having a first input N1331, a second input N2332, a third input P1333, and a fourth input P2334. The outputs of the different amplifiers 335 are VON 337 and VOP 338. Latch 340 is coupled to generate outputs D-342 and D +342 in response to receiving VON 337 and VOP 338 from differential amplifier 335. Successive approximation register ("SAR") 370 is coupled to reset at reset node 371 in response to receiving a digital high signal on D-342. SAR 370 is coupled to binary-weighted capacitor array 380, binary-weighted capacitor array 380 is coupled to input node 326, and input node 326 is coupled to first input 331 and second input 332 of input stage circuit 330 via capacitors.

FIG. 3B illustrates an example differential amplifier 335 with selectable inputs according to an embodiment of the invention. When the signal DCG 339 is digital low, the switches over the inputs N1331 and P1333 are closed and the differential amplifier amplifies the signals on the inputs N1331 and P1333. Inputs N1331 and P1333 are a first pair of inputs to the differential amplifier 335. When signal DCG 339 is a digital high, the switches over inputs N2332 and P2334 are closed and the differential amplifier amplifies the signals on inputs N2332 and P2334. Inputs N2332 and P2334 are a second pair of inputs to differential amplifier 335.

Fig. 3C includes an example regenerative latch 340 for coupling to a differential amplifier 335 according to an embodiment of the invention. Regenerative latch 340 is coupled to generate outputs D-342 and D +342 in response to receiving VON 337 and VOP 338 from differential amplifier 335. In one embodiment, regenerative latch 340 has 12-bit resolution.

Fig. 4 shows a timing diagram for operating the ADC 300, according to an embodiment of the invention. The signals shown in fig. 4 may be controlled by the control circuit 108 and/or by the readout circuit 104. At time t0, DAC _ RST 327 is pulsed to reset/discharge binary weighted capacitor array 380. At time t1, SHX 425 goes high, which closes SHX gate 325 and drives the first reset signal (generated at low conversion gain) from V_IN323 to the input node 326. Also at time t1, the CMP _ RST 1461 signal goes high, closing the CMP _ RST 1361 gate and resetting the voltages of inputs N1331 and P1333 to outputs VON 337 and VOP 338, respectively. Since signal DCG 439 is low, inputs N1331 and P1333 are valid inputs to differential amplifier 335 at time t 1. At time t2, the CMP _ RST 1461 signal goes low, which turns off the CMP _ RST 1361 switch and the differential amplifier amplifies the first reset signal (generated at low conversion gain) on input N1331 onto its output, and sets the amplified version of the first reset signal on the regenerative latch 340 for comparison and digital conversion by the ADC. At time t3, signal SHX 425 goes low, which closes SHX gate 325. Also at time t3, signal DCG 439 goes high, which switches the inputs of differential amplifier 335 from N1331 and P1333 (the first pair of inputs) to N2332 and P2334 (the second pair of inputs).

At time t4, SHX 425 again goes high, closing SHX gate 325 and driving the second reset signal (generated at high conversion gain) from V_IN323 to the input node 326. Also at time t4, the CMP _ RST 2462 signal goes high, closing the CMP _ RST2362 gate and resetting the voltages of inputs N2332 and P2334 to outputs VON 337 and VOP 338, respectively. At time t5, the CMP _ RST 2462 signal goes low, which turns off the CMP _ RST2362 switch and the differential amplifier amplifies the second reset signal (generated at high conversion gain) on input N2333 onto its output and sets the amplified version of the second reset signal on the regenerative latch 340 for comparison and digital conversion by the ADC. At time t6, signal SHX 425 goes low, which closes SHX gate 325. Thus, the ADC 300 has the advantage of having a replicated input stage in the input stage circuit 330A potential that enables the two reset levels at both high and low conversion gains to be sampled. Since the signal DCG 439 selects between the first pair of inputs (N1331 and P1333) and the second pair of inputs (N2332 and P2334), a duplicated input stage is possible by having the differential amplifier 335 include selectable inputs.

At time t7, SHX 425 again goes high, closing SHX gate 325 and driving the high-gain image signal (generated at high conversion gain) from V_IN323 to the input node 326. Since DCG 439 is still high, the second pair of inputs N2332 and P2334 are still valid inputs to differential amplifier 335. The differential amplifier 335 amplifies the high-gain image signal (generated at high conversion gain) on input N2333 onto its output and sets the amplified version of the high-gain reset signal on the regenerative latch 340 for comparison and digital conversion by the ADC. At time t8, signal SHX 425 goes low, which closes SHX gate 325.

Also at time t8, DCG 439 goes low, which selects the first pair of inputs N1331 and P1333 as the active inputs of differential amplifier 335. At time t9, SHX 425 again goes high, which closes SHX gate 325 and changes the low-gain image signal (at low conversion gain) from V_IN323 to the input node 326. Differential amplifier 335 amplifies the low-gain image signal (generated at low conversion gain) on input N1331 onto its output and sets the amplified version of the low-gain reset signal on regenerative latch 340 for comparison and digital conversion by the ADC. At time t10, signal SHX 425 goes low, which closes SHX gate 325.

As shown in FIG. 4, the difference between the first reset voltage and the second reset voltage is Δ V_RST451. The correlated double sampling ("CDS") value at high conversion gain for pixel 210 is shown as Δ V_{CDS_HI}452 while the CDS value at low conversion gain of pixel 210 is shown as av_{CDS_LO}453. Δ V can be made by low conversion gain_{CDS_LO}453 to produce a digital image signal of the pixel 210 at a low conversion gain, whereas av may be made by a high conversion gain_{CDS_HI}452 are multiplied to produce a digital image signal of the pixel 210 at a high conversion gain.

The process explained above is described in terms of computer software and hardware. The described techniques may constitute machine-executable instructions embodied within a tangible or non-transitory machine (e.g., computer) readable storage medium, that when executed by a machine will cause the machine to perform the operations described. Additionally, the processes may be embedded within hardware, such as an application specific integrated circuit ("ASIC") or otherwise.

A tangible, non-transitory machine-readable storage medium includes any mechanism that provides (i.e., stores) information in a form accessible by a machine (e.g., a computer, network device, personal digital assistant, manufacturing tool, any device with a set of one or more processors, etc.). For example, a machine-readable storage medium includes recordable/non-recordable media (e.g., Read Only Memory (ROM), Random Access Memory (RAM), magnetic disk storage media, optical disk storage media, flash memory devices, etc.).

The foregoing description of illustrated embodiments of the invention, including what is described in the abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.

These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims (19)

1. An image sensor, comprising:

an array of pixels;

control circuitry coupled to the pixel array for facilitating image acquisition, wherein pixels in the pixel array are configured to sequentially generate a first reset signal at a first conversion gain, a second reset signal at a second conversion gain greater than the first conversion gain, a high-gain image signal at the second conversion gain, and a low-gain image signal at the first conversion gain in the following order; and

a successive approximation register, SAR, analog-to-digital converter, ADC, comprising an input stage circuit having a first selectable input and a second selectable input, wherein the SAR ADC is coupled to sequentially receive the first reset signal, the second reset signal, the high gain image signal, and the low gain image signal in the following order, and wherein the input stage circuit is configured to select the first selectable input when receiving the first reset signal and the low gain image signal, and configured to select the second selectable input when receiving the second reset signal and the high gain image signal.

2. The image sensor of claim 1, wherein the input stage circuit includes a differential amplifier including the first and second selectable inputs.

3. The image sensor of claim 2, wherein the first selectable input is included in a first pair of selectable inputs and the second selectable input is included in a second pair of selectable inputs, and wherein the first pair of selectable inputs is coupled to be reset by a first reset signal, the second pair of selectable inputs is coupled to be reset by a second reset signal separate from the first reset signal.

4. The image sensor of claim 1, wherein the SAR ADC comprises:

a binary weighted capacitor array coupled to an input node, wherein the first selectable input and the second selectable input are also coupled to the input node, and wherein the input node is coupled to a sample and hold switch; and

a successive approximation register SAR coupled to the binary-weighted capacitor array.

5. The image sensor of claim 4, wherein the SAR ADC includes:

a regenerative latch coupled between an output of the input stage circuit and an input of the SAR.

6. The image sensor of claim 1, wherein the pixel array includes pixels arranged in rows and columns.

7. The image sensor of claim 1, wherein the image sensor includes a plurality of the SAR ADCs, and wherein each of the plurality of SAR ADCs is coupled to a column of the pixel array itself.

8. The image sensor of claim 1, wherein the input stage circuit is configured to sequentially output the first reset signal, the second reset signal, a difference between the second reset signal and the low-gain image signal, and a difference between the first reset signal and the high-gain image signal in the following order in response to sequentially receiving the first reset signal, the second reset signal, the high-gain image signal, and the low-gain image signal in the following order.

9. A readout circuit for an image sensor, the readout circuit comprising:

a plurality of Successive Approximation Register (SAR) analog-to-digital converter (ADC) including an input stage circuit having a first selectable input and a second selectable input, wherein the SAR ADC is coupled to sequentially receive a first reset signal, a second reset signal, a high gain image signal, and a low gain image signal in that order, and wherein the input stage circuit is configured to select the first selectable input when receiving the first reset signal and the low gain image signal, and configured to select the second selectable input when receiving the second reset signal and the high gain image signal,

wherein an input stage circuit is for coupling to a bitline of a pixel array, and wherein each of the plurality of SAR ADCs includes an output for transmitting a digital conversion of the first reset signal, the second reset signal, the high gain image signal, and the low gain image signal.

10. The readout circuit of claim 9, wherein the input stage circuit includes a differential amplifier including the first and second selectable inputs.

11. The readout circuit of claim 10, wherein the first selectable input is included in a first pair of selectable inputs and the second selectable input is included in a second pair of selectable inputs, and wherein the first pair of selectable inputs is coupled to be reset by a first reset signal, the second pair of selectable inputs is coupled to be reset by a second reset signal separate from the first reset signal.

12. The readout circuit of claim 9, wherein each of the plurality of SAR ADCs comprises:

a binary weighted capacitor array coupled to an input node, wherein the first selectable input and the second selectable input are also coupled to the input node, and wherein the input node is coupled to a sample and hold switch; and

a successive approximation register SAR coupled to the binary-weighted capacitor array.

13. The readout circuit of claim 12, wherein the SAR ADC comprises:

a regenerative latch coupled between an output of the input stage circuit and an input of the SAR.

14. A method, comprising:

sequentially receiving, at an input stage circuit, a first reset signal, a second reset signal, a high-gain image signal, and a low-gain image signal in the following order, wherein the first reset signal and the low-gain image signal are generated by an image sensor pixel at a first conversion gain, and wherein the second reset signal and the high-gain image signal are generated by the image sensor pixel at a second conversion gain that is greater than the first conversion gain;

selecting a first selectable input of the input stage circuit for amplification and output for comparison by an analog-to-digital converter (ADC) when the first reset signal and the low-gain image signal are received by the input stage circuit; and

selecting a second selectable input of the input stage circuit to amplify and output for comparison by the ADC when the second reset signal and the high gain image signal are received by the input stage circuit.

15. The method of claim 14, wherein the input stage circuit includes a differential amplifier including the first and second selectable inputs.

16. The method of claim 15, further comprising:

resetting a first pair of selectable inputs prior to receiving the second reset signal and not resetting the first pair of selectable inputs between receiving the second reset signal and receiving the low gain image signal, wherein the first selectable input is included in the first pair of selectable inputs; and

resetting a second pair of selectable inputs after receiving the first reset signal and not resetting the second pair of selectable inputs between receiving the high gain image signal and receiving the low gain image signal, wherein the second selectable inputs are included in the second pair of selectable inputs; and wherein the second pair of selectable inputs is coupled to be reset by a second reset signal separate from the first reset signal.

17. The method of claim 14, wherein the ADC is a successive approximation register, SAR, ADC, and the SAR ADC comprises:

a binary weighted capacitor array coupled to an input node, wherein the first selectable input and the second selectable input are also coupled to the input node, and wherein the input node is coupled to a sample and hold switch; and

a successive approximation register SAR coupled to the binary-weighted capacitor array.

18. The method of claim 17, wherein the ADC comprises:

a regenerative latch coupled between an output of the input stage circuit and an input of the SAR.

19. The method of claim 14, wherein an image sensor arranged in rows and columns of the image sensor pixels includes a plurality of the input stage circuits, and wherein each row or column of the image sensor is coupled to an input stage circuit of the plurality of input stage circuits.