HK1222260B - Wire bond sensor package and method - Google Patents

Description

Wire bonding sensor package and method

Related applications

This application claims the benefit of U.S. Provisional Application No. 62/038,429, filed August 18, 2014, which is incorporated herein by reference.

Technical Field

The present invention relates to packaged integrated circuit (semiconductor) chips.

Background Art

Integrated circuit chips mounted on substrates by wire bonding have become a staple in the chip packaging industry. As consumer demand for slimmer mobile devices increases, chip packaging structures must also decrease in size, particularly package height, to meet the slim device trend.

A conventional packaging solution is disclosed in US Published Application 2003/0201535 and is shown in Figure 1. Package 1 contains an image sensor chip 2 bonded to an organic package substrate 3, where chip 2 is electrically connected to substrate 3 via bond wires 4. Bond wires 4 are sealed with resin 5 and then again with encapsulant 6, while leaving active area 7 of chip 2 exposed. Active area 7 is enclosed by a transparent element 8. Image sensor chip 2 is affixed to substrate 3 via adhesive 9. Electrical conductivity outside the package is achieved using solder balls 10.

A problem with this packaging configuration is that its size, and particularly its height, cannot be scaled down as desired.

Summary of the Invention

The above-described problems and needs are addressed by a packaged chip assembly comprising a semiconductor chip including a first substrate of semiconductor material having a first top surface and a first bottom surface, a semiconductor device integrally formed on or in the first top surface, and a first bonding pad at the first top surface electrically coupled to the semiconductor device. A second substrate includes a second top surface and a second bottom surface, a first hole extending between the second top surface and the second bottom surface, one or more second holes extending between the second top surface and the second bottom surface, a second bonding pad at the second top surface, a third bonding pad at the second bottom surface, and a conductor electrically coupled to the second bonding pad and the third bonding pad. The first top surface is secured to the second bottom surface such that the semiconductor device is aligned with the first hole and each of the first bonding pads is aligned with one of the one or more second holes. A plurality of leads are each electrically connected between one of the first bonding pads and one of the second bonding pads and each passes through one of the one or more second holes.

The packaged chip assembly includes a semiconductor chip comprising a first substrate of semiconductor material having a first top surface and a first bottom surface, a semiconductor device integrally formed on or in the first top surface, a first bonding pad on the first top surface electrically coupled to the semiconductor device, one or more trenches formed in the first top surface, and a plurality of conductive traces, each of the plurality of conductive traces having a first portion electrically connected to one of the first bonding pads, a second portion extending above and insulated from the first top surface, and a third portion extending downwardly into one of the one or more trenches. A second substrate comprises a second top surface and a second bottom surface, a second bonding pad on the second top surface, a third bonding pad on the second bottom surface, and a conductor electrically coupled to the second bonding pad and the third bonding pad. The first bottom surface is secured to the second top surface. A plurality of leads are each electrically connected between one of the third portions of one of the plurality of conductive traces and one of the second bonding pads.

A method for forming a packaged chip assembly includes providing a semiconductor chip, providing a second substrate, securing the two together, and electrically connecting the two together. The semiconductor chip includes a first substrate of semiconductor material having a first top surface and a first bottom surface, a semiconductor device integrally formed on or in the first top surface, and a first bonding pad electrically coupled to the semiconductor device at the first top surface. The second substrate includes a second top surface and a second bottom surface, a first hole extending between the second top surface and the second bottom surface, one or more second holes extending between the second top surface and the second bottom surface, a second bonding pad at the second top surface, a third bonding pad at the second bottom surface, and a conductor electrically coupled to the second bonding pad and the third bonding pad. The securing includes securing the first top surface to the second bottom surface such that the semiconductor device is aligned with the first hole and each of the first bonding pads is aligned with one of the one or more second holes. The electrically connecting includes electrically connecting each of a plurality of leads between one of the first bonding pads and one of the second bonding pads, wherein each of the plurality of leads passes through one of the one or more second holes.

A method for forming a packaged chip assembly comprises providing a semiconductor chip (comprising a first substrate of semiconductor material having a first top surface and a first bottom surface, a semiconductor device integrally formed on or in the first top surface, and a first bonding pad at the first top surface electrically coupled to the semiconductor device), forming one or more grooves within the first top surface, forming a plurality of conductive traces (each having a first portion electrically connected to one of the first bonding pads, a second portion extending above and insulated from the first top surface, and a third portion extending downward into one of the one or more grooves), providing a second substrate (comprising a second top surface and a second bottom surface, a second bonding pad at the second top surface, a third bonding pad at the second bottom surface, and a conductor electrically coupled to the second bonding pad and the third bonding pad), securing the first bottom surface to the second top surface, and electrically connecting each of a plurality of leads between one of the third portions of one of the plurality of conductive traces and one of the second bonding pads.

Other objects and features of the present invention will become apparent by reviewing the specification, claims and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a side cross-sectional view of a conventional semiconductor package.

2A-2I are side cross-sectional views illustrating steps in forming the packaged chip assembly of the present invention.

FIG. 3A illustrates the relationship of components of a packaged chip assembly when viewed from side and top cross-sectional views.

FIG. 3B illustrates the relationship of the components of the packaged chip assembly when viewed from the side and bottom cross-sections.

4 is a side cross-sectional view illustrating the packaged chip assembly mounted to a host substrate.

5A-5M are side cross-sectional views illustrating steps in forming an alternative embodiment of the packaged chip assembly of the present invention.

6 is a side cross-sectional view illustrating an alternative embodiment of a packaged chip assembly mounted to a host substrate.

7 and 8 are top views illustrating alternative embodiments of a packaged chip assembly mounted to a host substrate.

9 is a side cross-sectional view illustrating an alternative embodiment of a packaged chip assembly mounted to a host substrate.

DETAILED DESCRIPTION

The present invention is a packaged chip assembly that offers substantial thickness advantages over existing packaging solutions. The overall package height can be reduced by optimizing the bond wire loop height through an improved fan-out package structure and modifications to the die geometry.

2A-2I illustrate the formation of a packaged chip assembly, which begins with fabricating or providing a fan-out substrate 20, which can be made of a rigid or flexible material, such as ceramic, polyimide, FR4, BT, semiconductor silicon, glass, or any other well-known interposer substrate material. The substrate 20 can be single-layer or multi-layer, having at least one electrical wiring layer containing electrical conductors 22. The layout/design of the electrical conductors 22 can be random or pseudo-random and depends largely on the layout/design of the die. As illustrated in FIG2A , the electrical wiring conductors 22 electrically connect wire bonding pads 24 on the top surface of the substrate to interconnect (bonding) pads 26 on the bottom surface of the substrate. If the substrate 20 is made of a conductive material, the conductors 22 and pads 24/26 are insulated from the substrate material by an insulating material.

Active area holes 28 are formed through substrate 20 (which will be aligned with the active area of the semiconductor chip discussed below). A plurality of bonding pad holes 30 are also formed through substrate 20 (which will be aligned with the bonding pads of the semiconductor chip discussed below). As illustrated in FIG. 2B , preferably, holes 28 and 30 do not affect any of conductors 22, wire bonding pads 24, and interconnect pads 26. Holes 28, 30 can be formed using a punch, a CNC router, etching, or any other suitable cutting method. Holes 28, 30 can have tapered or vertical sidewalls. FIG. 2C and 2D illustrate two different layout configurations of holes and pads of substrate 20. In each configuration, each bonding pad hole 30 will be aligned with a plurality of bonding pads of the semiconductor chip.

The substrate 32 is attached to the substrate 20 using an adhesive 34. The substrate 32 extends over the hole 28, as shown in FIG2E . For semiconductor chips with optically active areas (discussed below), the substrate 32 can be optically transparent or translucent. For such applications, the substrate 32 can be poly(methyl methacrylate), glass, sapphire, polycarbonate, or any other transparent or translucent material. Preferably, the substrate is optically transparent glass. The preferred thickness of the substrate 32 ranges from 50 μm to 1000 μm. The substrate 32 can be coated with a scratch-resistant and impact-resistant coating, an oleophobic coating, one or more optical layers such as IR, AR, or any other suitable optical layer. The substrate 32 can be cut to a suitable size (preferably slightly larger than the hole 28) by applying a dicing tape to the substrate 32 (which protects and holds the substrate 32 during the dicing process) and using mechanical cutting, etching, laser, or any other well-known dicing method to dicing the substrate. The diced substrates 32 can be separated from the dicing tape by UV deactivation and a pick-and-place process. Adhesive 34 can be a polymer, epoxy, resin, or any other suitable bonding agent. For example, an epoxy-based adhesive material can be dispensed onto substrate 32 using a jetting system. A pick-and-place system can be used to place substrate 32 onto substrate 20.

As shown in FIG2F , a semiconductor chip 36 is next provided. Chip 36 includes a semiconductor substrate 38 and an active area 40 at the upper surface (top surface) of the substrate, the active area including a semiconductor device 42 such as an image sensor, an infrared sensor, a light sensor, etc. Bonding pads 44 at the top surface of the substrate are electrically coupled directly or indirectly to the semiconductor device 42 (i.e., for off-chip electrical conductivity). Chip 36 can be made, for example, from a wafer containing a plurality of semiconductor devices 42, wherein a dicing tape is applied over the top surface of the wafer, after which the wafer can be thinned (etched from the bottom surface—the wafer is preferably thinned to 150 μm or less) before being divided into individual chips 36. Chips such as chip 36 are well known in the art and will not be described further herein.

Adhesive 46 is then deposited on substrate 20 and/or substrate 38. Adhesive 46 can be a polymer, epoxy, resin, die attach tape, or any other suitable bonding agent or method well known in the art. For example, an epoxy-based adhesive can be dispensed onto substrate 20 using a jetting system. Chip 36 is picked up and placed onto substrate 20 using a pick-and-place process, whereby adhesive 46 secures the bottom surface of substrate 20 to the top surface of chip 36, forming a hermetically sealed cavity 48 between active area 40 and substrate 32. The resulting structure is shown in FIG2G .

As shown in FIG2H , leads 50 are used to connect chip 36 to substrate 20. Specifically, each lead 50 has one end connected to one of bonding pads 24 (of substrate 20) and another end connected to one of bonding pads 44 (of chip 36). These connections provide signals from device 42 to conductor 22 and to interconnect pads 26. The coil height (i.e., the highest point of the looped lead 50 above the upper surface of substrate 20/38) is preferably lower than the top surface of substrate 32. Encapsulant 52 is then deposited over the leads 50 and bonding pads 22/44. Preferably, the upper surface of the encapsulant material 52 is higher than the coil height of the leads 50 but lower than the top surface of substrate 32. Preferably, encapsulant 52 is also deposited over the perimeter of chip substrate 38 and on the bottom surface of substrate 20. The purpose of encapsulant 52 is to seal and protect the underlying structures. Interconnects 54 are then formed on interconnect pads 26 of substrate 20. The interconnect 54 can be, for example, a ball grid array (BGA), a land grid array (LGA), or any other suitable interconnect method. BGA is one of the preferred interconnect types and is shown in the figures. The BGA interconnect 54 can be formed on the substrate 20 using a solder ball jetting process or a solder ball dropping process. The BGA interconnect 54 should extend downwardly lower than the bottom surface of the chip 36 and the encapsulant 52 thereon to achieve easy connection to the BGA interconnect 54. The resulting packaged chip assembly 56 is shown in FIG. 2I .

FIG3A illustrates the relationship of the components of packaged chip assembly 56 when viewed from the side and top cross-sectional views. FIG3B illustrates the relationship of the components of packaged chip assembly 56 when viewed from the side and bottom views. FIG4 illustrates packaged chip assembly 56 mounted to a host substrate 58 (e.g., using an SMT process). Host substrate 58 can be a rigid or flexible printed circuit board or any other type of host substrate having contact pads 60 (electrically contacting interconnects 54 and conductors 62).

In a packaged chip assembly 56, semiconductor chip 36 is attached to substrate 20, whereby the chip's electrical signals on contact pads 44 are routed via wires 50 to bond pads 24, through conductors 22, and to interconnect pads 26 and interconnects 54 connected thereto. Substrate 20 includes apertures 30 for leaving bond pads 44 of chip 36 exposed to allow for the wire bonding process. Substrate 20 also includes active area apertures 28 for leaving active area 40 of chip 36 exposed to allow active area 40 (and semiconductor device 42 therein) to receive light or other sensing energy. Substrate 32 is attached to the top side of substrate 20, thereby hermetically sealing and protecting chip active area 40. Substrate 20 has interconnects 26 on its bottom side for mounting packaged chip assembly 56 to a host substrate 58. Because chip 36 is bonded to the bottom side of substrate 20, occupying a portion of the space that would normally be wasted when mounting the assembly to a host substrate using interconnects such as BGA, a substantial height reduction can be achieved. Furthermore, the bond wires 50 pass through the substrate 20, thereby further reducing the height profile compared to existing packaging solutions. This structure is particularly ideal for image sensors, IR sensors, light sensors, or any other optical related sensors.

Fig. 5A-5M illustrates the formation of an alternative embodiment of the chip assembly of package.Comparable or similar components will be indicated with identical element numbers.As illustrated in Fig. 5A, this formation begins with providing the semiconductor chip 36 discussed above, except when still in wafer form (i.e. multiple chips 36 are formed on the single wafer substrate 38, after selectable thinning, and before segmentation). Photoresist 70 is deposited on the active side of substrate 38, covering active area 40 and bonding pad 44. Photoresist 70 can be deposited with spin coating, spray coating, dry film or any other suitable photoresist deposition method.As shown in Fig. 5B, photoresist 70 is developed (develop) (that is, using photolithography exposure and etching process to expose and selectively remove), and its patterning (pattern) photoresist is to expose the silicon substrate 38 (but not exposing active area 40 and bonding pad 44) between two adjacent tube cores.

The exposed portion of substrate 38 is etched using an anisotropic dry etch process to form trenches 72 in the top surface of substrate 38. The etchant can be, for example, CF4, SF6, or any other suitable etchant. The walls of trench 72 are preferably, but not necessarily, tapered. Trench 72 can be formed on all four sides, three sides, two sides, or a single side of active area 40 and its associated bonding pads 44. Preferably, the depth of trench 72 does not exceed 75% of the vertical height of substrate 38. FIG5C shows the resulting structure after photoresist 70 has been removed.

A photoresist 74 is then deposited on the active side of substrate 38 and developed (i.e., exposed and selectively removed), which patterns the photoresist 74 to expose silicon substrate 38 (but leaving the photoresist 74 only disposed over active area 40 and bonding pads 44, without being disposed in the region between them), as shown in FIG5D . A passivation (i.e., insulating material) 76 is deposited on the structure. Passivation 76 can be silicon dioxide, silicon nitride, titanium, a combination of the above passivations, or any other suitable silicon passivation electrically insulating material. Passivation 76 can and preferably is deposited using physical vapor deposition (PVD). The resulting structure is shown in FIG5E (after photoresist 74 removal).

A photoresist 78 is then deposited on the active side of the semiconductor device wafer and developed (i.e., exposed and selectively removed), leaving photoresist 78 only above active area 40. An electrically conductive material layer 80 is deposited over passivation layer 76 and photoresist 78. Conductive material layer 80 can be copper, aluminum, or any other suitable conductive material and can be deposited using physical vapor deposition (PVD), electroplating, or any other suitable deposition method. Preferably, electrically conductive material layer 80 is copper and is deposited by sputtering and then electroplating. A photoresist 82 is then deposited over conductive layer 80 and developed (i.e., exposed and selectively removed), leaving photoresist 82 intact except above active area 40 and at or near the center of trench 72, as shown in FIG5F. Etching is then used to remove the exposed portions of conductive layer 80, leaving conductive material traces 80 each extending from one of bond pads 44 downwardly into one of trenches 72, as shown in FIG5G (after photoresist 82 and 78 are removed). Trace 80 makes electrical contact with bond pad 44 but is insulated from substrate 38 by passivation layer 76 , thereby electrically routing bond pad 44 into trench 72 .

As shown in FIG5H , substrate 32 is attached directly to active area 40. As described above, substrate 32 can be poly(methyl methacrylate), glass, sapphire, polycarbonate, or any other suitable material, can be optically transparent or translucent, and can be treated with a scratch-resistant and impact-resistant coating, an oleophobic coating, one or more optical layers such as IR, AR, or any other suitable optical layer. Substrate 32 is attached using a bonding adhesive 84, which can be optically transparent/translucent. Adhesive 84 can be deposited on active area 40 or on substrate 32 using a spray deposition process, and then substrate 32 is directly attached to active area 40. There is no gap or cavity between substrate 32 and active area 40 as in the previously described embodiments.

Given that substrate 32 is mounted directly to active area 40, substrate 32 can be sapphire, and more specifically, multiple single-crystal sapphire sheets stacked in different crystal orientations. The multiple layers of sapphire sheets are joined using welding, adhesive bonding, or any other suitable bonding technique. Optionally, multilayer sapphire substrate 32 can include a conductive grid, a conductive mesh, or a suspended layer of conductive particles. Such a conductive layer can be connected to a ground element to prevent electrostatic discharge (ESD) damage to semiconductor device 42. Such a conductive layer can also be designed to enhance the device's heat dissipation rate. Sapphire can be desirable due to its hardness, durability, and scratch resistance. These strengths can be enhanced when sapphire sheets are stacked in different crystal orientations. Due to these strengths, the silicon die can be better protected from physical forces such as finger pressure. Sapphire's superior strength allows it to be thinner than other materials, such as glass. The thickness of the sapphire substrate can be 100 μm to 1000 μm and still provide adequate protection for chip 36. Thinner sapphire allows for a thinner device overall and allows for a more sensitive active area 40. This can be particularly important if semiconductor device 42 is a capacitive sensor for fingerprint recognition, where the closer the finger is to active surface 40, the better. The sapphire is preferably segmented using a laser cutting process before being mounted on chip 36.

FIG5I shows an alternative embodiment for mounting substrate 32 onto chip 36, wherein no adhesive is deposited between substrate 32 and active area 40 of chip 36, which improves the sensitivity of the active area, reduces optical or tactile loss, and reduces the overall device height. Substrate 32 is attached to its sides with a sealant/adhesive material 86 deposited by a jetting method, preferably under vacuum. Material 86 is preferably lower than the top surface of substrate 32.

Wafer-level dicing/singling is then performed along the scribe lines 88 passing through the grooves 72, resulting in individual semiconductor chips 36 as shown in FIG5J . Singulation can be performed by mechanical dicing, laser dicing, chemical etching, or any other suitable process. The singulated chips 36 are then bonded to the top surface of the substrate 20 discussed above, but in this embodiment, the substrate 20 does not include holes 28 and 30, and the chips 36 are not bonded to the bottom surface of the substrate 20. Leads 50 are used to connect the chips 36 to the substrate 20. In particular, each lead 50 has one end connected to one of the bonding pads 24 (of the substrate 20) and another end connected to one of the traces 80 (of the chip 36) in one of the grooves 72. These connections provide signals from the device 42, passing through the bonding pads 42, traces 80, leads 50, bonding pads 24, conductors 22, and reaching the interconnect pads 26. The coil height (i.e., the highest point of the looped leads 50) is preferably lower than the top surface of the substrate 32. Given the depth of trench 72, the coil height can be made lower (compared to having to route leads 50 from any portion of trace 80 and/or bond pad 44 along the top surface of substrate 38). Encapsulant 52 is then deposited over leads 50, bond pad 24, and trace 80. As shown in FIG5K , the top surface of encapsulant material 52 is preferably lower than the top surface of substrate 32, but higher than the peak height of leads 50 by some amount (e.g., 5 μm). Encapsulant 52 can be deposited using jetting, injection molding, or any other suitable encapsulation process well known in the art. Preferably, the deposition method is injection molding.

Interconnects 54 are then formed on the interconnect pads 26 of the substrate 20. The interconnects 54 can be, for example, a ball grid array (BGA) as shown in FIG. 5L , a land grid array (LGA) as shown in FIG. 5M , or any other suitable interconnect technology. As shown in FIG. 6 , the packaged chip assembly 56 is then mounted on the main substrate 58 (e.g., using an SMT process). FIG. 7 and FIG. 8 show examples of other components that can be mounted/connected to the main substrate 58, including electrical devices 90 such as processors, memories, capacitors, etc., and connectors 92 for the substrate 58. Given the contact between the substrate 32 and the semiconductor device 42 (directly or via an adhesive 84), this embodiment structure is ideal for biometric semiconductor devices.

FIG9 illustrates an alternative embodiment to the embodiment shown in FIG2I . Instead of a substrate 20 containing electrical wiring conductors 22 therein (for electrically connecting wire bonding pads 24 on the top surface of the substrate to interconnect (bonding) pads 26 on the bottom surface of the substrate), the substrate 20 can be made of a solid material, such as a conductive semiconductor material or a glass material. The substrate 20 in this embodiment contains a hole 96 extending between the top and bottom surfaces of the substrate 20. Conductive material is deposited in the hole 96 to form an electrical interconnect 98 that extends through the substrate 20. The leads 50 are connected to the electrical interconnect 98 near the top surface of the substrate 20 (directly or using bonding pads 100), and the interconnect 54 is connected to the electrical interconnect 98 near the bottom surface of the substrate (directly or using bonding pads 102).

The electrical interconnect 98 is insulated from the substrate 20 by a layer of compliant dielectric material 104. A compliant dielectric is a relatively soft material (e.g., solder mask) that exhibits compatibility in all three orthogonal directions and is able to accommodate the coefficient of thermal expansion (CTE) mismatch between substrate materials such as semiconductor crystals (~2.6 ppm/°C) and interconnect materials such as Cu (~17 ppm/°C). The compliant dielectric material 104 is preferably a polymer such as BCB (phenylcyclobutene), solder mask, solder resist, FR4, molding compound, or BT epoxy. The compliant dielectric material 104 serves to electrically insulate the electrical interconnect 98 from the substrate 20 when the substrate 20 is made of a conductive semiconductor material (so the two are not electrically shorted together). The compliant dielectric material 104 serves to reduce metal stress on the substrate 20 when the substrate 20 is made of glass.

It is to be understood that the present invention is not limited to the embodiments illustrated herein and described above, but encompasses any and all variations that fall within the scope of the appended claims. For example, references to the present invention herein are not meant to limit the scope of any claim or claim clause, but rather merely to refer to one or more features that may be covered by one or more claims. The materials, processes, and numerical examples described above are exemplary only and should not be considered to limit the claims. Furthermore, it will be apparent from the claims and specification that not all method steps need to be performed in the exact order illustrated or claimed, but rather in any order that allows for the proper formation of the packaged chip assembly of the present invention. Finally, a single layer of material may form multiple layers of such or similar material, and vice versa.

It should be noted that, as used herein, the terms "over" and "on" both include "directly on" (without intervening materials, elements, or spaces disposed therebetween) and "indirectly on" (without intervening materials, elements, or spaces disposed therebetween) in an inclusive manner. Similarly, the term "adjacent" includes "directly adjacent" (without intervening materials, elements, or spaces disposed therebetween) and "indirectly adjacent" (without intervening materials, elements, or spaces disposed therebetween), "mounted to" includes "directly mounted to" (without intervening materials, elements, or spaces disposed therebetween) and "indirectly mounted to" (without intervening materials, elements, or spaces disposed therebetween), and "electrically coupled to" includes "directly electrically coupled to" (without intervening materials or elements electrically connecting the elements together) and "indirectly electrically coupled to" (with intervening materials or elements electrically connecting the elements together), for example, forming an element "over a substrate" can include: forming the element directly on the substrate, with no intervening materials/elements between them; and forming the element indirectly on the substrate, with one or more intervening materials/elements between them.

Claims (22)

1. A packaged chip assembly, comprising: Semiconductor chips, which include: A first substrate of semiconductor material having a first top surface and a first bottom surface. A semiconductor device integrally formed on or within the first top surface, and Electrically coupled to a first bonding pad at the first top surface of the semiconductor device; The second substrate comprises: Second top surface and second bottom surface, A first hole extending between the second top surface and the second bottom surface. One or more second holes extending between the second top surface and the second bottom surface. The second bonding pad at the second top surface The third bonding pad at the second bottom surface, and Conductors electrically coupled to the second bonding pad and the third bonding pad; Wherein, the first top surface is fixed to the second bottom surface such that the semiconductor device is aligned with the first hole, and each of the first bonding pads is aligned with one of the one or more second holes; Multiple leads, each electrically connected between one of the first bonding pads and one of the second bonding pads, and each passing through one of the one or more second holes; and The third substrate comprises: The third top surface and the third bottom surface, and The fourth bonding pad at the third top surface; Electrical interconnects, each electrically coupling one of the third bonding pads to one of the fourth bonding pads. 2. The component of claim 1, further comprising: a fourth substrate fixed to the second top surface and covering the first hole. 3. The component of claim 2, wherein the fourth substrate is optically transparent or translucent. 4. The component of claim 3, wherein the semiconductor device is one of an image sensor, an infrared sensor, and a light sensor. 5. The component of claim 1, further comprising: a sealant covering the lead and filling the one or more second holes. 6. The component of claim 1, further comprising: a sealant extending from the second bottom surface, along the sidewall of the first substrate, and toward the first bottom surface. 7. The component of claim 1, further comprising: A plurality of holes extending between the second top surface and the second bottom surface, wherein the conductor is a conductive material in the plurality of holes, each extending between one of the second bonding pads and one of the third bonding pads. 8. A packaged chip assembly, comprising: Semiconductor chips, which include: A first substrate of semiconductor material having a first top surface and a first bottom surface. A semiconductor device integrally formed on or within the first top surface. Electrically coupled to the first bonding pad at the first top surface of the semiconductor device. One or more grooves are formed in the first top surface, and Multiple conductive traces, each having a first portion electrically connected to one of the first bonding pads, a second portion extending over and insulated from the first top surface, and a third portion extending downward into one of the one or more trenches; The second substrate comprises: Second top surface and second bottom surface, The second bonding pad at the second top surface The third bonding pad at the second bottom surface, and Conductors electrically coupled to the second bonding pad and the third bonding pad; Wherein the first bottom surface is fixed to the second top surface; and Multiple leads, each electrically connected between one of the third portions of one of the multiple conductive traces and one of the second bonding pads; A third substrate having a third top surface and a third bottom surface, wherein the third bottom surface is fixed to the first top surface and disposed on the semiconductor device, and wherein the third substrate includes at least one of a conductive grid, a conductive mesh, and a layer of suspended conductive particles. 9. The component of claim 8, wherein the third substrate is directly attached to the first top surface without any intervening material. 10. The component of claim 8, further comprising: an adhesive material disposed between the third substrate and the first top surface. 11. The component of claim 8, wherein the third substrate comprises a plurality of single-crystal sapphire wafers stacked with different crystal orientations. 12. The component of claim 8, further comprising: A coating formed on the third top surface, wherein the coating is at least one of a scratch-resistant and impact-resistant coating and an oleophobic coating. 13. The component of claim 8, further comprising: a sealant covering the lead and the conductive trace. 14. The component of claim 8, further comprising: A fourth substrate, comprising: The fourth top surface and the fourth bottom surface, and The fourth bonding pad at the fourth top surface; Electrical interconnects, each electrically coupling one of the third bonding pads to one of the fourth bonding pads. 15. A method of forming a packaged chip assembly, comprising: A semiconductor chip is provided, the semiconductor chip comprising: A first substrate of semiconductor material having a first top surface and a first bottom surface. A semiconductor device integrally formed on or within the first top surface, and Electrically coupled to a first bonding pad at the first top surface of the semiconductor device; A second substrate is provided, the second substrate comprising: Second top surface and second bottom surface, A first hole extending between the second top surface and the second bottom surface. One or more second holes extending between the second top surface and the second bottom surface. The second bonding pad at the second top surface The third bonding pad at the second bottom surface, and Conductors electrically coupled to the second bonding pad and the third bonding pad; The first top surface is fixed to the second bottom surface such that the semiconductor device is aligned with the first hole, and each of the first bonding pads is aligned with one of the one or more second holes; Each of the plurality of leads is electrically connected between one of the first bonding pads and one of the second bonding pads, wherein each of the plurality of leads passes through one of the one or more second holes; A third substrate is provided, comprising: The third top surface and the third bottom surface, and The fourth bonding pad at the third top surface; The third top surface is secured to the second bottom surface using electrical interconnects, each of which electrically couples one of the third bonding pads to one of the fourth bonding pads. 16. The method of claim 15, further comprising: A fourth substrate is fixed to the second top surface, wherein the fourth substrate covers the first hole and is optically transparent or translucent, and wherein the semiconductor device is one of an image sensor, an infrared sensor, and a light sensor. 17. The method of claim 15, further comprising: covering the lead with a sealant and filling the one or more second holes therein. 18. A method of forming a packaged chip assembly, comprising: A semiconductor chip is provided, the semiconductor chip comprising: A first substrate of semiconductor material having a first top surface and a first bottom surface. A semiconductor device integrally formed on or within the first top surface, and Electrically coupled to a first bonding pad at the first top surface of the semiconductor device; One or more grooves are formed within the first top surface; Multiple conductive traces are formed, each of the multiple conductive traces having a first portion electrically connected to one of the first bonding pads, a second portion extending over and insulated from the first top surface, and a third portion extending downward into one of the one or more trenches; A second substrate is provided, the second substrate comprising: Second top surface and second bottom surface, The second bonding pad at the second top surface The third bonding pad at the second bottom surface, and Conductors electrically coupled to the second bonding pad and the third bonding pad; Fix the first bottom surface to the second top surface; Each of the plurality of leads is electrically connected between one of the third portions of one of the plurality of conductive traces and one of the second bonding pads; and A third substrate having a third top surface and a third bottom surface is fixed to the first top surface, wherein the third substrate is disposed on the semiconductor device, and the third substrate includes at least one of a conductive grid, a conductive mesh, and a layer of suspended conductive particles. 19. The method of claim 18, further comprising: A coating is formed on the third top surface, wherein the coating is at least one of a scratch-resistant and impact-resistant coating and an oleophobic coating. 20. The method of claim 18, wherein the third substrate comprises a plurality of single-crystal sapphire wafers stacked with different crystal orientations. 21. The method of claim 18, further comprising: covering the lead and the conductive trace with a sealant. 22. The method of claim 18, further comprising: A fourth substrate is provided, the fourth substrate comprising: The fourth top surface and the fourth bottom surface, and The fourth bonding pad at the fourth top surface; The third top surface is secured to the second bottom surface using electrical interconnects, each of which electrically couples one of the third bonding pads to one of the fourth bonding pads.