HK1208291B - Method and system for aligning signals widely spaced in frequency for wideband digital predistortion in wireless communication systems - Google Patents

Description

Method and system for wideband digital predistortion of widely spaced signals in wireless communication systems

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to U.S. Provisional Patent Application No. 61/674,771, filed on July 23, 2012, entitled “Method and System for Wideband Digital Predistortion Aligning Widely Frequency-Spaced Signals in Wireless Communication Systems,” the disclosure of which is incorporated herein by reference in its entirety for all purposes.

Background Art

Predistortion is a technique used in communication systems to improve the linearity of power amplifiers. Because power amplifiers can have nonlinear input/output characteristics, predistortion is used to linearize the input/output characteristics of the power amplifier. Essentially, "inverse distortion" is introduced into the input feeding the power amplifier, thereby counteracting the nonlinear characteristics of the power amplifier.

Current predistortion technologies used to linearize power amplifiers in mobile communication systems are mainly: analog predistorters implemented at IF/RF by analog circuits and digital predistorters at baseband using digital signal processing (DSP) technology.

Analog predistorters produce linearization of the power amplifier based on the principles of error subtraction and power matching. Because the nonlinear characteristics of a power amplifier can be complex and involve many variables, analog predistortion can result in less than optimal predistortion accuracy and consumes considerable power.

Despite advances in predistortion technology, there exists a need in the art for improved methods and systems for digital predistortion systems.

Summary of the Invention

Therefore, the present invention was developed in light of the above problems, and its purpose is to provide a robust method for estimating the delay between a transmit signal and a feedback signal in a wideband digital predistortion system. To achieve this, according to an embodiment of the present invention, the technique utilizes a Farrow-based fractional delay filter and an algorithm in the feedback path to precisely control the feedback path delay. This embodiment of the present invention enables highly accurate time alignment of the transmit signal and the feedback signal at all times.

According to one embodiment of the present invention, a simple and robust delay estimation method is provided for wideband digital predistortion (DPD) with widely spaced carrier frequencies. The present invention also provides a method for time-aligning transmit and feedback signals for a wideband DPD system. To achieve the above objectives, according to an embodiment of the present invention, the technique utilizes a programmable fractional delay filter based on a third-order Lagrangian-Faro structure that is very easy to design and control. The embodiments described herein enable signal alignment in DPD systems with instantaneous bandwidths greater than 100 MHz.

According to one embodiment of the present invention, a system for time-aligning widely spaced frequency signals is provided. The system includes a digital predistortion (DPD) processor and a power amplifier coupled to the DPD processor and operable to provide a transmit signal at the power amplifier output. The system also includes a feedback loop coupled to the power amplifier output. The feedback loop includes: an analog-to-digital converter (ADC) unit coupled to the power amplifier output and outputting a feedback signal, wherein the ADC unit has a sampling rate; an adaptive fractional delay filter coupled to the ADC unit and configured to delay the feedback signal based on a fraction of the sampling rate; a delay estimator coupled to one or more outputs of the DPD processor and coupled to the adaptive fractional delay filter; and a DPD coefficient estimator coupled to the delay estimator.

According to another embodiment of the present invention, a method for time-aligning signals is provided. The method includes: a) calculating a value of a delay parameter; b) receiving multiple transmit signals; and c) receiving multiple feedback signals. The method also includes: d) determining a function related to timing error using the multiple transmit signals and the multiple feedback signals; e) determining that the function related to timing error is greater than or equal to a predetermined threshold; and f) incrementing a counter. The method also includes: g) repeating one or more of steps a) to f) one or more times; h) determining that the function related to timing error is less than a predetermined threshold; and i) fixing the delay parameter.

Numerous benefits are achieved through the present invention over conventional techniques. For example, embodiments of the present invention provide enhanced control over delays in the feedback path, thereby improving the performance characteristics of the digital predistortion system. These and other embodiments of the present invention, as well as many of its advantages and features, are described in more detail below and in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic block diagram illustrating a multi-carrier broadband system including digital predistortion with delay estimation according to an embodiment of the present invention;

FIG2 is a schematic block diagram illustrating a system for aligning a broadband signal according to an embodiment of the present invention; and

FIG3 is a simplified flow chart illustrating a method of temporally aligning signals according to an embodiment of the present invention.

DETAILED DESCRIPTION

The present invention generally relates to broadband communication systems using multiplexing modulation techniques. More particularly, the present invention relates to a method for aligning widely spaced frequency signals for broadband digital predistortion linearization in a wireless transmitter.

With the increasing importance of spectral efficiency in wireless communication systems, the linearity and efficiency of radio frequency (RF) power amplifiers (PAs) have become critical design issues for non-constant envelope digital modulation schemes with high peak-to-average power ratios (PARs). RF PAs exhibit nonlinearities that produce amplitude modulation-to-amplitude modulation (AM-AM) and amplitude modulation-to-phase modulation (AM-PM) distortion at the PA output. These effects cause spectral regrowth in adjacent channels and in-band distortion that degrades error vector magnitude (EVM). Consequently, one of various linearization techniques is typically applied to RF PAs. Numerous linearization techniques, such as feedback, feedforward, and predistortion, have been proposed in the literature.

The most promising linearization technique is baseband digital predistortion (DPD), which leverages recent advances in digital signal processors. When compared to the widely used conventional feedforward linearization technique, DPD can achieve good linearity and good power efficiency with reduced system complexity. In addition, software implementation provides the digital predistorter with reconfigurability suitable for multi-standard environments. In addition, PAs using efficiency enhancement techniques such as Doherty power amplifiers (DPAs) can achieve higher efficiency than traditional PA designs at the expense of linearity. Therefore, combining DPD with DPAs using efficiency enhancement techniques has the potential to maximize system linearity and overall efficiency.

Typical wireless communication systems support an instantaneous bandwidth of approximately 20 MHz to 25 MHz. Common delay estimation for digital predistortion algorithms uses the amplitude correlation between a transmit signal and a feedback signal with two or more times oversampling.

However, the requirements for instantaneous bandwidth (>25 MHz) for next-generation wireless systems continue to increase, which means that wideband multi-carriers may be widely spaced in frequency. For example, for a system supporting 65 MHz instantaneous bandwidth, the carrier spacing can be as high as 60 MHz. This can produce several correlation peaks with very small time differences due to the large carrier spacing. This can lead to undesirably large delay alignment errors. Therefore, embodiments of the present invention provide a wideband digital predistortion system with robust delay estimation.

FIG1 is a schematic block diagram illustrating a digital predistortion (DPD) circuit, an interpolator, a digital-to-analog converter (DAC), a modulator, a power amplifier, a duplexer, an RF downconversion circuit for coupling an output at the output of the PA, an analog-to-digital converter (ADC) for the digital predistortion feedback path, and a digital downconverter. The digital predistortion system utilizes delay estimation based on the amplitude of the complex signal (I and Q). Typically, the sampling rate of the feedback ADC is twice that of the digital predistorter. For example, if the digital predistortion sampling rate is 125 MHz, the sampling rate of the feedback ADC is typically at least 250 MHz, which means that the minimum resolution of the hardware controllable delay is 4 ns (1/250 MHz). In some embodiments, in the case of widely spaced carriers, the minimum resolution is not small enough to align the delay between the transmit and feedback paths with the desired accuracy.

The delay estimator receives input from the feedback path and input from the output of the DPD circuit. The delay estimator calculates the difference between these inputs and provides the input to the coefficient estimator to time-align the signals as part of the error minimization process. In certain embodiments of the present invention, the delay estimator provides a value that is a function of the timing error between the in-phase component at the output of the DPD circuit and the in-phase component of the feedback signal, and the quadrature-phase component at the output of the DPD circuit and the quadrature-phase component of the feedback signal.

As an example of calculation of the function of the timing error (Error), which can also be referred to as a function related to the timing error, the function may be the difference in mean square error between the complex feedback signal and the complex output of the DPD circuit.

Where, is the in-phase feedback signal

is the quadrature phase feedback signal

I is the in-phase output DPD signal

Q is the quadrature phase output DPD signal

Figure 2 is a schematic block diagram illustrating a system for aligning a wideband signal according to an embodiment of the present invention. The system shown in Figure 2 includes a digital predistortion (DPD) circuit, an interpolator, a digital-to-analog converter, a modulator, a power amplifier, a duplexer, a radio frequency down-conversion circuit for coupling the output at the output of the PA, an analog-to-digital converter for the feedback path, a digital down-converter, and a fractional delay filter with a controllable parameter (mu), which in some embodiments is in the range of 0 to 1.

According to the present invention, the fractional delay filter is implemented based on a third-order Lagrangian Farrow structure that enables a simple implementation and operates at digital predistortion sampling rates. Higher-order Lagrangian Farrow filters can be used as appropriate for specific applications. The minimum delay resolution can be 10 times or more the sampling rate, which means that for a feedback ADC with a 1 GHz sampling rate, the minimum delay resolution can be as small as 0.1 ns. Of course, in some implementations the minimum delay resolution will depend on the number of bits. To provide a similar minimum delay, conventional systems would use a 10 GHz sampling rate interpolator in hardware or a complex and time-consuming software filtering algorithm.

Fractional delay filters allow for signal shifting (i.e., signal time shifting) at fractions of the sampling rate. As an example, if the sampling rate is 100 MHz, a conventional system will only sample at a rate that results in 10 ns (i.e., 1/100 MHz) between each sample. As shown in FIG2 , the fractional delay filter includes a parameter shown as mu. This parameter enables signal shifting to change the delay at a predetermined fraction of the sampling rate (e.g., one-tenth of the sampling rate). Therefore, for mu values in the range of 0 to 1, the fractional delay filter enables the minimum delay to be reduced from 10 ns to 1 ns. Therefore, embodiments of the present invention utilize fractional delay filtering in the context of digital predistortion in broadband communication systems.

Referring again to Figure 2, the fractional delay filter acts as a low pass filter with a variable delay as a function of the parameter mu.Additional description is provided below regarding variations in the parameter mu during operation.

FIG3 is a flow chart illustrating a method for time-aligning signals according to an embodiment of the present invention. When delay estimation begins, a counter (n) is set to zero and mu is set to the value of the counter multiplied by the step size (mu=n*step size), thereby setting mu to zero. The step size can be set to a variety of values, such as 0.2, 0.1, 0.05, and so on. As an example, if the ADC operates at a sampling rate of 1 MHz (i.e., 1 μs per sample) and the step size is set to 0.1, then as the counter increments, mu will be set to multiples of 0.1 to provide a minimum delay resolution of 0.1 μs.

A signal is captured at the output of the DPD circuit and the output of the feedback path (i.e., the output of the digital down converter). The output of the DPD circuit and the output of the feedback path are amplitude aligned. Using the aligned captured signals of the two paths, calculation of the function of the timing error is performed in the delay estimator as shown in Figure 2. During the first iteration, n=0 and mu=0, the parameter mu=0 is provided to the fractional delay filter. If the function of the timing error obtained is greater than or equal to a predetermined threshold, the counter is incremented and mu is recalculated for the next iteration (i.e., in this example, for the second iteration, mu=1*step size=1*0.1=0.1). The process is iterated until the function of the timing error is less than the predetermined threshold, mu is fixed, and the value from the delay estimator is provided to the coefficient estimator (i.e., the coefficient estimation algorithm). The step size is not limited to the value 0.1 in this example, and can be set to other suitable values, for example, 0.2, 0.1, 0.05, etc.

Embodiments of the present invention provide real-time adaptive processing to reduce signal errors to a predetermined level. As will be apparent to those skilled in the art, a predetermined number of symbols (e.g., 4000 samples) are captured, a calculation of a function of the timing error is performed to determine a delay estimate, and the delay is then provided to a coefficient estimator.

Referring to FIG3 , a method for temporally aligning signals is provided. The method includes: a) calculating a value of a delay parameter; b) receiving a plurality of transmit signals; and c) receiving a plurality of feedback signals. As shown in FIG3 , calculating the value of the delay parameter may include multiplying a counter by a step size parameter. The step size parameter can be in the range of 0 to 1. The method also includes: d) determining a function of timing error using the plurality of transmit signals and the plurality of feedback signals; and e) determining that the function of timing error is greater than or equal to a predetermined threshold. Determining the function of timing error using the plurality of transmit signals and the plurality of feedback signals may include filtering the plurality of transmit signals and the plurality of feedback signals and estimating the timing error.

The method further comprises: f) incrementing a counter; and g) repeating a) to f) one or more times. In some embodiments, a subset of a) to f) is repeated one or more times. As shown in FIG3 , iterations of a) to f) are performed as long as the function of the timing error is greater than or equal to a predetermined threshold.

After a plurality of iterations and increases in the value of the delay parameter, the method includes: h) determining that the function of the timing error is less than a predetermined threshold; and i) fixing the delay parameter. In one embodiment, the method further includes estimating predistortion coefficients using the delay parameter.

It should be understood that the specific steps shown in FIG3 provide a specific method for aligning signals in time according to an embodiment of the present invention. According to alternative embodiments, other step sequences may also be performed. For example, alternative embodiments of the present invention may perform the steps outlined above in different orders. In addition, the individual steps shown in FIG3 may include multiple sub-steps, which may be performed in various sequences suitable for the individual steps. In addition, additional steps may be added or removed depending on the specific application. Those of ordinary skill in the art will appreciate many variations, modifications, and alternatives.

It will also be understood that the examples and embodiments described herein are for illustrative purposes only and will suggest various modifications or changes based on these examples and embodiments to those skilled in the art, and such modifications or changes should be included within the spirit and purview of this application and the scope of the appended claims.

Claims (14)

1. A system for time-aligning wide-frequency-spaced signals, the system comprising: Digital predistortion (DPD) processor; A power amplifier coupled to the DPD processor and operable to provide a transmit signal at the power amplifier output; and A feedback loop coupled to the output of the power amplifier, wherein the feedback loop includes: An analog-to-digital converter (ADC) unit is coupled to the output of the power amplifier and outputs a feedback signal, wherein the ADC unit has a sampling rate; An adaptive fractional delay filter, coupled to the ADC unit, is configured to delay the feedback signal based on a fraction of the sampling rate; A delay estimator, coupled to one or more outputs of the DPD processor, and coupled to the adaptive fractional delay filter; and The DPD coefficient estimator is coupled to the delay estimator. 2. The system of claim 1, wherein the delay estimator further includes a control algorithm. 3. The system of claim 1, wherein the fractional delay filter is based on a third-order or higher-order Lagrange-Faro filter. 4. The system of claim 1, wherein the delay estimator is operable to calculate a function of timing error. 5. The system of claim 4, wherein the delay estimator is operable to calculate a function of the timing error by filtering the transmitted signal and the output of the adaptive fractional delay filter. 6. The system of claim 5, wherein the function of the timing error includes an amplitude squared function. 7. The system of claim 5, wherein the function of the timing error includes an amplitude peak correlation function. 8. The system of claim 5, wherein the function of the timing error includes the error vector magnitude (EVM) function. 9. The system of claim 1, wherein the adaptive fractional delay filter is a low-pass filter. 10. The system of claim 1, wherein the adaptive fractional delay filter includes a delay parameter. 11. The system of claim 10, wherein the DPD coefficient estimator is operable to use the delay parameter to estimate the predistortion coefficients. 12. The system of claim 10, wherein the delay parameter is calculated by multiplying the counter by the step size parameter. 13. The system of claim 12, wherein the step size parameter is in the range of 0 to 1. 14. The system of claim 10, wherein the delay parameter is in the range of 0 to 1.