HK1260671A1 - System and method for reducing programming voltage stress on memory cell devices - Google Patents

Description

System and method for reducing programming voltage stress on memory cell devices

Cross Reference to Related Applications

This application claims priority and benefit of non-provisional application No.15/061,882 filed at united states patent and trademark office at 3, 4/2016, which is hereby incorporated by reference in its entirety.

Technical Field

Aspects of the present disclosure relate generally to memories and, in particular, to systems and methods for reducing gate oxide voltage stress during programming of memory cell devices.

Background

Typically, an Integrated Circuit (IC), such as a system on a chip (SOC), includes one-time programmable (OTP) memory that allows one or more cores of the IC to permanently write data to the memory. OTP memories typically do not contain data when the IC is manufactured. During initialization or subsequently throughout operation of the IC, one or more cores may permanently write data to the OTP as needed, such as, for example, calibration data, initialization data, identification data, or other data.

OTP memories typically include a two-dimensional array of memory cells. The memory cells common to a row are coupled to respective Word Lines (WL) of the memory. The memory cells common to the columns are coupled to respective Bit Lines (BL) of the memory. Each memory cell of the OTP memory may be configured as an Electronic Fuse (EFUSE) type cell, where the cell includes a fuse element coupled in series with a transistor (e.g., in series with the drain and source of a Field Effect Transistor (FET)) between a corresponding Bit Line (BL) and a power supply rail VSS (e.g., ground). Each transistor of each memory cell includes a control terminal (e.g., gate) coupled to a corresponding Word Line (WL).

Generally, programming of (writing data to) OTP memories can be performed one bit at a time. In this regard, the voltages on the Word Line (WL) and the Bit Line (BL) corresponding to the memory cell (to be programmed) are both raised to the programming voltage (e.g., 1.8V). This produces a current through the corresponding fuse element and FET that is sufficient to blow the fuse element (e.g., an open circuit in the fuse metallization due to electromigration). A fuse blown memory cell may be assigned a bit value (e.g., a logical one (1)), while a fuse unblown memory cell may be assigned another bit value (e.g., a logical zero (0)).

Typically, the programming voltage of an OTP memory cell is higher than the rating of the core device (e.g., FET). For example, the core FET may have a voltage rating of no more than 1.0V, while a programming voltage of 1.8V will exceed the rating of this core device. Thus, OTP memory cells have traditionally been configured with higher rated devices, such as those used for input/output (I/O) operations, where the gate oxide of such devices is made thicker to be able to withstand the programming voltage. However, the disadvantages of using higher rated devices are: OTP memory must occupy a large area of the IC.

It is desirable to implement OTP memories using lower rated devices, such as core devices, to reduce the IC area required to implement the memory while reducing the stress on the core devices associated with the programming voltage.

Disclosure of Invention

The following presents a simplified summary of one or more embodiments in order to provide a basic understanding of such embodiments. This summary is not an extensive overview of all contemplated embodiments, and is intended to neither identify key or critical elements of all embodiments nor delineate the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later.

One aspect of the present disclosure relates to a memory. The memory includes a first global word line; a first group of bit lines; a first local word line; a first set of memory cells coupled to a first local word line and respectively coupled to a first set of bit lines; a first local word line driver configured to generate a first assert signal on a local word line in response to: a second assertion signal is received from the global word line and a third assertion signal is received.

Another aspect of the disclosure relates to a method of accessing at least one memory cell. The method includes generating a first assert signal on a global word line; generating a second assertion signal; in response to receiving the second assertion signal from the global word line and receiving the third assertion signal, a third assertion signal is generated on the local word line for accessing at least one memory cell of the group of memory cells.

Another aspect of the disclosure relates to an apparatus comprising means for generating a first assert signal on a global word line; means for generating a second assert signal; and means for generating a third assert signal on the local word line for accessing at least one memory cell of the group of memory cells in response to receiving the second assert signal from the global word line and receiving the third assert signal.

To the accomplishment of the foregoing and related ends, the one or more embodiments comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more embodiments. These aspects are indicative, however, of but a few of the various ways in which the principles of various embodiments may be employed and the description of the embodiments is intended to include all such aspects and their equivalents.

Drawings

Fig. 1 illustrates a block diagram of an example Integrated Circuit (IC) in accordance with an aspect of the present disclosure.

FIG. 2 illustrates a schematic diagram of an exemplary EFUSE OTP memory in accordance with another aspect of the disclosure.

FIG. 3 illustrates a schematic diagram of an exemplary OTP memory in accordance with another aspect of the disclosure.

FIG. 4 illustrates a schematic diagram of an exemplary EFUSE OTP memory in accordance with another aspect of the disclosure.

FIG. 5 illustrates a schematic diagram of an exemplary global Word Line (WL) driver in accordance with another aspect of the disclosure.

FIG. 6 shows a schematic diagram of an exemplary multiple input OR gate circuit, according to another aspect of the present disclosure.

FIG. 7 illustrates a schematic diagram of an exemplary Local Wordline (LWL) driver in accordance with another aspect of the disclosure.

FIG. 8 illustrates a flow chart of an exemplary method of accessing at least one of a set of memory cells in accordance with another aspect of the disclosure.

Detailed Description

The detailed description set forth below in connection with the appended drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description section includes specific details for the purpose of providing a thorough understanding of various concepts. It will be apparent, however, to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

Fig. 1 illustrates a block diagram of an example Integrated Circuit (IC)100 in accordance with an aspect of the present disclosure. As an example, the IC 100 may be configured as a system on a chip (SOC). IC 100 includes a set of one or more cores, such as cores 110, 120, 130, and 140. Each core may be configured to perform a particular function. For example, there may be a Central Processing Unit (CPU) core, graphics core, modem core, and the like.

As discussed above, IC 100 includes one-time programmable (OTP) memory 160 and associated arbiter or secure processor 150. The OTP memory 160 may be based on an EFUSE type cell or an antifuse type cell. OTP memory 160 may be blank, e.g., not containing any data, when the fabrication of IC 100 has been completed. OTP memory 160 may be used by one or more cores 110-140 as needed to permanently write data to memory. As previously discussed, typically one or more cores 110-140 may write data to OTP memory 160 during initialization of IC 100. Such data may include calibration data, identification data (type or version of core), and other initialization data. Additionally, if desired, one or more cores 110-140 may permanently write data to OTP memory 160 during operations other than initialization. When accessing the OTP 160 for programming and reading purposes, one or more of the cores 110-140 sends an access request to the arbiter 150, which the arbiter 150 grants or denies for security reasons.

Fig. 2 shows a schematic diagram of an exemplary EFUSE OTP memory 200 in accordance with another aspect of the present disclosure. OTP memory200 includes a Word Line (WL) decoder 210, an EFUSE fuse controller 220 (for single bit programming), and an M N two dimensional memory cell array C₁₁To C_MN。

WL decoder 210 includes M word line drivers WD1 through WDM, the outputs of which are coupled to word lines WL1 through WLM, respectively. As discussed further herein, for single bit memory cell programming, a selected one of word line drivers WD 1-WDN (which corresponds to the word line coupled to the single cell to be programmed) is configured to generate a program voltage VDD _ PX (e.g., 1.8V) on the corresponding word line. To read an entire row of memory cells, a selected one of word line drivers WD 1-WDN (which corresponds to the word line coupled to the cell to be read) is configured to generate a lower (core) read voltage VDD _ MX (e.g., 1.0V).

The EFUSE fuse controller 220 is configured to generate bit line programming signals bl1 through bln as inputs to a set of bit line drivers BD1 through BDN, respectively. The bit line drivers BD1 through BDN are configured to generate a program voltage VDD _ PX (e.g., 1.8V) sufficient to perform single-bit memory cell programming. The outputs of the bit line drivers BD1 through BDN are coupled to the bit lines BL1 through BLN, respectively. Thus, to enable single bit memory cell programming, a selected one of the bit line programming signals bl 1-bln (which corresponds to the bit line coupled to the single memory cell to be programmed) is asserted to cause a corresponding one of the bit line drivers BD 1-BDN to generate a programming voltage VDD _ PX (e.g., 1.8V) on the corresponding bit line.

Memory cell C₁₁To C_MNRespectively comprising Field Effect Transistors (FET) M₁₁To M_MNAnd fuse element F₁₁To F_MN。FET M₁₁To M_MNMay be configured as an n-channel metal oxide semiconductor (NMOS) FET. Fuse element F₁₁To F_MNEach of which may be configured as a thin metallization strip that is capable of being disconnected ("blown") when a sufficient amount of current is driven through the metallization strip due to electromigration.

In each cell, a fuse element is coupled in series with the drain and source of the FET between a corresponding bit line and a voltage rail VSS (e.g., ground). The corresponding FET includes a gate coupled to a corresponding word line.

The single bit programming operation of EFUSE OTP memory 200 may be as follows. In this example, cell C is illustrated₁₁To be programmed. Programming of other cells operates in a similar manner. When the cell C is to occur₁₁When programmed, this represents cell C₁₁Corresponding fuse element F₁₁To be blown, WL decoder 210 activates the coupling to cell C₁₁FET M of₁₁Word line driver WD1 to generate the program voltage VDD _ PX (e.g., 1.8V). In the unit C₁₁The other word line drivers WD2 through WDM of the WL decoder 210 are not activated during the programming.

In addition, EFUSE fuse controller 220 asserts the bit line programming signal bl1 to cause the bit line driver BD1 to be coupled to cell C₁₁The program voltage VDD _ PX (e.g., 1.8V) is generated on the bit line BL 1. Since this is only a single bit programming, the EFUSE fuse controller 220 does not assert the other bit line programming signals BL 2-BLN corresponding to the other bit lines BL 2-BLN, respectively. Word line WL1 and bit line BL1 are driven to respective programming voltages VDD _ PX (e.g., 1.8V) to generate a pass through fuse element F₁₁And FET M₁₁Is sufficient (e.g., 10 to 15 milliamps (ma)), which causes fuse element F to be₁₁And fusing.

Memory cells with a blown fuse element may be assigned a particular logic level, such as a logic one (1), while memory cells with an unblown fuse element may be assigned an opposite logic level, such as a logic zero (0). In the unit C₁₁After programming, if the corresponding bit should be, for example, a logical one (1), the next cell C may be programmed₁₂Programming is performed. In this example, the maximum number of cells per row that can be programmed is N, which may be 64, for example.

A problem created by EFUSE OTP memory 200 is the stress induced on the FETs exposed to the programming voltage VDD _ PX. For example, when cell C is being paired₁₁Activation at a programming voltage (e.g., 1.8V) while programmingWord line WL1 in the remaining cell C₁₂To C_1NFET M of₁₂To M_1NCauses stress even though the corresponding bit lines BL2 through BLN are grounded. This is not a problem if the FETs of the cells are designed to handle the programming voltage, such as by configuring these cells with thicker oxide in input/output (I/O) devices. However, configuring OTP memory 200 with a thicker oxide device would require a large amount of IC area to implement OTP memory 200, which is generally undesirable.

Conversely, to reduce the IC area required to implement OTP memory 200, the FETs of the cells may be configured as core devices. As core devices, each FET may only be rated to handle, for example, a 1.2V continuous maximum voltage for a 28nm device or a 0.8V continuous maximum voltage for a 10nm device. Therefore, in an attempt to minimize stress on the FETs by subjecting them to programming voltages higher than their nominal voltage (e.g., 1.8V), the programming time becomes very short (e.g., 10 microseconds (μ s)), just enough to blow the fuse element).

The reliability of any FET depends on the programming voltage applied thereto and the duration of time the programming voltage is applied. Taking the programming duration as 10 mus for example, if the number of cells in each row, N, is 64, then the maximum duration that any corresponding FET can withstand the programming voltage is 640 mus. This may be the case if all fuse elements of the cells in the row are blown. This prolonged exposure to programming voltages can lead to Time Dependent Dielectric Breakdown (TDDB) in the FET due to current tunneling through the gate oxide.

Accordingly, there is a need for an OTP memory that uses a small core device to reduce the amount of IC area required to implement the memory, while reducing the amount of stress on the FET due to high programming voltages.

Fig. 3 shows a schematic diagram of an exemplary OTP memory 300 in accordance with another aspect of the present disclosure. In general, the memory cells of OTP memory 300 are divided into sub-arrays along the word line dimension to reduce the number of FETs subject to the word line programming voltage VDD _ PX. Each cell of OTP memory 300 may be configured as an EFUSE memory cell, an antifuse memory cell, or other type of OTP memory cell.

In particular, OTP memory 300 includes OTP memory cells C coupled to bit lines BL 1-BLJ and local word lines LWLl 1-LWLM 1₁₁To C_MJA sub-array of (a). Specifically, memory cell C₁₁To C_1JCoupled to local word lines LWL11 and bit lines BL1 through BLJ, respectively. Similarly, memory cell C₂₁To C_2JCoupled to local word lines LWL21 and bit lines BL1 through BLJ, respectively. And, a memory cell C_M1To C_MJCoupled to local word lines LWLM1 and bit lines BL1 through BLJ, respectively.

Memory cell C₁₁To C_MJThe sub-arrays of (a) include local (word line) drivers LD11 through LDM1, the outputs of which are coupled to local word lines LWL1 through LWLM1, respectively. The local drivers LD11 to LDM1 are configured to generate local word line signals LWL11 to LWLMs on the local word lines LWL1 to LWLM1, respectively. The local drivers LD 11-LDM 1 comprise respective first inputs coupled to the global word lines GWL 1-GLWM, respectively. Local drivers LD11 through LDM1 also include respective second inputs coupled to the outputs of multiple-input OR gate 330-1. The bit line programming signals BL 1-BLJ associated with the activation of the respective bit lines BL 1-BLJ for programming purposes are applied to the inputs of a multiple-input or gate 330-1. In addition, a read enable signal R _ EN is applied to an input of the multiple-input OR gate 330-1.

OTP memory 300 includes at least memory cell C coupled to bitlines BLK through BLN and local wordlines LWL1K through LWLMK_1KTo C_MNAnother sub-array of (a). Specifically, memory cell C_1KTo C_1NCoupled to local word lines LWL1K and bit lines BLK-BLN, respectively. Similarly, memory cell C_2KTo C_2NCoupled to local word lines LWL2K and bit lines BLK through BLN, respectively. And, a memory cell C_MKTo C_MNCoupled to local word lines LWLMK and bit lines BLK through BLN, respectively.

Memory cell C_1KTo C_MNIncludes local (wordline) drivers LD1K through LDMK, the outputs of these drivers being coupled to local wordlines LWL1K through LWLMK, respectively. The local drivers LD1K through LDMK are configured at local word lines LWL1K through LWL, respectivelyLocal wordline signals lwl1k through lwlmk are generated on MK. The local drivers LD1K to LDMK comprise respective first inputs coupled to global word lines GWL1 to GLWM, respectively. Local drivers LD1K through LDMK also include respective second inputs coupled to the outputs of multiple-input OR gate circuits 330-K. The bit line programming signals BLK-BLN associated with the activation of the respective bit lines BLK-BLN for programming purposes are applied to the inputs of a multiple-input or gate circuit 330-K. In addition, a read enable signal R _ EN is applied to an input of the multiple-input OR gate 330-K.

The OTP memory 300 further comprises a Word Line (WL) decoder 310, the WL decoder 310 comprising M global word line drivers WD1 through WDM, the outputs of these drivers being coupled to global bit lines GWL1 through GWLM, respectively. Word line drivers WD1 through WDM are configured to generate global word line signals GWL1 through gwlm on global word lines GWL1 through GWLN, respectively. During programming, a selected one of the global word line signals gwl1 through gwlm is set to the programming voltage VDD _ PX (e.g., 1.8V). During reading, a selected one of the global word line signals gwl1 through gwlm is set to the read (core) voltage VDD _ MX (e.g., 1.0V).

OTP memory 300 also includes BL program decoder 320. The BL program decoder 320 generates bit line program signals BL1 through blj, the bit line program signals BL1 through blj being applied to respective inputs of the bit line drivers BD1 through BDJ and an input of the multi-input or gate circuit 330-1. In addition, the BL program decoder 320 generates a read enable signal R _ EN, which is applied to the other respective inputs of the bit line drivers BD1 through BDJ and to the other input of the or gate circuit 330-1. In response to the set of bit line programming signals bl1 through blj and R _ EN being "ored", the multiple-input or gate circuit 330-1 generates the subarray enable signal sa _ EN 1.

The bit line drivers BD 1-BDJ include outputs coupled to bit lines BL 1-BLJ, respectively. The bit line drivers BD1 through BDJ are configured to generate a program voltage VDD _ PX (e.g., 1.8V) sufficient to program a selected memory cell. During programming, a selected one of the bit line drivers BD1 through BDJ is configured to generate a program voltage VDD _ PX, and the remaining bit line drivers each generate a logic low voltage VSS (e.g., ground) to prevent programming of unintended cells. During reading, all bitline drivers BD 1-BDJ are tri-stated (e.g., configured to produce a sufficiently high impedance at their respective outputs so as not to adversely affect the reading of the memory cells by sense amplifiers 340, as discussed further herein).

Similarly, BL program decoder 320 generates at least another set of bit line programming signals blk through bln, which are applied to respective inputs of bit line drivers BDK through BDN and to inputs of multi-input OR gate 330-K, another set of bit line programming signals blk through bln. In addition, the BL program decoder 320 generates a read enable signal R _ EN, which is applied to other respective inputs of the bit line drivers BDK to BDN and to the other input of the or gate circuit 330-K. In response to the set of bit line programming signals blk to bln and R _ EN being ORed, the multiple-input OR gate 330-K generates the subarray enable signal sa _ enk.

Bit line drivers BDK through BDN include outputs coupled to bit lines BLK through BLN, respectively. The bit line drivers BD1 through BDJ are configured to generate a program voltage VDD _ PX (e.g., 1.8V) sufficient to program a selected memory cell. During programming, a selected one of the bit line drivers BD1 through BDJ is configured to generate a program voltage VDD _ PX, and the remaining bit line drivers each generate a logic low voltage VSS (e.g., ground) to prevent programming of unintended cells. During reading, all bitline drivers BD 1-BDJ are tri-stated (e.g., configured to produce a sufficiently high impedance at their respective outputs so as not to adversely affect the reading of the memory cell by sense amplifier 340).

As described above, OTP memory 300 also includes sense amplifier 340 coupled to bit lines BD1 through BDN. During a read operation, sense amplifiers 340 are configured to read data from a row of memory cells at a time. The sense amplifier 340 is configured to output the read data.

OTP memory 300 also includes a controller 350, controller 350 having inputs for receiving write data, addresses, and read/write (R/W) control signals. Based on these input signals, the controller 350 is configured to control the WL decoder 310, the BL program decoder 320, and the sense amplifier 340. For example, based on the address, the write data, and the R/W control signal indicating the program operation, the controller 350 controls the WL decoder 310 to generate the program voltage VDD _ PX on the selected global word line corresponding to the memory cell to be programmed, and controls the BL program decoder 320 to generate the program voltage VDD _ PX on the selected bit line coupled to the memory cell to be programmed.

Based on the address and the R/W control signals indicating the read operation, the controller 350 controls the WL decoder 310 to generate a read (core) voltage VDD _ MX on a selected global word line corresponding to the row of memory cells to be read, and the controller 350 controls the sense amplifier 340 to sense the voltage and/or current on the bit line to read the corresponding data. During a read operation, controller 350 also controls BL program decoder 320 to assert a read enable signal R _ EN, which tri-states bitline drivers BD1 through BDN so that these bitline drivers create a sufficiently high impedance at their respective outputs so as not to adversely affect the read operation performed by sense amplifier 340. Furthermore, the asserted read enable signal R _ EN causes OR gates 330-1 through 330-K to generate asserted subarray enable signals sa _ EN1 through sa _ enk, respectively.

The single bit programming operation of OTP memory 300 is as follows. In this example, cell C is illustrated₁₁Is programmed (typically accessed). Programming of other cells operates in a similar manner.

Controller 350 receives an address indicating that memory cell C1 is to be programmed and write data indicating a logic one (1) that causes the programming voltage to be generated to permanently alter memory cell C₁₁Is detected (e.g., fuses are blown in the case of an EFUSE cell), and the controller 350 receives an R/W control signal indicating that the memory operation to be performed is a program (write) operation. In response to receiving these signals, the controller 350 sends corresponding control signals to the WL decoder 310 and the BL program decoder 320. In response, WL decoder 310 causes word line driver WD1 to generate a write-asserted word line signal gwl1 (e.g., set it to the programming voltage VDD _ PX). The write-asserted global word line signal gwl1 is appliedTo respective first inputs of local drivers LD11 through LD 1K. WL decoder 310 also causes the remaining word line drivers WD2 through WDM to generate write de-asserted global word line signals gwl2 through gwlm (e.g., set them to VSS (e.g., ground)) to prevent programming of unintended memory cells.

In addition, in response to controller 350, BL program decoder 320 generates an asserted bit line program signal BL1 (e.g., set it to a program voltage VDD _ PX) to cause bit line driver BD1 to be coupled to cell C₁₁The program voltage VDD _ PX (e.g., 1.8V) is generated on the bit line BL 1. An asserted bit line programming signal bl1 applied to one input of or gate 330-1 causes or gate 330-1 to assert the subarray enable signal sa _ en1 (e.g., set to the programming voltage VDD _ PX). The asserted subarray enable signal sa _ en1 is applied to a respective second input of local drivers LD11 through LDM 1. BL program decoder 320 generates deasserted bit line signals BL 2-bln (e.g., sets them to VSS (e.g., ground)) to cause corresponding bit line drivers BD 2-BDN to generate deasserted signals (e.g., sets them to VSS (e.g., ground)) to prevent undesired programming of unintended memory cells. Since none of the bit line programming signals blK-bln applied to the OR gate 330-K is asserted, the OR gate 330-K generates a deasserted subarray enable signal sa _ enk.

The local driver generates a write-asserted signal at a programming voltage VDD _ PX (e.g., 1.8V) in response to its two inputs receiving the asserted signal. Thus, in this example, when the first input of local driver LD11 receives an asserted global word line signal gwl1 and the second input of local driver LD11 receives an asserted subarray enable signal sa _ en1, local driver LD11 generates a write-asserted local word line signal lwl11 at a programming voltage VDD _ PX (e.g., 1.8V). Since the bit line driver BD1 also generates the program voltage VDD _ PX (e.g., 1.8V), the cell C is paired with₁₁Programming is performed.

In the unit C₁₁The remaining local drivers do not generate the write-asserted local word line signals lwl12 through lwlmk because they each haveDoes not receive both asserted signals. For example, the second input of local driver LD1K receives the sub-array enable signal sa _ enk de-asserted because of memory cell C to be programmed₁₁Not in the same sub-array as local driver LD 1K. Similarly, the respective first inputs of the local drivers LD 21-LDM 1 receive the respective deasserted global word line signals gwl 2-gwlm, since the memory cell C to be programmed₁₁Not in the row corresponding to the global word line signals gwl2 through gwlm. The remaining local drivers LD2K through LDMK also receive deasserted signals at their respective inputs because these local drivers do not belong to the memory cell C to be programmed₁₁And also not coupled to memory cell C₁₁An associated global word line. Thus, these remaining local drivers generate a deasserted local word line signal (e.g., at VSS (e.g., ground)) to prevent programming of unintended memory cells.

Although single-cell programming is illustrated, it should be understood that one or more cells (e.g., such as cell C) coupled to an enabled local drive (e.g., local drive LD11)₁₁To C_1JOne or more of) may be programmed. In this case, BL program decoder 320 asserts one or more bit line programming signals (e.g., such as one or more of BL 1-blj) to cause corresponding one or more bit line drivers (e.g., such as one or more of BD 1-BDJ) to generate one or more programming voltages VDD _ PX, respectively.

Thus, the concept behind OTP memory 300 is: in response to receiving an asserted global word line signal via a corresponding global word line and an asserted subarray enable signal via a corresponding multiple-input or gate circuit, a local driver is caused to generate a write-asserted local word line signal at a programming voltage.

The advantages of OTP memory 300 are: the programming voltage VDD _ PX is applied to fewer FETs; thereby reducing stress on the FET. For example, if the number of cells coupled to a local word line is eight (8) (e.g., a 64 cell per row memory array divided into eight (8) sub-arrays), the maximum number of times each cell can be subjected to a programming voltage is eight (8), in contrast to 64 times for the OTP 200. For example, if the programming duration is 10 μ s, the maximum duration that a cell in OTP memory 300 can withstand the programming voltage is 80 μ s, as compared to 640 μ s for a cell in OTP memory 200.

As a result, the cells of OTP memory 300 experience significantly less stress during programming, which helps prevent damage to the FETs of the cells. This allows OTP memory 300 to be implemented with core devices to reduce the IC area used to achieve the same storage capacity compared to memories using thicker oxide devices, such as I/O devices.

The read operation of OTP memory 300 is as follows. In this example, memory cells C from a row are illustrated₁₁To C_1NIs read (typically accessed). Data reads from other rows of memory cells operate in a similar manner.

Controller 350 receives an indication of memory cell C₁₁To C_1NAn address signal indicating that data in the row of (b) is to be read, and an R/W control signal indicating a memory operation to be performed in a read operation (in the read operation, the controller 350 may ignore a write data signal). In response to receiving these signals, the controller 350 sends corresponding control signals to the WL decoder 310, the BL program decoder 320, and the sense amplifier 340.

In response, WL decoder 310 causes word line driver WD1 to generate a read-asserted global word line signal gwl1 (e.g., set to a read (core) voltage VDD _ MX). The read-asserted global word line signal gwl1 is applied to respective first inputs of local drivers LD11 through LD 1K. WL decoder 310 also causes the remaining word line drivers WD2 through WDM to generate de-asserted global word line signals gwl2 through gwlm (e.g., set them to VSS (e.g., ground)) to prevent reading of unintended memory cells and thereby disturbing memory cell C₁₁To C_1NIs read.

In addition, in response to controller 350, BL program decoder 320 generates an asserted read enable signal R _ EN to configure bitline drivers BD1 through BDN to a tri-state configuration (e.g., to create a sufficiently high impedance at their respective outputs so as not to interfere with the read operation performed by sense amplifier 340). The asserted read enable signal R _ EN also causes all OR gates 330-1 through 330-K to generate the asserted subarray enable signals sa _ EN1 through sa _ enk, respectively.

Similarly, the local driver generates a read-asserted local word line signal at a read (core) voltage VDD _ MX (e.g., 1.0V) in response to its input receiving an asserted signal. Thus, in this example, when the respective first inputs of the local drivers LD 11-LD 1K receive the asserted global word line signal gwl1 and the respective second inputs of the local drivers LD 11-LD 1K receive the asserted subarray enable signals sa _ en 1-sa _ enk, the local drivers LD 11-LD 1K generate the asserted local word line signals lwl 11-lwl 1k at the read (core) voltage VDD _ MX. Sense amplifier 340 senses the current and/or voltage on bit lines BD1 through BDK to respectively determine the voltage stored in memory cell C₁₁To C_1KThe data of (1).

In the first row of memory cells C₁₁To C_1NThe local drivers associated with the remaining rows of memory cells do not generate a read-asserted local word line signal because their respective first inputs receive the deasserted global word line signals gwl 2-glwn. In response to the deasserted signal at their respective first inputs, these remaining local drivers generate a deasserted local word line signal at the VSS potential (e.g., ground) to prevent the remaining memory cells C₂₁To C_MNFor memory cell C₁₁To C_1NInterference with data reading.

Fig. 4 illustrates a schematic diagram of another exemplary OTP memory 400 in accordance with an aspect of the present disclosure. OTP memory 400 is a more detailed implementation of OTP memory 300 previously discussed. That is, OTP memory 400 includes substantially similar elements as OTP memory 300, including WL decoder 410, BL program decoder 420, sense amplifier 440, and controller 450. In addition, OTP memory 400 includes multiple-input OR-gates 430-1 through 430-K, bitline drivers BD1 through BDK, local (wordline) drivers LD11 through LDMK, and memoryReservoir unit C₁₁To C_MN. The operation of the foregoing elements of OTP memory 400 are configured and operate in substantially the same manner as the corresponding elements of OTP memory 300 previously discussed.

In OTP memory 400, memory cell C₁₁To C_MNAre configured as EFUSE-type memory cells. That is, each memory cell in OTP memory 400 includes a fuse element and a FET. More specifically, memory cell C₁₁To C_1JIncludes a FET M and₁₁to M_1JFuse element F serially coupled between bit lines BL 1-BLJ and VSS rail₁₁To F_1J。FET M₁₁To M_1JIs coupled to the output of local driver LD 11. Similarly, memory cell C₂₁To C_2JIncludes a FET M and₂₁to M_2JFuse element F serially coupled between bit lines BL 1-BLJ and VSS rail₂₁To F_2J。FET M₂₁To M_2JIs coupled to the output of local driver LD 21. In a similar manner, memory cell C_MITo C_MJIncludes a FET M and_MIto M_MJFuse element F serially coupled between bit lines BL 1-BLJ and VSS rail_M1To F_MJ。FET M _M1To M_MJIs coupled to the output of the local driver LDM 1.

Similarly, memory cell C_1KTo C_1NIncludes a FET M and_1Kto M_1NFuse element F serially coupled between bit lines BLK-BLN and VSS rail_1KTo F_1N。FET M_1KTo M_1NIs coupled to the output of local driver LD 1K. Similarly, memory cell C_2KTo C_2NIncludes a FET M and_2Kto M_2NFuse element F serially coupled between bit lines BLK-BLN and VSS rail_2KTo F_2N。FET M_2KTo M_2NIs coupled to the output of local driver LD 2K. In a similar manner, memory cell C_MKTo C_MNIncludes a FET M and_MKto M_MNCoupled in series at a bit lineFuse elements F between BLK to BLN and VSS rails_MKTo F_MN。FET M_MKTo M_MNIs coupled to the output of the local driver LDMN.

Programming of EFUSE memory cells has been previously discussed herein. That is, the selected bit line driver is configured to generate the program voltage VDD _ PX on the bit line coupled to the memory cell. The selected local word line driver is configured to generate a write-asserted local word line signal at a programming voltage VDD _ PX on a local word line coupled to the memory cell. The programming voltage applied to the drain and gate of the corresponding FET generates sufficient current to blow the corresponding fuse element of the cell.

Data read from a row of EFUSE memory cells operates as follows. The sense amplifier discharges all bit lines. A selected set of local word line drivers corresponding to a row of cells is configured to generate a read-asserted local word line signal at a read (core) voltage VDD _ MX on a corresponding local word line coupled to the memory cells. Thus, the read (core) voltage VDD _ MX is applied to the gates of the FETs of the memory cells to enable these cells for reading.

The sense amplifier then gradually raises the voltage on the bit line to detect the current in the bit line. The sense amplifier gradually raises the voltage to prevent inadvertent programming of the memory cell (e.g., blowing of a fuse element). If the bit line current is below the threshold, the fuse element of the corresponding memory cell is blown and the sense amplifier reads the corresponding data as a logic one (1). If the current is above the threshold, the fuse element of the corresponding memory cell is not blown and the sense amplifier reads the corresponding data as a logic zero (0). The sense amplifier outputs the read data for use by one or more external devices.

FIG. 5 illustrates a schematic diagram of an exemplary global word line driver 500 in accordance with another aspect of the disclosure. Global word line driver 500 is an example of a detailed implementation of any of global word line drivers WD1 through WDM of the OTP memory previously discussed. For ease of description, global word line driver 500 is depicted as a detailed implementation of global word line driver WD 1.

Specifically, the global word line driver 500 includes a power multiplexer ("power mux") 510, a Word Line (WL) decoding circuit 520, an inverter I₅₃Voltage level shifter 530 and inverter I₅₄. The power multiplexer 510 further includes an inverter I₅₁P-channel metal oxide semiconductor (PMOS) FET M51, inverter I₅₂And PMOS M52.

With respect to power multiplexer 510, inverter I₅₁Includes an input configured to receive a read/non-write enable signal based on a control signal received from controller 350 or 450 of OTP memory 300 or 400, respectivelyInverter I₅₁Comprising a gate coupled to PMOS M51 and an inverter I₅₂Is input to the input of (1). The source and drain of PMOS M51 are coupled between the read voltage domain rail VDD _ MX and the output domain rail VDD _ WL of power multiplexer 510. Inverter I₅₂Including an output coupled to the gate of PMOS M52. The source and drain of PMOS M52 are coupled between the programming voltage domain rail VDD _ MX and the output domain rail VDD _ WL of power multiplexer 510. As shown, inverter I₅₁And I₅₂Supplied by the programming voltage domain VDD _ PX.

WL decoding circuit 520 receives address bits Addr _1 through Addr _3 based on a control signal received from controller 350 or 450 in OTP memory 300 or 400 discussed previously. The WL decoding circuit 520 generates a word line enable signal WL _ en based on the address bits Addr _1 to Addr _ 3. For example, WL decode circuit 520 asserts a word line enable signal WL _ en based on a unique value (e.g., 000) of address bits Addr _1 through Addr _3, which is configured to assert a corresponding global word line signal for programming or reading purposes. The word line enable signal wl _ en is applied to the inverter I₅₃Is input. WL decode circuit 520 and inverter I₅₃Are all supplied by the core voltage domain VDD _ MX.

Inverter I₅₃Is coupled to an input of a voltage level shifter 530. The voltage level shifter 530 includes a first inverter I coupled to a second inverter I₅₄Is transported byAnd (4) input and output. Inverter I₅₄The corresponding global word line signal gwl1 is output. Voltage level shifter 530 and inverter I₅₄Is powered by the output voltage domain VDD _ WL of the power multiplexer 510.

In operation, during programming, a read/non-write enable signalIs set to a logic low voltage (e.g., at VSS). In response, inverter I₅₁A logic high voltage (e.g., at VDD _ PX) is generated. This causes PMOS M51 to turn off and inverter I₅₂A logic low voltage (e.g., at VSS) is output. By an inverter I₅₂The logic low voltage of the output causes PMOS M52 to turn on. Therefore, the power multiplexer 510 generates the output voltage domain VDD _ WL with the programming voltage VDD _ PX.

Based on the unique values (e.g., 000) of the address bits Addr _1 through Addr _3, the WL decode circuit 520 generates the asserted word line enable signal WL _ en as a logic high voltage (e.g., at VDD _ MX). In response, inverter I₅₃A logic low voltage (e.g., at VSS) is generated. The voltage level shifter 530 shifts the input logic low voltage from the VDD _ MX voltage domain to the VDD _ WL voltage domain, which the power multiplexer 510 has set to the VDD _ PX voltage domain. Thus, the voltage level shifter 530 generates a logic low voltage (e.g., VSS). In response, inverter I₅₄The write-asserted global word line signal gwl1 is generated as a logic high voltage in the programming voltage VDD _ PX.

During a read operation, a read/non-write enable signalIs set to a logic high voltage (e.g., at VDD _ PX). In response, inverter I₅₁A logic low voltage (e.g., at VSS) is generated. This causes PMOS M51 to turn on and inverter I₅₂A logic high voltage (e.g., at VDD _ PX) is output. By an inverter I₅₂The output logic high voltage causes PMOS M52 to turn off. Thus, the power multiplexer 510 generates the output voltage domain VDD _ WL with the read (core) voltage VDD _ MX.

Based on the unique values (e.g., 000) of the address bits Addr _1 through Addr _3, the WL decode circuit 520 generates the asserted word line enable signal WL _ en as a logic high voltage (e.g., at VDD _ MX). In response, inverter I₅₃A logic low voltage (e.g., at VSS) is generated. The voltage level shifter 530 shifts the input logic low voltage from the VDD _ MX voltage domain to the VDD _ WL voltage domain, which the power mux 510 has set to. Thus, the voltage level shifter 530 generates a logic low voltage (e.g., VSS). In response, inverter I₅₄The read-asserted global word line signal gwl1 is generated as a logic high voltage in the read (core) voltage domain VDD _ MX.

When the global word line driver 500 is idle (e.g., generating a deasserted global word line signal gwl1), the WL decode circuit 520 generates a deasserted word line enable signal WL _ en (e.g., a logic low signal) based on the value of address bits Addr _1 through Addr _3 (e.g., a value other than 000) that does not result in an asserted global word line signal gwl 1. In response, inverter I₅₃A logic high voltage is generated (e.g., at VDD _ MX). The voltage level shifter 530 generates a logic high voltage of the VDD _ WL voltage domain, which may be at VDD _ PX or VDD _ MX, depending on the configuration of the power multiplexer 510. In response, inverter I₅₄The deasserted global word line signal gwl1 is generated as a low logic voltage (e.g., at VSS).

FIG. 6 shows a schematic diagram of an exemplary multiple-input OR gate 600, according to another aspect of the invention. Or gate 600 is an example of a detailed implementation of any of the multiple-input or gates 330-1 through 330-K and 430-1 through 430-K of OTP memories 300 and 400 previously discussed. For ease of description, multiple-input OR gate 600 is depicted as a detailed implementation of multiple-input OR gate 330-1.

The OR gate circuit 600 includes a set of cascaded NOR gates and inverter pairs A₆₁-I₆₁、A₆₂-I₆₂To A_6J-I_6J. The number of nor gate and inverter pairs is equal to the number of bit lines in the sub-array. For example, referring to OTP memories 300 and 400, a subset of memory cells C11 through CMJ is includedThe array includes J bit lines. First NOR gate A₆₁Inputs are included for receiving a read enable signal R _ EN and a first bit line programming signal bl 1. Second NOR gate A₆₂Comprising an input for receiving a first inverter I₆₁And a second bit line programming signal bl 2. J-th NOR gate A_6JComprising an input for receiving a previous inverter I_6(J-1)And a jth bit line programming signal blj. All NOR gates A₆₁To A_6JAnd inverter I61-A6J is powered by programming voltage VDD _ PX.

In operation, during programming of a memory cell coupled to a selected one of bit lines BD 1-BDJ, a corresponding bit line programming signal is asserted (e.g., at VDD _ PX). This causes the multiple-input or gate circuit 600 to generate the asserted subarray enable signal sa _ en 1. As previously described, the asserted subarray enable signal sa _ en1 is applied to a respective second input of local drivers LD11 through LDM 1. Also, as previously described, the global word line associated with the memory cell to be programmed is asserted, which is applied to a corresponding one of these local drivers LD11 through LDM 1. Such local drivers receive the asserted global word line signal and the asserted subarray enable signal and, thus, generate a write-asserted local word line signal at the programming voltage VDD _ PX to program the selected memory cell.

As previously described, during a read operation, the read enable signal R _ EN is asserted (e.g., set to the programming voltage VDD _ PX). This causes the multiple-input or gate circuit 600 to generate the asserted subarray enable signal sa _ en1 (e.g., at VDD _ PX). As previously described, all other multiple-input or gates of the OTP memory generate the sub-array enable signal that is asserted. Local drivers that receive the asserted subarray enable signal and the asserted global word line signal, respectively, generate a read-asserted local word line signal at a read (core) voltage VDD _ MX to enable data reading from the memory cells by the sense amplifiers.

Fig. 7 shows a schematic diagram of an exemplary local (wordline) driver 700 in accordance with another aspect of the present disclosure. The local driver 700 is an example of a detailed implementation of any of the local drivers LD11 through LDMN of OTP memories 300 and 400 previously discussed. For ease of description, local driver 700 is described as a detailed implementation of local driver LD 11.

Specifically, the local driver 700 includes a power multiplexer ("power multiplexer") 710, a nand gate a₇₁And an inverter I₇₃. The power multiplexer 710 further includes an inverter I₇₁PMOS M71, inverter I₇₂And PMOS M72.

With respect to the power multiplexer 710, inverter I₇₁Includes an input configured to receive a read/non-write enable signal based on a control signal generated by controller 350 or 450 of OTP memory 300 or 400Inverter I₇₁Including an output coupled to the gate of PMOS M71 and inverter I₇₂Is input. The source and drain of PMOS M71 are coupled between the read voltage domain rail VDD _ MX and the output voltage domain rail VDD _ WL of power multiplexer 710. Inverter I₇₂Including an output coupled to the gate of PMOS M72. The source and drain of PMOS M72 are coupled between the programming voltage domain rail VDD _ MX and the output voltage domain rail VDD _ WL of power multiplexer 710. As shown, inverter I₇₁And I₇₂Powered by the programming voltage VDD _ PX.

NAND gate A₇₁Including a first input for receiving a global word line signal GWL1 from a corresponding global word line GWL1 and a second input for receiving a subarray enable signal sa _ en1 from a multi-input or gate circuit 330-1 or 430-1. NAND gate A₇₁Is coupled to an inverter I₇₃Is input. Inverter I₇₃A local wordline signal lwl11 is generated. And gate A₇₁And an inverter I₇₃The selected voltage domain VDD _ WL output by the power multiplexer 710 is powered.

In operation, during programming, a read/non-write enable signalIs set to a logic low voltage (e.g., at VSS). In response, inverter I₇₁GeneratingA logic high voltage (e.g., at VDD _ PX). This causes PMOS M71 to turn off and inverter I₇₂A logic low voltage (e.g., at VSS) is output. By an inverter I₇₂The logic low voltage of the output causes PMOS M72 to turn on. Therefore, the power multiplexer 710 generates the output voltage domain VDD _ WL with the programming voltage VDD _ PX.

In addition, during programming, nand gate a₇₁A write-asserted global word line signal gwl1 and an asserted subarray enable signal sa _ en1 are received. In response, NAND gate A₇₁A logic low voltage (e.g., at VSS) is generated. In response to a logic low voltage, inverter I₇₃The write-asserted local word line signal lwl11 is generated as a logic high voltage (e.g., at VDD _ PX) for programming one or more memory cells that receive the signal.

During reading, read/non-write enable signalIs set to a logic high voltage (e.g., at VDD _ PX). In response, inverter I₇₁A logic low voltage (e.g., at VSS) is generated. This causes PMOS M71 to turn on and inverter I₇₂A logic high voltage (e.g., at VDD _ PX) is output. By an inverter I₇₂The output logic high voltage causes PMOS M72 to turn off. Thus, the power multiplexer 710 generates the output voltage domain VDD _ WL with the read (core) voltage VDD _ MX.

In addition, during reading, the NAND gate A₇₁A read asserted global word line signal gwl1 and an asserted subarray enable signal sa _ en1 are received. In response, NAND gate A₇₁A logic low voltage (e.g., at VSS) is generated. In response to a logic low voltage, inverter I₇₃The read-asserted local word line signal lwl11 is generated as a logic high voltage (e.g., at VDD _ MX) for enabling reading of data from the one or more memory cells that receive the signal.

FIG. 8 illustrates a flow chart of an exemplary method 800 of accessing (programming or reading) at least one of a group of memory cells in accordance with another aspect of the invention. The method 800 includes generating a first asserted signal on a global word line (block 810). Examples of means for generating the first assertion signal on the global word line include any one of the global word line drivers WD1 through WDM in the OTP memories 300 and 400, and the global word line driver 500.

The method 800 also includes generating a second assert signal (block 820). Examples of means for generating the second assert signal include any of the multiple-input or gates 330-1 through 330-K, 430-1 through 430-K, and the multiple-or gate 600.

The method 800 also includes generating a third asserted signal on the local word line for accessing at least one memory cell of the set of memory cells in response to receiving the second asserted signal from the global word line and receiving the third asserted signal (block 830). Examples of means for generating the third assertion signal include any one of the local word line drivers LD11 through LDMK and the local word line driver 700 in the OTP memories 300 and 400.

The previous description of the invention is provided to enable any person skilled in the art to make or use the invention. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (27)

1. A memory, comprising:

a first global word line;

a first group of bit lines;

a first local word line;

a first set of memory cells coupled to the first local word line and respectively coupled to the first set of bit lines;

a first local word line driver configured to generate a first assert signal on the first local word line in response to: receiving a second assertion signal from the first global word line and receiving a third assertion signal;

a first set of bit line drivers configured to apply programming voltages on the first set of bit lines based on a first set of bit line programming signals, respectively; and

a multi-input OR gate configured to generate the third asserted signal in response to at least one bit line programming signal of the first set of bit line programming signals being asserted.

2. The memory of claim 1, wherein the third asserted signal indicates that: at least one of the programming voltages is applied to at least one bit line of the first set of bit lines to respectively program at least one memory cell of the first set of memory cells.

3. The memory of claim 1, wherein the first asserted signal is configured to enable programming of the at least one memory cell in the first set of memory cells.

4. The memory of claim 1, further comprising a sense amplifier coupled to the first set of bit lines, wherein the first asserted signal is configured to enable a data read from the first set of memory cells through the sense amplifier.

5. The memory of claim 4, wherein the first set of bit line drivers are configured to be in a high impedance state during the reading of data from the first set of memory cells by the sense amplifier.

6. The memory of claim 1, wherein at least one memory cell in the first set of memory cells is configured as an EFUSE memory cell.

7. The memory of claim 1, wherein at least one memory cell in the first set of memory cells comprises a fuse element coupled in series with a transistor between a corresponding bit line in the first set of bit lines and a voltage rail.

8. The memory of claim 1, wherein at least one memory cell in the first set of memory cells is configured as an antifuse memory cell.

9. The memory of claim 1, wherein at least one memory cell in the first set of memory cells each includes at least one core device.

10. The memory of claim 1, further comprising:

a second local word line;

a second group of bit lines;

a second set of memory cells coupled to the second local word line and respectively coupled to the second set of bit lines; and

a second local word line driver configured to generate a fourth assert signal on the second local word line in response to: the second assertion signal is received from the first global word line, and a fifth assertion signal is received.

11. The memory of claim 1, further comprising:

a second global word line;

a second local word line;

a second set of memory cells coupled to the second local word line and respectively coupled to the first set of bit lines; and

a second local word line driver configured to generate a fourth assert signal on the second local word line in response to: a fifth assertion signal is received from the second global word line and the third assertion signal is received.

12. The memory of claim 1, further comprising a word line decoder comprising a global word line driver configured to generate the second asserted signal.

13. The memory of claim 12, wherein the global word line driver is configured to:

generating the second asserted signal at a first voltage for enabling programming of at least one memory cell of the first group of memory cells; or

Generating the second asserted signal at a second voltage for enabling a data read from at least one memory cell in the first group of memory cells.

14. A method, comprising:

generating a first asserted signal on a global word line;

generating a second assertion signal;

in response to receiving the first assertion signal from the global word line and receiving the second assertion signal, generating a third assertion signal on a local word line for accessing at least one memory cell of a group of memory cells;

generating at least one programming voltage on a set of bit lines based on a set of bit line programming signals, respectively; and

performing a logical OR operation of the bit line programming signal to generate the second asserted signal.

15. The method of claim 14, wherein the third asserted signal indicates that the at least one of the programming voltages is applied to at least one bit line of the set of bit lines coupled to the set of memory cells, respectively.

16. The method of claim 14, wherein the third asserted signal is configured to enable programming of the at least one memory cell in the group of memory cells.

17. The method of claim 14, further comprising generating a fourth assertion signal configured to enable a data read from the at least one memory cell of the group of memory cells, wherein the fourth assertion signal is generated in response to receiving a fifth assertion signal from the global word line and receiving a sixth assertion signal.

18. The method of claim 14, wherein at least one memory cell in the set of memory cells is configured as an EFUSE memory cell.

19. The method of claim 14, wherein at least one memory cell in the set of memory cells is configured as an antifuse memory cell.

20. The method of claim 14, wherein at least one memory cell in the set of memory cells each includes at least one core device.

21. An apparatus, comprising:

means for generating a first assert signal on a global word line;

means for generating a second assert signal;

means for generating a third assertion signal on a local word line for accessing at least one memory cell of a group of memory cells in response to receiving the first assertion signal from the global word line and receiving the second assertion signal; and

means for generating at least one programming voltage on a set of bit lines based on a set of bit line programming signals, respectively; and

means for performing a logical OR operation of the bit line programming signal to generate the second asserted signal.

22. The device of claim 21, wherein the third asserted signal indicates that: a program voltage is applied to at least one bit line of the set of bit lines for programming the at least one memory cell of the set of memory cells.

23. The apparatus of claim 21, wherein the third asserted signal is configured to enable programming of at least one memory cell of the group of memory cells.

24. The apparatus of claim 21, further comprising means for generating a fourth assert signal configured to enable a data read from at least one memory cell in the set of memory cells, wherein the fourth assert signal is generated in response to receiving a fifth assert signal from the global word line and receiving a sixth assert signal.

25. The apparatus of claim 21, wherein at least one memory cell in the set of memory cells is configured as an EFUSE memory cell.

26. The apparatus of claim 21, wherein at least one memory cell in the set of memory cells is configured as an antifuse memory cell.

27. The apparatus of claim 21, wherein at least one memory cell in the set of memory cells comprises at least one core device.