HK1138691B - Method and system for processing communication signals - Google Patents

Description

Method and system for processing communication signals

Technical Field

Certain embodiments of the present invention relate to a method and system for Reference Signal (RS) clock loop for OFDM symbol synchronization and tracking.

Background

Mobile communications have changed the way people communicate, and mobile phones have also changed from a luxury item to an essential part of everyday life. Today, the use of mobile devices is governed by the social environment and is not limited by geography or technology. Although voice communication can satisfy the basic requirements of people for communication and mobile voice communication has further penetrated people's daily lives, the next stage of mobile communication development is the mobile internet. The mobile internet will become a common source of everyday information and it is of course desirable to enable simple and universal mobile access to such data.

Third Generation (3G) cellular networks are specifically designed to meet these future demands of the mobile internet. With the proliferation and use of these services, cost-effective optimization of network capacity and Quality of Service (QoS) factors will become more important to cellular network operators than today. These factors can be achieved through careful network planning and operation, improvement of transmission methods, and improvement of receiver technology. Accordingly, operators need new techniques to increase downstream throughput to provide better QoS capacity and rate than those of cable modem and/or DSL service providers. Recently, advances in multi-antenna technology and other physical layer technologies have begun to significantly increase the available communication data rates.

Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.

Disclosure of Invention

A method and/or system for a Reference Signal (RS) clock loop for OFDM symbol synchronization and tracking, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.

Clock loop according to an aspect of the invention, a method for processing a communication signal, comprises:

tracking a symbol clock in an Orthogonal Frequency Division Multiplexing (OFDM) signal based at least on a reference symbol group; and

adjusting a receiver clock based at least on the symbol clock.

Preferably, the method further comprises tracking the symbol clock by generating an output signal, the output signal being a guard time Δ t_gAs a function of (c).

Preferably, the method further comprises generating the output signal in a phase discrimination feedback loop.

Preferably, the method further comprises generating the set of Reference Symbols (RS) from at least a fast fourier transform of the received OFDM signal in an RS extraction module.

Preferably, the method further comprises fine tuning the symbol clock.

Preferably, the method further comprises coarse adjusting the symbol clock prior to the fine adjustment.

Preferably, the method further comprises generating the coarse symbol clock adjustment based on processing at least a primary synchronization signal and a secondary synchronization signal.

Preferably, the reference symbol group includes a plurality of time-frequency slots (slots).

Preferably, the plurality of time-frequency gaps vary according to a pseudo-noise sequence that shifts and modulates the set of reference symbols.

Preferably, the OFDM signal conforms to a Universal Mobile Telecommunications Standard (UMTS) Long Term Evolution (LTE) signal.

Preferably, the method further comprises controlling the adjustment of the receiver clock by a receiver clock generator.

According to an aspect, there is provided a system for processing a communication signal, comprising:

one or more circuits in a receiver to at least:

tracking a symbol clock in an Orthogonal Frequency Division Multiplexing (OFDM) signal based at least on a reference symbol group; and

adjusting a receiver clock based at least on the symbol clock.

Preferably, the one or more circuits track the symbol clock by generating an output signal, the output signal being a guard time Δ t_gAs a function of (c).

Preferably, the one or more circuits generate the output signal in a phase discrimination feedback loop.

Preferably, the one or more circuits generate the set of Reference Symbols (RS) from at least a fast fourier transform of the received OFDM signal in an RS extraction module.

Preferably, the one or more circuits fine-tune the symbol clock.

Preferably, the one or more circuits coarsely adjust the symbol clock prior to the fine adjustment.

Preferably, the one or more circuits generate the coarse symbol clock adjustment based on processing at least a primary synchronization signal and a secondary synchronization signal.

Preferably, the reference symbol group includes a plurality of time-frequency slots.

Preferably, the plurality of time-frequency gaps vary according to a pseudo-noise sequence that shifts and modulates the set of reference symbols.

Preferably, the OFDM signal conforms to a Universal Mobile Telecommunications Standard (UMTS) Long Term Evolution (LTE) signal.

Preferably, the one or more circuits control adjustment of the receiver clock by a receiver clock generator.

Various advantages, aspects and novel features of the invention, as well as details of an illustrated embodiment thereof, will be more fully described with reference to the following description and drawings.

Drawings

FIG. 1A is a diagram of exemplary cellular multipath communications between a base station and a mobile computing terminal, according to an embodiment of the present invention;

fig. 1B is a schematic diagram of an exemplary MIMO communication system in accordance with an embodiment of the present invention;

FIG. 2 is a diagram of an exemplary OFDM symbol stream in accordance with an embodiment of the present invention;

FIG. 3A is a schematic diagram of an exemplary OFDM clock acquisition and tracking system according to an embodiment of the present invention;

FIG. 3B is a schematic diagram of phase offsets for an exemplary clock offset according to various embodiments of the invention;

FIG. 3C is a diagram of exemplary clock offset phase offset by subcarrier, according to various embodiments of the invention;

FIG. 4 is a flow diagram of an exemplary clock acquisition and tracking process according to an embodiment of the invention.

Detailed Description

Certain embodiments of the invention may be used in methods and systems for RS clock loops (timing loops) for OFDM symbol synchronization and tracking. An aspect of a method and system for Reference Signal (RS) clock loop for OFDM symbol synchronization and tracking may include tracking a symbol clock in an Orthogonal Frequency Division Multiplexing (OFDM) signal based at least on a reference symbol group. A receiver clock may be adjusted based at least on the symbol clock.

The symbol clock can be tracked by generating an output signal that is the guard time Δ t in the phase discrimination feedback loop_gAs a function of (c). A set of Reference Symbols (RS) may be generated in an RS extraction module or circuit from at least a fast fourier transform of the received OFDM signal. The receiver clock may be coarsely adjusted and then finely adjusted. A coarse receiver clock adjustment may be generated based on processing at least the primary synchronization signal and the secondary synchronization signal. The reference symbol group includes a plurality of time-frequency slots (slots). The plurality of time-frequency slots vary according to the frequency shift and the PN sequence of the modulated reference symbol group. The PN generated sequence may be determined by a base station discriminator. This base station discriminator is determined by the Primary Synchronization Signal (PSS) and the Secondary Synchronization Signal (SSS). The OFDM signal may conform to a Universal Mobile Telecommunications Standard (UMTS) Long Term Evolution (LTE) signal. The adjustment of the receiver clock may be controlled by the receiver clock generator.

FIG. 1A is a diagram of exemplary cellular multipath communications between a base station and a mobile computing terminal, according to an embodiment of the present invention. Referring to fig. 1A, a building 140 (e.g., a house or office), a mobile terminal 142, a factory 124, a base station 126, a car 128, and communication paths 130, 132, and 134 are shown.

The base station 126 and the mobile terminal 142 may comprise suitable logic, circuitry, and/or code that may enable generating and/or processing MIMO communication signals.

Wireless communications between base station 126 and mobile terminal 142 may occur over a wireless channel. The wireless channel may include multiple communication paths, such as communication paths 130, 132, and 134. The wireless channel may change dynamically as the mobile terminal 142 and/or the automobile 128 move. In some cases, the mobile terminal 142 may be located within a line of sight (LOS) of the base station 126. In other cases, the mobile terminal 142 and the base station 126 may not be in direct line of sight and the radio frequency signals may travel along reflected communication paths between the communicating entities, as shown by exemplary communication paths 130, 132, and 134. The radio frequency signal may be reflected by artificial structures (e.g., buildings 140, factories 124, or automobiles 128) or natural obstacles (e.g., hills). Such a system may be referred to as a non line of sight (NLOS) communication system.

The signal communication of the communication system may include LOS and NLOS signal components. If an LOS signal component is present, it will be much stronger than an NLOS signal component. In some communication systems, NLOS signal components can create interference and degrade receiver performance. This may be referred to as multipath interference. The communication paths 130, 132, and 134 may reach the mobile terminal 142 with different delays. Communication paths 130, 132, and 134 may also be impaired to varying degrees. In the downlink, for example, the received signal at the mobile terminal 142 may be a summation of the communication paths 130, 132, and/or 134 attenuated to varying degrees, where the communication paths 130, 132, and/or 134 may not be synchronized and may dynamically change. Such a channel may be referred to as a fading multipath signal.

Fading multipath signals can introduce interference, but it can also introduce diversity and degrees of freedom into the wireless channel. Communication systems having multiple antennas at the base station and/or mobile terminal, such as MIMO systems, are particularly well suited to use the characteristics of the wireless channel, can obtain significant performance gains from a fading multipath channel, and can significantly increase performance, especially for NLOS signals, as compared to communication systems having a single antenna at the base station 126 and/or mobile terminal 142. In addition, Orthogonal Frequency Division Multiplexing (OFDM) systems may also be applicable to wireless systems with multipath.

Fig. 1B is a schematic diagram of an exemplary MIMO communication system in accordance with an embodiment of the present invention. Referring to fig. 1B, a MIMO transmitter 102 and a MIMO receiver 104 are shown, along with antennas 106, 108, 110, 112, 114, and 116. MIMO transmitter 102 may include a processor module 118, a memory module 120, and a signal processing module 122. The MIMO receiver 104 may include a processor module 124, a memory module 126, and a signal processing module 128. Also shown is a wireless channel comprising a communication path h₁₁、h₁₂、h₂₂、h₂₁、h_{2 NTX}、h_{1 NTX}、h_{NRX 1}、h_{NRX 2}、h_{NRX NTX}Wherein h is_mnRepresenting the channel coefficients from transmit antenna n to receiver antenna m. May have N_TXA transmitting antenna and N_RXA receiving antenna. Also shown is a transmitted symbol x₁、x₂、x_NTXAnd receiving the symbol y₁、y₂、y_NRX。

The MIMO transmitter 102 may comprise suitable logic, circuitry, and/or code that may enable generation of a transmit symbol x_i，i∈{1，2，...N_TXH, transmit symbol x_iMay be transmitted by transmit antennas, such as transmit antennas 106, 108, and 110 in fig. 1B. The processor module 118 may comprise suitable logic, circuitry, and/or code that may enable processing of signals. The memory module 120 may comprise suitable logic, circuitry, and/or code that may enable storage and/or retrieval of information for processing in the MIMO transmitter 102. The signal processing module 122 may comprise suitable logic, circuitry, and/or code that may be operable to process signals, for example, according to one or more MIMO transmission protocols.The MIMO receiver 104 may comprise suitable logic, circuitry, and/or code that may enable processing of the received symbols y_i，i∈{1，2，...N_RXReceives the symbol y_iMay be received by receive antennas, such as receive antennas 112, 114, and 116 in fig. 1B. The processor module 124 may comprise suitable logic, circuitry, and code that may enable processing of signals. The memory module 126 may comprise suitable logic, circuitry, and/or code that may enable storage and/or retrieval of information for processing in the MIMO receiver 104. The signal processing module 128 may comprise suitable logic, circuitry, and/or code that may be operable to process signals according to one or more MIMO protocols, for example. The input-output relationship of the transmitted and received signals in a MIMO system is as follows:

y＝Hx+n

wherein y ═ y₁，y₂，...y_NRX]^TMay be of N_RXThe column vector of the elements.^TCan represent vector transposition, H ═ H_ij]：i∈{1，2，...N_RX}；j∈{1，2，...N_TXCan be of dimension N_RX*N_TXX ═ x₁，x₂，...X_NTX]^TMay be of N_TXColumn vector of elements, N being of N_RXA column vector of random samples of elements.

The system shown in fig. 1B illustrates an exemplary multi-antenna system, which is used in a Universal Mobile Telecommunications System (UMTS) Long Term Evolution (LTE) system. Can pass through N_TXEach of which transmits a stream of symbols, e.g., x via antenna 106₁(t) of (d). A stream of symbols, e.g. x₁(t) may comprise one or more symbols, where each symbol may be modulated to a different subcarrier. OFDM systems typically use a relatively large number of subcarriers in parallel for each symbol stream. For example, the symbol stream x₁(t) may include a carrier f_m: m ∈ {1, 2.. M }, M may be a subset of the FFT size that may be employed at the receiver. For example, with an FFT size of N, M < N, guard audio may be generated, which when employed, allowsDifferent bandwidths are utilized. The M subcarriers may comprise a stream of symbols x₁(t), the symbol stream x₁(t) may occupy a bandwidth of several kilohertz to several megahertz. The universal bandwidth may be between 1 mhz and 100 mhz. Thus, each symbol stream may include one or more subcarriers, and for each subcarrier, the wireless channel may include multiple transmit paths. For example, a wireless channel h from the transmit antenna 108 to the receive antenna 112₁₂And, as shown, may be multi-dimensional. In particular, the radio channel h₁₂A time impulse response may be included that includes one or more multipath components. Radio channel h₁₂May also include a stream of symbols (e.g., x)₂(t)) of each subcarrier f_mDifferent time impulse responses. Finally, the wireless channel as shown in fig. 1b describes the spatial dimension of the wireless channel, since the signal transmitted by each transmit antenna can be received differently at each receive antenna. Thus, the channel impulse response of each subcarrier can be measured and/or estimated.

Fig. 2 is a diagram of an exemplary OFDM symbol stream in accordance with an embodiment of the present invention. Referring to fig. 2, a time axis 210 is shown, time domain symbol 0 including cyclic prefix CP (0)202a, Inverse Fast Fourier Transform (IFFT) symbol less CP (0) (IFFT (0))202b, and cyclic prefix CP (0)202c, time domain symbol 1 including cyclic prefix CP (1)204a, IFFT symbol less CP (1) (IFFT (1))204b, and cyclic prefix CP (1)204 c. IFFT (0)202b and CP (0)202c may together form a complete IFFT symbol for time domain symbol 0. CP (0)202a may be completely similar to CP (0)202 c. Similarly, IFFT (1)204b and CP (1)204c may together form a complete IFFT symbol for time domain symbol 1, and CP (1)202a may be completely similar to CP (1)202 c. Also shown is an FFT input window 206, a guard time Δ t_gAnd gap markings 208. LET slot composition, for example, each slot (2 slots are shown in fig. 2) may include 3, 6, or 7 OFDM symbols.

To generate Orthogonal Frequency Division Multiplexed (OFDM) symbols, the output of the IFFT, including IFFT (0)202b and CP (0)202c, can be used to generate CP (0)202a from CP (0)202c and append it to IFFT (0)202 b. The cyclic prefix CP (0)202 may be used to avoid inter-symbol interference at the OFDM receiver when multipath propagation occurs in the wireless channel.

At an OFDM receiver, for example, MIMO receiver 104, the sampled input signal may be processed for each received symbol through FFT input window 206. To decode these received symbols, it is desirable for the FFT input window to be located within the time domain symbol slot, e.g., at time domain symbol 0. In particular, it is desirable that the FFT input window 206 does not extend to adjacent symbols to avoid inter-symbol interference. Thus, as shown in fig. 2, the gap marker may indicate the start of a gap, e.g., time domain symbol slot 0. Gap mark 208 is equal to Δ t_gTogether defining the position of the FFT input window 206 in the symbol interval. In most cases, to keep the interference at the receiver due to multipath channels as low as possible, it is desirable that Δ t be_gAnd remain small.

Therefore, it is desirable to acquire a symbol level clock (symbol level timing) and keep it so that the symbol level clock may drift due to propagation changes caused by movement. In some cases, this may be combined with other clock stage acquisition and tracking, such as frame synchronization. In many cases, synchronization by Primary Synchronization Signals (PSS) and Secondary Synchronization Signals (SSS) may be achieved by other means. The symbol clock may be obtained by a clock acquisition and tracking system that may employ a Reference Signal (RS) embedded in the OFDM signal. The reference symbols may be known symbols that are transmitted in an OFDM system on time, frequency and spatial sources in a known manner. In other words, the reference symbols may be transmitted over certain antennas on known OFDM subcarriers with certain known clocking conditions. By decoding and processing the RS symbols, the receiver can determine the correct clock information by coherent demodulation. RS symbols may be transmitted from each antenna in a multi-antenna OFDM system.

In an Enhanced Universal Terrestrial Radio Access (EUTRA) interface, RS symbols may be generated based on a cell-specific hopping pattern. The RS symbol may include a Pseudo Noise (PN) carrier sequence (pseudo noise) of the reference symbol. According to embodiments of the present invention, the RS tone spacing (tone spacing) may be, for example, 6 carriers per transmit antenna. The RS audio interval may be, for example, 2 or 4 carriers, according to various embodiments of the present invention. The RS sequence may not be known to the mobile terminal (user equipment, UE) during initial acquisition by the synchronization signal. In some cases, after acquiring the Primary Synchronization Signal (PSS) and Secondary Synchronization Signal (SSS), the UE may have obtained a cell-specific hopping pattern of RS symbols, as well as the PN covering sequence. This information can be used to obtain a coarse frame clock. The RS symbols are then decoded in a clock acquisition and tracking module to provide fine clocking and tracking according to various embodiments of the invention. Thus, for example, Universal Mobile Telecommunications Standard (UMTS) Long Term Evolution (LTE) may use a three step process for clock recovery. The three steps include: a) recovering a gap clock from the PSS; b) recovering a frame clock from the SSS; and c) obtaining an estimate of clock bias and tracking from the RS symbol.

Fig. 3A is a schematic diagram of an exemplary OFDM clock acquisition and tracking system, according to an embodiment of the invention. Referring to fig. 3, a common receiver portion 342 is shown, along with a clock portion 340. The clock section 340 may include the RS phase discriminator 302, the adder 304, the delay module 306, the integrator 308, and the threshold module 310. Also shown are the RS bank input, the error signal ek, the accumulator signal tt _ loop _ accum, the threshold input signal, the reset control signal reset _ cntrl, and the output signal to _ accum. The common receiver portion 342 may include a clock generator 312, an RS extraction module or circuit 314, a channel estimation module 316, a receiver execution module (RXCVR)318, a Fast Fourier Transform (FFT) module 320, a buffering module 330, a sampling Bandwidth (BW) filter 332, and an analog-to-digital conversion module 334. Also shown are the RF filter input, the gap clock input from the PSS, the RS bank output, the to _ accum signal, the RS _ strb signal, and the slot _ strb signal.

The clock section 340 may comprise suitable logic, circuitry, and/or code that may enable extraction of clock information by processing the set of RSs of the signal, which may generate, for example, the output to _ accum of the control clock generator 312. The RS phase discriminator 302 may includeSuitable logic, circuitry and/or code that may enable comparing a clock of an RS group input signal with, for example, an input clock signal and generating an error signal e_k。

The adder 304 may comprise suitable logic, circuitry, and/or code that may enable generation of a weighted sum signal at its output based on a plurality of inputs. The delay block 306 may comprise suitable logic, circuitry, and/or code that may enable delaying an input signal by a particular time interval, such as one or more sample periods.

The integrator 308 may comprise suitable logic, circuitry, and/or code that may enable generation of an output that is an integration of one or more input signals, and the integrator 308 may be reset by the reset _ cntrl signal. The threshold module 310 may comprise suitable logic, circuitry, and/or code that may enable comparing a threshold input signal with a tt _ loop _ accum input signal and generating output signals reset _ cntrl and to _ accum. For example, when the tt _ loop _ accum signal exceeds a threshold level, the reset _ cntrl signal may activate and reset, for example, the integrator 308.

The common receiver portion 342 may comprise suitable logic, circuitry, and/or code that may enable receiving and processing of radio frequency signals. The processing includes FFT computation, RS symbol extraction, channel estimation, and other receiver signal processing. The clock generator 312 may comprise suitable logic, circuitry, and/or code that may enable generation of a clock signal RS _ strb and a slot clock slot _ strb for RS extraction. The signal slot _ strb may be used to control, for example, the FFT clock in the buffer block 330. The block or circuit 314 may comprise suitable logic, circuitry, and/or code that may enable extraction of RS symbols from the FFT block or circuit 320 output.

The channel estimation block or circuitry 316 may comprise suitable logic, circuitry, and/or code that may enable estimation of the wireless channel response of the RS symbol, as may be required for receiver operation. The receiver operation module or circuit (RXCVR)318 may comprise suitable logic, circuitry, and/or code that may enable measuring and/or verifying performance during operation of the receiver. The Fast Fourier Transform (FFT) block or circuit 320 may comprise suitable logic, circuitry, and/or code that may enable generation of a fast fourier transform for an input signal. The buffering module or circuitry 330 may comprise suitable logic, circuitry, and/or code that may enable interaction with an FFT engine. The caching module or circuitry 330 may facilitate, for example, dedicated procedures, measurement procedures, Multimedia Broadcast Multicast Service (MBMS), and/or SSS processing for hop-variant decisions. In some cases, each of these processes may be performed in parallel. The sampling BW filter 332 may comprise suitable logic, circuitry, and/or code that may be operable to filter a signal at its input and generate an output signal with a limited bandwidth.

The analog-to-digital conversion (A2D) block or circuit 334 may comprise suitable logic, circuitry, and/or code that may be operable to receive an analog RF filtered signal and convert it at an output to a representation of a digital signal, with any number of bits. The main timer 336 may comprise suitable logic, circuitry, and/or code that may enable basic timing functions in a receiver. In some cases, main timer 336 may count for more than 10ms and may count at, for example, 30.72 MHz. The main timer 336 may include a gap timer, a sample timer. The input to main timer 336 may be provided by an operating RF crystal (also referred to as TXCO).

The common receiver portion 342 may receive and process radio frequency signals. Processing may include FFT computation, RS symbol extraction, channel estimation, and other receiver signal processing. Some clock aspects of the common receiver portion 342 may be controlled by the clock portion 340. For example, the symbol clock on one or more receiver sub-carriers/carrier frequencies (e.g., f1 and/or f2 in fig. 2) may be determined.

The RS phase discriminator 302 may receive at its input a set of RS symbols, which may be extracted in an RS extraction module or circuit 314 to determine clock information associated with the RS carrier. A second input of the adder 304 may be connected to an output of the delay block or circuit, and an output of the adder 304 may be a weighted sum of its inputs. The delay module or circuit may delay the input signal by a particular time interval, such as one or more sampling phases. The delay module or circuit 306 may provide an appropriate delay for the feedback signal provided to the summer 304 from the integrator 308.

An output tt _ loop _ accum of the adder 304 is communicatively coupled to a first input of a threshold module or circuit 310 and to a first input of an integrator 308. A second input of the threshold module or circuit 310 is connected to a threshold-level defining signal. The threshold module or circuit 310 may compare the threshold signal to the tt _ loop _ accum signal to generate output signals reset _ cntrl and to _ accum. For example, when the tt _ loop _ accum signal exceeds a threshold level, reset _ cntrl may activate and reset integrator 308, the to _ accum signal may increase at a rate that is a function of Δ t, and the to _ accum signal allows information about Δ t to be passed to, for example, clock generator 312, which in turn controls the position of the FFE input window in the time domain, according to embodiments of the present invention. The second input to integrator 308 may be set at a known constant level, such as zero. The integrator 308 may integrate one or more input signals, and the integrator 308 may be reset by the reset _ cntrl signal.

An analog-to-digital conversion (A2D) module or circuit 334 may receive the analog RF filtered signal and convert it at an output to a digital signal representation with any number of bits. An output of A2D 334 is communicatively coupled to an input of sampling BW filter 332. The sampling BW filter 332 may filter the signal at its input and generate an output signal of limited bandwidth and/or attenuate certain frequency bands. The output of the sampling BW filter 332 is communicatively coupled to a first input of a buffer module or circuit 330. A second input to the buffer block or circuit 330 is communicatively coupled to the output signal slot strb of the clock generator 312. The buffer module or circuit 330 may interact with the FFT engine. The buffer module or circuitry 330 may facilitate, for example, dedicated procedures, measurement procedures, Multimedia Broadcast Multicast Service (MBMS), and/or SSS processing for RS PN sequence decisions. In some cases, each of these processes may be performed in parallel. The buffer module or circuit 330 is communicatively coupled to the FFT module or circuit 320.

The FFT module or circuit 320 may generate a fast fourier transform for an input signal that is communicatively coupled to the self-buffering module or circuit 330. Similar to the buffer module or circuitry 330, the FFT module or circuitry 320 may facilitate, for example, dedicated procedures, measurement procedures, Multimedia Broadcast Multicast Service (MBMS), and/or SSS processing for radio time frame and hopping pattern decisions. A first output of the FFT module or circuit 320 is communicatively coupled to a first input of the RS extraction module or circuit 314. The RS extraction module or circuit 314 may extract RS symbols from the output of the FFT module or circuit 320. In some cases, it may be desirable to use hopping sequences and/or pseudo-noise (PN) carriers (covering) generated from demodulating base station signals for RS decoding. The RS symbols extracted and output at the RS extraction module or circuit 314 may be communicatively coupled to the clock section 340 and to an input of the channel estimation module or circuit 316. As shown in fig. 3A, the hopping pattern can be fed to the RS extraction module or circuit 314 through the RS _ hopping _ pattern signal on the second input terminal. The RS extraction module or circuit 314 may be clocked by a third input signal RS _ strb, which is communicatively coupled to an output of the clock generator 312.

Clock generator 312 may generate a clock signal RS _ strb for RS extraction, and a slot clock slot _ strb. The signal slot _ strb may be used to control, for example, the FFT clock in the buffer block or circuit 330. Clock generator 312 may generate an output clock signal for clock correction and tracking. The main timer input signal is communicatively coupled to an output of the main timer 336. The main timer 336 may provide basic timing functions in the receiver. In some cases, main timer 336 may count for more than 10ms and may count at, for example, 30.72 MHz. The main timer 336 may include a gap timer, a sample timer. The input to the main timer 336 may be provided by an operating RF crystal (TXCO), such as a temperature controlled crystal oscillator.

The channel estimation module and circuitry 316 may estimate the wireless channel response of the RS symbol, as required for receiver operation. The channel estimate output is communicatively connected to RXCVR 318. The RXCVR 318 may functionally measure and/or confirm the performance of the receiver.

Fig. 3B is a schematic diagram of phase offsets for an exemplary clock offset, according to various embodiments of the invention. Referring to FIG. 3B, a clock bias curve 350a is shown, with Δ t_g1 corresponds to; clock bias curve 350b, and Δ t_gCorresponds to 2; clock bias curve 350c, and Δ t_gCorresponds to 3; and clock bias curve 350d, and Δ t_gCorresponds to 4.

The gap markings may be obtained from the PSS and SSS for locating the received signal within the bandwidth of, for example, the PSS processing. In order for the FFT to equalize the selectivity of the channel, it is desirable that the Cyclic Prefix (CP) can cover the delay spread of the (cover) channel. Also expected is Δ t_gIs minimized to avoid that the sampled input to the FFT process includes adjacent symbols (inter symbol interference-ISI), which degrades performance. But at_gCan be tracked and can guard against clock shifts due to activity, for example.

Shown in the figure as Δ t_gNot equal to 1, a phase offset can be introduced into the FFT output, Δ t_g1 corresponds to no phase offset. The phase offset may be represented by a complex multiplicative factor z (k) applied to the subcarrier, and for subcarrier k may be represented by the following relation:

z(k)＝e^{j(Δtg-1)*(k-1)*2n/N}

where N may be the size of the FFT. When sampling the cyclic prefix, the clock offset may be represented by an increasing phase offset that is exponential in tone. For RS audio, the received channel coefficients may be given by the following relation:

hrx_k＝z_k*h_k+n_k

wherein hrx_kIs the received channel coefficient affected by the phase offset z (k). h is_kIs a channel coefficient without phase offset, and n_kIs the noise term (noise term)). In FIG. 3B, each curve represents a different value of Δ t_gWherein the clock bias curve 350a corresponds to Δ t_gClock bias curve 350b corresponds to Δ t ═ 1_gClock bias curve 350c corresponds to Δ t ═ 2_gAt 3, the clock bias curve 350d corresponds to Δ t_g4. As shown in fig. 3B, the clock bias may introduce a linearly decreasing phase as a function of frequency.

Fig. 3C is a diagram of phase offset for an exemplary clock offset by subcarrier, according to various embodiments of the invention. Referring to FIG. 3, a clock bias curve 352a is shown, with Δ t_gCorresponds to 0; clock bias curve 352b, Δ t with subcarrier 512_g1 corresponds to; clock bias curve 352c, Δ t of subcarrier 511_gCorresponds to 2; and clock bias curve 352d, Δ t of subcarrier 510_gCorresponds to 3.

For Δ t_gThe FFT may be sampled later, and sample clock adjustments are desired. As shown in fig. 3C, for later samples, the clock offset may indicate a phase offset over the bandwidth of the channel, with the phase offsets for the multiple subcarriers being shown as curves 352a-352 d. In some cases, the slope of the phase offset as a function of frequency is linear with the positive slope of the FFT sampled earlier, and the negative slope of the FFT sampled later. An exemplary phase detector may use adjacent RS tones for each OFDM symbol and may be represented by the following relationship:

wherein hrx₁And hrx₁₊₆The phase variation between (another RS tone, spaced by 6 subcarriers) can be averaged over all desired tones and all desired antennas, which is N_tAn item.

FIG. 4 is a flow diagram of an exemplary clock acquisition and tracking process according to an embodiment of the invention. In step 402 after initialization, the primary and secondary synchronization signals (PSS) and (SSS) are decoded in step 404. Decoding of PSS and SSS may provide coarse clock information for synchronization of frames and slots, for example. Using the clock information, the FFT module 320 may generate an FFT of the received signal. From this FFT, the RS extraction module 314 can extract from its internal RS group. This RS group may be fed to the clock section 340. In step 340, clock portion 340 may track Δ t using the feedback loop shown in FIG. 3A_g. Since the output signal to _ accum can be regarded as Δ t_gThe output signal to _ accum from the threshold module 310 may be generated with respect to Δ t_gIs carried to the clock generator 312. Thus, the output signal to _ accum may track the symbol clock and adjust the clock of the receiver, the clock within the clock generator 312. In step 410, the clock generator 312 may adjust the clock based on the input signal in _ accum. The adjusted and tracked clock is communicatively connected from the clock generator 312 to the caching module 330, wherein the clock of the FFT input window may be adjusted accordingly.

In accordance with embodiments of the present invention, a method and system for an RS clock loop for OFDM symbol synchronization and tracking includes tracking a symbol clock in an Orthogonal Frequency Division Multiplexing (OFDM) signal based at least on a reference symbol group, as described in FIGS. 2 and 3A. The receiver clock as described in fig. 2 and 3A may be adjusted based at least on the symbol clock.

The symbol clock can be tracked by generating an output signal that is a guard time Δ t in a phase discrimination feedback loop_gSuch as clock section 340. A set of Reference Symbols (RS) may be generated in an RS extraction module or circuit 314 from at least a fast fourier transform of the received OFDM signal. The receiver clock may be coarsely adjusted and then finely adjusted. A coarse receiver clock adjustment may be generated based on processing at least the primary and secondary synchronization signals, as shown in fig. 3A. The reference symbol group includes a plurality of time-frequency slots (slots). The plurality of time-frequency slots vary according to the frequency shift and the PN sequence of the modulated reference symbol group. OFDM signal complying with universal mobile telecommunicationsStandard (UMTS) Long Term Evolution (LTE) signals. The adjustment of the receiver clock may be controlled by the receiver clock generator 312.

One embodiment of the present invention provides a machine-readable storage or computer-readable storage and/or medium having stored therein a machine code and/or a computer program comprising at least one code section for execution by a machine to cause the machine to perform the steps in the above method and system for an RS clock loop for OFDM symbol synchronization and tracking.

The present invention can be realized in hardware, software, or a combination of hardware and software. The present invention can be realized in a centralized fashion in at least one computer system, or in a distributed fashion where different elements are spread across several interconnected computer systems. Any kind of computer system or other apparatus adapted for carrying out the methods described herein is suited. A typical combination of hardware and software could be a general purpose computer system with a computer program that, when being loaded and executed, controls the computer system such that it carries out the methods described herein. The method is implemented in a computer system using a processor and a memory unit.

The present invention can also be implemented by a computer program product, which comprises all the features enabling the implementation of the methods of the invention and which, when loaded in a computer system, is able to carry out these methods. The computer program in the present document refers to: any expression, in any programming language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following a) conversion to another language, code or notation; b) reproduced in different formats to implement specific functions.

While the invention has been described with reference to several embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from its scope. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims (8)

1. A method for processing a communication signal, the method comprising:

tracking a symbol clock in the orthogonal frequency division multiplexing signal based at least on the reference symbol group; and

adjusting a receiver clock based at least on the symbol clock;

wherein the reference symbol group comprises a plurality of time-frequency slots;

the plurality of time-frequency gaps vary according to a pseudo-noise sequence that frequency shifts and modulates the set of reference symbols;

the reference symbol group is generated in a reference symbol extraction module from a fast fourier transform of the received orthogonal frequency division multiplex signal.

2. The method according to claim 1, characterized in that the method further comprises tracking the symbol clock by generating an output signal, which is a guard time Δ t_gAs a function of (c).

3. The method of claim 2, further comprising generating the output signal in a phase discrimination feedback loop.

4. The method of claim 1, further comprising fine tuning the symbol clock.

5. The method of claim 4, further comprising coarsely adjusting the symbol clock prior to the fine adjustment.

6. A system for processing a communication signal, comprising:

one or more circuits in a receiver to at least:

tracking a symbol clock in an orthogonal frequency division multiplexed signal, wherein the tracking is based at least on a reference symbol group; and

adjusting a receiver clock based at least on the symbol clock;

wherein the reference symbol group comprises a plurality of time-frequency slots;

the plurality of time-frequency gaps vary according to a pseudo-noise sequence that frequency shifts and modulates the set of reference symbols;

the reference symbol group is generated in a reference symbol extraction module from a fast fourier transform of the received orthogonal frequency division multiplex signal.

7. The system according to claim 6, characterized in that said one or more circuits track said symbol clock by generating an output signal, said output signal being a guard time Δ t_gAs a function of (c).

8. The system according to claim 7, wherein said one or more circuits generate said output signal in a phase discrimination feedback loop.