HK1138425B - Nonvolatile nanotube diodes - Google Patents

Description

Nonvolatile nanotube diode

Reference to related application

The present application claims the benefit of U.S. patent Act § 119(e) of the following applications, the entire contents of which are incorporated herein by reference:

U.S. provisional patent application No.60/855,109, entitled "Nonvolatile Nanotube Blocks", filed 2006, month 10, 27;

U.S. provisional patent application No.60/840,586, entitled "Nonvolatile Nanotube Diode", filed on 28.8.2006;

U.S. provisional patent application No.60/836,437, entitled "Nonvolatile Nanotube Diode", filed 8/2006;

U.S. provisional patent application No.60/836,343, filed 8/2006, entitled "scalable nonvolatile Nanotube switch as an Electronic Fuse Replacement element" ("scalable nonvolatile Nanotube Switches as Electronic Fuse Replacement Elements");

U.S. provisional patent application No.60/918,388, filed on 16.3.2007 entitled "Memory Elements and Cross-Point Switches and Arrays thereof using non-volatile Nanotube Blocks" ("Memory Elements and Cross points Switches and Arrays of Same");

this application is a continuation of the following and claims priority under U.S. patent Act 120, which is hereby incorporated by reference in its entirety:

U.S. patent application No.11/280,786, filed on 15.11.2005, entitled "Two-Terminal Nanotube Devices And systems And Methods Of Making Same" ("Two-Terminal Nanotube Devices And systems And Methods Of Making Same");

U.S. patent application No.11/274,967, entitled "Memory Arrays using nanotubes With alterable Resistance," filed on 15.11.2005 entitled "Memory Arrays using nanotube Arrays With repeatable Resistance"; and

U.S. patent application No.11/280,599, entitled "nonvolatile Shadow Latch with Nanotube Switch" filed on 15.11.2005 entitled "Non-Volatile Shadow Latch Using A Nanotube Switch".

This application is related to the following concurrently filed applications, the entire contents of which are incorporated herein by reference:

U.S. patent application No. (to be claimed), entitled "non-volatile Resistive memory with scalable two-Terminal Nanotube switch" ("Nonvolatile reactive Memories Having scaling scalable two-Terminal Nanotube Switches");

U.S. patent application No. (to be announced), entitled "Latch circuit and operating circuit with Scalable non-volatile Nanotube switch as electronic Fuse Replacement element" ("Latch Circuits and operation Circuits with Scalable Nonvolatile Nanotube Switches");

U.S. patent application No. (to be announced), entitled "Nonvolatile Nanotube diodes and Nonvolatile Nanotube Blocks and Systems and methods of Making the Same" ("Nonvolatile Nanotube diodes and Systems Using the Same and methods of Making the Same");

U.S. patent application No. (to be announced), entitled "Nonvolatile Nanotube diodes and Nonvolatile Nanotube Blocks and Systems and methods of Making the Same" ("Nonvolatile Nanotube diodes and Systems Using the Same and methods of Making the Same");

U.S. patent application No. (to be announced), entitled "Nonvolatile Nanotube diodes and Nonvolatile Nanotube Blocks and Systems and methods of Making the Same" ("Nonvolatile Nanotube diodes and Systems Using the Same and methods of Making the Same");

U.S. patent application No. (to be announced), entitled "Nonvolatile Nanotube diodes and Nonvolatile Nanotube Blocks and Systems and methods of Making the Same" ("Nonvolatile Nanotube diodes and Systems Using the Same and methods of Making the Same");

U.S. patent application No. (to be announced), entitled "Nonvolatile Nanotube diodes and Nonvolatile Nanotube Blocks and Systems and Methods of Making the Same" ("Nonvolatile Nanotube diodes and Systems Using Same and Methods of Making Same"); and

U.S. patent application No. (to be claimed) entitled "Nonvolatile Nanotube diodes and Nonvolatile Nanotube Blocks and Systems and methods of Making the Same" ("Nonvolatile Nanotube diodes and Systems Using the Same and methods of Making the Same").

Technical Field

The present invention relates to non-volatile switching devices having nanotube elements, and methods of forming these devices.

Discussion of the prior art

There is an ever increasing demand for higher density memory that allows for larger memory functions, including both free-standing and embedded, ranging from hundreds of KB to over 1GB of memory. These larger memories, which are required to have higher and higher densities, are sold in increasing quantities, and are priced at a lower price per bit, present challenges to the semiconductor industry to rapidly improve geometric process features. For example, such demands push lithography to smaller line and pitch dimensions, corresponding improved alignment between layers, improved process features/structures such as, for example, smaller transistors and storage elements, but also including increased chip size required to accommodate larger memory functions, or combined memory and logic functions. Due to the smaller geometry, the sensitivity to smaller sized defects increases, while the total defect density must be significantly reduced.

When switching to new higher density technology nodes, lithography and corresponding process changes typically result in 0.7 times reduction in the dimensions of insulators and conductors in the X and Y directions, or a 2 times reduction in area, for logic and memory support circuits. Process features unique to the memory cell are typically added, resulting in an additional area reduction of typically 0.7 times the area reduction due to the lithographic modifications, so that the memory cell achieves a cell area reduction of about 2.8 times. In DRAMs, for example, process feature changes such as buried trench or stacked storage capacitors are introduced with a correspondingly optimized cell contact approach between a capacitor plate and the source of a cell select FET formed in a semiconductor substrate. The trade-offs described with respect to DRAM memory are similar to other memory types, such as EPROM, EEPROM, and flash.

Memory efficiency is determined by comparing the respective overheads of the bit storage area and the corresponding support circuit area. The area of the support circuitry is minimized relative to the area of the array reservoirs. For 2-D memories, i.e., memories in which cell select transistors are formed in a semiconductor substrate, to transition to higher density new technology nodes (new generation technology), the bit area reduction may exceed the supporting circuit area, as further described above with respect to the memory example in which the bit area is reduced by a factor of 2.8 while supporting a circuit area reduction of 2. To maintain memory efficiency, the memory architecture can be changed to make larger sub-arrays, i.e., sub-arrays with more bits per word line and more bits per bit line. To continue to improve memory performance while suppressing power consumption, new memory architectures use global and local (segmented) word line and global and local (segmented) bit line architectures to accommodate larger sub-arrays having more bits per word line and bit line, such as described in U.S. patent 5,546,349, which is incorporated by reference herein in its entirety.

In addition to the increase in size of memory sub-arrays, the chip area may also increase. For example, if the memory function on the new technology node is to have 4 times more bits, the chip area will grow at least 1.4 to 1.5 times if the bit area is reduced by a factor of 2.8.

Continuing with the memory example described above, if the chip area of the memory on the current technology node is 60% bit area array and 40% support circuit area, assuming no change in chip architecture, and if the bit area efficiency of the new technology node is improved by a factor of 2.8, while the support circuit layout is improved by a factor of 2, then the bit area and support circuit areaThe die area will be about 50% of the die area. Architectural changes and circuit design and layout improvements described in U.S. patent 5,546,349 to increase the number of bits per bit line and word line, such as word lines and bit lines for global and local segments, for example, can be used to achieve 60% bit area and 40% support circuitry for a new 4 times larger memory function chip design on a new technology node. However, the chip area will be 1.4 to 1.5 times larger for 4 times the memory function. Thus, for example, if the current chip area is 100mm²The new chip area would be 140 to 150mm for a 4 times larger memory ²(ii) a If the current chip area is 70mm²Then the new chip area would be at least 100mm for a 4 times larger memory²。

From a manufacturing (production) perspective, mass production of memory functions transitioning to a new 4 x size on a new technology node is not realized unless the cost per bit of the new memory function is competitive with respect to the current generation technology. Typically, at least two and sometimes three new chips are designed with 10 to 15% each incremental reduction (shrink) in lithographic linear dimensions to reduce the 4-fold memory functional chip area to 100mm²Or smaller to increase the number of chips per wafer and to reduce the price per bit of memory to a level that can compete with the current generation of memory.

U.S. patent 5,536,968 to Crafts et al, the entire contents of which are incorporated herein by reference, discloses an OTP field programmable memory having cells formed by diodes in series with nonvolatile OTP elements, which in this patent are polysilicon fuse elements. Each cell includes a polysilicon fuse, typically several hundred ohms, formed in state, and a series select diode. The memory array is a 2-D memory array with long folded narrow poly fuse (poly fuse) elements. If so, a milliamp current blows the selected polysilicon fuse, rendering it non-conductive. Because of the large poly fuse size, the storage cells are large, and therefore the OTP memory described in U.S. patent 5,536,968 does not address memory scaling as described further above.

U.S. patent No. 4,442,507 to Roesner, the entire contents of which are incorporated herein by reference, discloses a programmable one-time (OTP) field programmable memory that uses three-dimensional (3-D) memory cells and corresponding processes, designs, and architectures instead of a two-dimensional (2-D) memory approach, the so-called two-dimensional (2-D) approach being directed to increasing chip area and reducing individual element sizes (transistors) and interconnects for each new generation of memory. U.S. Pat. No. 4,442,507 shows an EPROM (programmable one-time) memory having a 3-D EPROM array in which the cell selection device, the storage device, and the interconnect are not fabricated in or on a semiconductor substrate, but are formed on an insulating layer located on support circuitry formed in or on the semiconductor substrate and having interconnects between the support circuitry and the 3-D EPROM memory array. This 3-D memory approach significantly reduces the lithography and process requirements associated with higher density larger memory functions.

The 3-D EPROM prior art array 100 shown in fig. 1 is representative of the corresponding structure of the prior art in U.S. patent 4,442,507. The memory cell includes a vertically oriented Schottky diode in series with an antifuse (anti-fuse) formed on the Schottky diode using lightly doped polysilicon. Support circuits and interconnects 110 are formed in and on a semiconductor substrate 105 supporting, for example, silicon. Interconnects (not shown in fig. 1) through insulator 115 are used to connect support circuitry to array lines, such as conductor 120 and conductor 170. The memory cell is fabricated on the surface of insulator 115, including schottky diode 142, antifuse 155, and interconnected to conductive barrier 160 by combination conductor 120 and N + polysilicon conductor 122, and metal conductor 170. Note that although the surface of the insulator 115 is shown as planar, it is in fact non-planar, as described in more detail in U.S. patent 4,442,507, since VLSI planarization technology was not available at the time of this invention.

The N + polysilicon patterned layer semiconductor 122 is used as a schottky diode 142 contact andserving as array interconnect lines. The N + polysilicon semiconductor 122 may be, for example, silicon or germanium, and is typically doped to 10²⁰Dopant atoms/cm³(atoms/cubic centimeter or atoms/cm)³) And has a resistance of 0.04 Ohms/□ (Ohms/square). Although the semiconductor 122 may be used as an array line, a lower resistance array line may be formed by depositing an N + polysilicon semiconductor 122 on the molybdenum silicide conductor 120 between the N + semiconductor layer and the surface of the insulator 115. A second patterned layer of N-polysilicon or germanium semiconductor (semiconductor) 125, typically at 10, in contact with semiconductor 122¹⁴To 10¹⁷Dopant atom/cm³The range is doped, has a resistance of 15 ohms/□, and forms the cathode terminal of schottky diode 142, schottky diode 142 being used as a cell select device. The dopant may be, for example, arsenic, phosphorus, and antimony. Polysilicon conductors 122 and 125 are typically 400nm thick and 2um wide.

The anode of schottky diode device 142 is formed from patterned conductor 140 deposited on N-polysilicon conductor 125 using a noble metal such as platinum with a thickness of 25nm and heated to 600 c to form a compound (e.g., platinum silicide) with the underlying polysilicon material. This silicide 140 of noble metal forms a junction 145 of schottky diode 142 with the underlying N-polysilicon semiconductor 125. Measurements of the schottky diode 142 show a turn-on voltage of about 0.4 volts and a reverse breakdown voltage of about 10 volts.

The nonvolatile state of the memory cell is stored as a resistance state in antifuse 155. The resistance state of antifuse 155 can be changed (programmable) Once (OTP) after the fabrication process is complete. Preferably, the material 150 used to form the antifuse 155 is a single-element N-semiconductor, such as silicon or germanium, typically having less than 10¹⁷Atom/cm³And arsenic and phosphorus are suitable N-type dopants, as further described in U.S. patent 4,442,507. After patterning to form antifuse 155, a conductive barrier layer 160 of TiW 100nm thick is deposited to contact antifuse 155 and insulator 130. An 800nm aluminum layer is then deposited and patterned to form the conductor 170. Both the conductor 170 and the conductive barrier 160 are coveredAnd (6) patterning. A conductive barrier layer 160 is used to prevent aluminum migration into the N-polysilicon material 150.

The resistance of the antifuse in its as-formed state is typically 10⁷Ohm. Initially, all antifuses in all cells have about 10 of the manufacturing state⁷Ohmic resistance value. If a cell is selected and programmed to reach an antifuse threshold voltage of about 10 volts, the antifuse resistance changes to 10²Ohm and the programming current is limited to about 50uA and the programming time is limited to the microsecond range. The antifuse can only be programmed once and the new, lower resistance state of the nonvolatile is stored in the memory cells of the 3-D EPROM memory, with the array region being located on the underlying support circuitry 110, and the support circuitry 110 being located in and on the semiconductor substrate 105.

Although U.S. Pat. No.4,442,507 describes the concept of a 3-D EPROM memory array having all cell components and interconnects decoupled from the semiconductor substrate and the supporting circuitry described above, this approach is limited to OTP memories.

Prior art FIG. 2 illustrates CMOS structures 200 and 200' fabricated including four conductor layers (metal 1-metal 4) with a planar local interconnect metal layer and an additional relatively global planar stack, as well as stacked contacts and filled vias (contact studs) as described in the Ryan, J.G. et al prior art reference, "the concept of interconnection technology at IBM", Journal of Research and Development, Vol.39, No.4, July 1995, pp.371-381, the entire contents of which are incorporated herein by reference. Metal 5 is non-planar and is used to provide off-chip connections. For the local interconnect and wiring layer metal 1, metal 2, metal 3, metal 4, and metal 5, for example, al (Cu), W, Mo, Ti, Cu can be used. The tight metal pitch (pitch) requires both metal and oxide planarization, and near vertical, zero-overlap via studs (via stud) are typically formed of tungsten (W), as shown in fig. 2. The widely used chemical-mechanical polishing (CMP) planarization technique enables the formation of structures 200 and 200'. CMP techniques are also described in U.S. patent 4,944,836, 1990, 7, 31, which is also entitled to methods for CMP, the entire contents of which are incorporated herein by reference. CMP techniques are also selected for their ability to remove prior process defects.

U.S. patent 5,670,803 to Bertin, which is incorporated herein by reference in its entirety, discloses a 3-D SRAM array structure having simultaneously defined sidewall dimensions. The structure includes vertical sidewalls that are defined by both trenches cut through the multi-layer doped silicon to avoid (minimize) multiple alignment steps and insulating regions. The trenches cut through the plurality of semiconductor and oxide layers and Support Insulator (SiO) between the 3-D SRAM array structure and the underlying semiconductor substrate₂) Stopping on the top surface of the layer. U.S. patent 5,670,803 also teaches in-trench (in-trench) vertical local cell interconnect wiring within the trench region to form a vertically routed 3-D SRAM cell. Us patent 5,670,803 also teaches vertical interconnect routing through trenches (through-trenches) that run through the trench regions to the top surface of 3-D SRAM storage cells that have been routed locally within the trench cells.

Disclosure of Invention

The invention provides a nonvolatile nanotube diode, a nonvolatile nanotube block, a system using the same, and a method for manufacturing the same.

In one aspect of the invention, a non-volatile nanotube diode device includes a first terminal and a second terminal; a semiconductor element including a cathode and an anode and capable of forming a conductive path between the cathode and the anode in response to an electrical stimulus applied to a first conductive terminal; and a nanotube switching element comprising a nanotube fabric article in electrical communication with the semiconductor element, the nanotube fabric article being disposed between the semiconductor element and the second terminal and capable of forming a conductive pathway therebetween, wherein electrical stimuli applied to the first and second terminals result in a plurality of logic states.

One or more embodiments include one or more of the following features. In a first logic state of the plurality of logic states, the conductive path between the first and second terminals is substantially disabled, and in a second logic state of the plurality of logic states, the conductive path between the first and second terminals is enabled. The nanotube article has a relatively high resistance in the first logic state and a relatively low resistance in the second logic state. The nanotube fabric article comprises a non-network of unaligned nanotubes. In a second logic state, the non-woven network of unaligned nanotubes includes at least one conductive path between the semiconductor element and the second terminal. The nanotube fabric article is a multilayer structure. The semiconductor element is capable of flowing a current from the anode to the cathode above a threshold voltage between the first and second terminals, and is incapable of flowing a current from the anode to the cathode below the threshold voltage between the first and second terminals. In the first logic state, the conductive path between the anode and the second terminal is disabled. In the second logic state, the conductive path between the anode and the second terminal is enabled. The conductive contact is disposed between the nanotube fabric article and the semiconductor component and provides an electrical communication path between the nanotube fabric article and the semiconductor component. The first terminal is in electrical communication with the anode, and the cathode is in electrical communication with the conductive contact of the nanotube switching element. In the second logic state, the device is capable of carrying current substantially flowing from the first terminal to the second terminal. The first terminal is in electrical communication with the cathode, and the anode is in electrical communication with the conductive contact of the nanotube switching element. When in the second logic state, the device is capable of carrying current to flow substantially from the second terminal to the first terminal. The anode comprises a conductive material and the cathode comprises an n-type semiconductor material. The anode comprises a p-type semiconductor material and the cathode comprises an n-type semiconductor material.

In another aspect of the invention, a two-terminal non-volatile state device includes: a first terminal and a second terminal; a semiconductor field effect element having a source, a drain, a gate in electrical communication with one of the source and the drain, and a channel disposed between the source and the drain, the gate being capable of controllably forming a conductive path in the channel between the source and the drain; a nanotube switching element having a nanotube structured article and a conductive contact, the nanotube structured article being disposed between the conductive contact and the second terminal and being capable of forming a conductive path between the conductive contact and the second terminal; wherein the first terminal is in electrical communication with one of the source and the drain, and the other of the source and the drain is in electrical communication with the conductive contact; and wherein a first set of electrical stimuli to the first and second conductive terminals results in a first logic state and a second set of electrical stimuli to the first and second conductive terminals results in a second logic state.

One or more embodiments include one or more of the following features. The first logic state corresponds to a relatively non-conductive path between the first and second terminals, and the second logic state corresponds to a conductive path between the first and second terminals. The first set of electrical stimuli causes a relatively higher resistance state in the nanotube fabric article, while the second set of electrical stimuli causes a relatively lower resistance state in the nanotube fabric article. The nanotube fabric article comprises a non-woven network of unaligned nanotubes. The nanotube fabric article includes a multilayer structure. In response to the second set of electrical stimuli, the non-woven network of unaligned nanotubes provides at least one electrically conductive path between the conductive contact and the semiconductor field effect element. In response to the second set of electrical stimuli, a conductive path between the source and the drain is formed in the conductive channel. The semiconductor field effect element comprises a PFET. The semiconductor field effect element includes an NFET. The source of the semiconductor field effect element is in electrical communication with the first terminal and the drain is in electrical communication with the conductive contact of the nanotube switching element. The drain of the semiconductor field effect element is in electrical communication with the first terminal, and the source of the semiconductor field effect element is in electrical communication with the conductive contact of the nanotube switching element.

In another aspect of the present invention, a voltage selection circuit includes: inputting a voltage source; an output voltage terminal and a reference voltage terminal; a resistive element; and a non-volatile nanotube diode device, comprising: a first terminal and a second terminal; a semiconductor element in electrical communication with the first terminal; a nanotube switching element disposed between the semiconductor element and the second terminal and capable of conducting an electrical stimulus between the semiconductor element and the second terminal; wherein the non-volatile nanotube diode device is capable of conducting an electrical stimulus between the first and second terminals, wherein the resistive element is disposed between an input voltage source and an output voltage terminal, the non-volatile nanotube diode device is disposed between and in electrical communication with the output voltage terminal and a reference voltage terminal, and, wherein the voltage selection circuit is capable of providing a first output voltage level which, when responsive to electrical stimuli on the input voltage source and the reference voltage terminal, the non-volatile nanotube diode is substantially prevented from electrical stimuli being conducted between the first and second terminals, and wherein the voltage selection circuit is capable of providing a second output voltage level, the non-volatile nanotube diode conducting electrical stimulation between the first and second terminals in response to electrical stimulation on the input voltage source and the reference voltage terminal.

One or more embodiments include one or more of the following features. The semiconductor element includes an anode in electrical communication with the first terminal and a cathode in communication with the nanotube switching element. The semiconductor element includes a field effect element having a source region in electrical communication with the first terminal, a drain region in electrical communication with the nanotube switching element, a gate region in electrical communication with one of the source region and the drain region, and a channel region capable of controllably forming and removing a conductive path between the source and drain in response to electrical stimulation to the gate region. The first output voltage level is substantially equivalent to the input voltage source. The second output voltage level is substantially equivalent to the reference voltage terminal. Nanotube switching elements include nanotube-structured articles that can have a high resistance state and a low resistance state. The high resistance state of the nanotube fabric article is substantially higher than the resistance of the resistive element, and wherein the low resistance state of the nanotube fabric article is substantially lower than the resistance of the resistive element. The first output voltage level is determined based in part on the relative resistance of the resistive element and the high resistance state of the nanotube fabric article, and wherein the second output voltage level is determined based in part on the relative resistance of the resistive element and the low resistance state of the nanotube fabric article.

In another aspect of the invention, a nonvolatile nanotube diode includes: a substrate; a semiconductor element disposed over the substrate, the semiconductor element having an anode and a cathode and being capable of forming a conductive path therebetween; a nanotube switching element disposed over the semiconductor element, the nanotube switching element including a conductive contact and a nanotube fabric element having a plurality of resistance states; and a conductive terminal disposed spaced apart from the conductive contacts, wherein the nanotube fabric element is interposed between and in electrical communication with the conductive contacts, and the conductive contacts are in electrical communication with the cathode, and wherein the non-volatile nanotube diode is capable of forming a conductive path between the anode and the conductive terminal in response to an electrical stimulus applied to the anode and the conductive terminal.

One or more embodiments include one or more of the following features. The anode comprises a conductive material and the cathode comprises a semiconductive material. The anode material includes at least one of: al, Ag, Au, Ca, Co, Cr, Cu, Fe, Ir, Mg, Mo, Na, Ni, Os, Pb, Pd, Pt, Rb, Ru, Ti, W, Zn, CoSi₂、MoSi₂、Pd₂Si、PtSi、RbSi₂、TiSi₂、WSi₂And ZrSi₂. The semiconductor element includes a schottky barrier diode. A second conductive terminal interposed between the substrate and the anode is in electrical communication with the anode, wherein the non-volatile nanotube diode is capable of forming a conductive path between the second conductive terminal and the conductive terminal in response to electrical stimulation on the second conductive terminal and the conductive terminal. The anode comprises a first type of semiconductor material and the cathode region comprises a second type of semiconductor material. The first type of semiconductor material is positively doped, the second type of semiconductor material is negatively doped, and the semiconductor elements form PN junctions. The nanotube fabric elements are arranged substantially vertically. The nanotube fabric elements are arranged substantially horizontally. The nanotube fabric element includes a non-woven multi-layer structure. The nanotube fabric element has a thickness between about 20nm and about 200 nm. The conductive contact is arranged as Substantially coplanar with a lower surface of the nanotube fabric element, and the conductive terminal is disposed substantially coplanar with an upper surface of the nanotube fabric element. The semiconductor element is a field effect transistor.

In another aspect of the invention, a nonvolatile nanotube diode includes: a substrate; a conductive terminal disposed over the substrate; a semiconductor element disposed over the conductive terminal, the semiconductor element having a cathode and an anode and being capable of forming a conductive path between the cathode and the anode; and a nanotube switching element disposed over the semiconductor element, the nanotube switching element including a conductive contact and a nanotube fabric element having a plurality of resistance states, wherein the nanotube fabric element is interposed between and in electrical communication with the anode and the conductive contact, and the cathode is in electrical communication with the conductive terminal, and wherein the non-volatile nanotube diode is capable of forming a conductive path between the conductive terminal and the conductive contact in response to an electrical stimulus applied to the anode and the conductive terminal.

One or more embodiments include one or more of the following features. The anode comprises a conductive material and the cathode comprises a semiconductive material. The anode material includes at least one of: al, Ag, Au, Ca, Co, Cr, Cu, Fe, Ir, Mg, Mo, Na, Ni, Os, Pb, Pd, Pt, Rb, Ru, Ti, W, Zn, CoSi ₂、MoSi₂、Pd₂Si、PtSi、RbSi₂、TiSi₂、WSi₂And ZrSi₂. The semiconductor element includes a schottky barrier diode. A second conductive terminal is interposed between the anode and the patterned region of the non-woven nanotube structure and provides a conductive path non-woven therebetween. The anode comprises a first type of semiconductor material and the cathode region comprises a second type of semiconductor material. The first type of semiconductor material is positively doped, the second type of semiconductor material is negatively doped, and the semiconductor elements form PN junctions. The nanotube fabric elements are arranged substantially vertically. The nanotube fabric elements are arranged substantially horizontally. The nanotube fabric element comprises a layer of non-woven nanotubes having a thickness between about 0.5nm and about 20 nm. Nanotube junctionThe structural element comprises a non-woven multi-layer structure. The conductive contact is disposed substantially coplanar with a lower surface of the nanotube fabric element and the conductive terminal is disposed substantially coplanar with an upper surface of the nanotube fabric element. The semiconductor element includes a field effect transistor.

In another aspect of the invention, a memory array includes a plurality of word lines; a plurality of bit lines; a plurality of memory cells, each memory cell responsive to electrical stimulation on a word line and a bit line, each memory cell comprising: a two-terminal non-volatile nanotube switching device, comprising: a first terminal and a second terminal, a semiconductor diode element, and an article of nanotube fabric, the semiconductor diode and the article of nanotube fabric disposed between and in electrical communication with the first and second terminals, wherein the article of nanotube fabric is capable of having a plurality of resistance states, and wherein the first terminal is coupled to a word line and the second terminal is coupled to a bit line, electrical stimulation applied to the first and second terminals capable of changing the resistance state of the article of nanotube fabric; and memory operation circuitry operatively coupled to each of the plurality of bit lines and each of the plurality of word lines, the operation circuitry being capable of selecting the respective cell by activating at least one of the bit line and the word line coupled to the cell to apply a selected electrical stimulus to each of the respective first and second terminals, and the operation circuitry being further capable of detecting a resistance state of the nanotube fabric article of the selected memory cell and adjusting the electrical stimulus applied to each of the respective first and second terminals in response to the resistance state to controllably induce the selected resistance state in the nanotube fabric article, wherein the selected resistance state of the nanotube fabric article of the respective memory cell corresponds to an information state of the memory cell.

One or more embodiments include one or more of the following features. Each memory cell non-volatilely stores a respective information state in response to an electrical stimulus applied to each of the respective first and second terminals. The semiconductor diode element includes a cathode and an anode, the anode in electrical communication with the second terminal, and the cathode in electrical communication with the nanotube switching element. The cathode includes a first semiconductor material and the anode includes a second semiconductor material. The semiconductor diode element includes a cathode in electrical communication with the first terminal and an anode in electrical communication with the nanotube switching element. The cathode includes a first semiconductor material and the anode includes a second semiconductor material. The cathode includes a semiconducting material and the anode includes a conductive material and forms a conductive contact to the nanotube fabric article. A conductive contact is interposed between the semiconductor diode element and the nanotube fabric article. The nanotube fabric article includes a network of unaligned nanotubes capable of providing at least one conductive path between a first conductive contact and one of first and second terminals. The nanotube fabric article includes a multi-layered nanotube fabric. The thickness of the multilayer nanotube article defines a spacing between the conductive contact and one of the first and second conductive terminals. The plurality of memory cells includes a plurality of pairs of stacked memory cells, wherein a first memory cell of each pair of stacked memory cells is disposed over and in electrical communication with a first bit line, and a word line is disposed over and in electrical communication with the first memory cell; and wherein a second memory cell of each pair of stacked memory cells is disposed over and in electrical communication with the word line, and a second bit line is disposed over and in electrical communication with the second memory cell. The resistance state of the nanotube article in the first memory cell is substantially unaffected by the resistance state of the nanotube article in the second memory cell, and the resistance state of the nanotube article in the second memory cell is substantially unaffected by the resistance state of the nanotube article in the first memory cell. The resistance state of the nanotube article in the first memory cell is substantially unaffected by the operating circuit selecting the second memory cell, and the resistance state of the nanotube article in the second memory cell is substantially unaffected by the operating circuit selecting the resistance state of the first memory cell. The resistance state of the nanotube article in the first memory cell is substantially unaffected by the operating circuitry detecting the resistance state of the nanotube-structured article of the second memory cell, and the resistance state of the nanotube article in the second memory cell is substantially unaffected by the operating circuitry detecting the resistance state of the nanotube-structured article of the first memory cell. The resistance state of the nanotube article in the first memory cell is substantially unaffected by the operating circuit adjusting the electrical stimulus applied to each of the respective first and second terminals of the second memory cell, and the resistance state of the nanotube article in the second memory cell is substantially unaffected by the operating circuit adjusting the electrical stimulus applied to each of the respective first and second terminals of the first memory cell. The memory device includes an insulating region disposed over a memory operation circuit, a plurality of memory cells disposed over the insulating region, and a plurality of conductive interconnects operatively coupling the memory operation circuit to a plurality of bit lines and a plurality of word lines. The adjustment of the electrical stimulation includes incrementally changing the voltage applied to each of the respective first and second terminals. Incrementally changing the voltage includes applying a voltage pulse. The amplitude of subsequent voltage pulses is increased in increments of about 200 mV. The adjustment of the electrical stimulation includes changing a current supplied to at least one of the respective first and second terminals. Substantially removing the electrical stimulus from the respective bit line and word line occurs after controllably inducing the selected resistive state in the nanotube fabric article to substantially preserve the selected resistive state of the nanotube fabric article. Detecting the resistance state of the nanotube fabric article further comprises detecting a change in electrical stimulation to the corresponding bit line over time. Detecting the resistance state of the nanotube fabric article further comprises detecting a current flowing through the corresponding bit line. In each two-terminal non-volatile nanotube switching device, current can flow from the second terminal to the first terminal and substantially avoid flowing from the first terminal to the second terminal. When the threshold voltage is reached by applying an electrical stimulus to each of the respective first and second terminals, current can flow from the second terminal to the first terminal. The selected resistance state of the nanotube fabric article of each memory cell includes one of a relatively higher resistance state and a relatively lower resistance state, the relatively higher resistance state corresponding to a first information state of the memory cell and the relatively lower resistance state corresponding to a second information state of the memory cell. The third information state of each memory cell corresponds to a state in which current can flow from the second terminal to the first terminal, and wherein the fourth information state of each memory cell corresponds to a state in which current is substantially prevented from flowing from the first terminal to the second terminal. The two-terminal non-volatile nanotube switching device can operate independently of a polarity of a voltage between the first and second terminals. The two-terminal non-volatile nanotube switching device can operate independently of a direction of current flow between the first and second terminals. The plurality of memory cells includes a plurality of pairs of stacked memory cells, wherein a first memory cell of each pair of stacked memory cells is disposed over and in electrical communication with a first bit line, and a word line is disposed over and in electrical communication with the first memory cell; wherein the insulator material is disposed over the first memory cell; wherein a second memory cell in each pair of stacked memory cells is disposed on and in electrical communication with a second wordline disposed over the insulator material, and wherein a second bitline is disposed over and in electrical communication with the second memory cell. The plurality of memory cells includes a plurality of pairs of stacked memory cells, wherein a first memory cell of each pair of stacked memory cells is disposed over and in electrical communication with a first bit line, and a word line is disposed over and in electrical communication with the first memory cell; wherein the insulator material is disposed over the first memory cell; wherein a second memory cell of each pair of stacked memory cells is disposed over and in electrical communication with a second bit line disposed over the insulator material, and wherein a second word line is disposed over and in electrical communication with the second memory cell.

In another aspect of the invention, a method of fabricating a nanotube switch comprises: providing a substrate having a first conductive terminal; depositing a multi-layer nanotube structure over the first conductive terminal; and depositing a second conductive terminal on the multi-layered nanotube structure, the nanotube structure having a thickness, density, and composition selected to avoid direct physical and electrical contact between the first and second conductive terminals.

One or more embodiments include one or more of the following features. The first and second conductive terminals and the multi-layered nanotube structure are lithographically patterned to have substantially the same lateral dimensions, respectively. The first and second conductive terminals and the multi-layered nanotube structure each have a substantially circular lateral shape. The first and second conductive terminals and the multi-layered nanotube structure each have a substantially rectangular lateral shape. The first and second conductive terminals and the multi-layered nanotube structure each have a lateral dimension between about 200nmx200nm and about 22nmx22 nm. The first and second conductive terminals and the multi-layered nanotube structure each have a lateral dimension between about 22nm and about 10 nm. The first and second conductive terminals and the multi-layered nanotube structure each have a lateral dimension of less than 10 nm. The thickness of the multilayer nanotube structure is between about 10nm and about 200 nm. The multilayer nanotube structure has a thickness between about 10nm and about 50 nm. The substrate includes a diode located below the first conductive terminal, the diode being addressable by the control circuit. The first and second conductive terminals, the multi-layer nanotube structure, and the diode are lithographically patterned to have substantially the same lateral dimensions, respectively. Providing a second diode over the second conductive terminal, depositing a third conductive terminal over the second diode, depositing a second multi-layered nanotube structure over the third conductive terminal, and depositing a fourth conductive terminal over the second multi-layered nanotube structure. The multilayer nanotube structure, the diode, and the conductive terminal are lithographically patterned to have substantially the same lateral dimensions, respectively. The diode includes a layer of N + polysilicon, a layer of N polysilicon, and a layer of conductor. The diode includes a layer of N + polysilicon, a layer of N polysilicon, and a layer of P polysilicon. A diode is provided on the second conductive terminal, the diode being addressable by the control circuit. The diode is annealed at a temperature in excess of 700 c. The first and second conductive terminals, the multi-layer nanotube structure, and the diode are lithographically patterned to have substantially the same lateral dimensions, respectively. The substrate includes a semiconductor field effect transistor, at least a portion of which is located below the first conductive terminal, the semiconductor field effect transistor being addressable by the control circuit. Depositing the multi-layered nanotube structure includes spraying nanotubes dispersed in a solvent onto a first conductive terminal. Depositing the multi-layered nanotube structure includes spin coating nanotubes dispersed in a solvent onto a first conductive terminal. Depositing the multi-layered nanotube structure includes depositing a mixture of nanotubes dispersed in a solvent and a matrix material on a first conductive terminal. After depositing the second conductive terminal, the matrix material is removed. The matrix material comprises polypropylene carbonate (polypropylene carbonate). The first and second conductive terminals each comprise a conductive material independently selected from the group consisting of: ru, Ti, Cr, Al (Cu), Au, Pd, Pt, Ni, Ta, W, Cu, Mo, Ag, In, Ir, Pb, Sn, TiAu, TiCu, TiPd, PbIn, TiW, RuN, RuO, TiN, TaN, CoSix, and TiSix. A porous dielectric material is deposited on the multi-layered nanotube structure. The porous dielectric material includes one of a spin-on-glass and a spin-on low- κ dielectric. A non-porous dielectric material is deposited on the multi-layered nanotube structure. The non-porous dielectric material comprises a high- κ dielectric. The non-porous dielectric material comprises hafnium oxide. Providing the word line in electrical communication with the second conductive terminal.

In another aspect of the present invention, a method of fabricating a nanotube diode includes: providing a substrate having a first conductive terminal; depositing a multi-layer nanotube structure over a first conductive terminal; depositing a second conductive terminal on the multi-layered nanotube structure, the nanotube structure having a thickness, density, and composition selected to avoid direct physical and electrical contact between the first and second conductive terminals; and providing an electrical contact for the diode to one of the first and second conductive terminals.

One or more embodiments include one or more of the following features. The diode is provided after deposition of the multi-layered nanotube structure. The diode is annealed at a temperature in excess of 700 c. The diode is disposed on and in electrical contact with the second conductive terminal. The diode is disposed under and in electrical contact with the first conductive terminal. The first and second conductive terminals, the multi-layer nanotube structure, and the diode are lithographically patterned to have substantially the same lateral dimensions, respectively. The first and second conductive terminals, the multi-layered nanotube structure, and the diode each have a substantially circular lateral shape. The first and second conductive terminals, the multi-layered nanotube structure, and the diode each have a substantially rectangular lateral shape. The first and second conductive terminals and the multi-layered nanotube structure each have a lateral dimension of between about 200nmx200nm and about 22nmx22 nm.

In another aspect of the invention, a non-volatile nanotube switch includes a first conductive terminal; the nanotube block comprises a multilayer nanotube structure, and at least one part of the nanotube block is arranged on at least one part of the first conductive terminal and is contacted with at least one part of the first conductive terminal; a second conductive terminal, at least a portion of which is disposed on and in contact with at least a portion of the nanotube block, wherein the nanotube block is constructed and arranged to avoid direct physical and electrical contact between the first and second conductive terminals; and control circuitry in electrical communication with the first and second conductive terminals and capable of applying an electrical stimulus to the first and second conductive terminals, wherein the nanotube block is capable of switching between a plurality of electrical states in response to a respective plurality of electrical stimuli applied to the first and second conductive terminals by the control circuitry, and wherein for each different electrical state of the plurality of electrical states, the nanotube block provides an electrical path having a respective different resistance between the first and second conductive terminals.

One or more embodiments include one or more of the following features. Substantially the entire nanotube block is located on substantially the entire first conductive terminal, and wherein substantially the entire second conductive terminal is located on substantially the entire nanotube block. The first and second conductive terminals and the nanotube block each have a substantially circular lateral shape. The first and second conductive terminals and the nanotube block each have a substantially rectangular lateral shape. The first and second conductive terminals and the nanotube block each have a lateral dimension between about 200nm and about 22 nm. The first and second conductive terminals and the nanotube block each have a lateral dimension between about 22nm and about 10 nm. The first and second conductive terminals and the nanotube block each have a lateral dimension of less than about 10 nm. The nanotube block has a thickness between about 10nm and about 200 nm. The nanotube block has a thickness between about 10nm and about 50 nm. The control circuit includes a diode in direct physical contact with the first conductive terminal. The first conductive terminal is disposed on the diode. The diode is arranged on the second conductive terminal. The diode, the nanotube block, and the first and second conductive terminals have substantially the same lateral dimensions. The diode includes a layer of N + polysilicon, a layer of N polysilicon, and a layer of conductor. The diode includes a layer of N + polysilicon, a layer of N polysilicon, and a layer of P polysilicon. The control circuit includes a semiconductor field effect transistor in contact with a first conductive terminal. The first and second conductive terminals each comprise a conductive material independently selected from the group consisting of: ru, Ti, Cr, Al (Cu), Au, Pd, Pt, Ni, Ta, W, Cu, Mo, Ag, In, Ir, Pb, Sn, TiAu, TiCu, TiPd, PbIn, TiW, RuN, RuO, TiN, TaN, CoSix, and TiSix. The nanotube block further comprises a porous dielectric material. The porous dielectric material includes one of a spin-on-glass and a spin-on low- κ dielectric. The nanotube block further comprises a non-porous dielectric material. The non-porous dielectric material comprises hafnium oxide.

In another aspect of the present invention, a high density memory array comprises: a plurality of word lines and a plurality of bit lines; a plurality of memory cells, each memory cell comprising: a first conductive terminal; a nanotube block on the first conductive terminal, the nanotube block comprising a multi-layered nanotube structure; a second conductive terminal located on the nanotube block and in electrical communication with a word line of the plurality of word lines; and a diode in electrical communication with a bit line of the plurality of bit lines and one of the first and second conductive terminals, wherein the nanotube block has a thickness that defines a spacing between the first and second conductive terminals, and wherein a logic state of each memory cell is selectable by activating only the bit line and the word line connected to the memory cell. The diode is arranged below the first conductive terminal. The diode is arranged on the second conductive terminal. The diode, the first and second conductive terminals, and the nanotube block all have substantially the same lateral dimensions. The diode, the first and second conductive terminals, and the nanotube block each have a substantially circular lateral shape. The diode, the first and second conductive terminals, and the nanotube block each have a substantially rectangular lateral shape. The diode, the first and second conductive terminals, and the nanotube block each have a lateral dimension between about 200nm and about 22 nm. The memory cells are spaced from each other by about 200nm to about 22 nm. The first and second conductive terminals, and the nanotube block each have a lateral dimension between about 22nm and about 10 nm. The memory cells of the array are spaced from each other by about 220nm to about 10 nm. Some memory cells of the array are laterally spaced relative to one another and other memory cells of the array are stacked upon one another. Some memory cells of the array that are stacked on top of each other share bitlines. Some memory cells of the array that are laterally spaced relative to each other share a word line. The plurality of word lines are substantially perpendicular to the plurality of bit lines. The nanotube block has a thickness between about 10nm and about 200 nm. The nanotube block has a thickness between about 10nm and about 50 nm. .

In another aspect of the present invention, a high density memory array comprises: a plurality of word lines and a plurality of bit lines; a plurality of memory cells, each memory cell comprising: a first conductive terminal; a nanotube block on the first conductive terminal, the nanotube block comprising a multi-layered nanotube structure; a second conductive terminal located on the nanotube block and in electrical communication with one of the plurality of bit lines; and a diode in electrical communication with one of the plurality of word lines, wherein a thickness of the nanotube block defines a spacing between the first and second conductive terminals, wherein a logic state of each memory cell is selectable by activating only bit lines and word lines connected to the memory cell. The diode is arranged below the first conductive terminal. The diode is arranged on the second conductive terminal. The diode, the first and second conductive terminals, and the nanotube block all have substantially the same lateral dimensions. The diode, the first and second conductive terminals, and the nanotube block each have a substantially circular lateral shape. The diode, the first and second conductive terminals, and the nanotube block each have a substantially rectangular lateral shape. The diode, the first and second conductive terminals, and the nanotube block each have a lateral dimension between about 200nm and about 22 nm. The memory cells are spaced from each other by about 200nm to about 22 nm. The diode, the first and second conductive terminals, and the nanotube block each have a lateral dimension between about 22nm and about 10 nm. The memory cells of the array are spaced from each other by about 220nm to about 10 nm. Some memory cells of the array are laterally spaced relative to one another and other memory cells of the array are stacked upon one another. Certain memory cells of the array that are stacked on top of each other share a bit line. Some memory cells of the array that are laterally spaced relative to each other share a word line. The plurality of word lines are substantially perpendicular to the plurality of bit lines. The nanotube block has a thickness between about 10nm and about 200 nm. The nanotube block has a thickness between about 10nm and about 50 nm.

In another aspect of the present invention, a high density memory array comprises: a plurality of word lines and a plurality of bit lines; a plurality of memory cell pairs, each memory cell pair comprising: a first storage unit comprising: a first conductive terminal, a first nanotube element located over the first conductive terminal, a second conductive terminal located over the nanotube element, and a first diode in electrical communication with one of the first and second conductive terminals and a first bit line of the plurality of bit lines; and a second storage unit including: a second diode electrically connected to one of the third and fourth conductive terminals and a second bit line of the plurality of bit lines, wherein the second memory cell is disposed on the first memory cell, and wherein the first and second memory cells share a word line of the plurality of word lines; wherein each memory cell pair of the plurality of memory cells is capable of switching between at least four different resistance states corresponding to the four different logic states in response to electrical stimulation on the first and second bit lines and the shared word line.

In another aspect of the present invention, a high density memory array comprises: a plurality of word lines and a plurality of bit lines; a plurality of memory cell pairs, each memory cell pair comprising: a first storage unit comprising: a first conductive terminal, a first nanotube element positioned over the first conductive terminal, a second conductive terminal positioned over the nanotube element, and a first diode in electrical communication with one of the first and second conductive terminals and a first word line of the plurality of word lines; and a second storage unit including: a second diode in electrical communication with one of the third and fourth conductive terminals and a second word line of the plurality of word lines, wherein the second memory cell is disposed on the first memory cell, and wherein the first and second memory cells share a bit line of the plurality of bit lines; wherein each memory cell pair of the plurality of memory cells is switchable between at least four different resistance states corresponding to the four different logic states in response to electrical stimuli on the first and second word lines and the shared bit line.

In another aspect of the invention, a nanotube diode comprises: a cathode formed of a semiconductor material; and an anode formed from a nanotube, wherein the cathode is in fixed and direct physical contact with the anode; and wherein the cathode and anode are constructed and arranged to enable application of sufficient electrical stimulation energy to the cathode and anode to establish an electrically conductive path between the cathode and anode.

One or more embodiments include one or more of the following features. The anode includes a non-woven nanotube structure having a plurality of unaligned nanotubes. The non-woven nanotube structure includes a layer of nanotubes having a thickness between about 0.5nm and about 20 nm. The non-woven nanotube structure includes a nanotube block. The nanotubes include metallic nanotubes and semiconducting nanotubes. The cathode includes an n-type semiconductor material. The Schottky barrier layer is formed between the n-type semiconductor material and the metal nanotube. A PN junction is formed between the n-type semiconductor material and the semiconducting nanotubes. A PN junction is formed between the n-type semiconductor material and the semiconducting nanotubes. The Schottky barrier layer and the PN junction provide an electrically parallel communication path between the cathode and the anode. Further in electrical communication with the non-volatile memory cell, the nanotube diode is capable of controlling electrical stimulation to the non-volatile memory cell. Further in electrical communication with the non-volatile nanotube switch, the nanotube diode can control electrical stimulation to the non-volatile nanotube switch. Further in electrical communication with the switching element electrical network, the nanotube diode is capable of controlling electrical stimulation to the switching element electrical network. Further in communication with the storage element, the nanotube diode is capable of selecting the storage element in response to an electrical stimulus. The storage element is non-volatile. Further in communication with the integrated circuit, the nanotube diode may be used as a rectifier for the integrated circuit.

In another aspect of the invention, a nanotube diode comprises: a conductive terminal; a semiconductor element disposed on and in electrical communication with the conductive terminal, wherein the semiconductor element forms a cathode; and a nanotube switching element disposed on and in fixed electrical communication with the semiconductor element, wherein the nanotube switching element forms an anode, wherein the nanotube switching element comprises a conductive contact and a nanotube fabric element having a plurality of resistive states, and wherein the cathode and the anode are constructed and arranged such that, in response to a sufficient electrical stimulus applied to the conductive contact and the conductive terminal, the non-volatile nanotube diode is capable of forming a conductive path between the conductive terminal and the conductive contact.

One or more embodiments include one or more of the following features. The nanotube fabric device includes a patterned region of nanotubes, and the semiconductor device includes an n-type semiconductor material. The patterned region of nanotubes includes metallic nanotubes and semiconducting nanotubes. The Schottky barrier layer is formed between the n-type semiconductor material and the metal nanotubes, which include a patterned region of nanotubes. A PN junction is formed between an n-type semiconductor material and a semiconducting nanotube, which includes a patterned region of nanotubes. The Schottky barrier layer and the PN junction provide an electrically parallel communication path between the conductive terminal and the nanotube structure element. Further in electrical communication with the non-volatile memory cell, the nanotube diode is capable of controlling electrical stimulation to the non-volatile memory cell. Further in electrical communication with the non-volatile nanotube switch, the nanotube diode can control electrical stimulation to the non-volatile nanotube switch. Further in electrical communication with the switching element electrical network, the nanotube diode is capable of controlling electrical stimulation to the switching element electrical network. Further in communication with the storage element, the nanotube diode is capable of selecting the storage element in response to an electrical stimulus. The storage element is non-volatile. Further in communication with the integrated circuit, the nanotube diode may be used as a rectifier for the integrated circuit.

Brief Description of Drawings

Figure 1 shows a prior art variation employing 3D-EPROM cells, where the array is located on an insulating layer located over memory support circuitry formed in and on an underlying semiconductor substrate.

Figure 2 shows a prior art CMOS structure with planarized conductive lines and stacked vertical vias.

Fig. 3 illustrates one embodiment of a substantially horizontal orientation of a non-volatile nanotube switch, where two terminals are each deposited at opposite ends of a patterned nanotube channel element.

Fig. 4 illustrates one embodiment of a substantially horizontal orientation of a non-volatile nanotube switch in which a conformal nanotube channel element is deposited over a predefined terminal area.

Fig. 5 illustrates one embodiment of a non-volatile nanotube switch in which nanotube channel elements are deposited in a substantially horizontal orientation on predefined terminal regions that include coplanar insulator regions between the terminals.

Fig. 6A-6B show SEM views of various embodiments of a non-volatile nanotube switch, similar to the embodiment of the non-volatile nanotube switch shown in fig. 3 in an ON state and an OFF state.

Fig. 7A illustrates one embodiment of a conformal nanostructure layer having a substantially vertical orientation over a stepped region.

FIG. 7B is a cross-sectional view of a representative embodiment of a 3-D memory cell having a vertically oriented non-volatile nanotube-switched storage element.

FIG. 8 illustrates a schematic diagram of an embodiment of a non-volatile nanotube switch.

Figures 9A-9B illustrate ON and OFF resistance values for exemplary nanotube channel element channel lengths of 250nm and 22 nm.

Figure 10 illustrates a non-volatile nanotube switch erase voltage as a function of non-volatile nanotube channel length for a plurality of exemplary nanotube switches.

11A-11B illustrate non-volatile nanotube switch voltage and current operating waveforms for erase, program, and read modes of operation for an exemplary nanotube switch.

FIG. 12 illustrates a schematic diagram of an embodiment of a two-terminal non-volatile nanotube diode formed from a diode in series with a non-volatile nanotube switch, with a cathode-to-nanotube electrical connection.

FIG. 13 illustrates a schematic diagram of an embodiment of a two-terminal non-volatile nanotube diode formed from a diode in series with a non-volatile nanotube switch, with an anode-to-nanotube electrical connection.

Fig. 14 and 15 show schematic diagrams of embodiments of two-terminal non-volatile nanotube diodes, formed from NFET-diodes in series with non-volatile nanotube switches.

Fig. 16 and 17 show schematic diagrams of embodiments of two-terminal non-volatile nanotube diodes formed by PFET-diodes in series with non-volatile nanotube switches.

FIG. 18 illustrates an embodiment with the non-volatile nanotube diode of FIG. 12 and two stimulus sources.

FIG. 19 illustrates an embodiment with the non-volatile nanotube diode of FIG. 15 and two stimulus sources.

20A-20B illustrate mode setting waveforms for changing the nonvolatile state of a nonvolatile nanotube diode, in accordance with some embodiments.

Figures 21A-21E illustrate circuit and device electrical characteristics of a non-volatile nanotube diode similar to that shown in figure 12, according to some embodiments.

FIG. 22 illustrates circuit operating waveforms for the circuit shown in FIG. 21A according to some embodiments.

FIG. 23A illustrates one embodiment of a circuit using a non-volatile nanotube diode similar to that shown in FIG. 15.

FIG. 23B illustrates circuit operating waveforms for the circuit shown in FIG. 23A, according to some embodiments.

FIG. 24 illustrates an embodiment of a transfer circuit using a non-volatile nanotube diode corresponding to the non-volatile nanotube diode of FIG. 12.

FIG. 25 illustrates circuit operating waveforms of the circuit shown in FIG. 24 according to some embodiments.

FIG. 26A schematically illustrates an embodiment of a memory that uses the non-volatile nanotube diode shown in FIG. 12 as a non-volatile memory cell.

FIG. 26B illustrates operational waveforms of the memory shown in FIG. 26A, according to some embodiments.

27A-27B illustrate a method of fabricating a memory cell using a non-volatile nanotube diode similar to that shown in FIG. 12, in accordance with some embodiments.

Fig. 28A shows a three-dimensional cross-sectional view of an embodiment of a high density 3D cell structure formed with a cathode-to-nanotube non-volatile nanotube diode with a schottky diode in series with a vertically oriented non-volatile nanotube switch within a vertical cell boundary.

Figure 28B illustrates a three-dimensional cross-sectional view of one embodiment of a high density 3D cell structure formed with a cathode-to-nanotube non-volatile nanotube diode with PN diodes in series with vertically oriented non-volatile nanotube switches within the vertical cell boundaries.

Fig. 28C shows a three-dimensional cross-sectional view of an embodiment of a high density 3D cell structure formed with a cathode-to-nanotube non-volatile nanotube diode with a schottky diode in series with a horizontally oriented non-volatile nanotube switch within a vertical cell boundary.

FIG. 29A schematically illustrates one embodiment of a memory that uses the nonvolatile nanotube diode shown in FIG. 13 as a nonvolatile memory cell.

FIG. 29B illustrates operational waveforms of the memory shown in FIG. 29A, according to some embodiments.

Figures 30A-30B illustrate a method of fabricating a memory cell using a non-volatile nanotube diode similar to that schematically illustrated in figure 13, in accordance with some embodiments.

Fig. 31A shows a three-dimensional cross-sectional view of an embodiment of a high density 3D cell structure formed with an anode-to-nanotube non-volatile nanotube diode with a schottky diode in series with a vertically oriented non-volatile nanotube switch within a vertical cell boundary.

FIG. 31B illustrates a three-dimensional cross-sectional view of one embodiment of a high density 3D cell structure formed with an anode-to-nanotube non-volatile nanotube diode with PN diodes in series with vertically oriented non-volatile nanotube switches within the vertical cell boundaries.

Fig. 31C shows a three-dimensional cross-sectional view of an embodiment of a high density 3D cell structure formed with anode-to-nanotube non-volatile nanotube diodes with schottky diodes and PN diodes in parallel and both schottky and PN parallel diodes in series with vertically oriented non-volatile nanotube switches within the vertical cell boundaries.

Figure 32 illustrates a method of fabricating a stacked 3D memory array according to some embodiments using cathode-to-nanotube and anode-to-nanotube non-volatile nanotube diodes similar to those schematically illustrated in figures 12 and 13.

Figure 33A shows a perspective view of one embodiment of a two stack 3D memory array using both cathode-to-nanotube and anode-to-nanotube 3D arrays.

33B and 33B' show cross-sectional views of two embodiments of stacked 3D memory array structures with shared word lines.

FIG. 33C illustrates a cross-sectional view of an embodiment of a stacked 3D memory array, which is a variation of the structure of FIG. 33B.

FIG. 33D illustrates operational waveforms for the memory structure shown in FIGS. 33A, 33B, and 33B', according to some embodiments.

Figures 34A-34FF illustrate a method of fabricating a cathode-on-nanotube memory cross-sectional structure having the vertically oriented non-volatile nanotube switch shown in figures 28A and 28B within a vertical cell boundary, according to some embodiments.

35A-35S illustrate a method of fabricating a cathode-on-nanotube memory cross-sectional structure having the horizontally-oriented non-volatile nanotube switch shown in FIG. 28C within a vertical cell boundary, in accordance with some embodiments.

Figures 36A-36FF illustrate a method of fabricating a cross-sectional anode-on-nanotube memory structure having the vertically oriented non-volatile nanotube switches shown in figures 32A, 32B, and 32C within vertical cell boundaries, according to some embodiments.

Figure 37 shows a three-dimensional cross-sectional view of one embodiment of a high density 3D cell structure formed with a cathode-to-nanotube or anode-to-nanotube non-volatile nanotube diode with the diode portion of the structure schematically shown in series with a near-cell-center placed vertically oriented non-volatile nanotube switch within a vertical cell boundary.

Fig. 38 illustrates an embodiment of a nanotube layer formed on a substrate by a spray coating method and having a relatively small void area.

FIG. 39 illustrates an embodiment similar to that shown in FIG. 37 with a thicker non-volatile nanotube switch including nanotube elements placed far-cell-center within a vertical cell boundary.

FIG. 40 illustrates a three-dimensional cross-sectional view of one embodiment of a high density 3D cell structure formed with a cathode-to-nanotube or anode-to-nanotube non-volatile nanotube diode with the diode portion of the structure shown schematically in series with a non-volatile nanotube switch, and within a vertical cell boundary, the non-volatile nanotube switch including a nanotube element and filling a region within the cell boundary.

Figures 41A-41B illustrate diagrams of methods of forming controlled shapes in and over vertical sidewalls of a recessed (trench) structure, according to some embodiments.

Fig. 42A-42H illustrate methods of fabricating a non-volatile nanotube switch with nanotube elements outside the cell boundary region and within and over the vertical sidewalls of the trench structure, in accordance with some embodiments.

Fig. 43A-43C illustrate embodiments of nonvolatile nanotube switches having nanotube elements of different thicknesses outside the cell boundary region and within and over the vertical sidewalls of the trench structure.

Fig. 44A-44B illustrate embodiments of nonvolatile nanotube switches having nanotube elements with different thicknesses within and outside of cell boundary cell regions (but within and above the vertical sidewalls of the trench structure).

Fig. 45 shows a variation of the embodiment of fig. 43A-43C in which two non-volatile nanotube switches share a single select (steering) diode to form a double high density 3D memory array, rather than stacking two arrays as shown in fig. 33B, 33B', and 33C.

Fig. 46 shows a variation of the embodiment of fig. 44A-44B in which two non-volatile nanotube switches share a single select (steering) diode to form a double high density 3D memory array, rather than stacking two arrays as shown in fig. 33B, 33B', and 33C.

Fig. 47 shows a three-dimensional cross-section of an embodiment of a high density 3D cell structure formed with a cathode-to-NT non-volatile nanotube diode with a schottky diode in series with a horizontally oriented self-aligned terminal contacted nanotube switch connected to a contact area using trench sidewall wiring.

Fig. 48A-48BB illustrate a method of fabricating the structure shown in fig. 47, using a trench-filled conductor method to create trench sidewall routing, in accordance with some embodiments.

Fig. 49 illustrates an embodiment of a non-volatile nanotube switch in a substantially horizontal orientation, wherein two terminals are disposed at opposite ends of a patterned nanotube channel element and contact only a nanotube element termination region.

Fig. 50 illustrates operation of the switch of fig. 49 according to some embodiments.

Fig. 51 and 52 show respective three-dimensional cross-sectional views of embodiments of high density 3D cell structures formed with anode-to-NT non-volatile nanotube diodes with schottky diodes in series with horizontally oriented self-aligned terminal contacted nanotube switches connected to contact areas using trench sidewall wiring.

FIG. 53 illustrates a perspective view of one embodiment of a stacked dual high memory array using cathode-over-NT and anode-over-NT stacked arrays.

FIGS. 54A-54B illustrate cross-sectional views of embodiments of dual high memory arrays using the 3D memory structures of FIGS. 47, 48, 51, and 52.

Fig. 55A-55F illustrate cross-sectional views of 3D memory cells using sidewall wiring formed within trench openings using conformal conductor deposition, without using the trench fill methods of fig. 47, 48A-48BB, 51, and 52, according to some embodiments.

Fig. 56A-56F show perspective views of embodiments of nonvolatile nanotube switches that include switch contact regions at opposite ends of a nanotube element, as well as embodiments of nonvolatile nanotube block-based switches having contacts at the top, bottom, and termination regions.

Fig. 57A-57C show perspective views of embodiments of non-volatile nanotube block based switches having contact areas with top, bottom, and terminals and various insulator options.

Fig. 58A-58D show cross-sectional and SEM views of an embodiment of a non-volatile nanotube-block based switch having contacts on the top, bottom, and terminals.

Fig. 59 illustrates the electrical ON/OFF switching characteristics of the non-volatile nanotube block based switching embodiment shown in fig. 58A-58D.

Fig. 60A-60C show cross-sectional and SEM views of one embodiment of a non-volatile nanotube block based switch with only terminal contacts.

Fig. 61 illustrates the near-ohm resistance of the non-volatile nanotube block based switch embodiment in fig. 60A-60C in the ON state.

Fig. 62A-62B illustrate cross-sectional views of non-volatile nanotube block based switch embodiments with bottom contacts and combined top and terminal contacts.

FIGS. 63A-63B illustrate the electrical ON/OFF switching characteristics of the non-volatile nanotube block based switching embodiment shown in FIGS. 62A-62B.

Fig. 64A-64C illustrate plan, cross-sectional, and SEM views of an embodiment of a non-volatile nanotube-block based switch with top and bottom contacts.

Fig. 65 illustrates the electrical ON/OFF switching characteristics of the non-volatile nanotube block based switching embodiment shown in fig. 64A-64C.

Fig. 66A-66C illustrate a method of fabricating a non-volatile nanotube block using various types of nanotube solutions and insulators, according to some embodiments.

Fig. 67 shows a three-dimensional cross-sectional view taken along the word line (X-direction) of an embodiment of a high density 3D cell structure formed with a cathode-to-NT non-volatile nanotube diode, the diode portion of the structure in series with a non-volatile nanotube block based switch that includes a non-volatile nanotube block within a vertical cell boundary and fills the area within the cell boundary.

68A-68I illustrate methods of fabricating cathode-on-nanotube memory cross-sectional structures with nonvolatile nanotube diodes including nonvolatile nanotube block based switches within vertical cell boundaries such as those shown in FIGS. 67 and 40, in accordance with some embodiments.

Fig. 69 shows a three-dimensional cross-sectional view taken along the bit line (Y-direction) of an embodiment of a high density 3D cell structure formed with an anode-to-NT non-volatile nanotube diode, the diode portion of the structure in series with a non-volatile nanotube block based switch that includes a non-volatile nanotube block within a vertical cell boundary and fills the area within the cell boundary.

Fig. 70 shows a three-dimensional cross-sectional view taken along the word line (X-direction) of an embodiment of a high density 3D cell structure formed with an anode-to-NT non-volatile nanotube diode, the diode portion of the structure in series with a non-volatile nanotube block based switch that includes a non-volatile nanotube block within a vertical cell boundary and fills the area within the cell boundary.

Figure 71 shows a 3D perspective view of one embodiment of a dual-high stack three-dimensional non-volatile nanotube block based switch with top and bottom contacts and sharing word lines between the upper and lower arrays.

Figure 72A shows a three-dimensional cross-sectional view taken along the word line (X-direction) of one embodiment of a dual-high stacked three-dimensional non-volatile nanotube-block based switch having top and bottom contacts and sharing word lines between the upper and lower arrays.

Figure 72B shows a three-dimensional cross-sectional view taken along the bit line (Y-direction) of one embodiment of a dual-high stacked three-dimensional non-volatile nanotube block based switch with top and bottom contacts and sharing word lines between the upper and lower arrays.

Figure 73 shows a 3D perspective view of one embodiment of a dual-high stack three-dimensional non-volatile nanotube block based switch with top and bottom contacts and no array lines (e.g., word lines) shared between the upper and lower arrays.

Figure 74 shows a three-dimensional cross-sectional view taken along the word line (X-direction) of one embodiment of a dual-high stacked three-dimensional non-volatile nanotube block based switch with top and bottom contacts and no array lines (e.g., word lines) shared between the upper and lower arrays.

FIG. 75 illustrates a 3-D perspective view of one embodiment of a non-volatile memory array including four 3-D non-volatile memory cells, each cell including a 3-D non-volatile nanotube diode, the 3-D non-volatile nanotube diode including non-volatile nanotube block-based switches and cell interconnects formed by bit lines and word lines.

FIGS. 76A-76D illustrate methods of fabricating a cathode-on-nanotube memory cross-sectional structure with a non-volatile nanotube diode that includes a non-volatile nanotube-block based switch as shown in FIG. 75 within vertical cell boundaries, according to some embodiments.

Figure 77 shows a 3D perspective view of one embodiment of a multi-layer, high-stack, three-dimensional, non-volatile nanotube block-based switch with top and bottom contacts and no array lines (such as word lines) shared between the upper and lower arrays.

Detailed Description

Various embodiments of the present invention provide non-volatile diodes and non-volatile nanotube blocks and systems using them and methods of making the same.

Some embodiments of the invention provide 3-D cell structures that enable high density non-volatile memory arrays, including nanotube switches and diodes, that can write logic 1 and 0 states in multiple cycles, and that are integrated on a single semiconductor (or other) substrate. It should be noted that such non-volatile memory arrays may also be configured as NAND and NOR arrays in PLA, FPGA, and PLD configurations to perform independent and embedded logic functions.

Some embodiments of the present invention provide diode devices having non-volatile characteristics due to the combination of the diode and non-volatile nanotube elements, and methods of forming such devices.

Some embodiments of the present invention also provide nanotube-based nonvolatile random access memories including nonvolatile nanotube diode device cells having a relatively high density, and methods of forming these memory devices.

Some embodiments of the present invention provide non-volatile devices that combine diodes in non-volatile nanotube switch (NV NT switch) and non-volatile nanotube diode (NV NT diode) devices, such as described in U.S. patent application No.11/280,786. Suitable diodes include schottky, PN, PIN, PDB (planar-doped-block), Esaki (Esaki), LED (light emitting), laser and other diodes, and FET diodes. The combination of NV NT switches with PDB and esaki diodes can be used for fast switching applications, while the combination of NV NT switches with LEDs and laser diodes can be used as light (photon) sources for communication and display applications, as well as photon-based logic and memory applications. Non-volatile nanotube diodes (NVNT diodes) formed using various diode and NVNT switch combinations, such as cathode-to-nanotube and anode-to-nanotube interconnects, are described. NV NT diode operation is also described. Devices fabricated using NV NT diodes are also described.

Although in some embodiments, NV NT diodes are formed by combining NV NT switches formed using silicon and metallurgically typical CMOS processes with various diodes, a wide variety of semiconductor materials and conductors can be used to form various diode and various conductor combinations. Examples of semiconductor materials are e.g. Si, Ge, SiC, GaP, GaAs, GaSb, InP, InAs, InSb, ZnS, ZnSe, CdS, CdSe, CdTe. Schottky diodes may be formed by combining various semiconductor materials with conductors, such as Al, Ag, Au/Ti, Bi, Ca, Co, CoSi ₂、Cr、Cu、Fe、In、Ir、Mg、Mo、MoSi₂、Na、Ni、NiSi₂、Os、Pb、Pd、Pd₂Si、Pt、PtSi、Rh、RhSi、Ru、Sb、Sn、Ti、TiSi₂、W、WSi₂、Zn、ZrSi₂And the like. LEDs and laser diodes may use semiconductor materials that determine the wavelength of light emission, such as GaInAsPt, GaAsSb, InAsP, InGaAs, and many other material combinations.

Alternatively, a FET diode may be formed by combining a NV NT switch with a three terminal FET, wherein the gate is electrically connected to one of the two diffusion terminals to form a two terminal FET diode device. When combined with NV NT switches and FET diodes, the nonvolatile nanotube diode may also be referred to as a nonvolatile nanotube FET-diode, abbreviated NV NTFET-diode, to highlight its differences from schottky, PN, PIN, and other diodes. However, the differences between the NV NT switch and the combination of FET diodes and Schottky, PN, PIN and other diodes need not be highlighted and may all be referred to as NV NT diodes.

Also described are 2-D non-volatile memory embodiments that include free-standing and embedded logic (e.g., a processor) that uses non-volatile nanotube diodes (NV NT diodes) as storage elements. These NV NT diodes may be formed in and/or on a semiconductor substrate, have memory support circuitry and logic functions, and be integrated on a single substrate, such as a semiconductor chip or wafer, to form 2-D memory and logic functions.

Embodiments of 3-D architectures of non-volatile memories are also described, including stand-alone and embedded logic (e.g., processors) that use NV NT diodes as 3-D cells of a 3-D memory array, which can write logic 1 and 0 states over multiple cycles. It should be noted that some embodiments of 3-D memories using NV NT diode cell arrays are described in relation to memory arrays that are not fabricated in or on a semiconductor substrate, but rather are formed on an insulating layer on support circuitry formed in and on the semiconductor substrate with interconnects between the support circuitry and the 3-D memory array.

The NV NT diode array may also be formed on a planar insulating surface on the support circuitry and have array interconnects through and on the insulating layer, wherein in the fabrication method used to form the NV NT diode array, the array features are self-aligned in the X and Y directions so that the array feature size does not increase to accommodate alignment requirements.

It should also be noted that currently available planarization techniques, such as chemical-mechanical planarization (CMP), combine silicon-on-insulator (SOI) technology with Thin Film Transistor (TFT) technology so that 3-D memory arrays using NV NT diodes as 3-D cells can be fabricated in a flat, high-density stacked structure on a single substrate, where the substrate is not a semiconductor substrate. The combined planarization technique and display-application-drive enhancement TFT technique enables a non-semiconductor substrate (such as a glass, ceramic, or organic substrate) as an alternative to using a semiconductor substrate.

Various methods of fabricating 3-D memories are described.

Although NV NT diode based nonvolatile memory is described, it should be noted that such nonvolatile memory arrays can also be configured as NAND and NOR arrays for PLA, FPGA, and PLD functions to perform stand-alone and embedded logic functions.

Two terminal non-volatile nanotube diode device

Some embodiments provide a non-volatile nanotube diode device that acts like a diode, enabling direct electrical communication in a forward bias direction and avoiding reverse direction communication if the nanotube diode is in an ON (or state) mode. However, if the non-volatile nanotube diode device is in an OFF mode (or state), direct communication is avoided, whether in the forward or reverse direction. The ON (ON) mode or OFF (OFF) mode of a non-volatile nanotube-diode device is non-volatile and is maintained without power being supplied to the element. The mode of the non-volatile nanotube-diode device can be changed from ON to OFF or OFF to ON by applying appropriate voltage and current levels using a stimulus circuit.

Some embodiments of non-volatile devices are formed by combining non-volatile nanotube switches (NV NT switches) with diodes (e.g., schottky, PN, PIN, and other diodes and FET diodes) to form non-volatile nanotube diode (NV NT diode) devices, which are described in U.S. patent application No.11/280,786, U.S. patent application No. (to be declared), filed concurrently herewith, and/or U.S. patent application No. (to be declared), entitled "memory elements and cross-point switches and arrays thereof using non-volatile nanotube blocks," filed concurrently herewith. In some embodiments, the non-volatile nanotube diode (NV NT diode) is a two-terminal device with one terminal in contact with one terminal of the non-volatile nanotube switch and the other terminal in contact with the anode or cathode of the diode. In some embodiments, a shared internal contact connects the second terminal of the nonvolatile nanotube switch and the cathode or anode of the diode to form a nonvolatile nanotube diode device.

Some embodiments of NV NT diodes may be scaled to large non-volatile array structures. Some embodiments use processes compatible with CMOS circuit fabrication. It should be noted that the P and N regions of the illustrated example may be interchanged with a corresponding change in polarity of the applied voltage based on the principle of duality in the semiconductor device.

A non-volatile nanotube diode device, a cathode of the diode connected to a terminal of the non-volatile nanotube switch; and other non-volatile nanotube diode devices, the anode of the diode being connected to a terminal of the non-volatile nanotube switch

Non-volatile nanotube switches (NV NT switches) are described in U.S. patent application No.11/280,786 and briefly summarized below. The NV NT switch includes a patterned nanotube element and two terminals in contact with the patterned nanotube (nanostructure) element. Methods of forming nanotube structures and elements and their characteristics are described in more detail in the incorporated patent references. The non-volatile nanotube switching operation is not dependent on voltage polarity, and positive or negative voltages may be used. The first terminal may be at a higher or lower voltage relative to the second terminal. There is no preferred current flow direction. The current may flow from the first terminal to the second terminal or from the second terminal to the first terminal.

FIG. 3 illustrates an embodiment of NV NT switch 300, including a patterned nanotube element 330 on an insulator 340 supported by a substrate 350. Terminals (conductive elements) 310 and 320 are deposited directly on patterned nanotube element 330 and at least partially overlap opposite ends of patterned nanotube element 330. Non-volatile nanotube switch channel length L_SW-CHIs the spacing between 310 and 320. L is_SW-CHIs important to the operation of the non-volatile nanotube switch 300, as described further below. Substrate350 may be an insulator, such as ceramic or glass; a semiconductor; or an organic rigid or flexible substrate. Substrate 350 may also be organic and may be flexible or rigid. Insulator 340 may be SiO₂、SiN、Al₂O₃Or other insulator material. Terminals (contacts) 310 and 320 can be formed using various contact and interconnect element metals, such as Ru, Ti, Cr, Al (Cu), Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn, and metal alloys, such as TiAu, TiCu, TiPd, PbIn, and TiW, other suitable conductors, or conductive nitrides, oxides, or silicides, such as RuN, RuO, TiN, TaN, CoSi_xAnd TiSi_x。

FIG. 4 illustrates one embodiment of NV NT switch 400, including a patterned nanotube element 430 on an insulator 440 supported by a substrate 450. Patterned nanotube element 430 is a non-planar conformal (conformal) nanostructure that also partially overlaps and contacts terminals (conductive elements) 410 and 420 on the top and side surfaces. Terminals (contacts) 410 and 420 are deposited and patterned directly on substrate 450 prior to the formation of patterned nanotube element 430. Patterned nanotube element 330 is formed using conformal nanostructures that at least partially overlap terminals 410 and 420. Non-volatile nanotube switch channel length L _SW-CHIs the spacing between terminals 410 and 420. L is_SW-CHIs important to the operation of the non-volatile nanotube switch 400, as described further below. The substrate 450 may be an insulator, such as ceramic or glass; semiconductor, or organic rigid or flexible substrates. Substrate 450 may also be organic and may be flexible or rigid. Insulator 440 may be SiO₂、SiN、Al₂O₃Or other insulator material. Terminals 410 and 420 can be formed using various contact and interconnect elemental metals, such as Ru, Ti, Cr, Al (Cu), Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn, and metal alloys, such as TiAu, TiCu, TiPd, Pbin, and TiW, other suitable conductors, or conductive nitrides, oxides, or silicides, such as RuN, RuO, TiN, TaN, CoSi_xAnd TiSi_x。

Fig. 5 shows an embodiment of NV NT switch 500, comprising a patterned nanotube element 530 on an insulator 535, the insulator 535 being on an insulator 540, the insulator 540 being supported by a substrate 550. Patterned nanotube element 530 is a nanostructure on a planar surface that also partially overlaps and contacts terminals (conductive elements) 510 and 520. Terminals (contacts) 510 and 520 are deposited and patterned directly on substrate 550 before patterned nanotube element 530 is formed. The overlap distance 560 of patterned nanotube element 530 to terminal 520 does not significantly alter the operation of non-volatile nanotube switch 500. Non-volatile nanotube switch channel length L _SW-CHIs the spacing between terminals 510 and 520. L is_SW-CHIs important to the operation of the non-volatile nanotube switch 500, as described further below. Substrate 550 may be an insulator, such as a ceramic or glass, semiconductor, or organic rigid or flexible substrate. Substrate 550 may also be organic and may be flexible or rigid. Insulators 535 and 540 can be SiO₂、SiN、Al₂O₃Or other insulator material. Terminals 510 and 520 can be formed using various contact and interconnect elemental metals, such as Ru, Ti, Cr, Al (Cu), Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn, and metal alloys, such as TiAu, TiCu, TiPd, Pbin, and TiW, other suitable conductors, or conductive nitrides, oxides, or silicides, such as RuN, RuO, TiN, TaN, CoSi_xAnd TiSi_x。

In some embodiments, NV NT switch 500 may be modified (not shown) to include a gate region in insulator 535 with insulator 535 interposed between a portion of nanotube element 530 and insulator 540, as further described in U.S. patent application No. (to be declared) entitled "non-volatile resistive memory with scalable two-terminal nanotube switch," filed concurrently herewith, and/or U.S. patent application No. (to be declared) entitled "memory elements and cross-point switches and arrays thereof using non-volatile nanotube blocks. While not wishing to be bound by theory, it is believed that a reduced amount of heat is dissipated to the surrounding substrate in the suspended region, and thus, less voltage and current levels may be needed to heat the nanotube to a temperature sufficient for switching to occur. Other mechanisms are possible.

Fig. 6A shows an SEM image of an embodiment of a nonvolatile nanotube switch 600 prior to passivation and corresponding to the nonvolatile nanotube switch 300 shown in cross-section 300 in fig. 3. Non-volatile nanotube switch 600 includes patterned nanotube (nanostructure) element 630, terminals (contacts) 610 and 620, and insulator 640. The exemplary non-volatile nanotube switch 600 is fabricated with a terminal-to-terminal channel length (L) in the range of 250nm to 22nm_SW-CH) To reduce the nonvolatile nanotube switch size and lower the erase (write 0) voltage over a shorter channel length, as further described below. The program (write 1) voltage is typically maintained below the erase (write 0) voltage. Erase voltage measurements (data not shown) for nonvolatile nanotube switches with different channel widths showed when the channel width W was measured_SW-CHThere is no significant correlation between the erase voltage and the device channel width from 500nm to 150 nm. Measurements of erase voltages for non-volatile nanotube switches with different nanostructure-to-contact terminal overlap lengths (data not shown) showed a significant correlation between erase voltage and overlap length, such as the overlap length 660 in fig. 6A, when the overlap length was changed from about 800nm to 20 nm.

Fig. 6A and 6B are obtained using SEM voltage contrast plots of NV NT switch 600, NV NT switch 600 including patterned nanotube element 630 connected to terminals 610 and 620. Referring to fig. 6A, NV NT switch 600 is in the ON state, such that a voltage applied to terminal 620 is transmitted to terminal 610 through patterned nanotube element 630, which is in an electrically continuous ON state. Fig. 6B shows NV NT switch 600', which corresponds to NV NT switch 600 being in the OFF state. In the OFF state, patterned nanotube element 630 is electrically discontinuous within itself and/or is separated from one of terminals 610, 620. The SEM voltage contrast plot of NV NT switch 600 'in fig. 6B illustrates patterned nanotube element 630, where patterned nanotube element region 630' appears to be electrically connected to terminal 620 (light region), and patterned nanotube element region 630 "appears to be electrically connected to terminal 610 '(dark region), but patterned nanotube element regions 630' and 630" appear to be unconnected to each other, i.e., patterned nanotube element 630 "disconnected". Because of the apparent electrical discontinuity between patterned nanotube element regions 630 ' and 630 ", the voltage applied to terminal 620 does not reach terminal 610 ', and thus terminal 610 ' is dark. Note that terminal 610 'is identical to terminal 610 except that it is not electrically connected to terminal 620 of NVNT switch 600'.

The non-volatile nanotube switch embodiment 600 shown in fig. 6A-6B is fabricated on a horizontal surface. In general, patterned nanotube elements can be fabricated using conformal, patterned nanostructures that can be oriented at a variety of angles without limitation, as described in more detail in the incorporated patent references. Fig. 7A is an SEM image of an exemplary structure 700 after deposition with nanostructures 730 conforming to the underlying steps and having regions of vertical orientation 735. This conformal nature of the nanostructures can be used to fabricate vertically oriented non-volatile nanotube switches, enhance dimensional control and require less area (e.g., can be fabricated at higher densities), as further described below.

FIG. 7B is a diagram of an embodiment of a 3-D memory cell cross-section 750 storage element, which is described in greater detail in U.S. patent application No.11/280,786. The 3D memory cell storage areas 760A and 760B are mirror image storage devices using a non-volatile nanotube switch with vertically oriented nanotube elements 765 and 765'. Protective insulator materials 770 and 770 ', and 775, 775 ', and 775 "are used to improve the performance and reliability of nanotube elements 765 and 765 ', respectively. The cell storage areas 760A and 760B include lower contacts 780 and 780 ', respectively, and upper contacts 785 and 785', respectively. The upper contacts 785 and 785' include sidewall and top contact regions. Contacts 780 and 780' are embedded in insulator 790. Insulator 795 on the top surface of insulator 790 includes sidewall regions for defining the locations of nanotube channel elements 765 and 765'.

Fig. 8 illustrates a non-volatile nanotube switch 800, which schematically represents non-volatile nanotube switches 300, 400, 500 and other non-volatile nanotube switches (not shown), which may include a floating region, and may also include horizontal, vertical, or other directions, according to some embodiments. Two terminals (contacts) 810 and 820 are shown and correspond to terminals (contacts), such as terminals 310 and 320 of NV NT switch 300, terminals 410 and 420 of NV NT switch 400, and terminals 510 and 520 of NV NT switch 500.

The results of experimental testing of a single fabricated non-volatile nanotube switch (schematically represented by non-volatile nanotube switch 800 of fig. 8) are shown by curve 900 in fig. 9A. The switching results for non-volatile nanotube switch 800, shown by plot 900, over 5 million ON/OFF cycles, show an ON-state resistance (ON resistance) in the range of 10 kilo-ohms to 50 kilo-ohms, while an OFF-state resistance (OFF resistance) over 10 giga-ohms, with resistance values between the conductive and non-conductive states differing by more than 5 orders of magnitude. The non-volatile nanotube switch 800 has a channel length (L)_SW-CH) Is a 250nm patterned nanotube element. The non-volatile nanotube switch has a typical 8 volt erase voltage and a typical 5 volt programming voltage over a channel length of 250nm, as described further below, and in U.S. patent application No.11/280,786 and U.S. patent application No. (to be announced) entitled "non-volatile resistive memory with scalable two-terminal nanotube switch," filed concurrently herewith.

Figure 9B shows cycling data 900' for a fabricated device with a channel length of about 22nm and a channel width of about 22 nm. Devices with channel lengths of about 20nm typically have erase voltages in the range of 4 to 5 volts. The particular device characterized in FIG. 9B has an erase voltage of 5 volts, a program voltage of 4 volts, and 100 erase/program cycles. The ON resistance is below 100 kilo ohms and the OFF resistance is above 100M ohms.

The curve 1000 of FIG. 10 shows when L_SW-CHChannel length L decreases from more than 250nm to 50nm_SW-CHReducing voltage reduction effects on erase voltages of a plurality of fabricated non-volatile nanotube switches. L is_SW-CHRefer to the switching channel lengths described with reference to fig. 3, 4, and 5. The effect of channel length reduction is shown in terms of erase voltage reduction as a function of channel length reduction and erase/program cycle yield variation, where each data point represents 22 devices and the number of ON/OFF erase/program cycles is 5. As the non-volatile nanotube switch channel length is reduced from 250nm to 50nm, the erase voltage is a strong function of the channel length, decreasing (shrinking) from 8 volts to 5 volts, as shown by curve 1000 in fig. 10. The corresponding program voltage (not shown) is lower than the erase voltage, typically in the range of, for example, 3 to 5 volts. Non-volatile nanotube switch erase voltage measurements (data not shown) for different channel widths showed no significant correlation between erase voltage and device channel width when channel width was varied from 500nm to 150nm, and non-volatile nanotube switch erase voltage measurements (data not shown) for different nanostructure-to-contact terminal overlap lengths showed no significant correlation between erase voltage and overlap length (such as overlap length 660 in fig. 6A) when the overlap length was varied from about 800nm to 20 nm.

Fig. 11A shows an exemplary erase waveform 1100 of erase voltage and corresponding erase current as a function of time for a fabricated non-volatile nanotube switch having a channel length of 250nm, an erase voltage of 8 volts, and a corresponding erase current of 15 microamps. It is noted that during testing, a negative voltage is applied to the non-volatile nanotube switch. Non-volatile nanotube switches operate with either a positive or negative applied voltage and a current in either direction. The erase current is typically in the range of 1 to 50uA, depending on the number of activated SWNTs in the patterned nanotube element in the channel region. When the switch switches from the ON state to the OFF state, the erase current is typically not limited by the stimulus circuit.

Fig. 11B shows an exemplary waveform 1100' for a full non-volatile nanotube switching cycle, which includes read, erase, and program operations. For the fabricated non-volatile nanotube switch with a channel length of 250nm, an erase voltage of 8 volts, and a corresponding erase current of 15 microamps, the erase waveforms show the erase voltage and corresponding erase current as a function of time. The programming waveforms show the programming voltage and corresponding programming current as a function of time for a non-volatile nanotube switch with a channel length of 250nm, an erase voltage of 8 volts, and a corresponding erase current of 15 microamps. When the switch is switched from the OFF state to the ON state, the programming current is typically limited by the stimulus circuit to improve the programming characteristics. An example of limiting the programming current using a stimulus circuit is described in U.S. patent application No. (to be announced) entitled "non-volatile resistive memory with scalable two-terminal nanotube switches," filed concurrently herewith. The erase waveforms shown in FIG. 11A and the read, erase, and program waveforms in FIG. 11B are described in more detail in U.S. patent application No.11/280,786.

Non-volatile nanotube switches can be fabricated to exhibit a wide range of ON resistance values depending ON the switch channel length, and the number of individual nanotubes in the patterned nanotube (channel) element. Non-volatile nanotube switches may exhibit ON resistances in the range of 1 kilo-ohm to 10 mega-ohms, while OFF resistances are typically 100 mega-ohms or 1 giga-ohm or greater.

The non-volatile nanotube diode device is a series combination of a two-terminal semiconductor diode and a two-terminal non-volatile nanotube switch (similar to the non-volatile nanotube switches described above with reference to fig. 3-11). Various diode types are described in the references NG, k.k., "Complete Guide to semiconductor devices" Second Edition, John Wiley and Sons, 2002, the entire contents of which are incorporated herein by reference; schottky diodes (schottky-barrier diodes) are described on pages 31-41; junction (PN) diodes are described on pages 11-23; PIN diodes are described on pages 24-41; light Emitting Diodes (LEDs) are described at pages 396-407. FET-diodes are described in the references Baker, R.J. et al, "CMOS Circuit design, Layout, and Simulation", IEEE Press, 1998, pp.168-169, the entire contents of which are incorporated herein by reference.

Further describing NV NT diode embodiments below typically use schottky diodes, PN diodes, and FET-diodes. However, other types of diodes, such as PIN diodes, may be combined with non-volatile nanotube switches to form non-volatile nanotube PIN-diodes, which may enable or disable, for example, RF switching, attenuation and modulation, signal limiting, phase shifting, power rectification, and light detection. Further, the non-volatile LED diode may be combined with a non-volatile switch to form a non-volatile nanotube LED-diode, which may enable or disable the LED diode and provide a light output pattern that is stored in the non-volatile nanotube LED-diode in a non-volatile state.

Schottky diodes generally have a low forward voltage drop (which is an advantage) and good high frequency characteristics. These characteristics combined with the ease of fabrication make schottky diodes useful in a wide range of applications. The key step in fabrication is to prepare a clean surface to bring the metal into intimate contact with the semiconductor surface. Metal on silicon layers or metal silicides on silicon layers may also be used. Schottky diode 142 is shown in fig. 1 and described further above and in the referenced U.S. patent 4,442,507, platinum is used to form a platinum silicide schottky diode ON a silicon layer having a forward ON-voltage of about 0.4 volts and a reverse breakdown voltage of about 10 volts. Further described below, the nonvolatile nanotube diode can be fabricated from nonvolatile nanotube switches and schottky, PN, P-I-N, LED and other diodes (e.g., FET-diodes in series), depending on the application requirements.

Fig. 12 illustrates an embodiment of a non-volatile nanotube diode 1200 device formed by combining a diode 1205 and a non-volatile nanotube switch 1210 in series. Terminal T1 is connected to the anode 1215 of diode 1205, while terminal T2 is connected to contact 1225 of non-volatile nanotube switch 1210. Cathode 1220 of diode 1205 is connected to contact 1230 of non-volatile nanotube switch 1210 via contact 1235. The operation of the non-volatile nanotube diode 1200 will be further explained as follows.

Fig. 13 illustrates an embodiment of a non-volatile nanotube diode 1300 device formed by combining a diode 1305 and a non-volatile nanotube switch 1310 in series. Terminal T1 is connected to the cathode 1320 of diode 1305, and terminal T2 is connected to contact 1325 of non-volatile nanotube switch 1310. Anode 1315 of diode 1305 is connected to contact 1330 of non-volatile nanotube switch 1310 via contact 1335.

Fig. 14 shows an embodiment of a non-volatile nanotube diode 1400 device formed by combining an NFET diode 1405 and a non-volatile nanotube switch 1410 in series. Terminal T1 is connected to contact 1415 of NFET diode 1405 and terminal T2 is connected to contact 1425 of non-volatile nanotube switch 1410. Contact 1415 is wired to the gate of the NFET and to the first diffusion region to form the first NFET diode 1405 terminal. Second diffusion region 1420 forms a second terminal of NFET diode 1405. The second diffusion region 1420 of the NFET diode 1405 is connected to a contact 1430 of the non-volatile nanotube switch 1410 via a contact 1435.

Fig. 15 shows an embodiment of a non-volatile nanotube diode 1500 device formed by combining an NFET diode 1505 and a non-volatile nanotube switch 1510 in series. Terminal T1 is connected to the first NFET diffusion terminal 1515 of NFET diode 1505 and terminal T2 is connected to contact 1525 of non-volatile nanotube switch 151. Contact 1520 of NFET diode 1505 is connected to contact 1530 of non-volatile nanotube switch 1510 via contact 1535. The operation of the non-volatile nanotube diode 1200 will be further explained as follows.

Fig. 16 illustrates an embodiment of a non-volatile nanotube diode 1600 device, formed by combining a PFET diode 1605 and a non-volatile nanotube switch 1610 in series. Terminal T1 is connected to a first PFET diffusion terminal 1615 of PFET diode 1605, while terminal T2 is connected to contact 1625 of nonvolatile nanotube switch 1610. A contact 1620 is wired to the gate of the PFET and to the second diffusion region to form a second PFET diode 1605 terminal. Contact 1620 of PFET diode 1605 is connected to contact 1630 of non-volatile nanotube switch 1610 via contact 1635.

Fig. 17 illustrates an embodiment of a non-volatile nanotube diode 1700 device formed by combining a PFET diode 1705 and a non-volatile nanotube switch 1710 in series. Terminal T1 is connected to contact 1715 of PFET diode 1705, while terminal T2 is connected to contact 1725 of non-volatile nanotube switch 1710. Contact 1715 is wired to both the gate of the PFET and the first diffusion region to form a first PFET diode 1705 terminal. The second diffusion region 1720 forms a second terminal of the PFET diode 1705. The second diffusion region 1720 of the PFET diode 1705 is connected to a contact 1730 of the nonvolatile nanotube switch 1710 via a contact 1735.

Operation of non-volatile nanotube diode devices

FIG. 18 shows an embodiment of circuit 1800 in which stimulus circuit 1810 applies voltage V_T1Applied between terminal T1 and a reference terminal (e.g., ground) of NVNT diode 1200, and stimulus circuit 1820 applies a voltage V_T2Applied between terminal T2 of NV NT diode 1200 and a reference terminal (e.g., ground). NV NT diode 1200 is formed by series diode 1205 and nonvolatile nanotube switch 1210 as further described above with reference to fig. 12.

FIG. 19 shows an embodiment of circuit 1900 in which stimulus circuit 1910 applies a voltage V_T2Applied between the terminal T2 of the NV NT diode 1500 (or NV NTFET-diode 1500) and a reference terminal (e.g., ground), and the stimulus circuit 1920 applies a voltage V_T1Applied between terminal T1 of NV NT diode 1500 and a reference terminal (e.g., ground). NV NT diode 1500 is formed by a series FET diode 1505 and a non-volatile nanotube switch 1510, as further described above with reference to fig. 15.

In an exemplary write 0 (erase) operation, referring to circuit 1800 in FIG. 18, non-volatile nanotube diode 1200 transitions from the ON state to the OFF state during a mode-setting time interval when write 0 operation waveform 2000-1 is applied, as shown in FIG. 20A. Write 0 operation 2000-1 waveform illustrates voltage V before initial write 0 operation 2000-1 _T1At a low voltage, e.g., zero volts. Voltage V_T2Can be any voltage between zero volts and about 10 volts, with 10 volts being the approximate reverse bias breakdown voltage of NV NT diode 1200. The reverse bias breakdown voltage of NVNT diode 1200 is determined by the reverse breakdown voltage of diode 1205, which is based on that shown in FIG. 1 and specified in the United statesThe reverse breakdown voltage of the schottky diode 142 described in U.S. Pat. No. 4,442,507 is assumed to be about 10 volts. Write 0 operation 2000-1 is not composed of V_T2Initially, because the diode 1205 has a high impedance in the reverse bias mode, it reduces the voltage across the NV NT switch 1210 and limits the current flowing through the NV NT switch 1210, thereby not meeting the voltage condition of 2000-1 for write 0 operations across the terminals of the NV NT switch 1210 by 4-5 volts, and no transition from the ON resistance state to the OFF resistance state occurs. Before the start of a write 0 operation, the NV NT switch 1210ON resistance is typically in the range of 10 kilo-ohms to 100 kilo-ohms, as shown in FIGS. 9A and 9B.

Exemplary write 0 operation 2000-1 during a mode set time interval, as shown in FIG. 20A, to slave voltage V_T2Switching to a lower voltage, e.g. ground, begins. Then, the voltage V_T1Switching to the applied write 0 voltage of 5 volts. The rise time for applying the write 0 voltage may be relatively short, e.g., less than 1ns, or may be relatively long, e.g., over 100 us. The stimulating circuit 1810 applies the voltage V _T1Applied to terminal T1, and voltage V_T1The forward voltage minus diode 1205 is applied to terminal 1230 of non-volatile nanotube switch 1210. If the forward voltage bias drop of diode 1205 is assumed to be about 0.5 volts (similar to the forward voltage of a schottky diode used in U.S. patent 4,442,507 being about 0.4 volts), and since terminal T2 is held at ground, a voltage of about 4.5 volts will appear across NV NT switch 1210. If the erase threshold voltage of the NV NT switch 1210 is, for example, 4.5 volts (or lower), the NV NT switch 1210 transitions from the ON state to the OFF state. During write 0 operations 2000-1, current limiting is not required. Typical write 0 currents are below 1uA to 50 uA.

In an exemplary write 1 (program) operation, referring to circuit 1800 of FIG. 18, non-volatile nanotube diode 1200 transitions from the OFF state to the ON state during the mode set time interval instead when write 1 operation waveform 2000-2 is applied, as shown in FIG. 20A. Write 1 operation 2000-2 waveform shows voltage V before initial write 0 operation 2000-2_T1At a low voltage, e.g., zero volts. The NVNT switch 1210OFF resistance can range from greater than 100 megaohms to greater than 10 gigaohms as shown in FIG. 9A and9B. Therefore, the reverse bias resistance of the diode 1205 can be less than the OFF resistance of the NV NT switch 1210, and most of the applied write 1 voltage appears across the terminals 1230 and T2 of the NV NT switch 1210, as shown in FIG. 18. If the voltage V is _T2Transitioning beyond the write 1 threshold voltage of NV NT switch 1210, an undesired write 1 cycle may begin. When the NV NT switch 1210 resistance drops, the reverse biased diode 1205 resistance dominates and may prevent the write 1 operation from completing. However, to avoid partial write 1 operations, V_T2Limited to, for example, 4 volts.

As shown in FIG. 20A, during a mode-setting time interval, an exemplary write 1 operation 2000-2 operates to slave voltage V_T2Switching to a lower voltage, e.g. ground, begins. Then, the voltage V_T1Switching to the applied write 1 voltage 4 volts. The rise time of the applied write 1 voltage may be relatively short, e.g., less than 1ns, or may be relatively long, e.g., over 100 us. The stimulating circuit 1810 applies the voltage V_T1Applied to terminal T1, and voltage V_T1The forward voltage of the subtraction diode 1205 is applied to the terminal 1230 of the NV NT switch 1210. If the forward voltage bias drop of diode 1205 is about 0.4-0.5 volts, similar to the forward voltage of a schottky diode such as that used in U.S. patent 4,442,507, and since terminal T2 is held at ground, a voltage of about 3.5 volts will appear across NV NT switch 1210. If the NV NT switch 1210 has a write 1 threshold voltage of, for example, 3.5 volts (or less), the NV NT switch 1210 transitions from the OFF state to the ON state. During write 1 operation 2000-2, a current limit may be applied. An example of a stimulation circuit including a current limiting device is described in U.S. patent application No. (to be announced) entitled "non-volatile resistive memory with scalable two-terminal nanotube switches," filed at about the same time as this document. Write 1 currents are typically limited to less than 1uA to 50 uA.

In an exemplary write 0 operation, referring to circuit 1900 of FIG. 19, during the mode set time interval when write 0 operation waveform 2000-3 is applied, non-volatile nanotube diode 1500 (or NVNTFET-diode 1500) transitions from the ON state to the OFF state, as shown in FIG. 20B. Write 0 operations 2000-3 before the initial write 0 operation 2000-33 waveform shows voltage V_T2At a low voltage, e.g., zero volts. Voltage V_T1Can be any voltage between zero and 7 volts, where 7 volts is the reverse bias breakdown voltage of the NV NT diode 1500. The reverse bias breakdown voltage of NV NT diode 1500 is determined by the reverse breakdown voltage of FET diode 1505, which in this example is assumed to be 7 volts for a FET diode fabricated using a 0.18 μm CMOS process. Write 0 operations 2000-3 are not composed of V_T1Initially, because the FET diode 1505 has a high impedance in the reverse bias mode, it reduces the voltage across the NV NT switch 1510 and limits current flow through the NV NT switch 1510, thereby not complying with the 2000-3 voltage condition for write 0 operations across the terminals of the NV NT switch 1510 by 4-5 volts, and no transition from the ON resistance state to the OFF resistance state occurs. The NV NT switch 1510ON resistance is typically in the range of 10 kilo-ohms to 100 kilo-ohms before beginning the write 0 operation, as shown in FIGS. 9A and 9B.

As shown in FIG. 20B, during a mode-setting time interval, an exemplary write 0 operation 2000-3 operates to slave voltage V_T1Switching to a lower voltage, e.g. ground, begins. Then, the voltage V_T2Switching to the applied write 0 voltage of 5 volts. The rise time for applying the write 0 voltage may be relatively short, e.g., 1ns, or may be relatively long, exceeding, e.g., 100 us. The stimulating circuit 1910 applies the voltage V_T2Applied to terminal T2, and voltage V_T2Minus the forward voltage of the FET diode 1505 is applied to terminal 1530 of the non-volatile nanotube switch 1510. The terminal of FET diode 1505 in circuit 1900 is connected to the lowest voltage in the circuit, which in this case is ground. Assuming that the semiconductor substrate is also connected to ground, the FET diode 1505 threshold voltage does not increase the voltage applied to the FET diode 1505 relative to the corresponding semiconductor substrate. Using semiconductor manufacturing methods to control device characteristics such as oxide thickness and channel ion implant dose, the turn-on voltage of FET diode 1505 may be adjusted to less than 0.5 volts. If the forward bias voltage drop of the FET diode 1505 is below 0.5 volts, a voltage greater than 4.5 volts will appear across the NV NT switch 1510. If the NV NT switch 1510 has a write 0 threshold voltage of, for example, 4.5 volts (or lower), the NV NT switch 1510 transitions from the ON state to the OFF state. Operate at write 0 During the 2000-3 period, current limiting is not required. Typical write 0 currents are less than 1uA to 50 uA.

In an exemplary write 1 operation, referring to circuit 1900 of FIG. 19, during the mode set time interval when write 1 operation waveform 2000-4, non-volatile nanotube diode 1500(NV NTFET-diode 1500) transitions from the OFF state to the ON state, as shown in FIG. 20 AB. Prior to the initial write 1 operation 2000-4, the write 1 operation 2000-4 waveform shows a voltage V_T2At a low voltage, e.g., zero volts. The NV NT switch 1510OFF resistance can range from greater than 100 megaohms to greater than 10 Gohms as shown in FIGS. 9A and 9B. Thus, the FET diode 1505 reverse bias resistance can be less than the OFF resistance of the NV NT switch 1510, and most of the applied write 1 voltage appears across the NV NT switch 1510 terminals 1530 and T2, as shown in FIG. 19. If the voltage V is_T1Transitioning beyond the write 1 threshold voltage of the NV NT switch 1510, an undesired write 1 cycle may begin. When the NV NT switch 1510 resistance drops, the reverse biased FET diode 1505 resistance dominates and write 1 operation completion can be avoided. However, to avoid a portion of the write 1 operation, V_T1Limited to, for example, 4 volts.

As shown in FIG. 20B, during a mode-setting time interval, exemplary write 1 operations 2000-4 operate to slave voltage V _T1Switching to a lower voltage, e.g. ground, begins. Then, the voltage V_T2Switching to the applied write 1 voltage of 4 volts. The rise time of the applied write 1 voltage may be relatively short, e.g., less than 1ns, or may be relatively long, e.g., over 100 us. The stimulating circuit 1910 applies the voltage V_T2Applied to terminal T2, and voltage V_T2The forward voltage minus the FET diode 1505 is applied to terminal 1530 of NV NT switch 1510. One terminal of FET diode 1505 in circuit 1900 is connected to the lowest voltage in the circuit, which in this case is ground. Assuming that the semiconductor substrate is also connected to ground, the threshold voltage of the FET diode 1505 does not increase the voltage applied to the FET diode 1505 relative to the corresponding semiconductor substrate. Using semiconductor manufacturing methods to control device characteristics such as oxide thickness and channel ion implant dose, the turn-on voltage of FET diode 1505 can be adjusted lowAt 0.5 volts. If the forward bias voltage drop of the FET diode 1505 is below 0.5 volts, a voltage greater than 4.5 volts will appear across the NVNT switch 1510. If the NV NT switch 1510 has a write 1 threshold voltage of, for example, 3.5 volts (or less), then the NV NT switch 1510 transitions from the OFF state to the ON state. A current limit may be applied during write 1 operations 2000-4. An example of a stimulation circuit including a current limiting device is described in U.S. patent application No. (to be announced) entitled "non-volatile resistive memory with scalable two-terminal nanotube switches," filed concurrently herewith. Write 1 currents are typically limited to less than 1uA to 50 uA.

FET diode 1505 is designed to limit current using an alternative to the stimulation circuit with current limiting. That is, NV NT diode 1500 has built-in current limitation determined by the design of subassembly FET diode 1505. Examples of FET diodes are shown in reference Baker, R. et al, "CMOSCircuit Design, Layout, and Simulation", IEEE Press, 1998, pp.165-171.

Fig. 21A illustrates an embodiment of a circuit 2100 in which a stimulus circuit 2110 applies a voltage V to one terminal of a resistor R. The other terminal of the resistor R is connected to a terminal T1 of the NV NT diode 1200. NV NT diode 1200 has terminal T2 connected to a common reference voltage, such as ground. NV NT diode 1200 is formed by a series diode and NV NT switch, as further described above with reference to fig. 12. The output of circuit 2100 is terminal T1 voltage V_OUT(V_{Output of})。

Fig. 21B shows an equivalent circuit 2110 embodiment of NV NT diode 1200 in the ON state. The equivalent circuit 2110 corresponds to the NV NT switch 600 in the ON state, as shown in fig. 6A. FIG. 21C shows I-V electrical characteristics 2120 of non-volatile nanotube diode 1200 in the ON state. The NV NT diode 1200 turn-on voltage is, for example, about 0.4 to 0.5 volts. After turn-ON, the slope of the I-V curve corresponds to the ON resistance of NV NT switch 1210, where R _ON-NT(R_{NT conduction}) Typically in the range of 10 kilo-ohms to 100 kilo-ohms, as shown in fig. 9A-9B.

FIG. 21D showsAn equivalent circuit 2130 embodiment of NV NT diode 1200 in the OFF state is shown. This equivalent circuit corresponds to NV NT switch 600' in the OFF state as shown in fig. 6B. FIG. 21E shows the I-V electrical characteristic 2140 of non-volatile nanotube diode 1200 in the OFF state. I-V characteristic 2140 corresponds to R_OFF-NT(R_{NT cut-off}) For some NVNT switches, it is greater than 100 megaohms, and for others it is greater than 10 Gohms, as shown in FIGS. 9A-9B.

In an exemplary read operation, referring to circuit 2100 of FIG. 21A, output voltage V if NV NT diode 1200 is in a high OFF resistance state_OUTWill be a high voltage; and outputs a voltage V if NV NT diode 1200 is in a low ON resistance state_OUTWill be low as shown in fig. 22. In this example, R is assumed to be much larger than the ON resistance of NV NT diode 1200 and much smaller than the OFF resistance of NV NT diode 1200. Since the ON resistance of the NV NT diode 1200 may be in the range of 10 kilo-ohms to 100 kilo-ohms and the OFF resistance of the NV NT diode 1200 may be greater than 100 mega-ohms to 10 giga-ohms and higher as further described above, R may be selected to be, for example, 1 mega-ohms.

In an exemplary read operation in which NVNT diode 1200 is in the OFF state, the OFF resistance of NVNT diode 1200 is much greater than the resistance R and when read voltage waveform 2200-1 of FIG. 22 is applied to circuit 2100, V is caused_OUTTransitioning from zero to 2 volts when input V transitions from 0 to 2 volts. This is because the resistance R of 1 megaohm is much less than the NV NT diode 1200 resistance of 100 megaohms to 10 Gohms or more.

In an exemplary read operation in which the NV NT diode 1200 is in the ON state, the ON resistance of the NV NT diode 1200 is much less than the resistance R and when the read voltage waveform 2200-2 shown in FIG. 22 is applied to the circuit 2100, V is caused_OUTTransitioning from zero to 0.4-0.5 volts when input V transitions from 0 to 2 volts. This is because the resistance R of 1 megaohm is greater than the ON resistance of NV NT diode 1200. V_OUTIs 0.4-0.5 volts because it is the forward voltage of NV NT diode 1200. As explained further above, the forward voltage occurs byBecause diode 1205 is a subcomponent of NV NT diode 1200, as further described above with reference to fig. 12 and 21A-21E.

FIG. 23A illustrates one embodiment of a circuit 2300 in which a stimulus circuit 2310 applies a voltage V to one terminal of a resistor R. The other terminal of the resistor R is connected to a terminal T1 of the NV NT diode 1500. Terminal T2 of NV NT diode 1500 is connected to a common reference voltage, such as ground. NV NT diode 1500 is formed by serially connecting a FET diode with the NV NT switch as further described above with reference to fig. 15. The output of circuit 2300 is terminal T1 voltage V _OUT。

In a read operation, referring to circuit 2300 of FIG. 23A, if NV NT diode 1500 (NVNTFET-diode 1500) is in a high OFF resistance state, then the output voltage V is_OUTWill be a high voltage; whereas if the NV NT diode 1500 is in a low ON resistance state, the output voltage V is_OUTWill be low as depicted in fig. 23B. In this example, R is assumed to be much greater than the ON resistance of the NV NT diode 1500 and much less than the OFF resistance of the NV NT diode 1500. Since the ON resistance of the NV NT diode 1500 may be in the range of 10 kilo-ohms to 100 kilo-ohms and the OFF resistance of the NV NT diode 1500 may be greater than 100 mega-ohms to 10 giga-ohms and higher as further described above, R may be selected to be, for example, 1 mega-ohms.

In an exemplary read operation in which NVNT diode 1500 is in the OFF state, the OFF resistance of NVNT diode 1500 is much greater than resistance R and when read voltage waveform 2300-1 of FIG. 23B is applied to circuit 2300, resulting in V_OUTTransitioning from zero to 2 volts when input V transitions from 0 to 2 volts. This is because a resistance R of 1 megaohm is much less than the NV NT diode 1500 resistance of 100 megaohms to 10 Gohms or more.

In an exemplary read operation in which the NV NT diode 1500 is in the ON state, the ON resistance of the NV NT diode 1500 is much less than the resistance R and when the read voltage waveform 2300-2 shown in FIG. 23B is applied to the circuit 2300, V is caused _OUTAt input V transitions from 0 to 2 volts from zero to 0.5 volts. This is because the resistance R of 1 megaohm is greater than that of the NV NT diode 1500And an ON resistance. V_OUTIs 0.5 volts because it is the forward voltage of the NV NT diode 1500. As explained further above, this forward voltage occurs because the FET diode 1505 is a subcomponent of the NV NT diode 1500.

Fig. 24 illustrates an embodiment of a circuit 2400 in which NV NT diode 1200 includes a non-volatile two-terminal switching device. Stimulus circuit 2410 applies a voltage V to one terminal of resistor R. The other terminal of the resistor R is connected to a terminal T1 of the NV NT diode 1200. Terminal T2 of NV NT diode 1200 is connected to one terminal of second resistor R'; the other terminal of its resistor R' is connected to a common reference voltage, e.g. ground. NV NT diode 1200 is formed by a series diode with an NV NT switch, as further described above with reference to fig. 12. The equivalent circuit and I-V characteristics of NV NT diode 1200 are shown in FIGS. 21A-21E. The output of circuit 2400 is terminal T2 voltage V'_OUT。

In an exemplary signaling operation, referring to circuit 2400 of FIG. 24, the output voltage V if NV NT diode 1200 is in a high OFF resistance state _OUTWill be a low voltage; and outputs a voltage V if NV NT diode 1200 is in a low ON resistance state_OUTWill be high as shown in fig. 25. In this example, R is assumed to be much larger than the ON resistance of NV NT diode 1200 and much smaller than the OFF resistance of NV NT diode 1200. Since the ON resistance of the NV NT diode 1200 may be in the range of 10 kilo-ohms to 100 kilo-ohms and the OFF resistance of the NV NT diode 1200 may be greater than 100 mega-ohms to 10 giga-ohms and higher as further described above, R may be selected to be, for example, 1 mega-ohms. In this example, resistor R' is assumed to be equal to resistor R.

In an exemplary signaling operation in which the NV NT diode 1200 is in the OFF state, the OFF resistance of the NV NT diode 1200 is much greater than the resistance R, and the signaling voltage waveform 2500-1 shown in FIG. 25 is applied to the circuit 2400, resulting in V_OUTAnd is maintained at about zero volts when input V transitions from 0 to 2 volts. This is because the resistance R of 1 Mohm is much less than the resistance of NV NT diode 1200 of 100 Mohms to 10 Gohms or more, and the voltage V will go outNow across NV NT diode 1200; the resistor R' is also 1 megaohm.

In an exemplary signaling operation in which the NVNT diode 1200 is in the ON state, the ON resistance of the NVNT diode 1200 is much less than the resistance R, and the read voltage waveform 2300-2 shown in FIG. 25 is applied to the circuit 2400, causing the voltage V to be divided between two equal 1 Mohm resistance values R and R'. V' _OUTTransitioning from zero to about 1 volt when input V transitions from 0 to 2 volts. This is because the 1 megaohm resistor R is greater than the ON resistance of the NV NT diode 1200 and the resistor R' is also equal to 1 megaohm, the signaling circuit 2400 with the NV NT diode 1200 in the ON state acts as a 2: 1 voltage divider.

Non-volatile memory using non-volatile nanotube diode (NVNT diode) devices as cells

Further described is a bit-selectable non-volatile nanotube-based memory array comprising a plurality of memory cells, each cell receiving a bit line and a word line. Each memory cell includes a select diode having anode and cathode terminals (nodes). Each cell further includes a two-terminal non-volatile nanotube switching device whose state represents the logical state of the cell. The combined diode and non-volatile nanotube switch is considered a non-volatile nanotube diode (NV NT diode), as further described above. Each memory cell is formed using a non-volatile nanotube diode. The state of the non-volatile nanotube switch-part of the non-volatile nanotube diode can be changed (cycled) between an ON resistance state and an OFF resistance state that differ by at least one order of magnitude, but typically by two to five orders of magnitude. There is no practical limit to the number of times the non-volatile nanotube switch can be cycled between the ON and OFF states.

Each memory cell may be formed using a non-volatile nanotube diode with an internal cathode-to-non-volatile nanotube switch connection, or a non-volatile nanotube diode with an internal anode-to-non-volatile nanotube switch connection, either with a horizontal orientation or a vertical (three-dimensional) orientation to maximize density. To further maximize density, the memory array is integrated over support circuitry and interconnects that are integrated in and on the underlying semiconductor substrate.

Non-volatile memory using NVNT diode device with cathode-to-NT switch connection

In some embodiments, the non-volatile nanotube diode (NV NT diode) is a two-terminal non-volatile device formed from two devices in series, i.e., a diode (e.g., a two-terminal schottky or PN diode) in series with a two-terminal non-volatile nanotube switch (NV NT switch). Each of the two series devices has a shared series electrical connection. The cathode terminal of the cathode-to-nanotube NV NT diode is electrically connected to one of the two non-volatile nanotube switch terminals. One available terminal of the NV NT diode two-terminal non-volatile device is connected to the anode of the schottky or PN diode, and the second available terminal is connected to the free terminal of the NVNT switch. An exemplary embodiment of a cathode-to-NT nonvolatile nanotube diode is shown in fig. 12. PIN diodes, FET diodes, and other types of diodes may also be used.

In some embodiments, high density 3D memory can be formed using one NV NT diode per cell. Memory embodiments using NV NT diodes with cathode-to-NT connections are schematically illustrated and memory operations are further described below. A 3-D cell structure is illustrated, including a method of fabrication. The cell with NV NT diodes formed with NV NT switches having both vertical and horizontal orientations is further described below.

Nonvolatile system and circuit having the same

One embodiment of a non-volatile memory 2600 is shown in fig. 26A. Memory 2600 includes a memory array 2610 having cells C00-C33 formed using non-volatile nanotube diodes, similar to non-volatile nanotube diode 1200(NV NT diode 1200), having diode-cathode-to-non-volatile nanotube switch terminal connections, such as shown in fig. 12. A diode similar to diode 1205 of NV NT diode 1200 is used as a cell select device while a non-volatile storage switch similar to NV NT switch 1210 of NV NT diode 1200 is used to store a non-volatile ON (low resistance) state or a non-volatile OFF (high resistance) state. The ON and OFF states represent non-volatile logic "1" or "0" states, respectively. Note that the assignment of logic "1" and logic "0" states relative to the low and high resistance states is arbitrary and may be reversed, for example.

Fig. 26A shows a non-volatile memory 2600 that includes a memory array 2610, the memory array 2610 having a matrix of NV NT diode cells C00-C33 similar to NV NT diode 1200, as further described above. The non-volatile cell C00 includes one NV NT diode, referred to as NVNT diode C00, like the other cells in the array, which is similar to NV NT diode 1200 as described further above. An anode of the NV NT diode C00 is connected to the bit line BL0, and the other terminal of the NV NT diode C00, i.e., the NV NT switch terminal, is connected to the word line WL 0.

In the embodiment shown, memory array 2610 is a 4-word line by 4-bit line 16-bit memory array including word lines WL0, WL1, WL2, and WL3 and bit lines BL0, BL1, BL2, and BL 3. The word line driver circuit 2630 is connected to word lines WL 0-WL 3 and is selected by a word decoder and WL (word line) select logic 2620, providing stimuli during write 0, write 1, and read operations. BL (bit line) driver and sense circuit 2640 provides data Multiplexers (MUXs), BL drivers, and sense amplifiers/latches, and is connected to bit lines BL0 through BL3 and selected by bit decoder and BL select logic 2650, providing stimuli during write 0, write 1, and read operations; that is, data is received by the memory array 2610 and transferred to the memory array 2610. Data in the memory array 2610 is stored in a non-volatile state so that power (voltage) supplied to the memory 2600 can be removed without losing data. The BL driver and readout circuitry 2640 is also connected to a read/write buffer 2660. The read/write buffer 2660 transfers data from the memory array 2610 to the read/write buffer 2660, which in turn transfers the data off-chip. The read/write buffer 2660 also receives off-chip data and transfers the data to the BL driver and sense circuitry 2640, which in turn transfers the data to the array 2610 of nonvolatile storage. The address buffer 2670 provides address location information.

For an exemplary write 0 operation along word line WL0, while erasing cells C00, C01, C02, and C03, the data stored in cells C00-C03 may optionally be read before erasing and storing the data in the corresponding sense amplifiers/latches. A write 0 operation along word line WL0 continues on bit lines BL0, BL1, BL2, and B3, transitioning from zero to 5 volts, with the bit line drivers controlled by corresponding BL drivers in BL driver and sense circuit 2640. Next, WL driver circuit 2630 drives word line WL0 from 5 volts to zero volts, thereby forward biasing NV NT diodes C00, C01, C02, and C03 constituting cells C00, C01, C02, and C03, respectively. The write 0 voltage is about 4.5 volts (erase voltage 5 volts minus NV NT diode turn-ON voltage below 0.5 volts, as shown in fig. 21), causing the NV NT diode in the ON state to transition from the ON state to the OFF state; the NV NT diode in the OFF state maintains the OFF state. Thus, NV NT diodes C00-C03 are all in the OFF state after a write 0 operation along word line WL 0. Unselected word lines WL1, WL2, and WL3 remain unselected and at 5 volts, and the non-volatile data stored in the corresponding cells remains unchanged.

Note that while fig. 26A shows a 4x4 memory array 2610, the array may be arbitrarily enlarged (e.g., forming an array of approximately 8 kB), and the associated electronic components may be modified as appropriate.

The exemplary write 0 and write 1 operations shown in FIG. 26B are described with respect to a write 0 (erase) voltage of 4.5 volts and a write 1 (write) voltage of 3.5 volts applied across the two terminals of the NV NT switch. However, as the NV NT switch channel length (below 20 nm) is further reduced, and/or improved nanotube element WNT and/or MWNT materials, and/or improved device structures, for such NV NT switches including a suspended region as described further above, the write 0 and write 1 voltages can be reduced to, for example, the 1 to 3 volt range, or other ranges.

In this example, an exemplary write operation immediately follows a write 0 operation, as further described above. In other words, the NV NT diodes C00-C03 of the respective corresponding cells C00-C03 begin a write operation in the OFF state. For an exemplary write 0 operation, e.g., to cell C00, where a logic 0 state is to be stored, NV NT diode C00 will be maintained in a logic 0 high resistance state. Thus, the bit line BL0 is held at zero volts by the corresponding BL driver and sense circuit 2640. Next, word line WL0 is switched from 4 volts to zero volts by a stimulus from WL driver 2630. The NV NT diode C00 maintains reverse bias during write 0 operation, while the cell C00 maintains an OFF (high resistance) logic 0 state.

In a write 1 operation, if NV NT diode C00 transitions from OFF (high resistance state) to ON (low resistance state) representing a logic 1, then bit line BL0 transitions from zero volts to 4 volts by stimulus provided from a corresponding BL driver in BL driver and sense circuit 2640. Word line WL04 volts then transitions to zero volts. A write 1 voltage of about 4 volts causes the voltage across the terminals of the corresponding NV NT switching sub-assembly of NV NT diode C00 to be 3.5 volts (4 volts minus the NV NT diode turn-ON voltage below 0.5 volts, as shown in fig. 21), causing NV NT diode C00 to transition from the OFF state to the ON state.

For an exemplary read operation from, for example, cells C00-C03, a bit line driver in BL driver and sense circuit 2640 precharges bit lines BL0-BL3 to a high voltage, for example, a read voltage of 2 volts. The read bitline voltage is selected to be lower than both the write 0 and write 1 voltages to ensure that the stored logic state (bit) is not disturbed (changed) during the read operation. Word line driver circuit 2630 drives word line WL0 from 2 volts to zero volts. If the NV NT diode C00 in cell C00 is in the OFF state (storing a logic 0), then the bit line BL0 is not discharged and is maintained at 2 volts. A corresponding sense amplifier/latch of one of BL drivers and sense circuits 2640 stores a logic 0. However, if the NV NT diode C00 in the cell C00 is in the ON state, the bit line BL0 is discharged. The corresponding sense amplifier/latch in BL driver and sense circuit 2640 detects this reduced voltage and latches a logic 1.

FIG. 26B illustrates an example of an operating waveform 2600' that may be applied to the embodiment of the memory 2600 shown in FIG. 26A during write 0, write 1, and read operations (or modes). Prior to the write 0 operation, a pre-write 0 read operation may optionally be performed to record the cell state along the selected word line (such as word line WL0) in the corresponding latch. Cells C00, C01, C02, and C03 receive the write 0 pulse (almost) simultaneously. At the beginning of a write 0 operation, the bit lines BL0, BL1, BL2, and BL3 transition from zero to 5 volts, as shown by waveform 2600' in FIG. 26B. Word line WL0 then transitions from 5 volts to zero volts, thereby forward biasing NV NT diodes C00-C03. Approximately 4.5 volts appears across each respective NV NT switch in the NV NT diode due to a forward bias voltage drop below 0.5 volts. If the write 0 voltage of the corresponding NV NT switch is 4.5 volts (or less), then the NV NT diode transitions from the ON (low resistance) state to the OFF (high resistance) state; the NV NT diode in the OFF state is maintained in the OFF state. Thus, NV NT diodes C00-C03 are all in the OFF state after a write 0 operation along word line WL 0. The unselected word lines WL1, WL2, and WL3 all remain unselected and at 5 volts.

In this example, the write operation immediately follows the write 0 operation, as further described above with reference to FIG. 26A. In other words, for cells along word line WL0, NV NT diode C00-C03 is in the OFF state at the beginning of a write operation. For the exemplary write operation illustrated by waveform 2600', NV NT diodes C00 and C03 will be maintained in the OFF state for a write 0 operation, while NV NT diodes C01 and C02 will transition from the OFF state to the ON state in a write 1 operation.

Thus, at the beginning of a write cycle, the bit lines BL0 and BL3 are maintained at zero volts. Word line WL0 then transitions from 4 volts to zero volts. The NV NT diodes C00 and C03 remain reverse biased during a write 0 operation, and thus the NV NT diodes remain in the OFF state storing a logic 0 state.

Continuing the exemplary write cycle, cells C01 and C02 transition from the OFF state to the ON state. Bit lines BL1 and BL2 transition from zero to 4 volts. Word line WL0 then transitions from 4 volts to zero volts. The NV NT diodes C01 and C02 are forward biased during the write 1 operation, and approximately 3.5 volts appears across the NV NT switch corresponding to the NV NT diodes C01 and C02. NV NT diodes C01 and C02 transition from the OFF state to the ON state, which stores a logic 1 state.

For an exemplary read operation, as shown by waveform 2600' in fig. 26B, bit lines BL0, BL1, BL2, and BL3 are precharged to, for example, 2 volts and allowed to float. Word line WL0 then transitions from 2 volts to zero volts. Word lines WL1, WL2, and WL3 are maintained at 2 volts. For cells C00 and C03, the bit line BL0 and BL3 voltages remain unchanged because NV NT diodes C00 and C03 are in the OFF or high resistance state and the bit line BL0 and BL3 capacitances cannot discharge to ground (zero volts). However, for cells C01 and C02, bit lines BL1 and BL2 discharge to zero volts because NV NT diodes C01 and C02 are in an ON or low resistance state and the bit line capacitance of BL1 and BL2 can discharge to ground (zero volts). For BL1 and BL2, the respective sense amplifier/latch typically detects a drop in bit line voltage in the range of 100mV to 200mV, although this value may vary depending on the particular characteristics (design) of the sense/latch circuit. Respective sense amplifiers/latches in BL driver and readout circuitry 2640 determine that the BL1 and BL2 read voltages have been changed and latch a logic 1 state corresponding to the ON state of NV NT diodes C01 and C02 that make up cells C01 and C02. Respective sense amplifiers/latches in the BL driver and sense circuit 2640 determine that BL0 and BL3 are unchanged and latch a logic 0 state corresponding to the OFF state of NV NT diodes C00 and C03 constituting cells C00 and C03.

Three-dimensional cell structure fabrication method overview of non-volatile memory cells using NV NT devices

Non-volatile nanotube diodes 1200 and 1300(NV NT diodes 1200, 1300), and non-volatile nanotube diodes formed with FET diodes, referred to as NV NT diodes 1400, 1500, 1600, and 1700 or also NV NT FET-diodes 1400, 1500, 1600, and 1700, may be used as cells and interconnected in an array to form a non-volatile nanotube random access memory system. Such arrays may also be used to fabricate non-volatile array-based logic, such as PLAs, FPGAs, PLDs, and other such logic devices.

Fig. 27A shows an overview of a method 2700 of manufacturing some embodiments of the present invention. Although method 2700 is further described below with respect to nonvolatile nanotube diodes 1200 and 1300, method 2700 is sufficient to encompass the fabrication of many nonvolatile nanotube diodes as further described above. The methods 2700 may also be used to form logic embodiments based on NV NT diodes arranged as logic arrays, such as NAND and NOR arrays with logic support circuitry (rather than memory support circuitry) as used in PLAs, FPGAs, and PLDs.

Generally, the method 2710 fabricates support circuitry and interconnects in and on a semiconductor substrate. This includes NFET and PFET devices having drains, sources, and gates interconnected to form memory support circuits such as circuits 2620, 2630, 2640, 2650, 2660, and 2670 shown in fig. 26A. Such structures and circuits may be formed using known techniques, which are not described herein. The method 2710 can use known fabrication methods to form a base layer in and on which the nonvolatile nanotube diode control devices and circuits are fabricated.

Method 2720 manufactures intermediate structures including a planarized insulator and an interconnect and a non-volatile nanotube array structure on a surface of the planarized insulator. The interconnect means includes vertically oriented fill contacts, or studs, for interconnecting memory support circuitry in and over the semiconductor substrate under the planarized insulator, and the array of non-volatile nanotube diodes above and over the surface of the planarized insulator.

The word lines and bit lines may be used in a 3D array structure, as described further below, to interconnect the 3-D cells and form a 3-D memory, and may be substantially perpendicular to the X-Y plane, which is substantially parallel to the underlying memory support circuitry. In the figures, which illustrate the 3D array structure and the 3D array structure fabrication method, described further below, the word line direction is arbitrarily assigned along the X-axis, while the bit line direction is arbitrarily assigned along the Y-axis. In a "vertical cell" embodiment, such as described in more detail below, the Z-axis, which is substantially perpendicular to the X-Y plane, shows the vertical direction of the 3D cell orientation.

Method 2750 completes the fabrication of the semiconductor chip using industry standard fabrication techniques by adding additional wiring layers as needed, passivating the chip, and adding package interconnects.

Using diodes with vertical orientation and having cathode-to-NT switch connectionVertically orientedThree-dimensional cell structure of non-volatile cell of NV NT device of NT switch

Once the support circuitry and interconnects are defined in and on the semiconductor substrate, the method may be used to fabricate non-volatile nanotube diode arrays, such as shown in cross-section 2800 above the support circuitry and interconnect regions shown in fig. 28A. FIG. 28A shows a cross-section including cells C00 and C01 in one of several possible embodiments.

The method 2710 described further above may be used to define the support circuitry and interconnect 2801.

Next, method 2730 shown in fig. 27B deposits and planarizes insulator 2803. An interconnect means (not shown in cross-section 2800, but further shown below with reference to cross-section 2800 "in fig. 28C) through the planar insulator 2803 may be used to connect the metal array lines in the 3-D array to the respective supporting circuitry and interconnects 2801. As an example, bit line drivers in the BL driver and readout circuitry 2640 may be connected to the bit lines BL0 in the array 2610 of the memory 2600 shown in fig. 26A. At this point in the fabrication process, method 2740 may be used to form a memory array on the insulator 2803 surface, interconnecting with memory array support structure 2805-1 as shown in fig. 28A.

Method 2740 of fig. 27B deposits and planarizes metal, polysilicon, insulator, and nanotube elements to form non-volatile nanotube diodes, which in this example comprise polyA vertically oriented diode and a vertically oriented series pair of nonvolatile nanotube switches. To eliminate the accumulation of single layer alignment tolerances that would substantially increase the cell area, the single cell outer dimension is formed in a single etching step, each cell having a single NV NT diode defined by a single trench etching step after the layers (except the WL0 layer) have been deposited and planarized. The single cell size in the X direction is 1F (1 smallest feature) as shown in fig. 28A, while in the Y direction (not shown) perpendicular to the X direction is also 1F with a period of 2F in the X and Y directions. Thus, each cell occupies an area of about 4F². The placement of the vertically oriented (Z-direction) NV NT switch elements (nanotube elements) at X-direction R, in this case about equal to F/2, is parallel to the trench-defined outer dimension, with the separation distance of the NV NT switches (nanotube elements) controlled by self-aligned means, as further described below with reference to fig. 34A-34 FF. The configuration of the vertically-oriented NV NT switching elements (nanotube elements) in the Y-direction is generally not critical and generally does not require self-aligned devices.

Placement R of the vertically oriented nanotube element at about F/2 employs a nanotube film thickness much less than the cell size F. For a 45nm technology node, for example, the nanotube element has a thickness in the range of, for example, 0.5nm to 10 nm. The nanotube element can be formed using a single nanotube layer, or can be formed using multiple layers. Such nanotube element layers can be deposited, for example, using spin-coating techniques or spray-coating techniques, as described more fully in the incorporated patent references. 28A and 28B the 3-D memory array structure embodiment and the corresponding exemplary method of fabrication illustrated with reference to FIGS. 34A-34FF show a 3D array structure assuming that the vertically oriented nanotube elements are disposed at R, which is approximately equal to F/2. The device includes a bottom contact, a sidewall contact, and an electrically separated vertically oriented nanotube device channel length L_SW-CHAs further described below with reference to the embodiments of fig. 28A and 28B and corresponding exemplary methods of manufacturing fig. 34A-34 FF.

In one possible variation, for cells having a dimension F, placed at F/2, the thickness of the vertically oriented nanotube element may be too thick. For example, for a cell size F of 35nm, and a nanotube film thickness of 10-20nm, vertically oriented nanotube elements may be placed, for example, at F/3 to accommodate the nanotube elements and protective insulator, as further described below with reference to FIG. 39. Vertically oriented nanotube elements with lower, sidewall, and upper contacts can still be used.

In another possible variation, the nanotube element thickness may be equal to the overall cell size F. For example, for a cell size F of 35nm, a nanotube film thickness of 35nm may be used. Alternatively, for example, for a cell size F of 22nm, a nanotube film thickness of 22nm may be used. In this case, the nanotube element contact structure can be modified so that the sidewall contacts are eliminated and replaced by only the lower and upper contacts, as shown in FIG. 40 below. The thickness of the nanotube element need not be related in any way to the lateral cell dimension F.

In addition to defining the overall cell size simultaneously without multiple alignment steps, the minimized memory cell size (area) requires self-aligned placement of device elements within the sub-minimum size memory cell boundaries (in this case, the cell boundaries defined by the isolation trenches) that are used. Cross-sections 2800 and 2800' of fig. 28A and 28B, respectively, illustrate exemplary non-volatile nanotube switches, which are similar to cross-section 750 of fig. 7B, except that nanotube channel element locations R are self-aligned to isolation trenches that determine the overall cell size. In addition, the lower, sidewall, and upper contacts are self-aligned and fit within the isolation trench boundaries. Within the defined boundaries, self-aligned placement of device elements may be achieved by adjusting sidewall spacer methods, such as disclosed in U.S. patent 4,256,514, which is incorporated herein by reference in its entirety.

In some embodiments, the method fills the trench with an insulator and then planarizes the surface. The method then deposits and patterns word lines on the planarized surface.

Fabrication of the vertically oriented 3D cell in some embodiments proceeds as follows. Referring to fig. 28A, a method deposits a bit line wiring layer on insulator 2803, having a thickness of 50 to 500nm, for example as further described below with reference to fig. 34A-34 FF. The method etches the bit line wiring layer and defines the individual bit lines, such as bit lines 2810-1(BL0) and 2810-2(BL 1). Bit lines such as BL0 and BL1 are used as array wiring conductors and may also be used as anode terminals of schottky diodes. Alternatively, more optimized Schottky diode junctions 2818-1 and 2818-2 may be formed using metal or silicide contacts 2815-1 and 2815-2 to contact the N-polysilicon regions 2820-1 and 2820-2 while also forming ohmic contacts to bit lines 2810-1 and 2810-2, as further described below with reference to FIGS. 34A-34 FF. N-poly regions 2820-1 and 2820-2 may be doped to a doping range of, for example, 10¹⁴To 10¹⁷Dopant atom/cm³And may have a thickness in the range of, for example, 20nm to 400 nm. Contacts 2815-1 and 2815-2 may be in a thickness range of, for example, 10nm to 500 nm.

In some embodiments, by controlling the material properties of the polysilicon, such as depositing and patterning the polysilicon to form polysilicon regions 2820-1 and 2820-2, the electrical characteristics of the schottky (and PN) diode may be improved (e.g., low leakage). The polysilicon region may have a relatively large or relatively small grain boundary size, as determined by the method used in the semiconductor region. SOI deposition methods used in the semiconductor industry may be used which result in the polysilicon region being monocrystalline (no longer polycrystalline) or nearly monocrystalline to promote further electrical characteristics such as low diode leakage current.

Examples of contact and conductor materials are elemental metals such as Al, Au, W, Cu, Mo, Pd, Ni, Ru, Ti, Cr, Ag, In, Ir, Pb, Sn, and metal alloys such as TiAu, TiCu, TiPd, Pbin, and TiW, other suitable conductors, or conductive nitrides, oxides, or silicides such as RuN, RuO, TiN, TaN, CoSi_xAnd TiSi_x. The insulator can be SiO₂、SiN_x、Al₂O₃BeO, polyimide, Mylar (polyester resin), or other suitable insulating material.

In some cases, the conductive material is Al, Au, or the like,W, Cu, Mo, Ti, and other conductors may be used as both contacts and conductor materials as well as the anode of the schottky diode, in which case separate optional schottky anode contacts, such as 2815-1 and 2815-2, are not needed and may be omitted. However, in other cases, it is advantageous to optimize the anode material for low forward voltage drop and low diode leakage. The Schottky diode anode material may include Al, Ag, Au, Ca, Co, Cr, Cu, Fe, Ir, Mg, Mo, Na, Ni, Os, Pb, Pd, Pt, Rb, Ru, Ti, W, Zn, and other elemental metals. In addition, silicides such as CoSi may be used ₂、MoSi₂、Pd₂Si、PtSi、RbSi₂、TiSi₂、WSi₂And ZrSi₂. Schottky diodes formed using such metals and silicides are described in NG, k.k. "compact guiding Semiconductor Devices", Second Edition, John Wiley&Sons, 2002m pp.31-41, the entire contents of which are incorporated herein by reference.

Next, when the Schottky diode select device has been completed, N + polysilicon regions 2825-1 and 2825-2 are formed to contact N polysilicon regions 2820-1 and 2820-2, respectively, and contact regions are also formed for ohmic contact to contacts 2830-1 and 2830-2. The N + polysilicon is typically doped with arsenic or phosphorous to, for example, 10²⁰Dopant atom/cm³And has a thickness of, for example, 20 to 400 nm.

The method then forms a non-volatile nanotube switch in each cell, with one terminal shared with, for example, cathode contacts 2830-1 and 2830-2. To increase the density of cells C00 and C01, the nanotube element shown in FIG. 28A can be at least partially vertically oriented, as shown in FIG. 7. Vertically oriented nanotube switches are described in more detail in the incorporated patent references. The vertically oriented sidewalls, including the insulation and contact regions, are formed prior to forming vertically oriented nanotube elements 2845-1 and 2845-2. The vertically oriented sidewalls are formed at location R, which is approximately equal to F/2, using a self-aligned process. However, similar self-aligned fabrication methods can be used to place vertically oriented sidewalls in any location, such as F/3, F/4, or any other desired location.

Methods of forming nanotube elements 2845-1 and 2845-2 can include, first, forming insulators 2835-1 and 2835-2 and sidewall contacts 2840-1 and 2840-2 in contact with respective insulators 2835-1 and 2835-2, forming vertical sidewalls through both metal and insulator regions by directionally etching openings. The thickness of insulators 2835-1 and 2835-2 determines the nanotube element channel length, as shown in FIG. 28A. Insulators 2835-1 and 2835-2 may range from less than 5nm to greater than 250 nm. The vertical sidewalls of insulators 2835-1 and 2835-2 and sidewall contacts 2840-1 and 2840-2 are self-aligned with respect to the trench sidewalls, which are later etched in a process using a fabrication method as described further below with reference to fig. 34A-34 FF.

Next, the method forms conformal nanotube elements 2845-1 and 2845-2, as described in more detail in the incorporated patent references.

The method then forms protective conformal insulators 2850-1 and 2850-2 on the surfaces of conformal nanotube elements 2845-1 and 2845-2, respectively.

Next, the method forms an opening having an X dimension of about F and the method fills the opening with a conductive material that forms upper layer contacts 2865-1 and 2865-2 and contacts sidewall contacts 2840-1 and 2840-2, respectively. The methods used to form upper level contacts 2865-1 and 2865-2 may be similar to the methods disclosed in U.S. Pat. No. 4,944,836 and described further below with reference to FIGS. 34A-34 FF.

Contacts 2865-1 and 2865-2 provide conductive paths between sidewall contacts 2840-1 and 2840-2, respectively, and word line 2871(WL0), which are formed after forming cells C00 and C01 are completed.

Next, before forming the word line 2871(WL0), the dimensions of cell C00 and cell C01 may be defined by a trench etch that goes through all layers in the cell structure 2800 down to the top surface of the insulator 2803.

Next, the method fills the trench area with insulator 2860 and planarizes the structure before depositing word line 2871(WL 0).

The method then deposits and patterns word line 2871(WL 0).

Nonvolatile nanotube diode 2880, which schematically overlaps cross-section 2800 of fig. 28A, is an equivalent circuit corresponding to nonvolatile nanotube diode 1200 of fig. 12 (i.e., one of each of cells C00 and C01). The cells C00 and C01 shown in the cross-sectional view 2800 shown in fig. 28A correspond to the respective cells C00 and C01 of the memory array 2610 schematically shown in fig. 26A, and the bit lines BL0 and BL1 and the word line WL0 correspond to the array lines schematically shown in the memory array 2610.

The cross-sectional view 2800 ' of FIG. 28B shows an embodiment of memory array cells C00 ' and C01 ', which are similar to memory array cells C00 and C01 of FIG. 28A, except that NV NT diodes C00 ' and NV NT diodes C01 ' formed in respective cells C00 ' and C01 ' include PN diodes having PN diode junctions 2819-1 and 2819-2, rather than Schottky diodes having Schottky diode junctions 2818-1 and 2818-2.

P-poly regions 2817-1 and 2817-2 form a diode-anode and N-poly regions 2820-1 'and 2820-2' form a diode cathode, which together (in combination) form a PN diode with PN diode junctions 2819-1 and 2819-2. The P-poly regions 2817-1 and 2817-2 also form ohmic or near-ohmic contacts with bit lines 2810-1 '(BL 0) and 2810-2' (BL1), respectively. N polysilicon regions 2820-1 'and 2820-2' also form ohmic contact regions with N + polysilicon regions 2825-1 and 2825-2. The other structures of cells C00 'and C01' are similar to those illustrated and described with respect to cells C00 and C01, respectively.

The memory array support structure 2805-2 shown in figure 28B includes support circuitry and interconnects 2801 'and a planarized insulator 2803' which is similar to the memory support structure 2801 shown in figure 28A except that adjustments may be required to accommodate memory cells having PN diode select devices rather than schottky diode select devices.

Using diodes with vertical orientation and having cathode-to-NT switch connectionHorizontal orientationThree-dimensional cell structure of non-volatile cell of NV NT device of NT switch

Method 2720 of fig. 27B may be used to deposit and planarize metal, polysilicon, insulator, and nanotube elements to form a nonvolatile nanotube diode having a plurality of vertically oriented diodes and horizontally oriented serial pairs of nonvolatile nanotube switches, as shown in cross-section 2800 "of fig. 28C.

Cell C00 "in the embodiment of fig. 28C is formed over memory array support structure 2805-3, which includes support circuitry and interconnects 2801" and planarization insulator 2803 ". The support circuitry and interconnect 2801 "is similar to the support circuitry and interconnect 2801, while the planarized insulator 2803" is similar to the planarized insulator 2803 of fig. 28A, except that adjustments are needed to accommodate the differences in cell C00 "relative to cell C00. In addition, cross-sectional view 2800 "includes via fill contacts (studs) 2807 that interconnect bit lines 2810" (BL0) with support circuitry and interconnect 2801 "circuitry, as shown in cross-sectional view 2800" of fig. 28C. For example, via fill contacts (studs) 2807 may connect the bit line BL0 and BL driver and sense circuitry 2640, shown schematically in fig. 26A.

To eliminate the accumulation of single layer alignment tolerances that would substantially increase the cell area, the single cell outer dimension is formed in a single etch step, each cell having a single NV NT diode defined by a single trench etch step after the layers (except the WL0 layer) have been deposited and planarized. The single cell size is 2-3F in the X direction (1F being the smallest feature), as shown in fig. 28C, because the horizontal non-volatile nanotube switch orientation generally requires a larger area than a non-volatile nanotube switch with a vertical orientation, such as shown in fig. 28A and 28B. A minimum Y-direction (perpendicular to the X-direction, not shown), i.e. a Y-direction dimension 1F, is possible. Using a cell periodicity of 3-4F in the X direction and a periodicity of 2F in the Y direction, each cell occupies a range of 6-8F in some embodiments ²Or a larger area. In filling trenches with an insulatorThereafter, planarization follows, with word lines such as word line 2875 being deposited and patterned.

Cross-sectional view 2800 "shown in fig. 28C illustrates an embodiment of a memory array cell C00" that is similar to memory array cell embodiment C00 shown in fig. 28A, except that NVNT diode C00 "comprising cell C00" includes a horizontally oriented non-volatile nanotube switch instead of the vertically oriented non-volatile nanotube switch shown in cross-sectional view 2800 in fig. 28A.

In fig. 28C, cross-section 2800 "cell C00" selects a schottky diode including schottky diode junction 2821, which corresponds to schottky diode junction 2818-1 in cross-section 2800 of fig. 28A. Schottky diode junction 2821 is formed by forming the anode with bit line 2810 "(BL 0) and the cathode with N polysilicon 2820". Optional additional metal contacts, such as metal contact 2815-1, are not shown in cross-sectional view 2800 ", but may be added. N + poly 2825 "is added to contact N poly 2820" and corresponds to N + poly 2825-1 of FIG. 28A.

The method may be used to fabricate a non-volatile nanotube switch with a horizontal (rather than vertical) orientation and have one side of the non-volatile nanotube switch in electrical (non-physical) contact with the N + polysilicon region 2825 "and the other side of the non-volatile nanotube switch in electrical (non-physical) contact with the word line 2875.

First, the method deposits insulator 2830 "and contact 2835". The method then forms openings through both contact 2835 "and insulator 2830" to expose the surface of N + polysilicon region 2825 ".

The method then deposits a conformal insulating layer on the top, sidewalls, and bottom of the lower layer opening. Then, the method directionally etches the conformal insulating layer, thereby forming sidewall spacers 2840, the thickness of the sidewall spacers 2840 determining the channel length L of the non-volatile nanotube switch in cell C00 ″_SW-CH. Cross-sectional view 2800 "shows two L' s_SW-CHAnd (4) a region. The two L_SW-CHThe regions are electrically parallel (not shown by cross-sectional view 2800 ").Exemplary fabrication methods are further described below with reference to fig. 35A-S.

The method then fills the opening with contact metal, followed by planarization to form contact 2845, which forms an ohmic contact to N + polysilicon region 2825 "and is isolated from the contact 2835" region by sidewall spacer 2840.

Next, the method deposits nanotube element 2850 on and in physical and electrical contact with contact 2845, spacer 2840, and sidewall contact 2835 ". The spacing between contact 2845 and contact 2835 "due to the thickness of sidewall spacer 2840 determines the non-volatile nanotube switch channel length L _SW-CH. Nanotube element 2850 may optionally be patterned as shown in fig. 28C, or may be patterned as part of a post trench etch that determines the size of the final cell C00 ". Exemplary fabrication methods are further described below with reference to fig. 35A-35S.

Next, the method deposits insulator 2855.

Next, the method etches the insulator 2855, forming an opening. The method then etches (removes) the exposed portions of nanotube element 2850, for example, as described in more detail in the incorporated patent references.

The opening is then filled with contact metal 2865. The method forms contact metal 2865 by metal deposition followed by planarization. Contact 2865 physically and electrically contacts both contact 2835 "and nanotube element 2850.

Next, the method etches a trench through all layers, stopping on the surface of the insulator 2803 ", thereby defining the dimensions of cell C00".

Next, the method deposits and planarizes an insulating layer, forming insulator 2874.

The process then deposits and patterns the word line 2875(WL0), completing cell C00 ". Exemplary fabrication methods are further described below with reference to fig. 35A-35S.

Nonvolatile nanotube diode embodiment 2885 in FIG. 28C is an equivalent circuit, which corresponds to nonvolatile nanotube diode 1200 in cell C00 "of FIG. 12. The cells C00 ″ correspond to the respective cells C00, which are schematically shown in the memory array 2610 embodiment shown in fig. 26A, and the bit line BL0 and the word line WL0 correspond to the array lines schematically shown in the memory array 2610.

Non-volatile memory using NVNT diode device with anode-to-NT switch connection

In some embodiments, the non-volatile nanotube diode (NV NT diode) is a two-terminal non-volatile device formed from two devices in series, i.e., a diode (e.g., a two-terminal schottky or PN diode) in series with a two-terminal non-volatile nanotube switch (NV NT switch). Each of the two series devices has a shared series electrical connection. The anode-to-nanotube NV NT diode electrically connects the anode terminal to one of the two non-volatile nanotube switch terminals. One available terminal of the NV NT diode two-terminal non-volatile device is connected to the cathode of the schottky or PN diode, and the second available terminal is connected to the free terminal of the NVNT switch. An exemplary anode-to-NT nonvolatile nanotube diode is shown in fig. 13. PIN diodes, FET diodes, and other types of diodes may also be used.

In some embodiments, a high density 3D memory may be formed using one NV NT diode per cell. Memory embodiments using NV NT diodes with anode-to-NT connections are schematically illustrated, and memory operation is further described below. Exemplary 3-D cell structures, including fabrication methods, are illustrated. An exemplary cell having an NV NT diode formed with an NV NT switch and a vertically oriented switch is further described below.

Nonvolatile system and circuit having the same

One embodiment of a non-volatile memory 2900 is shown in FIG. 29A. The memory 2900 includes a memory array 2910 having cells C00 through C33, the cells C00 through C33 being formed using a non-volatile nanotube diode similar to the non-volatile nanotube diode 1300(NV NT diode 1300) formed using diode-anode-to-non-volatile nanotube switch terminal connections such as that shown in fig. 13. A diode similar to the diode 1305 of the NV NT diode 1300 is used as the cell select device, while a nonvolatile storage switch similar to the NV NT switch 1310 of the NV NT diode 1300 is used to store a nonvolatile ON (low resistance) state or a nonvolatile OFF (high resistance) state. The ON and OFF states represent non-volatile logic "1" or "0" states, respectively. Note that the assignment of logic "1" and logic "0" states relative to the low and high resistance states is arbitrary and may be reversed, for example.

The non-volatile memory 2900 shown in FIG. 29A includes a memory array 2910 having a matrix of NV NT diode cells C00 through C33 similar to the NV NT diode 1300 described further above. The non-volatile cell C00, like the other cells in the array, includes one NV NT diode, referred to as NV NT diode C00, which is similar to NV NT diode 1300 as described further above. The cathode of the NV NT diode C00 is connected to the word line WL0, and the other terminal of the NV NT diode C00, the NV NT switch terminal, is connected to the bit line BL 0.

In the embodiment shown, memory array 2910 is a 4-word line by 4-bit line 16-bit memory array including word lines WL0, WL1, WL2, and WL3 and bit lines BL0, BL1, BL2, and BL 3. Word line driver circuit 2930 is connected to word lines WL 0-WL 3 and is selected by word decoder and WL select logic 2920, word line driver circuit 2930 providing stimuli during write 0, write 1, and read operations. BL driver and sense circuit 2940 provides data Multiplexers (MUXs), BL drivers, and sense amplifiers/latches, which are connected to bit lines BL0 through BL3 and selected by a bit decoder, and BL select logic 2950 provides stimuli during write 0, write 1, and read operations; that is, data is received by the memory array 2910 and data is transferred to the memory array 2910. Data in the memory array 2910 is stored in a non-volatile state so that power (voltage) supplied to the memory 2900 can be removed without losing data. The BL driver and readout circuitry 2940 is also connected to a read/write buffer 2960. The read/write buffer 2960 transfers data through the memory array 2910 to the read/write buffer 2960, which in turn transfers the data off-chip. The read/write buffer 2960 also accepts data from off-chip and transfers this data to the BL driver and sense circuitry 2940, which in turn transfers the data to the nonvolatile storage array 2910. Address buffer 2970 provides address location information.

Note that while fig. 29A illustrates a 4x4 memory array 2910, the array may be arbitrarily enlarged (e.g., forming an approximately 8kB array), and the associated electronic elements may be modified as appropriate.

For an exemplary write 0 operation along word line WL0, while erasing cells C00, C01, C02, and C03, the data stored in cells C00-C03 may optionally be read before erasing and data storage in the respective sense amplifiers/latches. The write 0 operation continues along word line WL0 to bit lines BL0, BL1, BL2, and B3, transitioning from zero to 5 volts, the bit line drivers controlled by the corresponding BL drivers in BL driver and sense circuit 2940. Next, WL driver circuit 2930 drives word line WL0 from 5 volts to zero volts, thereby forward biasing NV NT diodes C00, C01, C02, and C03 that constitute cells C00, C01, C02, and C03, respectively. The write 0 voltage is about 4.5 volts (write 0 voltage 5 volts minus the NV NT diode turn-ON voltage below 0.5 volts) causing the NV NT diode in the ON state to transition from the ON state to the OFF state; the NV NT diode in the OFF state is maintained in the OFF state. Thus, NV NT diodes C00-C03 are all in the OFF state after a write 0 operation along word line WL 0. Unselected word lines WL1, WL2, and WL3 are all left unselected and at 5 volts, and the non-volatile data stored in the respective cells remains unchanged.

In this example, the write operation immediately follows the write 0 operation, as further described above. In other words, the NV NT diodes C00-C03 of the corresponding cells C00-C03 begin a write operation in the OFF state. For an exemplary write 0 operation to cell C00, for example, where a logic 0 state is to be stored, NV NT diode C00 will be maintained in a logic 0 high resistance state. Thus, bit line BL0 is held at zero volts by the corresponding BL driver and sense circuit 2940. Next, word line WL0 is transitioned from 4 volts to zero volts by a stimulus from WL driver 2930. The NV NT diode C00 maintains reverse bias during write 0 operation and the cell C00 maintains an OFF (high resistance) logic 0 state.

In a write 1 operation, if NV NT diode C00 transitions from OFF (high resistance state) to ON (low resistance state) representing a logic 1, then bit line BL0 transitions from zero volts to 4 volts by a stimulus provided from a corresponding BL driver in BL driver and sense circuit 2940. Word line WL0 then transitions from 4 volts to zero volts. A write 1 voltage of about 4 volts causes a 3.5 volt voltage across the terminals of the corresponding NV NT switch sub-element of NV NT diode C00 (4 volts minus the NV NT diode turn-ON voltage below 0.5 volts), causing NV NT diode C00 to transition from the OFF state to the ON state.

For an exemplary read operation from, for example, cells C00-C03, a bit line driver in BL driver and sense circuit 2940 precharges the bit lines BL0-BL3 to a high voltage, for example, a read voltage of 2 volts. The read bitline voltage is selected to be lower than both the write 0 and write 1 voltages to ensure that the stored logic state (bit) is not disturbed (changed) during the read operation. Word line driver circuit 2930 drives word line WL0 from 2 volts to zero volts. If the NV NT diode C00 in cell C00 is in the OFF state (storing a logic 0), then the bit line BL0 is not discharged and is maintained at 2 volts. The corresponding sense amplifier/latch in BL driver and sense circuit 2940 stores a logic 0. However, if the NV NT diode C00 in the cell C00 is in the ON state, the bit line BL0 is discharged. The corresponding sense amplifier/latch in BL driver and sense circuit 2940 detects the reduced voltage and latches a logic 1.

Fig. 29B illustrates an example of an operating waveform 2900' that may be applied to the embodiment of the memory 2900 shown in fig. 29A during write 0, write 1, and read operations (or modes). Prior to the write 0 operation, a pre-write 0 read operation may optionally be performed to record the cell state along the selected wordline (e.g., wordline WL0) in the corresponding latch. Cells C00, C01, C02, and C03 receive the write 0 pulse (almost) simultaneously. At the beginning of a write 0 operation, the bit lines BL0, BL1, BL2, and BL3 transition from zero to 5 volts, as shown by waveform 2900' in FIG. 29B. Word line WL0 then transitions from 5 volts to zero volts, thereby forward-biasing NV NT diodes C00-C03. Approximately 4.5 volts appears across each respective NV NT switch in the NV NT diode due to the less than 0.5 volt forward-bias voltage drop. If the write 0 voltage of the corresponding NV NT switch is 4.5 volts (or less), the NV NT diode transitions from an ON (low resistance) state to an OFF (high resistance) state; the NV NT diode in the OFF state is maintained in the OFF state. Thus, NV NT diodes C00-C03 are all in the OFF state after a write 0 operation along word line WL 0. The unselected word lines WL1, WL2, and WL3 are all left unselected and at 5 volts.

In this example, the write operation immediately follows the write 0 operation, as described further above with reference to FIG. 29A. In other words, for cells along word line WL0, NV NT diode C00-C03 is in the OFF state at the beginning of a write operation. For the exemplary write operation illustrated by waveform 2900', the NV NT diodes C00 and C03 will remain in the OFF state for a write 0 operation, and the NV NT diodes C01 and C02 will transition from the OFF state to the ON state in a write 1 operation.

Thus, at the beginning of a write (programming) cycle, the bit lines BL0 and BL3 are maintained at zero volts. Word line WL0 then transitions from 4 volts to zero volts. The NV NT diodes C00 and C03 remain reverse biased during a write 0 operation, and thus the NV NT diodes remain in the OFF state storing a logic 0 state.

Continuing the exemplary write cycle, cells C01 and C02 transition from the OFF state to the ON state. Bit lines BL1 and BL2 transition from zero to 4 volts. Word line WL0 then transitions from 4 volts to zero volts. The NV NT diodes C01 and C02 are forward biased during the write 1 operation, and approximately 3.5 volts appears across the NV NT switches corresponding to the NV NT diodes C01 and C02. NV NT diodes C01 and C02 transition from the OFF state to the ON state, which stores a logic 1 state.

For an exemplary read operation as illustrated by waveform 2900' in FIG. 29B, the bit lines BL0, BL1, BL2, and BL3 are precharged to, for example, 2 volts and allowed to float. Word line WL0 then transitions from 2 volts to zero volts. Word lines WL1, WL2, and WL3 are maintained at 2 volts. For cells C00 and C03, the bit line BL0 and BL3 voltages remain unchanged because NV NT diodes C00 and C03 are in the OFF or high resistance state and the bit line BL0 and BL3 capacitances cannot discharge to ground (zero volts). However, for cells C01 and C02, bit lines BL1 and BL2 discharge to zero volts because NV NT diodes C01 and C02 are in an ON or low resistance state and the bit line capacitance of BL1 and BL2 can discharge to ground (zero volts). For BL1 and BL2, the respective sense amplifiers/latches typically detect a drop in bit line voltage in the range of 100mV to 200mV, although this value may vary depending on the particular characteristics (design) of the sense/latch circuitry. Respective sense amplifiers/latches in the driver and sense circuit 2940 determine that the BL1 and BL2 read voltages have been changed and latch a logic 1 state corresponding to the ON state of NV NT diodes C01 and C02 that make up cells C01 and C02. The respective sense amplifiers/latches in the driver and sense circuit 2940 determine that BL0 and BL3 are unchanged and latch a logic 0 state corresponding to the OFF state of NV NT diodes C00 and C03 constituting cells C00 and C03.

Using diodes with vertical orientation and having anode-to-NT switch connectionsVertical orientationThree-dimensional cell structure of non-volatile cell of NV NT device of NT switch

Fig. 30A illustrates an exemplary method 3000 of fabricating an embodiment of a NV NT diode with a vertically oriented NT switch. Although method 3000 is further described below with respect to non-volatile nanotube diode 1300 as shown in fig. 13, method 3000 is sufficient to cover the fabrication of many of the non-volatile nanotube diodes described further above. It should be appreciated that although method 3000 is described below in the context of a memory embodiment, method 3000 may also be used to form a logic embodiment based on NV NT diodes arranged as a logic array such as NAND and NOR arrays with logic support circuits used in PLAs, FPGAs, and PLDs.

In general, method 3010 fabricates support circuits and interconnects in and on a semiconductor substrate. This includes NFET and PFET devices with drains, sources, and gates interconnected to form memory support circuits such as circuits 2920, 2930, 2940, 2950, 2960, and 2970 shown in FIG. 29A. Such structures and circuits may be formed using known techniques, which are not described herein. Method 3010 may be used to form a substrate in and on which nonvolatile nanotube diode control devices and circuits are fabricated using known fabrication methods.

Method 3020 produces an intermediate structure comprising a planarized insulator, an interconnect device on the surface of the planarized insulator, and a non-volatile nanotube array structure. The interconnect means includes vertically oriented fill contacts, or studs, for interconnecting memory support circuitry in and on the semiconductor substrate below the planarized insulator with the array of non-volatile nanotube diodes above and on the surface of the planarized insulator.

The word lines and bit lines may be used in a 3D array structure as described further below to interconnect the 3-D cells and form a 3-D memory, and may be substantially perpendicular to an X-Y plane that is substantially parallel to the underlying memory support circuitry. In the figures illustrating an exemplary 3D array structure and a method of fabricating the 3D array structure as further described below, the word line direction is arbitrarily assigned along the X-axis and the bit line direction is arbitrarily assigned along the Y-axis. The Z-axis, which is substantially perpendicular to the X-Y plane, shows the direction of the 3D cell orientation.

The method 3050 completes fabrication of the semiconductor chip using industry standard fabrication techniques by adding additional wiring layers, as needed, and a protective chip and adding package interconnects.

Once the support circuitry and interconnects are defined in and on the semiconductor substrate, the method may then fabricate a non-volatile nanotube diode array, such as shown in cross-section 3100 above the support circuitry and interconnect regions shown in fig. 31A. FIG. 31A shows a cross-section including cells C00 and C10 in several possible embodiments.

The method 3010, described further above, is used to define the support circuitry and interconnects 3101.

Next, method 3030 shown in fig. 30B deposits and planarizes insulator 3103. An interconnect means (not shown at section 3100, but further shown above with reference to section 2800 "of fig. 28C) through the flat insulator 3103 may be used to connect the routing metal lines in the array to the respective supporting circuitry and interconnects 3101. As an example, a word line driver in WL driver 2930 may be connected to word line WL0 in array 2910 of memory 2900 shown in fig. 29A. At this point in the fabrication process, a method may be used to form a memory array on the surface of insulator 3103, interconnecting memory array support structure 3105-1 as shown in FIG. 31A.

Method 3040 of FIG. 30B deposits and planarizes metal, polysilicon, insulator, and nanotube elements to form nonvolatile nanotube diodes, which in this case comprise a plurality of vertically oriented diodes and vertically oriented serial pairs of nonvolatile nanotube switches. The manufacturing method is further described in more detail below with reference to fig. 36A-36 FF. To eliminate the accumulation of alignment tolerances of the layers that substantially increase the cell area, a single cell outer dimension is formed in a single etch step, each cell having a single NV NT diode defined by a single trench etch step after the layers (except the BL0 layer) have been deposited and planarized. The single cell size in the Y direction is 1F (1 smallest feature) as shown in fig. 31A, while in the X direction (not shown) perpendicular to the Y direction is also 1F with a period of 2F in the X and Y directions. Thus, each cell occupies an area of at least about 4F ². The non-volatile nanotube diodes forming each cell are arranged in the Z (vertical) direction.

In addition to defining all cell sizes simultaneously without multiple alignment steps, the reduced cell size (area) may, in some embodiments, require self-aligned placement of device elements within the cell boundaries.

The method fills the trench with an insulator and then planarizes the surface. The method deposits and patterns word lines on the planarized surface.

Fabrication of some embodiments of the vertically oriented 3D cell proceeds as follows. The method deposits a wordline wiring layer on the surface of insulator 3103 with a thickness of 50 to 500nm, for example, as described further below with reference to fig. 36A-36 FF. The method etches the word line routing layer and defines individual word lines, such as word lines 3110-1(WL0) and 3110-2(WL 1). Word lines such as 3110-1 and 3110-2 are used as array wiring conductors and may also be used as respective cell contacts to N + polysilicon regions 3120-1 and 3120-2. The N + polysilicon regions 3120-1 and 3120-2 contact the cathode formed by the N polysilicon regions 3125-1 and 3125-2. Schottky diode junctions 3133-1 and 3133-2 may be formed using metal or silicide 3130-1 and 3130-2 regions in contact with N-polysilicon regions 3125-1 and 3125-2. The N-poly regions 3125-1 and 3125-2 may be doped with arsenic or phosphorous, for example, in the range of 10 ¹⁴To 10¹⁷Dopant atom/cm³And the thickness may have a range of, for example, 20nm to 400 nm. N + polysilicon is typically doped, for example, with arsenic or phosphorus to 10²⁰Dopant atom/cm³And for example has a thickness of 20 to 400 nm.

Examples of contact and conductor materials are elemental metals such as Al, Au, W, Cu, Mo, Pd, Ni, Ru, Ti, Cr, Ag, In, Ir, Pb, Sn, and metal alloys such as TiAu, TiCu, TiPd, PbIn, and TiW, other suitable conductors, or conductive nitrides, oxides, or silicides such as RuN, RuO, TiN, TaN, CoSi_xAnd TiSi_x. The insulator can be SiO₂、SiN_x、A1₂O₃BeO, polyimide, mylar, or other suitable insulating material.

In some cases, conductors such as Al, Au, W, Cu, Mo, Ti, and others may be used as the anodes 3130-1 and 3130-2 of the Schottky diodes. However, in other cases, it is advantageous to optimize the anode 3130-1 and 3130-2 materials for lower forward voltage drop and lower diode leakage. The anode material of the Schottky diode can comprise Al, Ag, Au, Ca, Co, Cr, Cu, Fe, Ir, Mg, Mo, Na, Ni, Os, Pb, Pd, Pt, Rb, Ru, Ti, W, Zn and the likeIt is an elemental metal. In addition, silicides, e.g., CoSi, may be used ₂、MoSi₂、Pd₂Si、PtSi、RbSi₂、TiSi₂、WSi₂And ZrSi₂. Schottky diodes formed using such metals and silicides are described in NG, k.k. "completeg guide to Semiconductor Devices", Second Edition, John Wiley&Sons, 2002m pp.31-41, the entire contents of which are incorporated herein by reference.

At this point in the exemplary process, the schottky diode select device has been formed. Next, a non-volatile nanotube switch is formed in each cell, with one terminal common to, for example, anodic metals 3130-1 and 3130-2. To increase the density of cells C00 and C10, the nanotube elements in the corresponding non-volatile nanotube switch are vertically oriented, as shown in FIG. 31A, with the corresponding nanotube switch 700 shown in FIG. 7. Vertically oriented nanotube switches are described in more detail in the incorporated patent references. Vertically oriented sidewalls including insulation and contact regions are formed prior to forming vertically oriented nanotube elements 3145-1 and 3145-2. The vertically oriented sidewalls are formed at R using a self-aligned process, where R is approximately equal to F/2 in this example, however, similar self-aligned fabrication methods may be used to place the vertically oriented sidewalls at any location, such as F/3, F/4, or any other desired location.

The method of forming nanotube elements 3145-1 and 3145-2 includes, first, forming insulators 3135-1 and 3135-2 and contacts 3140-1 and 3140-2 in contact with respective insulators 3135-1 and 3135-2, forming vertical sidewalls by directionally etching openings through both the metal and insulator regions. The vertical sidewalls of insulators 3135-1 and 3135-2 and sidewall contacts 3140-1 and 3140-2 are self-aligned with respect to the trench sidewalls, which are later etched in a process using a method as described further below with reference to fig. 36A-36 FF. The thickness of insulators 3135-1 and 3135-2 determines the channel length L_SW-CHAs shown in fig. 31A. Insulators 3135-1 and 3135-2 may range, for example, from less than 5nm to greater than 250 nm.

Next, the method forms conformal nanotube elements 3145-1 and 3145-2, as described in more detail in the incorporated patent references.

Methods then form protective conformal insulators 3150-1 and 3150-2 on the surfaces of conformal nanotube elements 3145-1 and 3145-2, respectively.

Next, the method fills the openings with an insulating material and the method planarizes the surface, exposing the top surfaces of sidewall contacts 3140-1 and 3140-2.

The method then forms contacts 3165-1 and 3165-2. Contacts 3165-1 and 3165-2 provide conductive paths between sidewall contacts 3140-1 and 3140-2 and bit line 3171(BL0), respectively, the bit line 3171(BL0) will be formed after forming cells C00 and C10 are completed. Contacts 3165-1 and 3165-2 correspond to the dimensions of the sacrificial layer that is used as a trench-etch mask layer of minimum dimension F prior to formation of contacts 3165-1 and 3165-2, which are self-aligned to NV NT switch elements 3145-1 and 3145, as described further below with reference to FIGS. 36A-36 FF.

The method then etches the trench regions, fills the trenches with insulator, and then planarizes the surface to form insulator 3160 before contacts 3165-1 and 3165-2 are formed, as further described below with reference to fig. 36A-36 FF.

The method then deposits and patterns bit line 3171(BL 0).

Nonvolatile nanotube diode 3190, which schematically overlaps cross-section 3100 of fig. 31A, is an equivalent circuit corresponding to nonvolatile nanotube diode 1300 of fig. 13, i.e., one of each of cells C00 and C10. Cells C00 and C10 of cross-section 3100 shown in fig. 31A correspond to respective cells C00 and C10 of memory array 2910 schematically shown in fig. 29A, and to word lines WL0 and WL1 and bit line BL0 of the array lines schematically shown in memory array 2910.

The cross-section 3100 ' shown in fig. 31B shows an embodiment of memory array cells C00 ' and C10 ', which are similar to the embodiment of memory array cells C00 and C10 shown in fig. 31A, except that NV NT diodes C00 ' and NV NT diodes C10 ' formed in respective cells C00 ' and C10 ' include PN diodes having PN diode junctions 3128-1 and 3128-2 instead of schottky diodes having schottky diode junctions 3133-1 and 3133-2.

P-polysilicon regions 3127-1 and 3127-2 form anodes and N-polysilicon regions 3125-1 'and 3125-2' form cathodes, which together (in combination) form a PN diode with PN diode junctions 3128-1 and 3128-2. The P-poly regions 3127-1 and 3127-2 also make ohmic or near-ohmic contact with contacts 3130-1 'and 3130-2'. The N polysilicon regions 3125-1 'and 3125-2' also form ohmic contact regions with the corresponding N + polysilicon regions. The other structures of cells C00 'and C10' are similar to those illustrated and described with respect to cells C00 and C10, respectively.

Memory array support structure 3105 of the embodiment shown in fig. 31B, including support circuitry and interconnects 3101 'and a planarized insulator 3103', is similar to memory support structure 3101 shown in fig. 31A, except that adjustments may be needed to accommodate memory cells having PN diode select devices, rather than schottky diode select devices.

Nonvolatile nanotube diode 3190 ' is an equivalent circuit corresponding to nonvolatile nanotube diode 1300 of fig. 13, i.e., one of each of cells C00 ' and C10 '. The cells C00 'and C10' correspond to the respective cells C00 and C10 of the memory array 2910 schematically shown in fig. 29A, and to the word lines WL0 and WL1 and the bit line BL0 of the array lines schematically shown in the memory array 2910.

The cross-section 3100 "shown in fig. 31C shows an embodiment of memory array cells C00" and C10 "that is similar to the embodiment of memory array cells C00 and C10 shown in fig. 31A, except that NV NT diode C00" and NV NT diode C10 "formed in respective cells C00" and C101 "include diode junctions 3147-1 and 3147-2 that are both PN and schottky diode junctions in parallel.

The P-type semiconductor nanotube element, a subset of NT elements 3145-1 "and 3145-2", is in physical and electrical contact with N-polysilicon regions 3125-1 "and 3125-2" forming a PN diode-anode, and N-polysilicon regions 3125-1 "and 3125-2" forming a cathode, which together form a PN diode, thereby making the PN diode as part of the combination of PN and schottky diode junctions 3147-1 and 3147-2. The metal-type nanotube elements, i.e., a subset of NT elements 3145-1 "and 3145-2", are in physical and electrical contact with N-polysilicon regions 3125-1 "and 3125-2" forming a schottky diode-anode, and N-polysilicon regions 3125-1 "and 3125-2" forming the cathode of a schottky diode having the schottky diode junction as part of the combined PN and schottky diode junctions 3147-1 and 3147-2. Thus, combined PN and Schottky diode junctions 3147-1 and 3147-2 are comprised of a PN-type diode and a Schottky-type diode in parallel and are formed by nanotube elements 3145-1 "and 3145-2" in contact with N-poly regions 3125-1 "and 3125-2", respectively.

The N polysilicon regions 3125-1 "and 3125-2" also form ohmic contact regions with the corresponding N + polysilicon regions 3120-1 "and 3120-2", respectively. Nanotube elements 3145-1 "and 3145-2" are also in physical and electrical contact with sidewall contacts 3140-1 "and 3140-2". Sidewall contacts 3140-1 '' and 3140-2 '' make contact with upper contacts 3165-1 '' and 3165-2 '', respectively, which make contact with bit line 3171 '' (BL 0). The formation of the upper contacts is briefly described above with further reference to fig. 31A and described in further detail below with reference to fig. 36A-36 FF. The other structures of the cells C00 "and C10" are similar to those illustrated and described with respect to cells C00 and C10, respectively.

The memory array support structure 3105-3 shown in the embodiment of fig. 31C, including support circuitry and interconnects 3101 "and a planarizing insulator 3103" is similar to the memory support structure 3101 and planarizing insulator 3103 shown in fig. 31A, except that adjustments may be needed to accommodate memory cells having PN diode select devices and schottky diode select devices in parallel.

Nonvolatile nanotube diode 3190 "is an equivalent circuit corresponding to nonvolatile nanotube diode 1300 of fig. 13, i.e., one of each of cells C00" and C10 ". Cells C00 "and C10" of cross-section 3100 "of the embodiment shown in fig. 31C correspond to respective cells C00 and C10 of memory array 2910 in the embodiment schematically shown in fig. 29A, and to word lines WL0 and WL1 and bit line BL0 of the array lines schematically shown in memory array 2910.

Non-volatile memory using NVNT diode device with both anode-to-NT switch connection and cathode-to-NT switch connection

Fig. 32 illustrates an exemplary method 3200 of fabricating embodiments having two memory arrays stacked on top of each other on an insulating layer over support circuitry formed under the insulating layer and stacked arrays, and having vias through the insulating layer. Although method 3200 is further described below with respect to nonvolatile nanotube diodes 1200 and 1300, method 3200 is sufficient to encompass the fabrication of many nonvolatile nanotube diodes as further described above. It is also noted that although method 3200 is described in a 3D memory embodiment, method 3200 can also be used to form a 3D logic embodiment based on NV NT diodes arranged as a logic array, such as NAND and NOR arrays with logic support circuitry (rather than memory support circuitry) as used for PLAs, FPGAs, and PLDs, for example.

Fig. 33A shows a 3D perspective view 3300 including an embodiment with a dual-high stacked three-dimensional array, a lower array 3302, and an upper array 3304. The lower array 3302 includes nonvolatile nanotube diode cells C00, C01, C10, and C11. The upper array 3304 includes nonvolatile nanotube diode cells C02, C12, C03, and C13. Word lines WL0 and WL1 are oriented along the X-direction, and bit lines BL0, BL1, BL2, and BL3 are oriented along the Y-direction and are substantially perpendicular to word lines WL1 and WL 2. Nanotube element channel length L _SW-CHAnd channel width W_SW-CHShown in 3D perspective view 3300. The cross-sections that can be used as embodiments of cells C00, C01, C02, and C03 are further as follows in FIG. 33B and FIG. 33CShown; also, embodiments that can be used as cells C00, C02, C12, and C10 are further illustrated in fig. 33B' as follows.

Generally, method 3210 manufactures support circuitry and interconnects in and on a semiconductor substrate. This includes NFET and PFET devices having drains, sources, and gates, which may be interconnected to form memory (or logic) support (or select) circuits. Such structures and circuits may be formed using known techniques, which are not described in this application. Method 3210 is used to form support circuitry and interconnect layer 3301 as part of cross-section 3305 shown in fig. 33B and cross-section 3305 'shown in fig. 33B' using known fabrication methods, wherein nonvolatile nanotube diode control and circuitry is fabricated in and on support circuitry and interconnect layer 3301. The support circuits and interconnects 3301 are similar to, for example, support circuits and interconnects 2801 and 3101 as described further above, but modified to accommodate two stacked memory arrays. Note that although a dual-high stack memory array is illustrated in fig. 33A-33D, 3D array stacks may be formed (fabricated) beyond dual-high, including but not limited to, for example, 4-high and 8-high stacks.

Next, method 3210 is also used to fabricate an intermediate structure that includes a planarized insulator with interconnect means and non-volatile nanotube array structures on a planarized insulator surface, such as insulator 3303 shown in section 3305 of FIG. 33B and correspondingly section 3305 'of FIG. 33B'. The interconnect means includes vertically oriented fill contacts, or studs, for interconnecting memory support circuitry in and on the semiconductor substrate below the planarized insulator, and the array of non-volatile nanotube diodes above and on the surface of the planarized insulator. The planarized insulator 3303 is formed using a method similar to method 2730 shown in fig. 27B, where the method deposits and planarizes the insulator 3303. Interconnect means (not shown in cross-sectional view 3300) through planar insulator 3303, similar to contacts 2807 shown in fig. 28C, may be used to connect array lines in first and second memory arrays 3310, 3320 to respective support circuits and interconnects 3301, as described further below. The support circuitry and interconnects 3301 and insulator 3303 form memory array support structures 3305-1.

Next, a method 3220 similar to method 2740 is used to fabricate the first memory array 3310 using a diode cathode-to-nanotube switch based on a non-volatile nanotube-diode array similar to that of cross-section 2800 shown in FIG. 28A, and the corresponding fabrication method is further described below with reference to FIGS. 34A-34 FF.

Next, method 3230, which is similar to method 3040 of FIG. 30B, fabricates a second memory array 3320 on the planar surface of first memory array 3310, but using a diode anode-to-nanotube switch based on a non-volatile nanotube diode array similar to the non-volatile nanotube diode array illustrated in cross-section 3100 of FIG. 31A, and the corresponding fabrication method is further described below with reference to FIGS. 36A-36 FF.

FIG. 33B illustrates a cross section 3305 that includes a first memory array 3310 and a second memory array 3320, both arrays sharing a common word line 3330, in accordance with some embodiments. Word lines such as 3330 may be defined (etched) during a trench etch, which defines the memory array (cells) when forming the array 3320. Cross section 3305 shows first memory array 3310 and second memory array 3320 combined in a word line or in the X-direction, with shared word line 3330(WL0), four bit lines BL0, BL1, BL2, and BL3, and corresponding cells C00, C01, C02, and C03. The array period in the X direction is 2F, where F is the minimum size of the technology node (generation).

FIG. 33B ' illustrates a cross section 3305 ' including a first memory array 3310 ' and a second memory array 3320 ', both sharing common word lines 3330 ' and 3332, in accordance with some embodiments. Word line 3330' is a cross-sectional view of word line 3330. Word lines such as 3330 'and 3332 may be defined (etched) during a trench etch that defines the memory array (cells) when the array 3320' is formed. Cross section 3305 'shows first memory array 3310' and second memory array 3320 'combined in bit lines or in the Y-direction, with shared word lines 3330' (WL0) and 3332(WL1), two bit lines BL0 and BL2, and corresponding cells C00, C10, C02, and C12. The array period in the Y direction is 2F, where F is the minimum size of the technology node (generation).

Because of the 2F period in the X and Y directions, the memory array cell area of 1 bit of the array 3310 can be reduced to 4F². Because of the 2F cycle in the X and Y directions, the memory array cell area of 1 bit of the array 3320 can be reduced to 4F²,. Because the memory arrays 3320 and 3310 are stacked, the memory array cell area per bit can be reduced to 2F². If four memory arrays (not shown) are stacked, the memory array cell area per bit can be reduced to 1F²。

Referring again to fig. 32, fabrication of the semiconductor chip is completed by adding additional wiring layers, passivating the chip and adding package interconnects using method 3240 of industry standard fabrication techniques.

The cross-section 3305 shown in FIG. 33B shows the stacking of the first and second memory arrays 3310, 3320 with the word locations aligned in the vertical (Z) direction, however, offsetting the stacked memory arrays may have interconnection and/or manufacturing advantages. FIG. 33C illustrates an embodiment having a cross-section 3350 "that is similar to the cross-section 3305 shown in FIG. 33B, where the second memory array 3320" is shifted by one cell location (half a cycle) relative to the cells in the first memory array 3310 "and the shared word line 3330". The support circuitry and interconnects 3301 "and insulator 3303' form a memory array support structure 3305-2, which is similar to memory array support structure 3305-1 shown in FIG. 33B.

In operation, the four stacked cells shown in FIG. 33B correspond to the cells C00 and C01 cathode-to-nanotube cells schematically shown in memory array 2610, with memory array 2610 forming memory arrays 3310, and C02 and C03 anode-to-nanotube cells schematically shown in memory array 2910 that make up memory array 3320. All four cells share a common word line WL0 in memory array cross-section 3300. The cells C00, C01, C02, and C03 are also shown in the 3D perspective view 3300 shown in fig. 33A. Memory array 3305 is about 2 times higher density on a per bit basis than a memory array such as cathode-to-NT cross-section 2800 shown in fig. 28A or anode-to-NT cross-section 3100 shown in fig. 31A. Additional word lines and bit lines (not shown) may be added to form a large memory array in the MB and GB ranges. The operation of the word line WL0 and the bit lines BL0, BL1, BL2, and BL3 is further described below in conjunction with the waveform 3375 shown in FIG. 33D with the word line WL0 selected.

For an exemplary write 0 operation along word line WL0, while erasing cells C00, C01, C02, and C03, the data stored in cells C00-C03 may optionally be read before erasing and data storage in the corresponding sense amplifiers/latches. The write 0 operation along word line WL0 continues and bit lines BL0, BL1, BL2, and B3 transition from zero to 5 volts, with the bit line voltages controlled by the respective BL drivers. The WL driver circuit then drives word line WL0 from 5 volts to zero volts, thereby forward biasing NV NT diodes C00, C01, C02, and C03 forming cells C00, C01, C02, and C03, respectively. The write 0 voltage is about 4.5 volts (erase voltage 5 volts minus the NV NT diode turn-ON voltage less than 0.5 volts, as shown in FIGS. 21A-21E), causing the NV NT diode in the ON state to transition from the ON state to the OFF state; the NV NT diode in the OFF state is maintained in the OFF state. Thus, NV NT diodes C00-C03 are all in the OFF state after a write 0 operation along word line WL 0. Unselected word lines WL1, WL2, and WL3 (not shown in FIG. 33B) remain unselected and at 5 volts, and the non-volatile data stored in the corresponding cells remains unchanged.

In this example, the write operation immediately follows the write 0 operation, as further described above. In other words, the NVNT diodes C00-C03 of the corresponding cells C00-C03 begin a write operation in the OFF state. For an exemplary write 0 operation, e.g., to cells C00 and C03, where a logic 0 state is to be stored, NV NT diodes C00 and C03 will remain in a logic 0 high resistance state. Thus, the bit lines BL0 and BL3 are held at zero volts by the respective BL driver and sense circuits. Next, word line WL0 is switched from 4 volts to zero volts by a stimulus from the corresponding WL driver. The NV NT diodes C00 and C03 maintain reverse bias during write 0 operation, and the cells C00 and C03 maintain OFF (high resistance) logic 0 state.

In a write 1 operation representing a logic 1, if NV NT diodes C01 and C02 are to transition from OFF (high resistance state) to ON (low resistance state), then bit lines BL1 and BL2 transition from zero volts to 4 volts by a stimulus provided from the respective BL drivers. Word line WL0 then transitions from 4 volts to zero volts. A write 1 voltage of about 4 volts causes a voltage of 3.5 volts across the terminals of the respective NV NT switching sub-assemblies of NV NT diodes C01 and C02 (4 volts minus the NV NT diode turn-ON voltage of less than 0.5 volts, as shown in fig. 21), and causes NV NT diodes C01 and C02 to transition from the OFF state to the ON state.

For an exemplary read operation, e.g., for cells C00-C03, a respective BL driver and sense circuit precharges a respective one of the bit lines BL0-BL3 to a high voltage, e.g., a read voltage of 2 volts. The read bitline voltage is selected to be lower than both the write 0 and write 1 voltages to ensure that the stored logic state (bit) is not disturbed (changed) during the read operation. Word line driver word line WL0 is driven from 2 volts to zero volts. The NV NT diodes C00 and C03 in the respective cells C01 and C03 are in the OFF state (storing a logic 0), and the bit lines BL0 and BL3 are not discharged and are maintained at 2 volts. The corresponding sense amplifier/latch stores the corresponding logic 0 state. However, since the NV NT diodes C01 and C02 in the respective cells C01 and C02 are in the ON state, the bit lines BL1 and BL2 are discharged. The respective sense amplifier/latch detects the reduced voltage and the latch stores the respective logic 1 state.

Note that the memory array of cross-section 3350 "shown in FIG. 33C can operate in a manner similar to the memory array shown in cross-section 3305, described further above with reference to FIG. 33B.

Method of manufacturing a non-volatile memory using non-volatile nanotube diode (NV NT diode) devices as cells

An exemplary method of making an embodiment of a three-dimensional cell structure of a non-volatile cell using NV NT devices with vertically oriented diodes and with cathode-to-NT switch connections is further described below with reference to FIGS. 34A-34FFVertically orientedNV NT switches, such as shown in cross-section 2800 shown in FIG. 28A and cross-section 2800' shown in FIG. 28B.

An exemplary method of making an embodiment of a three-dimensional cell structure of a non-volatile cell using NV NT devices having vertically oriented diodes and having cathode-to-NT switch connections is further described below with reference to FIGS. 35A-35Horizontally orientedNV NT switch, such as shown in section 2800 "shown in FIG. 28C.

An exemplary method of making an embodiment of a three-dimensional cell structure of a non-volatile cell using NV NT devices with vertically oriented diodes and anode-to-NT switch connections is further described below with reference to FIGS. 36A-FFVertically orientedNV NT switches, such as shown in cross-section 3100 shown in FIG. 31A, cross-section 3100' shown in FIG. 31B, and cross-section 3100 "shown in FIG. 31C.

Exemplary methods of fabricating stacked array embodiments based on three-dimensional cell structures of non-volatile cells using NV NT devices having vertically oriented diodes and connecting cell types using both cathode-to-NT switches and anode-to-NT switches are further described in combination with reference to FIGS. 34A-FF and 36A-FF Vertically orientedNV NT switches, such as section 3300 shown in FIG. 33A, section 3300 ' shown in FIG. 33A ', and section 3300 ' shown in FIG. 33B.

Method of manufacturing a non-volatile memory using NVNT diode devices with cathode-to-NT switch connections

As described further below with reference to FIGS. 34A-34FF, the method 2700 shown in FIGS. 27A and 27B may be used in an embodiment of manufacturing a memory using NV NT diode devices, NV NT twoThe polar tube device is provided with a tube forVertically orientedThe cathode-to-NT switch of the NV NT switch is connected, a vertically oriented NV NT switch such as those in cross-section 2800 shown in fig. 28A and cross-section 2800' shown in fig. 28B. Structures such as cross-sections 2800 and 2800' may be used to fabricate, for example, the memory 2600 schematically illustrated in fig. 26A.

The method of fabricating cross-sections 2800 and 2800' typically requires critical alignment (critical alignment) during the X-direction process steps. There is no critical alignment in the Y direction because the distance between the trenches in this example determines the width of the nanotube element. However, by using a method similar to that described further below, the width of the nanotube element with respect to the X-direction can be formed to be less than the trench-to-trench spacing. In the X-direction, the critical alignment requirement is eliminated by using a method of forming self-aligned internal cell vertical sidewalls that define the vertical nanotube channel element locations, the vertical channel element lengths (L) _{SW_CH}) And forming nanotube channel element contacts with respect to trench sidewalls that are later etched in the process to define outer cell dimensions using fabrication methods described further below with reference to fig. 34A-34 FF. In this example, the NV NT diode cell structure occupies a minimum dimension F in the X and Y directions, where F is the minimum lithographic dimension. In this example, the interior cell vertical sidewalls are positioned (by self-aligned techniques) at a distance of about R from the trench sidewalls, which are separated by a distance F and define the outer cell dimensions, as further described below with reference to fig. 34A-34 FF. FIGS. 34A-34FF show a pitch R of about F/2. However, methods using self-aligned techniques, as further described below with reference to FIGS. 34A-34FF, may use, for example, R values of F/4, F/3, F/2, 3F/4, etc. to position the vertical sidewalls at any location R within the cell region of width F.

As described further below with reference to fig. 35A-35S, method 2700 shown in fig. 27A and 27B can also be used in embodiments of manufacturing memory using NV NT diode devices having structures for use in fabricating memory devicesHorizontally orientedThe cathode-to-NT switch of the NV NT switch is connected,horizontally orientedNVNT switch such as28C, cross-section 2800 ". Structures such as cross-section 2800 "may also be used to fabricate memories, for example, memory 2600, shown schematically in fig. 26A.

Using diodes with vertical orientation and having cathode-to-NT switch connectionVertically orientedMethod for fabricating three-dimensional cell structure of non-volatile cell for NV NT device of NT switch

The method 2710 of FIG. 27A can be used to define support circuits and interconnects similar to those described further above with respect to the memory 2600 of FIG. 26A. The method 2710 applies well-known semiconductor industry technology design and fabrication techniques to the support circuits and interconnects 3401 fabricated in and/or on a semiconductor substrate as shown in fig. 34A. The support circuits and interconnects 3401 include FET devices in a semiconductor substrate and interconnects, such as vias and wires, on the semiconductor substrate.

Next, method 2730 shown in fig. 27B deposits and planarizes insulator 3403 on the surface of support circuitry and interconnects 3401. The interconnection through the planar insulator 3403, not shown in figure 34A, is further illustrated below with reference to figures 35A-35S. The combination of support circuitry and interconnects 3401 and planarization insulator 3403 is referred to as a memory support structure 3405, as shown in figure 34A.

Next, the method deposits conductor layer 3410 on the planarized surface of insulator 3403, as shown in fig. 34A, typically 50 to 500nm thick, using known industry methods. Examples of conductor layer materials are elemental metals such as Al, Au, W, Cu, Mo, Pd, Ni, Ru, Ti, Cr, Ag, In, Ir, Pb, Sn, and metal alloys such as TiAu, TiCu, TiPd, PbIn, and TiW, other suitable conductors, or conductive nitrides, oxides, or silicides such as RuN, RuO, TiN, TaN, CoSi _xAnd TiSi_x. In some cases, materials such as used in the conductor layer 3410 may also be used as the anode of the schottky diode, and in this example a separate layer, such as the contact layer 3415 used to form the anode of the schottky diode, is not required and may be omitted from the manufacturing process.

Next, the method deposits an optional conductive schottky anode contact layer 3415 on the surface of the conductor layer 3410, for example, in the range of 10 to 500nm in thickness. Anode contact layer 3415 may use materials similar to those used to form conductor layer 3410 (or contact layer 3415 may be omitted entirely and conductor layer 3410 may be used to form the schottky anode), or anode contact layer 3415 materials may be selected to optimize the anode material to enhance schottky diode properties, such as reduced forward voltage drop and/or reduced diode leakage. Anode contact layer 3415 can include Al, Ag, Au, Ca, Co, Cr, Cu, Fe, Ir, Mg, Mo, Na, Ni, Os, Pb, Pd, Pt, Rb, Ru, Ti, W, Zn, and other elemental metals. In addition, silicides such as CoSi may be used₂、MoSi₂、Pd₂Si、PtSi、RbSi₂、TiSi₂、WSi₂And ZrSi₂。

Next, an N polysilicon layer 3420 is deposited on the surface of the anode contact layer 3415 to a thickness of 10nm to 500 nm. The N-polysilicon layer 3420 may be doped with, for example, arsenic or phosphorous in the range of 10 ¹⁴To 10¹⁷Dopant atom/cm³. The N-polysilicon layer 3420 may be used to form the cathode of the schottky diode. In addition to the doping level, the polysilicon grain size (or grain structure) of the N-polysilicon layer 3420 may also be controlled by known industrial deposition methods. Furthermore, known industrial SOI deposition methods can be used which result in the polycrystalline silicon region being monocrystalline (no longer polycrystalline) or nearly monocrystalline.

Next, after completing the memory support structure 3405, a conductor layer 3410 is deposited, which may be used as an array wiring layer, and then the deposition of schottky diode forming layers 3415 and 3420 is completed by depositing an N + polysilicon layer 3425 on the surface of the N polysilicon layer 3420, as shown in fig. 34A, to form an ohmic contact layer. The N + polysilicon layer 3425 is typically doped with, for example, arsenic or phosphorous to 10²⁰Dopant atom/cm³And for example has a thickness of 20 to 400 nm.

At this point in the process, the remaining method may be used to fabricate NV NT diodes using schottky diode based cathode-to-NT switching structures such as that shown in fig. 28A. However, as described above with further reference to, for example, fig. 28B, the NV NT diode may be formed using a PN diode rather than a schottky diode. Therefore, alternatively, a PN diode alternative manufacturing method is illustrated in fig. 34A'.

The method 2700 described further above and with reference to fig. 34A can also be used to describe the fabrication of fig. 34A'. The support circuit and interconnect 3401 'shown in FIG. 34A' corresponds to the support circuit and interconnect 3401 shown in FIG. 34A, except that possibly small changes are introduced into the various circuits to accommodate differences in diode characteristics, such as the turn-on voltage between a Schottky diode and a PN diode.

Next, the method deposits a planarizing insulator 3403 ' on the surface of the support circuitry and interconnects 3401 ', as shown in fig. 34A '. The planarized insulator 3403 'corresponds to the planarized insulator 3403, except that possibly small changes are introduced into the insulator 3403' to accommodate differences in diode characteristics. The memory support structures 3405 'are thus similar to the support structures 3405, except that small changes may be introduced to the support circuitry and interconnects 3401' and the planarization insulator 3403 ', as further described above with reference to figure 34A'.

Next, the method deposits a conductor layer 3410 ' in contact with the surface of the planarized insulator 3403 ', as shown in fig. 34A ', having a thickness and material similar to the conductor layer 3410 described further above with reference to fig. 34A.

Next, the method deposits a P polysilicon layer 3417 with a thickness of 10nm to 500nm on the surface of the conductor layer 3410 ', as shown in fig. 34A'. The P polysilicon layer 3417 may be doped with boron, for example, in the range of 10 ¹⁴To 10¹⁷Dopant atom/cm³. The P polysilicon layer 3417 may be used to form the anode of the PN diode. In addition to the doping level, the polysilicon crystalline size of the P polysilicon layer 3417 may also be controlled by known industrial deposition methods. Furthermore, known industrial SOI deposition methods can be used which result in the polycrystalline silicon region being monocrystalline (no longer polycrystalline), or nearly monocrystalline.

Next, the method deposits an N polysilicon layer 3420' with a thickness of 10nm to 500nm on the surface of the P polysilicon layer 3417, which may be used to form the cathode of the PN diode. The N-polysilicon layer 3420' may be doped with arsenic or phosphorous in the range of 10, for example¹⁴To 10¹⁷Dopant atom/cm³. In addition to the doping level, the polysilicon grain size (grain structure) of the N-polysilicon layer 3420' may also be controlled by known industrial deposition methods. Furthermore, known industrial SOI deposition methods can be used which result in the polycrystalline silicon region being monocrystalline (no longer polycrystalline), or nearly monocrystalline.

Next, after the memory support structure 3405 'has been completed, a conductor layer 3410' which may be used as an array wiring layer is then deposited, and then deposition of PN diode forming layers 3417 and 3420 'is completed, and an N + polysilicon layer 3425' is deposited on the N polysilicon layer 3420 'to form an ohmic contact layer, as shown in fig. 34A'. The N + polysilicon layer 3425' is typically doped with, for example, arsenic or phosphorous to 10 ²⁰Dopant atom/cm³And has a thickness of, for example, 20 to 400 nm.

The description of the fabrication method continues with respect to the schottky-diode based structure described with reference to fig. 34A to form an NV NT diode cell structure corresponding to cross-section 2800 shown in fig. 28A. However, this fabrication method may also be applied to the PN diode-based structure described with reference to fig. 34A 'to form an NV NT diode cell structure corresponding to cross-section 2800' shown in fig. 28B.

At this point in the fabrication process, the method deposits a contact layer 3430 on the surface of the N + polysilicon layer 3425, as shown in fig. 34B. The thickness of the contact layer 3430 may be, for example, 10 to 500 nm. The contact layer 3430 may be formed using: al, Au, W, Cu, Mo, Pd, Ni, Ru, Ti, Cr, Ag, In, Ir, Pb, Sn, and metal alloys such as TiAu, TiCu, TiPd, Pbin, and TiW, other suitable conductors, or conductive nitrides such as oxides, or silicides such as RuN, RuO, TiN, TaN, CoSi_xAnd TiSi_x。

Next, the method deposits an insulator layer 3435 on the contact layer 3430 as shown in fig. 34B. The thickness of the insulator layer 3435 may be well controlled and may be used in some embodiments to determine the channel length of a vertically oriented non-volatile nanotube switch, as further described below with reference to fig. 34I. The thickness of the insulator layer 3435 can vary from less than 5nm to greater than, for example, 250 nm. Insulator 3435 can be formed of any insulator material known in the CMOS industry or the packaging industry, such as SiO ₂、SiN、A1₂O₃BeO, polyimide, PSG (phosphosilicate glass), photoresist, PVDF (polyvinylidene fluoride), sputtered glass, epoxy glass, and other dielectric materials and combinations of dielectric materials, such as A1₂O₃PVDF of the layer. U.S. patent application No.11/280,786 includes some examples of various dielectric materials.

Next, the method deposits a contact layer 3440 on the insulator layer 3435 as shown in fig. 34B. The thickness of the contact layer 3440 may be, for example, in the range of 10 to 500nm, and the contact layer 3440 may be formed using a variety of conductive materials similar to those described further above with respect to the contact 3430.

Next, the method deposits a sacrificial layer 3441 on the contact layer 3440 as shown in fig. 34C. The thickness of the sacrificial layer 3441 may be in the range of 10 to 500nm, for example, and the sacrificial layer 3441 may be formed using a conductor, semiconductor, or insulator material, such as the materials described further above with respect to the contact layer 3430, the semiconductor layers 3420 and 3425, and the insulator layer 3435.

Next, the method deposits and patterns a mask layer, such as mask layer 3442, on the top surface of sacrificial layer 3441 as shown in fig. 34C using known industry methods. The mask openings can be aligned to, for example, alignment marks in the planar insulating layer 3403; this alignment is non-critical.

Then, the method directionally etches the sacrificial layer 3441 to form an opening having a dimension D in the X direction_OPEN-1(D_Opening-1) Using a known industrial process as shown in FIG. 34DThe penetrating sacrificial layer 3441 stops at the surface of the contact layer 3440. As described further below, two memory cells are formed that include vertical nanotube channel elements that are self-aligned and positioned relative to the vertical edges of sacrificial regions 3441' and 3441 ". Dimension D in X direction_OPEN-1About 3F, where F is the minimum lithographic dimension. For the 65nm technology node, D_OPEN-1195nm, which is a non-minimum dimension and thus a non-critical dimension in any technology node. At this point in the process, sidewall spacer techniques are used to position the vertical sidewalls at a distance R from the inner surfaces of the sacrificial regions 3441' and 3441 ", as described further below.

Next, the method deposits a conformal sacrificial layer 3443, as shown in fig. 34E. In some embodiments, the thickness of the conformal sacrificial layer 3443 is selected to be R, which in this example is selected to be about F/2. In this example, since R is about F/2, and since F is about 65nm, the thickness of the conformal sacrificial layer 3443 is about 32.5 nm. The conformal sacrificial layer 3443 may be formed using a conductor, semiconductor, or insulator material, i.e., similar to the material used to form the sacrificial layer 3441 as described further above.

Next, the process directionally etches the conformal sacrificial layer 3443 using known industry methods, for example using Reactive Ion Etching (RIE), to form a dimension D_OPEN-2(D_Opening-2) The openings 3444 and the sacrificial regions 3443 ' and 3443 ", the sacrificial regions 3443 ' and 3443" having vertical sidewalls that are self-aligned and separated from the inner vertical sidewalls of the sacrificial regions 3441 ' and 3441 ", respectively, by a distance R in the X-direction as shown in fig. 34F. The distance R is approximately equal to F/2, or in this case approximately 32.5 nm. Dimension D of opening 3444_OPEN-2About 2F or about 130nm for a 65nm technology node, is a non-critical dimension.

Next, the method directionally etches openings through the contact layer 3440 to the top surface of the insulator layer 3435. An opening is formed in the contact layer 3440 using a directional etch such as RIE, with dimension D_OPEN-2Is about 2F (130 nm in this example) and forms sidewall contact regions 3440' and 3440 ", as shown in fig. 34G.

Next, the method directionally etches openings through the insulator layer 3435 to the top surface of the contact layer 3430. An opening 3444' is formed in the insulator layer 3435 using a directional etch such as RIE, having a dimension D_OPEN-2Is about 2F (130 nm in this example) and forms insulator regions 3435' and 3435 ", as shown in fig. 34H.

Next, the method deposits conformal nanotube element 3445 on the sidewalls of opening 3444' in a vertical (Z) orientation, as shown in fig. 34I. The size of opening 3444' is substantially the same as the size of opening 3444. Conformal nanotube element 3445 can have a thickness of, for example, 0.5 to 20nm, and can be fabricated as a single layer or as multiple layers using deposition methods such as spin-on and spray-on methods. Nanotube element fabrication methods are described in more detail in the incorporated patent references.

Since nanotube element 3445 is in contact with contact layer 3430 and the sidewalls of sidewall contact regions 3440 ' and 3440 ", sidewall contact regions 3440 ' and 3440" are separated by the thickness of insulator regions 3435 ' and 3435 ", respectively, two non-volatile nanotube switch channel regions are formed in part (channel width is not defined yet) with channel length L in the Z-direction_SW-CHThe range corresponding to the insulator regions 3435' and 3435 "is 5nm to 250nm thick as shown in fig. 34I. The vertical (Z-axis) portion of nanotube element 3445 is separated from the inner vertical sidewalls of sacrificial regions 3441' and 3441 "by a self-aligned distance R. Such partially formed vertical nonvolatile nanotube switches are analogous to vertically oriented nonvolatile nanotube elements 765 and 765' of memory storage areas 760A and 760B, respectively, as shown in FIG. 7B. Conformal nanotube element 3445 also makes contact with sacrificial regions 3443 'and 3443 "and sacrificial regions 3441' and 3441", as shown in FIG. 34I.

Next, the method deposits a conformal insulator layer 3450 on the nanotube element 3445 as an insulating and protecting layer, and reduces the opening 3444' to an opening 3451, as shown in fig. 34J. Opening 3451 is similar to opening 3444' except that a conformal insulator 3450 and a conformal nanotube element 3445 are added. In totalThe shaped insulator 3450 may be, for example, 5 to 200nm thick and may be formed of any insulator material known in the CMOS industry or the packaging industry, such as SiO₂、SiN、Al₂O₃BeO, polyimide, PSG (phosphosilicate glass), photoresist, PVDF (polyvinylidene fluoride), sputtered glass, epoxy glass, and other dielectric materials and combinations of dielectric materials, such as Al-coated₂O₃The PVDF of the layers. Insulator 3450 is deposited to a thickness sufficient to ensure protection of nanotube element 3445 from High Density Plasma (HDP) deposition.

At this point in the process, it is desirable to partially fill the opening 3451 by increasing the thickness of the bottom portion of the insulator 3450 vertically (Z direction) on a horizontal surface with little or no thickness increase on the sidewalls (vertical surfaces) of the insulator 3450 to form the insulator 3450'. An exemplary industrial method for filling an opening with a dielectric layer using HDP deposition is disclosed in U.S. patent 4,916,087, which is incorporated herein by reference in its entirety. However, us patent 4,916,087 fills the openings by depositing dielectric material on horizontal and vertical surfaces. Other methods of directional HDP insulator deposition may be used instead, for example, by directionally depositing dielectric material such that more than 90% of the insulator material is deposited on horizontal surfaces and less than 10% of the insulator material is deposited on vertical surfaces with well-controlled thickness. A short isotropic (isotropic) etch may be used to remove the insulator material deposited on the vertical surfaces. The thickness of the additional dielectric material is not critical. The additional dielectric material may be the same as the conformal insulator 3450, or may be a different dielectric material. The choice of dielectric material relative to the nanotube element is described in more detail in U.S. patent application No.11/280,786.

Next, the method directionally deposits insulator material in the openings 3451 using known industry methods such as selective HDP insulator deposition and increases insulator thickness primarily on horizontal surfaces, as shown by the insulator 3450 'in the openings 3451' and on the top surface in fig. 34K.

Next, the method deposits and planarizes insulator 3452, such as TEOS filled opening 3451' as shown in fig. 34L.

Next, the method planarizes the structure shown in fig. 34L to remove a top portion of insulator 3450' and a top portion of underlying nanotube element 3445, as shown in fig. 34M. The tops of sacrificial regions 3441 ', 3441 ", 3443', and 3443" may be used as CMP etch stop reference layers. Insulator 3450 "is the same as insulator 3450', except that the top horizontal layer has been removed. Nanotube element 3445' is the same as nanotube element 3445 except that the top horizontal layer has been removed. The insulator 3452' is identical to the insulator 3452, except that the insulator thickness has been reduced.

Next, the method etches (removes) sacrificial regions 3443 'and 3443 ″ and insulator 3452'. The exposed vertical sidewalls of nanotube element 3445' and conformal insulator 3450 "remain as shown in fig. 34N.

The method then etches (removes) the exposed portions of nanotube element 3445', forming nanotube element 3445 ", as shown in FIG. 34O. Methods of etching nanotube structures and elements are described in more detail in the incorporated patent references.

Then, the exposed portion of the insulator 3450 'is removed by a method such as directional etching to form an insulator 3450' ".

At this point in the process, a sidewall spacer method is applied as further illustrated below to form a self-aligned sacrificial region to be replaced by a conductor material in the fabrication process as further illustrated below to form an upper portion of the nanotube element contact, and also to define a self-aligned trench region for defining a self-aligned cell dimension along the X-direction, as also further illustrated below. The use of the sidewall spacer approach to form self-aligned structures without the need for masking and alignment results in minimal cell area.

In this example, referring to fig. 34P and 34Q, self-aligned sacrificial regions of X dimension F are formed using a method similar to that used in fig. 34E and 34F. Next, the method deposits a conformal sacrificial layer 3455, as shown in fig. 34P. The thickness of the conformal sacrificial layer 3455 is selected to be F. In this example, since F is about 65nm, the thickness of the conformal sacrificial layer 3455 is about 65 nm. The conformal sacrificial layer 3455 may be formed using a conductor, semiconductor, or insulator material, similar to the materials used to form the sacrificial layers 3441 and 3443 described further above.

Next, the process directionally etches the conformal sacrificial layer 3455 using known industry methods such as Reactive Ion Etching (RIE), forming an opening 3451 "having a size of about F, in this case about 65nm, as shown in FIG. 34Q. The inner sidewalls of opening 3451 "are defined by sacrificial regions 3455 'and 3455" and are self-aligned to the inner walls of sacrificial regions 3441' and 3441 "and separated by a distance of about F. Such an inner wall will be used to form one side of the upper portion of the nanotube contact area, as further exemplified below, and define one side of the cell in the X-direction.

Next, the method deposits and planarizes the sacrificial layer to form sacrificial regions 3456 coplanar with sacrificial regions 3455 ', 3455 ", 3441', and 3441", as shown in fig. 34R.

Next, the method applies a CMP etch to reduce the thickness of sacrificial region 3456 to form sacrificial region 3458; reducing the thickness of sacrificial regions 3455' and 3455 ", respectively, to form sacrificial regions 3455-1 and 3455-2; and reducing the thickness of sacrificial regions 3441 'and 3441 ", respectively, to form sacrificial regions 3458' and 3458", as shown in fig. 34. The thickness values of the coplanar sacrificial regions 3458, 3458', 3458 ", 3455-1, and 3455-2 are, for example, in the range 10nm to 200 nm.

At this point in the process, sacrificial regions 3455-1 and 3455-2 may be used as mask layers for directionally etching trenches using a method of defining the outer cell dimensions in the X-direction for 3D cells using one NV NT diode with cathode-to-nanotube connections. U.S. patent 5,670,803 to Bertin, a co-inventor, discloses a 3-D array (3D-SRAM in this example) architecture with simultaneousThe sidewall dimensions of the trench are defined. The structure includes vertical sidewalls simultaneously defined by cutting trenches through the multi-layer doped silicon and insulating regions to avoid multiple alignment steps. The trench-directed selective etch process cuts through multiple conductor, semiconductor, and oxide layers, stopping on a Support Insulator (SiO) between the 3D array structure and the underlying semiconductor substrate₂) On the top surface of the layer. The trench 3459 is formed first and then filled with insulator and planarized. Trenches 3459', and 3459 "are then formed simultaneously, then filled and planarized, as further illustrated below. Other corresponding trenches (not shown) are also etched in forming the memory array structure. Exemplary method steps that may be used to form trench regions 3459, 3459', and 3459 "and then fill the trenches to form the isolation trench regions are further described below.

Sacrificial regions 3458 'and 3458 "defining the location of trench regions 3459' and 3459" (formed as described further below) may be blocked with a sacrificial non-critical mask layer (not shown) while the method forms trench 3469 using known directional selective etch methods, such as Reactive Ion Etching (RIE). The trench 3459 forms a first of two opposing vertical sidewalls in the X-direction to define one side of the NV NT diode cell. Alternatively, sacrificial region 3458, which defines the location of trench region 3459 (formed further below), may be selectively etched to sacrificial regions 3458' and 3458 ", without the need for a non-critical mask layer.

First, the method directionally selectively etches (removes) exposed regions (portions) of sacrificial region 3458 using known industry methods, as shown in fig. 34T.

Next, the method selectively etches exposed regions (portions) of the conformal insulator 3450' "using known industry methods and forms conformal insulators 3450-1 and 3450-2, as shown in fig. 34U.

Next, the method selectively etches exposed areas of nanotube element 3445 "and forms nanotube elements 3445-1 and 3445-2, as shown in FIG. 34U. Methods of etching nanotube elements are described in more detail in the incorporated patent references.

Next, the method selectively etches the exposed regions of the contact layer 3430 using known industry methods.

Next, the method selectively etches the exposed regions of the N + polysilicon layer 3425 using known industry methods.

Next, the method selectively etches the exposed regions of the N-polysilicon layer 3420 using known industry methods.

Next, the method selectively etches exposed regions of contact layer 3415 using known industry methods.

The method then etches the exposed regions of conductor layer 3410 using known industry methods to form trenches 3459. The directional etch stops on the surface of planar insulator 3403.

Next, the method fills and planarizes trench 3459 with an insulator such as TEOS using known industry methods to form insulator 3460, as shown in fig. 34V.

Next, the method forms a non-critical mask region (not shown) on the insulator 3460.

Then, the sacrificial regions 3458' and 3458 "are selectively etched (removed), as shown in fig. 34W. By removing sacrificial regions 3458 'and 3458 "and leaving insulator 3460 protected by a masking layer (not shown), the method forms trenches 3469' and 3469" using known directionally selective etching techniques, such as RIE. Trenches 3459' and 3459 "form second vertical (Z) sidewalls in the X-direction of the NV NT diode cells.

First, the method directionally selectively etches (removes) the exposed portions of the contacts 3440 'and 3440 "using known industry methods, and exposes portions of the top surface of the semiconductor layers 3435' and 3435" and defines the contact 3440-1 and 3440-2 regions, as shown in fig. 34X.

Next, the method selectively etches exposed portions of insulator regions 3435' and 3435 "using known industry methods and forms insulator regions 3435-1 and 3435-2.

Next, the method selectively etches exposed portions of contact regions 3430' and 3430 "using known industry methods and forms contact regions 3430-1 and 3430-2.

Next, the method selectively etches exposed portions of the N + polysilicon layers 3425' and 3425 "using known industry methods and forms N + polysilicon regions 3425-1 and 3425-2.

Next, the method selectively etches the exposed portions of the N-poly layers 3420' and 3420 "using known industry methods and forms N-poly regions 3420-1 and 3420-2, as shown in FIG. 34X.

Next, the process selectively etches exposed regions of contact layers 3415' and 3415 "using known industry methods, and forms contact regions 3415-1 and 3415-2.

The process then selectively etches the exposed portions of the conductive layers 3410' and 3410 "using known industry methods, and forms bitlines 3410-1(BL0) and 3410-2(BL 1). The directional etch stops on the surface of planar insulator 3403 as shown in figure 34X.

Next, the method deposits and planarizes an insulator such as TEOS and fills trench openings 3459 'and 3459 "with insulators 3460' and 3460", respectively, as shown in fig. 34Y.

Next, the method etches (removes) sacrificial regions 3455-1 and 3455-2.

Next, the method deposits and planarizes conductor 3465' to form upper layer contacts 3465-1 and 3465-2, as shown in FIGS. 34Z and 34 AA.

Next, the method deposits and planarizes conductor layer 3471 using known industry methods to form cross-section 3470, as shown in fig. 34 BB. The cross-section 3470 corresponds to the cross-section 2800 shown in fig. 28A. If the process fabrication begins with FIG. 34A 'instead of FIG. 34A, a cross-section (not shown) corresponding to cross-section 2800' shown in FIG. 28B is formed as further described above.

At this point in the process, cross-section 3470 shown in fig. 34BB has been fabricated and includes NV NT diode cells with dimensions defined as 1F in the X-direction (where F is the minimum feature size) and corresponding array bit lines. Next, cell dimensions to define dimensions in the Y-direction are formed by a directional trench etch process, similar to that described further above with respect to cross-section 3470 shown in fig. 34 BB. The trenches defining the dimension in the Y direction are substantially perpendicular to the trenches defining the dimension in the X direction. In this example, the cell characteristics in the Y direction do not require the self-alignment techniques described further above with respect to the X-direction dimension. The cross-section of the structure in the Y-direction is illustrated with respect to cross-section a-a' shown in fig. 34 BB.

Next, the method deposits and patterns a mask layer, such as mask layer 3473, on the surface of word line layer 3471, as shown in fig. 34 CC. The mask layer 3473 may be non-critically aligned to alignment marks in the planar insulator 3403. Openings 3474, 3474', and 3474 "in mask layer 3473 determine the location of the trench-directed etch region, which in this example is substantially perpendicular to a bit line, such as bit line 3410-1(BL 0).

Next, the method forms trenches 3475, 3475 ', and 3475 ", respectively, corresponding to openings 3474, 3474', and 3474" in mask layer 3473. Trenches 3475, 3475', and 3475 "form two sides of a vertical sidewall in the Y-direction, thereby defining two opposite sides of the NV NT diode cell, as shown in fig. 34 DD.

The method then directionally selectively etches (removes) the exposed portions of word line layer 3471 shown in FIG. 34DD using known industry methods to form word lines 3471-1(WL0) and 3471-2(WL1) shown in FIG. 34 DD.

Next, the process selectively etches the exposed portions of contact region 3465-1 shown in FIG. 34CC using known industry methods to form contacts 3465-1 'and 3465-1' as shown in FIG. 34 DD.

Next, the method selectively etches the exposed portions of contact area 3440-1, nanotube element 3455-1, and conformal insulator 3450-1 shown in FIG. 34BB using known industry methods to form contacts 3440-1 ' and 3440-1 ", conformal insulator regions (not shown in section A-A ' of FIG. 34 DD), and nanotube elements 3445-1 ' and 3445-1", as shown in FIG. 34 DD.

Next, the method selectively etches exposed regions of insulator 3435-1, nanotube element 3455-1, and conformal insulator 3450-1, shown in FIG. 34BB, using known industry methods to form insulator regions and conformal insulator regions (not shown in section A-A 'of FIG. 34 DD) and nanotube elements 3445-1' and 3445-1 "shown in FIG. 34 DD.

Next, the process selectively etches the exposed portions of contact regions 3430-1 and 3430-2 as shown in FIGS. 34BB and 34CC using known industry methods and forms contacts 3430-1 'and 3430-1 "as shown in FIG. 34DD (section A-A').

Next, the process selectively etches the exposed portions of N + polysilicon regions 3425-1 and 3425-2 as shown in FIG. 34BB using known industry methods, and forms N + polysilicon regions 3425-1 'and 3425-1 as shown in FIG. 34DD (section A-A').

Next, the process selectively etches the exposed portions of N-poly regions 3420-1 and 3420-2 as shown in FIG. 34BB and forms N-poly regions 3420-1 'and 3420-1 "as shown in FIG. 34DD (section A-A') using known industry methods.

The process then selectively etches the exposed portions of contact regions 3415-1 and 3415-2, shown in fig. 34BB, using known industrial processes and forms insulators 3415-1 'and 3415-1 "shown in fig. 34DD (cross-section a-a'). The directional etch stops at the surface of bit line 3410-1.

Next, the process deposits an insulator 3476 as shown in fig. 34EE using known industry methods. The insulator 3476 may be TEOS, for example.

The process then planarizes the insulator 3476 using known industry methods to form an insulator 3476 'and to form a cross-section 3470' as shown in fig. 34 FF. The cross-section 3470' shown in FIG. 34FF and the cross-section 3470 shown in FIG. 34BB are representative of two cross-sections of the same passivated NV NT diode vertically oriented cell. The cross-section 3470 shown in fig. 34BB corresponds to the cross-section 2800 shown in fig. 28A.

At this point in the process, where cross-sections 3470 and 3470' shown in FIGS. 34BB and 34FF, respectively, have been fabricated, the vertically-oriented channel length L of the non-volatile nanotube element_SW-CHAnd a horizontally oriented channel width W_SW-CHIs defined to include the entire NV NT diode cell size of 1F in the X-direction and 1F in the Y-direction, and the corresponding bit line and word line array lines. Cross-section 3470 is a cross-section of two adjacent vertically oriented cathode-to-nanotube type nonvolatile nanotube diode-based cells in the X-direction, and cross-section 3470' is a cross-section of two adjacent vertically oriented cathode-to-nanotube type nonvolatile nanotube diode-based cells in the Y-direction. Sections 3470 and 3470' include respective word lines and bit line array lines. The non-volatile nanotube diode forms a steering and storage element in each cell shown in cross-sections 3470 and 3470' that each occupy an area of 1F by 1F. The spacing between adjacent cells is 1F, so the cell period can be as low as 2F in both the X and Y directions. Thus, a bit can occupy as little as 4F ². At a technology node of, for example, 65nm, the cell area is less than 0.02um²。

Using diodes with vertical orientation and having cathode-to-NT switch connectionHorizontal orientationMethod for fabricating three-dimensional cell structure of non-volatile cell for NV NT device of NT switch

The method 2710 of FIG. 27A can be used to define support circuitry and interconnects similar to those described with respect to the memory 2600 of FIG. 26A, as further described above. The exemplary method 2710 employs well known semiconductor industry design and fabrication techniques to fabricate support circuits and interconnects 3501 in and on a semiconductor substrate, as shown in fig. 35A. The support circuits and interconnects 3501 may include, for example, FET devices in a semiconductor substrate and interconnects, such as vias and wires, on a semiconductor substrate.

Next, method 2730 shown in fig. 27B deposits and planarizes insulator 3503 on the surface of the support circuitry and interconnect 3501 layer.

Next, the method forms interconnect contacts 3507 through the planar insulator 3503, as shown in fig. 35A. Contacts 3507 through planar insulator 3503 make contact with support circuitry and interconnects 3501. The combination of support circuitry and interconnects 3501 and planarizing insulator 3503 is referred to as a memory support structure 3505, as shown in fig. 35A.

Next, the process deposits a conductor layer 3510, as shown in fig. 35A, typically 50 to 500nm thick, on the planarized surface of insulator 3503 using known industry methods. Contacts 3507 through the planar insulator 3503 connect the conductor layer 3510 with the supporting circuitry and interconnects 3501. Examples of materials for conductor layer 3510 and contacts 3507 are elemental metals such as Al, Au, W, Cu, Mo, Pd, Ni, Ru, Ti, Cr, Ag, In, Ir, Pb, Sn, and metal alloys such as TiAu, TiCu, TiPd, Pbin, and TiW, other suitable conductors, or conductive nitrides, oxides, or silicides such as RuN, RuO, TiN, TaN, CoSi_xAnd TiSi_xMaterials such as those used for the conductive layer 3410 may be used to form the array lines and also to form the anode of the schottky diode.

Next, the method deposits a N polysilicon layer 3520 with a thickness of 10nm to 500nm on the surface of the conductor 3510. The N-polysilicon layer 3520 may be doped with arsenic or phosphorous in the range of, for example, 10¹⁴To 10¹⁷Dopant atom/cm³. N-polysilicon layer 3520 may be used to form the cathode of the schottky diode. In addition to the doping level, the polysilicon grain size (or grain structure) of the N-polysilicon layer 3420 may also be controlled by known industrial deposition methods. Furthermore, known industrial SOI deposition methods can be used which result in the polycrystalline silicon region being monocrystalline (no longer polycrystalline), or nearly monocrystalline.

Next, the method deposits an N + polysilicon layer 3525 on the surface of the N polysilicon layer 3520, as shown in fig. 35A, to form an ohmic contact layer. The N + polysilicon layer 3525 is typically doped with arsenic or phosphorous to, for example, 10²⁰Dopant atom/cm³And has a thickness of, for example, 20 to 400 nm.

Next, the method deposits an insulator layer 3530 over the N + layer 3525, as shown in fig. 35B. The thickness of the insulator layer 3530 can vary, for example, from 10nm to a thickness greater than 400 nm. Insulator 3530 can be formed from any insulator material known in the CMOS industry or the packaging industry, such as SiO₂、SiN、Al₂O₃BeO, polyimide, PSG (phosphosilicate glass), photoresist, PVDF (polyvinylidene fluoride), sputtered glass, epoxy glass, and other dielectric materials and combinations of dielectric materials, such as Al-coated₂O₃PVDF of the layer. U.S. patent application No.11/280,786 provides some examples of a variety of dielectric materials.

At this point in the manufacturing process, the method deposits a contact layer 3535 on the surface of the insulator layer 3530, as shown in fig. 35B. The thickness of the contact layer 3535 may be, for example, 10 to 500 nm. The contact layer 3535 may be formed using: al, Au, W, Cu, Mo, Pd, Ni, Ru, Ti, Cr, Ag, In, Ir, Pb, Sn, and metal alloys such as TiAu, TiCu, TiPd, Pbin, and TiW, other suitable conductors, or conductive nitrides, oxides, or silicides such as RuN, RuO, TiN, TaN, CoSi _xAnd TiSi_x。

Next, the method directionally etches an opening 3537 through the contact layer 3535 and the insulator layer 3530 to the top surface of the N + polysilicon layer 3525, as shown in fig. 35C. The directional etch may use, for example, RIE.

Next, the method deposits a conformal insulator layer 3540' in contact with a surface region of the contact 3535 and the N + polysilicon layer 3525 and on exposed sidewall surface regions of the contact 3535 and insulator 3530, as shown in fig. 35D. The conformal insulator 3540' can be, for example, 5 to 250nm thick, and can be formed of any insulator material known in the CMOS industry or the packaging industry, such as SiO₂、SiN、Al₂O₃BeO, polyimide, PSG (phosphosilicate glass), photoresist, PVDF (polyvinylidene fluoride), sputtered glass, epoxy glass, and other dielectric materials and materials for dielectric materialsCombinations, e.g. covered with Al₂O₃PVDF of the layer. Insulator 3540' is deposited to a thickness that forms the channel length region of the nanotube element, as described further below with respect to fig. 35I, and insulates the contact, as described further below with respect to fig. 35G, from contacting contact 3535.

Next, the method directionally etches insulator 3540' using known industry methods such as RIE and forms sidewall spacer regions 3540 as shown in fig. 35E, which define nanotube element channel lengths, as further described below with reference to fig. 35I.

Next, the method deposits and planarizes conductor 3545' to form contact 3545, as shown in fig. 35F and 35G.

Next, the method deposits conformal nanotube element 3550 on a coplanar surface formed by contact 3535, sidewall 3540, and contact 3545, as shown in fig. 35H. Conformal nanotube element 3550 can be, for example, 0.5 to 20nm thick and can be fabricated as a single layer or multiple layers using deposition methods such as spin-on and spray-on methods. Nanotube element fabrication methods are described in the incorporated patent references.

Next, the method deposits an insulator layer 3555 on nanotube element 3550 as an insulating and protective layer, as shown in fig. 35I. Channel length L of nanotube element 3550_SW-CHDefined by the surface dimensions of sidewall spacers 3540. The insulator layer 3555 can be, for example, 5 to 200nm thick and can be formed of any suitable known insulator material in the CMOS industry or the packaging industry, e.g., SiO₂、SiN、Al₂O₃BeO, polyimide, PSG (phosphosilicate glass), photoresist, PVDF (polyvinylidene fluoride), sputtered glass, epoxy glass, and other dielectric materials and combinations of dielectric materials, such as Al-coated₂O₃PVDF of the layer. Dielectric material selection with respect to nanotube elements is described in U.S. patent application No.11/280,786.

Next, the method patterns and etches the opening 3560 as shown in fig. 35J to the top of the contact 3535. The method etches a portion of opening 3560 using known industry methods. The method then etches the exposed areas of nanotube element 3550 using, for example, ashing (ashing) or other means described in the incorporated patent references.

Next, the method deposits and planarizes conductor 3565' to form contact 3565, as shown in fig. 35K and 35L.

Next, mask layer 3570 is patterned in the X-direction, as shown in fig. 35L, and defines openings for directional selective trench etching to form trench regions 3572 and 3572', as further described below with reference to fig. 35M.

Next, the method selectively etches exposed portions of the insulator 3555 using known industry methods and forms insulator regions 3555'.

The method then selectively etches exposed areas of nanotube element 3550 and forms nanotube element 3550', as shown in fig. 35M. Methods of etching nanotube elements are described in more detail in the incorporated patent references.

Next, the process selectively etches exposed portions of the contacts 3535 using known industry methods and forms contact regions 3535'.

Next, the method selectively etches exposed portions of insulator 3530 and forms insulator regions 3530'.

Next, the method selectively etches exposed portions of the N + polysilicon layer 3525 using known industry methods and forms N + polysilicon regions 3525'.

Next, the method selectively etches exposed portions of N-polysilicon layer 3520 using known industry methods and forms N-polysilicon region 3520', as shown in fig. 35M.

The process then selectively etches the exposed portions of conductor layer 3510 using known industry methods and forms bit line 3510' (BL 0). The directional etch stops on the planar insulator 3503 surface as shown in fig. 35M.

Next, a method deposits an insulator 3574, such as TEOS, to fill the trench openings 3572 and 3572 ', and then the method planarizes the insulator 3574 to form an insulator 3574', as shown in fig. 35N and 35O.

Next, the method deposits and planarizes a conductor layer 3575 corresponding to array word lines WL0 using known industry methods to form a cross-section 3580, as shown in fig. 35P. Section 3580 corresponds to section 2800 "shown in fig. 28C. The word line WL0 is oriented along the X-direction and the bit line BL0 is oriented along the Y-axis, as further described below.

At this point in the process, cross-section 3580, shown in FIG. 35P, has been fabricated and includes NV NT diode cells having dimensions defined in the X-direction to 2-3F (where F is the minimum feature size) along with the corresponding array bit lines. Next, cell dimensions to define dimensions in the Y-direction are formed by a directional trench etch process, similar to that described further above with respect to cross-section 3580 shown in fig. 35P. The trenches defining the dimension in the Y direction are substantially perpendicular to the trenches defining the dimension in the X direction. The cross-section of the structure in the Y-direction is described with respect to the cross-section X-X' shown in fig. 35P.

Next, the method deposits and patterns a mask layer, such as mask layer 3581, on the surface of word line layer 3575', as shown in fig. 35Q. The mask layer 3581 may be an alignment mark that is non-critically aligned into the planar insulator 3503. The openings in the mask layer 3581 determine the location of the directionally etched regions of the trench, which in this case are substantially perpendicular to a bit line, such as bit line 3510' (BL 0).

Next, the method forms trenches 3582 and 3582' corresponding to the openings in the mask layer 3581. Trenches 3582 and 3582' form two sides of vertical sidewalls in the Y-direction, thereby defining two opposite sides of the NV NT diode cell, as shown in fig. 35Q.

Next, the method directionally selectively etches (removes) the exposed portions of word line layer 3575 shown in fig. 35P using known industry methods to form word line 3575 '(WL 0) shown in fig. 35Q (cross-section X-X').

Next, the method selectively etches exposed portions of insulator 3555 ' as shown in fig. 35Q (cross-section X-X ') using known industry methods, and also selectively etches exposed portions of contacts 3565 (not shown in fig. 35Q) to form insulator regions 3555 "as shown in fig. 35Q, and also forms modified contacts 3565, which are not shown in fig. 35Q (cross-section X-X ').

The method then selectively etches (removes) the exposed portions of nanotube element 3550', forming nanotube element 3550 ", as shown in fig. 35Q. Methods of etching nanotube elements are described in more detail in the incorporated patent references.

Next, the method selectively etches the exposed portions of contacts 3545, forming contacts 3545 'as shown in fig. 35Q (section X-X'); the method also selectively etches exposed portions of the sidewall spacers 3540 to form modified sidewall spacers 3440, not shown in fig. 35Q; and the method also selectively etches exposed portions of the contacts 3535 to form modified contacts 3535 that are not shown in fig. 35Q.

Next, the method selectively etches exposed portions of insulator 3530 ' to form a modified insulator 3530 ', which is not shown in fig. 35Q (section X-X ').

Next, the process selectively etches the exposed portion of the illustrated N + polysilicon region 3525 'using known industry methods and forms an N + polysilicon region 3525 "as illustrated in fig. 35Q (cross-section X-X').

Next, the method selectively etches the exposed portion of the illustrated N polysilicon region 3520 'using known industry methods and forms an N + polysilicon region 3520 "as illustrated in fig. 35Q (cross-section X-X'). The directionally selective etch stops at the surface of bit line 3510' (BL 0).

Next, the process deposits an insulator 3585 using known industry methods, as shown in fig. 35R. Insulator 3585 can be, for example, TEOS.

The process then planarizes insulator 3585 using known industry methods to form insulator 3585 'and form cross-section 3580' as shown in fig. 35S. Section 3580' shown in fig. 35S and section 3580 shown in fig. 35P are representative of two sections of the same embodiment of a passivated NV NT diode with a vertically oriented diode and a horizontally non-volatile nanotube switch. The cross-section 3480 shown in fig. 35P corresponds to the cross-section 2800 "shown in fig. 28C.

Method of manufacturing non-volatile memory using NVNT diode device with anode-to-NT switch connection

Exemplary method 3000 shown in fig. 30A and 30B can be used in embodiments of fabricating memory using NV NT diode devices having anode-to-NT switch connectionsVertically orientedNV NT switches, such as those shown in section 3100 shown in FIG. 31A, section 3100' shown in FIG. 31B, and section 3100 "shown in FIG. 31C, as further described below with reference to FIG. 36. Structures such as sections 3000, 3000', and 3000 "may be used to fabricate the memory 2900 schematically illustrated in fig. 29A.

Exemplary methods of fabricating cross-sections 3000, 3000', and 3000 "may be performed using critical alignment in a Y-direction process step. There is no critical alignment in the X direction because the distance between the trenches in this example determines the width of the nanotube element. However, by using a method similar to that described further below, the width of the nanotube element with respect to the Y-direction can be formed to be less than the trench-to-trench spacing. In the Y-direction, the critical alignment requirement can be eliminated by using a method of forming self-aligned inner cell vertical sidewalls that define the vertical nanotube channel element location, the vertical channel element length (L) _{SW_CH}) And forming nanotube channel element contacts with respect to trench sidewalls that are later etched in the process to define outer cell dimensions using the fabrication method described further below with reference to fig. 36. In this example, the NV NT diode cell structure occupies a minimum dimension F in the X and Y directions, where F is the minimum lithographic dimension. In this example, the inner partIs positioned at a distance of about R from the trench sidewalls by a self-aligned technique, the trench sidewalls being separated by a distance F and defining an outer cell dimension, as further described below with reference to fig. 36A-36 FF. FIGS. 36A-36FF are shown with a pitch R of about F/2. However, using methods of self-aligned techniques, such as described further below with reference to FIGS. 36A-36FF, the vertical sidewalls may be positioned at any location R within the cell region of width F using R values, e.g., F/4, F/3, F/2, 3F/4, etc. In some embodiments, R is not specifically related to F.

Using diodes with vertical orientation and having anode-to-NT switch connectionsVertically orientedMethod for fabricating three-dimensional cell structure of non-volatile cell for NV NT device of NT switch

The example method 3010 of fig. 30A may be used to define support circuits and interconnects similar to that described further above with respect to the memory 2900 of fig. 29A. The method 3010 applies well-known semiconductor industry technology design and fabrication techniques to fabricate support circuits and interconnects 3601 in and over a semiconductor substrate, as shown in fig. 36A. The support circuits and interconnects 3601 include FET devices in a semiconductor substrate and interconnects, such as vias and wires, on a semiconductor substrate.

Next, method 3030 shown in fig. 30B deposits and planarizes insulator 3603 on the surface of the support circuit and interconnect 3601 layers. The interconnection of devices (not shown in fig. 36A) through the planar insulator 3603 is further illustrated below with reference to fig. 35A-35S. The combination of support circuitry and interconnects 3601 and planarization insulator 3603 is referred to as a memory support structure 3605, as shown in fig. 34A.

Next, the method deposits a conductor layer 3610 on the planarized surface of insulator 3603, as shown in fig. 36A, typically 50 to 500nm thick, using known industry methods. Examples of conductor layer materials are elemental metals such as Al, Au, W, Cu, Mo, Pd, Ni, Ru, Ti, Cr, Ag, In, Ir, Pb, Sn, and metal alloys such as TiAu, TiCu, TiPd, Pbin, and TiW, other suitable conductors, or conductive nitrides, oxides, or silicides such as，RuN、RuO、TiN、TaN、CoSi_xAnd TiSi_x。

Next, the method deposits an N + polysilicon layer 3620 on the surface of the conductor layer 3610, as shown in fig. 36A, to form an ohmic contact layer. The N + polysilicon layer 3620 is typically doped with arsenic or phosphorous to, for example, 10²⁰Dopant atom/cm³And has a thickness of, for example, 20 to 400 nm.

Next, the method deposits an N polysilicon layer 3625 with a thickness of 10nm to 500nm on the surface of the N + polysilicon layer 3620. The N-polysilicon layer 3625 may be doped with arsenic or phosphorous, for example, in the range of 10 ¹⁴To 10¹⁷Dopant atom/cm³. The N-polysilicon layer 3625 may be used to form the cathode of the schottky diode. In addition to the doping level, the polysilicon grain size (or grain structure) of the N-polysilicon layer 3625 may also be controlled by known industrial deposition methods. Furthermore, known industrial SOI deposition methods can be used which result in the polycrystalline silicon region being monocrystalline (no longer polycrystalline), or nearly monocrystalline.

Next, the method deposits a contact layer 3630 on the surface of the N-polysilicon layer 3625 to form a schottky diode anode layer. Contact layer 3630 may also be used to form the lower contacts for the nanotube element, as further described below with reference to fig. 36I. The thickness of the contact layer 3630 is, for example, in the range of 10 to 500 nm. The contact layer 3630 may use a material similar to that used to form the conductor layer 3610; alternatively, the contact layer 3630 material can be selected to optimize the anode material to enhance schottky diode properties, such as reducing forward voltage drop and/or reducing diode leakage. Anode contact 3630 can include Al, Ag, Au, Ca, Co, Cr, Cu, Fe, Ir, Mg, Mo, Na, Ni, Os, Pb, Pd, Pt, Rb, Ru, Ti, W, Zn, and other elemental metals. In addition, silicides, e.g., CoSi, may be used ₂、MoSi₂、Pd₂Si、PtSi、RbSi₂、TiSi₂、WSi₂And ZrSi₂(ii) a Alternatively, contact layer 3630 can be layered to include a conductive material on the lower layer to optimize schottky diode characteristics and a conductive material on the upper layer to optimize ohmic contact to the nanotube elementA material.

At this point in the process, the remaining methods may be used to fabricate NV NT diodes using schottky diode based anode-to-NT switching structures such as that shown in fig. 31A. However, as further described above with reference to, for example, fig. 31B, NV NT diodes may be formed using PN diodes instead of schottky diodes. Thus, alternatively, a PN diode alternative fabrication method is shown in fig. 34A'.

The method 3000 described further above and with reference to fig. 36A can also be used to describe the fabrication of fig. 36A'. The support circuit and interconnect 3601 'shown in fig. 36A' corresponds to the support circuit and interconnect 3601 shown in fig. 36A, except that possibly small changes may be introduced into the various circuits to accommodate differences in diode characteristics, such as the turn-on voltage between schottky diodes and PN diodes.

Next, the method deposits a planarizing insulator 3603 ' on the surface of the support circuitry and interconnects 3601 ', as shown in fig. 36A '. The planarized insulator 3603 'corresponds to the planarized insulator 3603 except that possibly small changes may be introduced into the insulator 3603' to accommodate differences in diode characteristics. The memory support structure 3605 'is thus similar to the support structure 3605, except that small changes may be introduced to the support circuitry and interconnects 3601' and the planarization insulator 3603 ', as described above with reference to fig. 36A'.

Next, the method deposits a conductor layer 3610 ' in contact with the surface of the planarized insulator 3603 ', as shown in fig. 36A ', which is similar in thickness and material to the conductor layer 3610 described further above with reference to fig. 36A.

Next, the method deposits an N + polysilicon layer 3620 ' on the surface of the conductor layer 3610 ', as shown in fig. 36A ', to form an ohmic contact layer. The N + polysilicon layer 3620' is typically doped with arsenic or phosphorous to, for example, 10²⁰Dopant atom/cm³And has a thickness of, for example, 20 to 400 nm.

Next, an N polysilicon layer 3625' with a thickness of 10nm to 500nm is deposited on the N + polysilicon layer3620'. The N-polysilicon layer 3625' may be doped with arsenic or phosphorous, for example, in the range of 10¹⁴To 10¹⁷Dopant atom/cm³. The N-polysilicon layer 3625' may be used to form the cathode of the schottky diode. In addition to the doping level, the polysilicon grain size (or grain structure) of the N-polysilicon layer 3625' may also be controlled by known industrial deposition methods. Furthermore, known industrial SOI deposition methods can be used which result in the polycrystalline silicon region being monocrystalline (no longer polycrystalline), or nearly monocrystalline.

Next, the method deposits a P-polysilicon layer 3627 with a thickness of 10nm to 500nm on the surface of the N-polysilicon layer 3625 ', as shown in fig. 36A'. The P-polysilicon layer 3627 may be doped with boron, for example, in the range of 10 ¹⁴To 10¹⁷Dopant atom/cm³. The P-poly layer 3627 may be used to form the anode of the PN diode. In addition to the doping level, the polysilicon crystal size of the P-polysilicon layer 3627 can also be controlled by known industrial deposition methods. Furthermore, known industrial SOI deposition methods can be used which result in the polycrystalline silicon region being monocrystalline (no longer polycrystalline), or nearly monocrystalline.

Next, the method deposits a contact layer 3630 'on the surface of the P-polysilicon layer 3627, forming an ohmic contact between the contact layer 3630' and the P-polysilicon layer 3627. Contact layer 3630' may also be used to form the lower contacts for the nanotube element, as further described below with reference to fig. 36I.

At this point in the process, the remaining methods may be used to fabricate NV NT diodes using PN diode based anode-to-NT switching structures such as that shown in fig. 31B. However, as further described above with reference to, for example, fig. 31C, NV NT diodes may be formed using schottky diodes and PN diodes in parallel. Thus, alternatively, an alternative method of manufacturing a combined parallel schottky diode and PN diode is shown in fig. 34A ".

The method 3000 described further above and with reference to fig. 36A may also be used to describe the fabrication of fig. 36A ". The support circuit and interconnect 3601 "shown in fig. 36A" corresponds to the support circuit and interconnect 3601 shown in fig. 36A, except that possibly small changes may be introduced in the individual circuits to accommodate differences in diode characteristics, such as the turn-on voltage between a schottky diode and a combined parallel schottky diode and PN diode, for example.

Next, the method deposits a conductor layer 3610 "in contact with the surface of the planarized insulator 3603", as shown in fig. 36A ", which is similar in thickness and material to the conductor layer 3610, as further described above with reference to fig. 36A.

Next, the method deposits an N + polysilicon layer 3620 "on the surface of the conductor layer 3610", as shown in fig. 36A ", to form an ohmic contact layer. The N + polysilicon layer 3620 "is typically doped with arsenic or phosphorous to, for example, 10²⁰Dopant atom/cm³And has a thickness of, for example, 20 to 400 nm.

Next, the method deposits an N polysilicon layer 3625 "with a thickness of 10nm to 500nm on the surface of the N + polysilicon layer 3620". The N-polysilicon layer 3625 "may be doped with arsenic or phosphorous, for example, in the range of 10¹⁴To 10¹⁷Dopant atom/cm³. The N-polysilicon layer 3625 "may be used to form the cathodes of the schottky diode and the PN diode in parallel. In addition to the doping level, the polysilicon grain size (or grain structure) of the N-polysilicon layer 3625 "may also be controlled by known industrial deposition methods. Furthermore, known industrial SOI deposition methods can be used which result in the polycrystalline silicon region being monocrystalline (no longer polycrystalline), or nearly monocrystalline.

At this point in the process, the remaining method may be used to fabricate a NV NT diode using a schottky diode and a PN diode in parallel to form an anode-to-NT switch structure such as that shown in fig. 31C. If the contact layer 3630 is omitted from the structure, a schottky diode and a PN diode can be formed in parallel, as further described below with reference to fig. 36I.

If contact layer 3630 is omitted from the structure, a schottky diode and a PN diode are formed in parallel because a nanotube element, such as nanotube element 3645 described further below with reference to fig. 36I, will contact N-polysilicon layer 3625. A subset of P-type semiconductor nanotube elements, NT elements 3645, will be in physical and electrical contact with N-polysilicon layer 3625 and will form a PN diode-anode and, together with N-polysilicon layer 3625 forming the cathode, a PN diode. Metallic nanotube elements, a subset of NT elements 3645, are also in physical and electrical contact with N-polysilicon layer 3625 and form a schottky diode-anode, and N-polysilicon layer 3625 forms the cathode of a schottky diode having a schottky diode junction as part of the parallel combination of PN and schottky diode junctions.

The description of the fabrication method continues with respect to the schottky diode-based structure described with reference to fig. 36A to form an NV NT diode cell structure corresponding to cross-section 3100 shown in fig. 31A. However, this fabrication method may also be applied to the PN diode-based structure described with reference to fig. 36A 'to form an NV NT diode cell structure corresponding to the cross-section 3100' shown in fig. 31B. In addition, this manufacturing method is also applicable to the structure with reference to fig. 36A "to form an NVNT diode cell structure corresponding to the cross section 3100" shown in fig. 31C.

At this point in the process, fabrication continues by using a method of depositing an insulator layer 3635 over the contact layer 3630 (as shown in fig. 36B). The thickness of the insulator layer 3635 can be well controlled and used to determine the channel length of the vertically oriented non-volatile nanotube switch, as further described below with reference to fig. 36I. The thickness of the insulator layer 3635 can vary from, for example, less than 5nm to a thickness greater than 250 nm. Insulator 3635 can be formed from any suitable known insulator material in the CMOS industry or the packaging industry, for example, SiO₂、SiN、Al₂O₃BeO, polyimide, PSG (phosphosilicate glass), photoresist, PVDF (polyvinylidene fluoride), sputtered glass, epoxy glass, and other dielectric materials and combinations of dielectric materials, such as Al-coated₂O₃PVDF of the layer. U.S. patent application No.11/280,786 includes some examples of various dielectric materials.

Next, the method deposits a contact layer 3640 on the insulator layer 3635, as shown in fig. 36B. The thickness of contact layer 3640 can be in a range, for example, of 10 to 500nm, and contact layer 3640 can be formed using a variety of conductor materials, i.e., similar to the materials described further above with respect to contact 3630.

Next, the method deposits a sacrificial layer 3641 on the contact layer 3640, as shown in fig. 36C. The thickness of sacrificial layer 3641 can be in the range 10-500 nm and sacrificial layer 3641 is formed using a conductor, semiconductor, or insulator material, i.e., such as described further above with respect to contact layer 3630, semiconductor layers 3620 and 3625, and insulator layer 3635.

Next, the process deposits and patterns a mask layer using known industry methods, such as mask layer 3642 deposited on the top surface of sacrificial layer 3641 as shown in FIG. 36C. The mask openings may be aligned to, for example, alignment marks in the planar insulating layer 3603; this alignment is non-critical.

Then, the method directionally etches the sacrificial layer 3641 using known industrial methods to form an opening through the sacrificial layer 3641 stopping on the surface of the contact layer 3640, the opening having a dimension D in the Y direction_OPEN-1’(D_{1 'from mouth'}) As shown in fig. 36D. As described further below, two memory cells are formed, including vertical nanotube channel elements that are self-aligned and positioned relative to the vertical edges of sacrificial regions 3641' and 3641 ". Dimension D in Y direction_OPEN-1’Is about 3F, where F is the minimum lithographic dimension. For the 65nm technology node, D_OPEN-1’195nm, which is non-minimum and therefore non-critical dimension on any technology node. At this point in the process, sidewall spacer techniques are used to locate vertical sidewalls at the inner surfaces R from the sacrificial regions 3641' and 3641 ", as described further below.

Next, the method deposits a conformal sacrificial layer 3643, as shown in fig. 36E. The thickness of the conformal sacrificial layer 3643 may be selected to be R, which in this example is selected to be about F/2. In this example, since R is about F/2, and since F is about 65nm, conformal sacrificial layer 3643 is about 32.5nm thick. The conformal sacrificial layer 3643 may be formed using a conductor, semiconductor, or insulator material, i.e., similar to the material used to form the sacrificial layer 3641 as described further above.

Next, the process directionally etches conformal sacrificial layer 3643 using known industry methods such as Reactive Ion Etching (RIE) to form a feature with dimension D_OPEN-2’(D_{2 'from mouth'}) The opening 3644 and the sacrificial regions 3643 ' and 3643 ", the sacrificial regions 3643 ' and 3643" both have vertical sidewalls that are self-aligned and separated from the inner vertical sidewalls of the sacrificial regions 3641 ' and 3641 "by a distance R in the Y-direction, as shown in fig. 36F. The distance R in this case is equal to about F/2, or about 32.5 nm. Dimension D of opening 3644_OPEN-2’About 2F, or about 130nm for a 65nm technology node, which is a non-critical dimension.

Next, the method directionally etches openings through the contact layer 3640 to the top surface of the insulator layer 3635. An opening having a dimension D is formed in the contact layer 3640 using a directional etch such as RIE_OPEN-2’About 2F (130 nm in this example), and sidewall contact regions 3640' and 3640 "are formed, as shown in fig. 36G.

Next, the method directionally etches openings through insulator layer 3635 to the top surface of contact layer 3630. An opening 3644' having a dimension D is formed in the insulator layer 3635 using a directional etch such as RIE_OPEN-2’Is about 2F (130 nm in this example) and forms insulator regions 3635' and 3635 ", as shown in fig. 36H.

Next, the method deposits conformal nanotube element 3645 vertically (Z) on the sidewalls of opening 3644', as shown in fig. 36I. The size of opening 3644' is approximately the same as the size of opening 3644. Conformal nanotube element 3645 can be, for example, 0.5 to 20nm thick and can be fabricated as a single layer or multiple layers using deposition methods such as spin-on and spray-on methods. Nanotube element fabrication methods are described in more detail in the incorporated patent references.

Due to the sidewall phase of nanotube element 3645 with contact layer 3630 and sidewall contact regions 3640' and 3640 ″Contacts separating the thickness of insulator regions 3635 'and 3635 ", respectively, so that two non-volatile nanotube switch channel regions are formed in part (channel width not yet defined) having a channel length L in the Z-direction corresponding to the thickness of insulator regions 3635' and 3635" in the range of 5nm to 250nm as shown in fig. 36I_SW-CH. The vertical (Z-axis) portion of nanotube element 3645 is separated from the inner vertical sidewalls of sacrificial regions 3641' and 3641 "by a self-aligned distance R. Such partially formed vertical nonvolatile nanotube switches are analogous to the vertically oriented nonvolatile nanotube elements 765 and 765' of memory storage areas 760A and 760B, respectively, shown in FIG. 7B. Conformal nanotube element 3645 also makes contact with sacrificial regions 3643 'and 3643 "and sacrificial regions 3641' and 3641", as shown in FIG. 36I.

Next, the method deposits a conformal insulator layer 3650 on nanotube element 3645 as an insulating and protective layer, and reduces opening 3644' to opening 3651, as shown in fig. 36J. Opening 3651 is similar to opening 3644' except that conformal insulator 3650 and conformal nanotube element 3645 are added. Conformal insulator 3650 can be, for example, 5 to 200nm thick and can be formed of any insulator material known in the CMOS industry or the packaging industry, such as SiO₂、SiN、Al₂O₃BeO, polyimide, PSG (phosphosilicate glass), photoresist, PVDF (polyvinylidene fluoride), sputtered glass, epoxy glass, and other dielectric materials and combinations of dielectric materials, such as Al-coated₂O₃PVDF of the layer. Insulator 3650 is deposited to a thickness sufficient to ensure protection of nanotube element 3645 from High Density Plasma (HDP) deposition.

At this point in the process, it is desirable to partially fill opening 3651 by increasing the bottom portion of insulator 3650 thickness vertically (Z-direction) on horizontal surfaces with little or no thickness increase on insulator 3650 sidewalls (vertical surfaces) as described above. The thickness of the additional dielectric material is not critical. The additional dielectric material may be the same as that of conformal insulator 3650 or may be a different dielectric material. The selection of dielectric materials with respect to nanotube elements is described in more detail in U.S. patent application No.11/280,786.

Next, the method directionally deposits insulator material in opening 3651 using known industrial methods such as directional HDP insulator deposition and increases insulator thickness primarily on horizontal surfaces in fig. 36K (e.g., insulator 3650 'in opening 3651) and on the top surface, forming opening 3651'.

Next, the method deposits and planarizes an insulator 3652, such as TEOS, filling the opening 3651', as shown in fig. 36L.

Next, the method planarizes the structure shown in fig. 36L to remove a top portion of insulator 3650' and a top portion of underlying nanotube element 3645, as shown in fig. 36M. The tops of sacrificial regions 3641 ', 3641 ", 3643', and 3643" may be used as CMP etch stop reference layers. Insulator 3650 "is the same as insulator 3650', except that the top horizontal layer has been removed. Nanotube element 3645' is the same as nanotube element 3645 except that the top horizontal layer has been removed. Insulator 3652' is the same as insulator 3652 except that the insulator thickness has been reduced.

The process then etches (removes) sacrificial regions 3643 'and 3643 "and insulator 3652'. The exposed vertical sidewalls of nanotube element 3645' and conformal insulator 3650 "remain as shown in fig. 36N.

Next, the method etches (removes) the exposed portions of nanotube element 3645', forming nanotube element 3645 ", as shown in FIG. 36O. Methods of forming nanotube elements are described in more detail in the incorporated patent references.

Then, a method such as directional etching removes the exposed portion of insulator 3650 'to form insulator 3650' ", as shown in fig. 36O.

At this point in the process, the sidewall spacer method is applied as further described below to form a self-aligned sacrificial region to be further replaced by a conductor material in the fabrication process described further below to form an upper portion of the nanotube element contact, and also to define a self-aligned trench region for defining a self-aligned cell dimension in the Y-direction, as further exemplified below. The use of sidewall spacer methods to form self-aligned structures without the need for masking and alignment can result in cell areas of reduced size.

In this example, referring to fig. 36P and 36Q, a self-aligned sacrificial region of X dimension F is formed using a method similar to that used in fig. 36E and 36F. Next, the method deposits a conformal sacrificial layer 3655, as shown in fig. 36P. The thickness of the conformal sacrificial layer 3655 is selected to be F. In this example, since F is about 65nm, the thickness of conformal sacrificial layer 3655 is about 65 nm. Conformal sacrificial layer 3655 can be formed using a conductor, semiconductor, or insulator material, i.e., similar to the materials used to form sacrificial layers 3641 and 3643 as described further above.

Next, the process directionally etches conformal sacrificial layer 3655 using known industry methods such as Reactive Ion Etching (RIE), forming openings 3651 "with a size of about F (about 65nm in this example), as shown in FIG. 36Q. The inner sidewalls of opening 3651 "are self-aligned to the inner walls of sacrificial regions 3641' and 3641" and are separated by a distance of about F. Such an inner wall would serve to form one side of the upper portion of the nanotube contact area, as described further below, and define one side of the cell in the Y-direction.

Next, the method deposits and planarizes the sacrificial layer to form sacrificial regions 3656 coplanar with sacrificial regions 3655 ', 3655 ", 3641', and 3641", as shown in fig. 36R.

Next, the method applies a CMP etch to reduce the thickness of sacrificial region 3656 to form sacrificial region 3658; reducing the thickness of sacrificial regions 3655' and 3655 ", respectively, to form sacrificial regions 3655-1 and 3655-2; and reducing the thickness of sacrificial regions 3641 'and 3641 ", respectively, to form sacrificial regions 3658' and 3658", as shown in fig. 36. The thickness values of the coplanar sacrificial regions 3658, 3658', 3655-1, and 3655-2 are in the range, for example, 10nm to 200 nm.

At this point in the process, sacrificial regions 3655-1 and 3655-2 may be used as a mask layer for directional etching of the trenches using a method to define the outer cell dimensions in the Y-direction for a 3D cell using one NVNT diode with cathode-to-nanotube connections. The trench 3659 is formed first and then filled with insulator and planarized. Trenches 3659', and 3659 "are then formed simultaneously, and then filled and planarized as described further below. Other corresponding trenches (not shown) are also etched in forming the memory array structure. Exemplary method steps may be used to form trench regions 3659, 3659', and 3659 "and then fill the trenches to form isolation trench regions, as described further below.

Sacrificial regions 3658 'and 3658 "defining the location of trench regions 3659' and 3659" (formed as described further below) may be blocked with a sacrificial non-critical mask layer (not shown) while the process forms trenches 3659 using known directional selective etch processes such as Reactive Ion Etching (RIE). Trench 3659 forms a first of two opposing vertical sidewalls in the Y-direction to define one side of the sense NV NT diode cell. Alternatively, sacrificial regions 3658 defining the location of trench regions 3659 (formed further below) may be selectively etched to sacrificial regions 3658' and 3658 ″ without the need for a non-critical mask layer.

First, the process directionally selectively etches (removes) exposed regions (portions) of sacrificial region 3658 using known industry methods, as shown in fig. 36T.

Next, the process selectively etches exposed regions (portions) of conformal insulator 3650 "' using known industry methods and forms conformal insulators 3650-1 and 3650-2, as shown in fig. 36U.

Next, the method selectively etches exposed areas of nanotube element 3645 "and forms nanotube elements 3645-1 and 3645-2, as shown in FIG. 36U. Methods of etching nanotube elements are described in more detail in the incorporated patent references.

Next, the method selectively etches exposed regions of contact layer 3630 using known industry methods, forming contact layer regions 3630' and 3630 ".

Next, the process selectively etches the exposed regions of the N-polysilicon layer 3625 using known industry methods, forming regions 3625' and 3625 ".

Next, the process selectively etches the exposed regions of the N + polysilicon layer 3620 using known industry methods, forming regions 3620' and 3620 ".

The process then etches the exposed regions of conductor layer 3610 using known industry methods to form conductor regions 3610' and 3610 ". The directional etch stops at the surface of the planar insulator 3603.

Next, the process fills and planarizes trench 3659 with an insulator such as TEOS using known industry methods, forming insulator 3660 as shown in fig. 36V.

Next, the method forms a non-critical mask region (not shown) on the insulator 3660.

Next, sacrificial regions 3658' and 3658 "are selectively etched, as shown in FIG. 36W. By removing sacrificial regions 3658 'and 3658 "and leaving insulator 3660 protected by a masking layer (not shown), the method forms trenches 3659' and 3659" using known directionally selective etching techniques such as RIE, as shown in fig. 36X. Trenches 3659' and 3659 "form second vertical (Z) sidewalls in the Y-direction of the NV NT diode cells.

To form trenches 3659 ' and 3659 ", the process directionally selectively etches (removes) the exposed portions of contacts 3640 ' and 3640" using known industry methods and exposes a portion of the top surface of insulator layers 3635 ' and 3635 "and defines contact 3640-1 and 3640-2 regions, as shown in fig. 36X.

Next, the process selectively etches exposed portions of insulator regions 3635' and 3635 "using known industry methods and forms insulator regions 3635-1 and 3635-2.

Next, the process selectively etches exposed portions of contact regions 3630' and 3630 "using known industry methods and forms contact regions 3630-1 and 3630-2.

Next, the process selectively etches exposed portions of N-poly layers 3625' and 3625 "using known industry methods and forms N-poly regions 3625-1 and 3625-2.

Next, the process selectively etches exposed portions of N + polysilicon layers 3620' and 3620 "using known industry methods and forms N + polysilicon regions 3620-1 and 3620-2, as shown in FIG. 36X.

The process then selectively etches the exposed portions of conductor layers 3410' and 3410 "using known industry methods and forms word lines 3610-1(WL0) and 3610-2(WL 1). The directional etch stops on the surface of planar insulator 3603 as shown in fig. 36X.

Next, the method deposits and planarizes an insulator such as TEOS and fills trench openings 3659 'and 3659 "with insulators 3660' and 3660", respectively, as shown in fig. 36Y.

Next, the process etches (removes) sacrificial regions 3655-1 and 3655-2.

Next, the process deposits and planarizes conductor 3665' to form upper contacts 3665-1 and 3665-2, as shown in FIGS. 36Z and 36 AA.

Next, the process deposits and planarizes conductor layer 3671 using known industry methods to form cross section 3670, as shown in fig. 36 BB. Section 3670 corresponds to section 3100 shown in fig. 31A. In some embodiments, if the process fabrication begins with fig. 34A 'instead of fig. 34A, a cross-section (not shown) corresponding to cross-section 3100' shown in fig. 31B is formed as further described above. Further, in some embodiments, if the process fabrication begins with fig. 34A ", a cross-section (not shown) corresponding to cross-section 3100" shown in fig. 31C is formed as further described above.

At this point in the process, cross section 3670 shown in FIG. 36BB has been fabricated and includes NV NT diode cells having a dimension defined as 1F in the Y direction (where F is the minimum feature size), and corresponding array bit lines. Next, cell dimensions to define dimensions in the X direction are formed by a directional trench etch process similar to that described further above with respect to cross-section 3670 shown in fig. 36 BB. The trenches defining dimensions in the X direction are substantially perpendicular to the trenches defining dimensions in the Y direction. In this example, the cell characteristics in the X direction do not require the self-alignment techniques described further above with respect to the Y direction dimension. The cross-section of the structure in the X-direction is illustrated with respect to the cross-section B-B' shown in fig. 36 BB.

Next, the method deposits and patterns a mask layer, such as mask layer 3673, on the surface of bit line conductor layer 3671, as shown in fig. 36 CC. Mask layer 3673 can be an alignment mark that is non-critically aligned into planar insulator 3603. Openings 3674, 3674', and 3674 "in mask layer 3673 determine the location of the trench directional etch region, in this example the trench is substantially perpendicular to the bit line, such as word line 3410-1(WL 0).

Next, the method forms trenches 3675, 3675 ', and 3675 "corresponding to openings 3674, 3674', and 3674" in mask layer 3673, respectively. Trenches 3675, 3675', and 3675 "form two sides of vertical sidewalls in the X-direction, defining opposite sides of the NV NT diode cell, as shown in fig. 36 DD.

The method directionally selectively etches (removes) the exposed portions of the bit line conductor layer 3671 shown in fig. 36DD using known industry methods to form bit lines 3671-1(BL0) and 3671-2(BL1) shown in fig. 36 DD.

Next, the process selectively etches 3665-1 and 3665-2 exposed in contact area FIG. 36CC using known industry processes to form contacts 3665-1' and 3665-1 "as shown in FIG. 36 DD.

Next, the method selectively etches, using known industry methods, the exposed portions of contact regions 3640-1 and 3640-2, nanotube elements 3645-1 and 3645-2, and conformal insulators 3650-1 and 3650-2 shown in FIG. 36BB to form contacts 3640-1 ' and 3640-1 ", conformal insulator regions (not shown in section B-B ' of FIG. 36 DD), and nanotube elements 3645-1 ' and 3645-1", as shown in FIG. 36 DD.

Next, the process selectively etches exposed regions of insulators 3635-1 and 3635-2 using known industry methods to form insulator regions 3635-1 'and 3635-1' as shown in FIG. 36 DD.

Next, the process selectively etches exposed portions of contact regions 3630-1 and 3630-2 as shown in FIGS. 36BB and 36CC using known industrial processes and forms contacts 3630-1 'and 3630-1 "as shown in FIG. 36DD (section B-B').

Next, the process selectively etches exposed portions of N-poly regions 3625-1 and 3625-2 as shown in FIG. 36BB using known industrial processes and forms N-poly regions 3625-1 'and 3625-1 "as shown in FIG. 36DD (cross-section B-B').

Next, the process selectively etches the exposed portions of N + polysilicon regions 3620-1 and 3620-2 as shown in FIG. 36BB and forms N + polysilicon regions 3620-1 'and 3620-1 "as shown in FIG. 36DD (cross-section B-B') using known industrial processes. The directional etch stops at the surface of word line 3610-1(WL 0).

Next, the process deposits insulator 3676 using known industrial processes, as shown in fig. 36 EE. Insulator 3676 can be, for example, TEOS.

The process then planarizes insulator 3676 using known industry methods to form insulator 3676 ', and forms cross-section 3670' as shown in figure 36 FF. Section 3670' shown in fig. 36FF and section 3670 shown in fig. 36BB are representative of two sections of the same embodiment of a vertically oriented cell of a passivated NV NT diode. Cross-section 3670 shown in fig. 36BB corresponds to cross-section 3100 shown in fig. 31A.

At this point in the process, cross-sections 3670 and 3670' shown in fig. 36BB and 36FF have been fabricated separately, with the vertically-oriented channel length of the non-volatile nanotube elementDegree L_SW-CHAnd a horizontally oriented channel width W_SW-CHIs defined to include the overall NV NT diode cell size of 1F in the Y direction and 1F in the X direction, along with the corresponding bit and word array lines. Cross section 3670 is a cross section in the Y direction of two adjacent vertically oriented anode-to-nanotube type nonvolatile nanotube diode-based cells, and cross section 3670' is a cross section in the X direction of two adjacent vertically oriented anode-to-nanotube type nonvolatile nanotube diode-based cells in the cell. Cross sections 3670 and 3670' include corresponding word lines and bit line array lines. The nonvolatile nanotube diode forms a steering and storage element in each cell shown in cross-sections 3670 and 3670' that each occupy a 1F by 1F area. The spacing between adjacent cells is 1F, so the cell periodicity is 2F in both the X and Y directions. So that one bit occupies an area of 4F². At 65nm technology node, the unit area is less than 0.02um²。

Method of manufacturing non-volatile memory using NVNT diode device having both anode-to-NT switch connection and cathode-to-NT switch connection

Some embodiments of a method of fabricating a stacked memory array are illustrated in figure 32 and in method 3200 as described further above. First, method 3210 fabricates support circuitry and interconnects on a semiconductor substrate, which is then insulated and planarized, as further described above with reference to fig. 34 and 36.

Next, the nanotube top cathode fabrication process forms the lower array 3310 of FIG. 33B and the corresponding lower array 3310 'of FIG. 33B', as further described above with reference to FIG. 34.

Next, an anode-over-nanotube fabrication process forms the upper array 3320 and corresponding upper array 3320 'of fig. 33B with a shared word line 3330 and a corresponding word line 3330', as further described above with reference to fig. 36. The only difference is that the method shown in fig. 36 is applied to the planarized top surface of the lower arrays 3310 and 3310' and that the shared word line wiring is shared between the lower and upper arrays.

Non-volatile 3D memory using non-volatile nanotube switches with vertical orientation of nanotube elements that change configuration to enhance performance and density

The 3D structure based on vertically oriented cathode-to-NT and anode-to-NT nonvolatile nanotube diodes as described further above exemplifies a thin nanotube element, wherein the thickness of these thin nanotube elements is typically less than 10nm thick (e.g., 1-5nm) and thin relative to the cell boundary level dimension of the nonvolatile nanotube diode. Cathode-to-nanotube nonvolatile nanotube diodes examples are shown in cross-section 2800 in fig. 28A and cross-section 3470 shown in fig. 34 BB. Anode-to-nanotube nonvolatile nanotube diodes examples are shown in cross section 3100 shown in fig. 31A and cross section 3670 shown in fig. 36 BB. The nonvolatile nanotube switches forming the data storage portion of the nonvolatile nanotube diode are identical to the cathode-NT and anode-on-NT diodes. Thus, the cell structure illustrating various non-volatile nanotube switch configurations is described further below, showing in schematic form the select (steering) diode portion of the non-volatile nanotube device structure.

Fig. 6A-6B and 7A-7B illustrate horizontally and vertically oriented nanotube (nanostructure) layers, respectively, comprised of a network of nanotubes that when patterned form a nanotube (nanostructure) layer and nanotube elements. As cell size is reduced from, for example, about 150 to 20nm, the number of nanotubes in contact with the nanotube terminals (contacts) is reduced for the same nanotube density (nanotubes per unit area). To compensate for the reduction in the number of nanotube-to-smaller terminal connections, nanotube density (nanotubes per unit area) can be increased by optimizing single layer deposition and by depositing multiple nanotube layers using spin-on and/or spray-on nanotube deposition techniques as described more fully in the incorporated patent references. The result is a nanotube (nanostructure) layer and patterned nanotube element that can increase in thickness as cell size decreases. Nanotube (nanostructure) layer lifting is further described below with reference to fig. 38.

The structural (geometric) details described further below illustrate various options for non-volatile nanotube switches. Non-volatile nanotube switches of different thicknesses may be formed within isolation trench defining cell boundaries using nanotube elements having different thicknesses to optimize non-volatile nanotube switching properties, as further described below with reference to fig. 37, 39, and 40.

Non-volatile nanotube switches of different thicknesses may also be formed using nanotube elements of different thicknesses within the isolation trench regions, outside the isolation trench-defining cell boundaries, as further described below with reference to fig. 42A-42H and 43A-43B.

Non-volatile nanotube switches of varying thicknesses may also be formed within the isolation trench-defining cell boundaries and within the isolation trench regions, as described further below with reference to fig. 44A-44B.

By storing two bits per 3D cell, which uses two non-volatile nanotube switches sharing a select (steering) diode, as described further below with reference to fig. 45 and 46, a double (2X) storage density can be achieved without the need for a stacked array, as described further above with reference to fig. 33.

Non-volatile 3D memory using vertically oriented non-volatile nanotube switches with nanotube elements of different thicknesses

Fig. 37 shows cross-section 3700, which includes two mirror image cells, cell 1 and cell 2, and isolation trenches A, B, and C, which form the boundaries of cells 1 and 2. Cells 1 and 2 are vertically oriented non-volatile nanotube diodes. The select (steering) diode portion is schematically represented by diodes D1-1 and D1-2 using schematic representation 3725; the non-volatile nanotube switch storage element is shown in mirror cross-section. Select (steering) diode D1-1 in combination with non-volatile nanotube switch 3705 to form a non-volatile nanotube diode cell of the NT upper cathode; select (steering) diode D1-2, in combination with nonvolatile nanotube switch 3705, forms a nanotube diode cell that is anodic on NT. Nonvolatile nanotube switch 3705' in cell 2 is a mirror image of nonvolatile nanotube switch 3705 in cell 1. Cross-section 3700 will be described primarily with respect to cell 1 and nonvolatile nanotube switch 3705.

Cross-section 3700 shown in fig. 37 illustrates relatively thin nanotube element 3745 in contact with the vertical sidewall at a distance R of approximately F/2, where F is the minimum dimension for the corresponding technology node. If select (steering) diode D1-1 is selected, cross section 3700 shown in fig. 37 corresponds to cross section 2800 in fig. 28 and cross section 3470 shown in fig. 34BB, whereas if select (steering) diode D1-2 is selected, cross section 3700 corresponds to cross section 3100 in fig. 31A and cross section 3670 in fig. 36 BB. In both cases, the non-volatile nanotube switch 3705 is the same.

For cell 1 formed using diode D1-1, array line 3710 shown in cross-section 3700 corresponds to array bit line 2810-1 shown in cross-section 2800 in FIG. 28A; diode D1-1, shown schematically in fig. 37, corresponds to a schottky diode having junction 2818-1 and corresponding structure in fig. 28A. However, diode D1-1 may also correspond to the PN diode with junction 2819-1 and corresponding structure shown in FIG. 28B. The lower contact 3730 shown in figure 37 corresponds to the lower contact 2830-1 shown in figure 28A; insulator 3735 corresponds to the channel length L used to define the nanotube element_SW-CHInsulator 2835-1; sidewall contact 3740 corresponds to sidewall contact 2840-1; nanotube element 3745 corresponds to nanotube element 2845-1; upper contact 3765 corresponds to upper contact 2865-1; insulator 3750 corresponds to insulator 2850-1; and array line 3771 corresponds to array word line 2871.

For cell 1 formed using diode D1-2, array line 3710 shown in cross-section 3700 corresponds to array word line 3110-1 shown in cross-section 3100 of FIG. 31A; the diode D1-2 schematically shown in fig. 37 corresponds to the schottky diode of fig. 31A with junction 3133-1 and corresponding structure. However, diode D1-2 may also correspond to the PN diode with junction 3128-1 and corresponding structure shown in fig. 31B. In addition, the diode D1-2 may also correspond to the device shown in FIG. 31CSchottky and PN diodes with a combination of junctions 3147-1 and corresponding structures. The lower contact 3730 shown in FIG. 37 corresponds to the lower contact 3130-1 shown in FIG. 31A; insulator 3735 corresponds to the channel length L used to define the nanotube element_SW-CHInsulating body 3135-1; sidewall contact 3740 corresponds to sidewall contact 3140-1; nanotube element 3745 corresponds with nanotube element 3145-1; upper contact 3765 corresponds to upper contact 3165-1; insulator 3750 corresponds to insulator 3150-1; and array line 3771 corresponds to array bit line 3171.

The nanotube network forms a relatively thin nanotube (nanostructure) layer and corresponding nanotube element, which typically has a nanotube density of about 500 nanotubes per square micron (um)²). The nanotube layer and the corresponding nanotube element typically include voids (void), i.e., the regions between the nanotubes. The void area may be relatively large, e.g., greater than 0.0192um ²Or may be relatively small, e.g., less than 0.0192um²For example. As cell sizes are reduced, nanotube density is increased by the corresponding increase in void area and the thickness of the nanotube layer and corresponding nanotube element. FIGS. 6A-6B and 7A-7B show a relatively thin nanotube element 630 and a relatively thin nanotube layer 700, respectively, at up to 500 nanotubes per um²The nanotube density of (a) is applied to the substrate by a spin coating method and has a relatively large void area. Fig. 38 shows a nanotube layer 3800 formed on a substrate by a spray coating method, which has a relatively small void area. For example, the nanotube layer 3800 is not greater than 0.0192um²Of (2) is provided. The nanotube layer 3800 also did not range between 0.0096 and 0.0192um²A void region therebetween; not between 0.0048 and 0.0096um²A void region therebetween; a relatively small number of hole regions 3810 between 0.0024 and 0048um²To (c) to (d); most of the hole area, e.g. hole area 3820 is less than 0.0024um²。

For a technology node (generation) with F of about 45nm and a nanotube element with a thickness of about, for example, 10nm, the location R of the vertical sidewall may be at about F/2 or about 22nm, as shown by nanotube element 3745 of non-volatile nanotube switch 3705 in cross-section 3700 shown in FIG. 37. In this example, sidewall contact 3740 is about 22nm and insulator 3750 is about 13 nm. The area of the upper layer contact 3765 to the sidewall contact 3740 is about 22 nm. The area of lower contact 3730 to nanotube element 3745 is about 22 nm.

Fig. 39 shows cross-section 3900 and includes nonvolatile nanotube switch 3905 in which nanotube element 3745' has a thickness that is substantially greater than the thickness of nanotube element 3745 shown in fig. 37. Non-volatile nanotube switch structures 3705 and 3905 are fabricated using a self-aligned fabrication method, as further described above with reference to figures 34 and 36. For a technology node (generation) where F is about 32nm and a nanotube element having a thickness of, for example, about 15nm, the location R of the vertical sidewalls may be at about F/3 or about 10nm, as shown by nanotube element 3745' of non-volatile nanotube switch 3905 in cross-section 3900 shown in FIG. 39. In this example, sidewall contact 3740 'is about 10nm and insulator 3750' is about 7 nm. The area of the upper contact 3765 'is about 10nm to the sidewall contact 3740'. The area of lower contact nanotube element 3745' is about 22 nm.

Fig. 40 shows cross section 4000 and includes nanotube switch 4005 with nanotube element 4050 having a thickness equal to cell dimension F. In this example, nanotube element 4050 can be deposited by a spray fabrication method, for example. The nanotube region fills the available cell area for a technology node (generation) with a F of about 22nm and a nanotube element with a thickness of, for example, about 22 nm. Sidewall contacts are eliminated and lower layer contact 4030 and upper layer contact 4065 form a two terminal (contact) area to nanotube 4050.

Non-volatile 3D memory using vertically oriented non-volatile nanotube switches with nanotube elements within trench isolation regions

As further described above with reference to fig. 37, 39, and 40, as technology nodes (generations) shrink to minimum dimension F and the nanotube element increases in thickness to reduce the void region, the nanotube element may eventually fill the available area within the isolation trench-defining cell region in some embodiments, and thereby avoid further increasing the nanotube element thickness. It is possible to continue to increase the overall thickness of the nanotube element by also forming the nanotube element within the isolation trench regions, as described further below. Alternatively, the nanotube element may be disposed entirely outside the isolation trench area and not within the cell boundary, as described further below.

Fig. 41A-41B are diagrams of a process for selectively forming vertical sidewall elements of controlled dimensions in and on the vertical sidewalls of a recess (trench) structure, as described in U.S. patent 5,096,849, which is incorporated herein by reference in its entirety (co-pending). The process described in us patent 5,096,849 includes filling the trench with a resist material to be removed or filling the trench with, for example, an insulator left in the region of the trench. Next, RIE is used to accurately remove the resist or insulator to a controlled depth d1, measured from the reference top surface. Then, a conformal layer of material having a controlled thickness is deposited. Next, RIE is used to remove the conformal layer on the horizontal surfaces, leaving the conformal layer on the vertical sidewalls of the trench. Next, a second resist or insulator fills the remaining trench openings. Next, RIE is used to accurately remove the sidewall film and resist or insulator to a controlled depth d 2. At this point in the process, vertical sidewall elements having vertical dimensions d1-d2 and a controlled thickness have been formed. If the trench is filled with resist, the resist may be removed. If the trench is filled with an insulator material, the insulator material may remain in the trench. The trench is then filled with an insulator and planarized.

Fig. 41A shows a view of a groove having an outer wall 4110. Insulator 4115 (e.g., SiO) for the lower part of the trench₂) Filling with its top surface at a controlled depth d1 from the trench surface. A conformal layer is deposited and the RIE removes the conformal layer material on horizontal surfaces, leaving partially completed vertical elements 4120 and 4120'. Resist or insulator 4130 fills the trench regions on the top surface of resist or insulator 4115.

Fig. 41B shows the view of fig. 41A after RIE is used to remove the resist or insulator material 4130, followed by the vertical sidewall elements 4120 and 4120 ' to the controlled depth d2, and to form the fill regions 4130 ' and the vertical sidewall elements 4145 and 4145 '. The vertical sidewall elements 4145 and 4145' have a vertical dimension d1-d2 and a controlled known thickness defined by the thickness of the conformal layer material. The resist or insulator 4130' may be removed or may be left in place. The trench opening may then be filled with an insulating material and planarized.

Figures 42A-42H illustrate a fabrication method for tuning the element of us patent 5,096,849 (shown in figure 41) to form a nanotube element within an isolation trench as further described above with reference to figures 28A-28C, 31A-31C, 33A-33D, 34A-34FF, 36A-36FF, 37, 39, and 40.

FIG. 42A shows opening 4205 formed in an insulating trench using a method such as selective controlled etching (using RIE, for example) and having sidewall regions defining vertical surfaces of lower contacts 4210 and 4210 ', upper contacts 4220 and 4220', and insulators 4215 and 4215 '(between the upper and lower contacts, respectively), wherein the thickness of insulators 4215 and 4215' defines channel length L of the nanotube element_SW-CHAs further shown in fig. 42D.

First, the method fills the trench openings 4205 with an insulator 4225 (e.g., TEOS), as shown in fig. 42B.

Next, the method selectively etches the insulator 4225 to a depth D1 (relative to the reference surface) using a selective and controlled RIE etch, as shown in fig. 42C.

Next, the method deposits a conformal nanotube layer 4235 using methods described in more detail in the incorporated patent references. At this point in the process, the channel length L_SW-CHIs defined as shown in fig. 42D.

The method then deposits a protective conformal insulator layer 4240, as shown in fig. 42D. The conformal insulator 4240 may be, for example, 5-50 nm, and may be formed of any suitable known insulator material in the CMOS industry or the packaging industry, e.g., SiO₂、SiN、Al₂O₃BeO, polyimide, PSG (phosphosilicate glass), photoresist, PVDF (polyvinylidene fluoride), sputtered glass, epoxy glass, and other dielectric materials and combinations of dielectric materials, such as Al-coated ₂O₃PVDF for the layers, as described in U.S. patent application No.11/280,786. Insulator 4240 is deposited to a thickness sufficient to ensure protection of nanotube element 4235 from RIE etching.

Next, the method directly etches the conformal insulator 4240 and the nanotube layer 4235 using RIE and removes the conformal layer material on the top horizontal surface and on the bottom horizontal surface at the bottom of the trench opening 4241, leaving the partially completed vertical elements 4240 ', 4240 ", 4235', and 4235", as shown in fig. 42E.

Next, the method fills the trench openings 4241 with an insulator 4242, such as TEOS, as shown in fig. 42F.

Next, the method selectively etches the insulator 4242, conformal insulators 4240 'and 4240 ", and nanotube elements 4235' and 4235" to a depth D2 (relative to the surface reference) using a selective and controlled RIE etch, as shown in fig. 42G. At this point in the process, an insulator 4242' is formed; nanotube elements 4245 and 4245' are formed; conformal insulators 4250 and 4250' are formed while trench openings 4255 remain.

The method then fills the trench openings 4255 with an insulator (e.g., TEOS) and the method planarizes to form an insulator 4260. At this point in the process, cross-section 4275 is formed, including nanotube channel elements 4270 and 4270'. Nanotube channel element 4270 comprises nanotube element 4245 and conformal insulator 4250, and nanotube channel element 4270 ' comprises nanotube element 4245 ' and conformal insulator 4250 '. Nanotube channel elements 4270 and 4270' are in contact with a portion of the vertical sidewalls of the upper and lower contacts and also define L _SW-CHAre in contact with each other. For example, nanotube channel element 4270 is in contact with upper contact 4220, lower contact 4210, and insulator 4215, while nanotube channel element 4270 'is in contact with upper contact 4220', belowPoint 4210 'and insulator 4215' are in contact.

Nanotube channel elements 4270 and 4270 'may be used in place of nanotube element 3745 (shown in fig. 37) and nanotube element 3745' (shown in fig. 39) to form new non-volatile nanotube switch structures, as shown in fig. 43A, 43B, and 43C. The new cell structure may be a cathode on NT or an anode on NT type cell. Fig. 43A, 43B, and 43C show a cathode type cell on NT for comparison with fig. 28A and 34A-34FF as further described above.

FIG. 43A shows cross-section 4300 in which a nonvolatile nanotube channel element storage device is positioned within isolation trench B, as shown by nonvolatile channel elements 4370-1 (positioned on a sidewall of a region of cell 1) and 4370-2 (positioned on a region of cell 2), which correspond to nonvolatile channel elements 4270 and 4270', respectively, shown in cross-section 4275 of FIG. 42H. Section 4300 shown in FIG. 43A shows that relatively thin nanotube elements 4345-1 and 4345-2 may have a thickness of less than 10nm, for example. Nanotube element 4345-1 of nanotube channel element 4370-1 includes sidewall contacts to lower layer contact 4330-1 and upper layer contact 4365-1 of cell 1. Nonvolatile nanotube switch 4305-1 is formed from lower contact 4330-1 and upper contact 4365-1, both of which are in contact with nanotube element 4345-1 of nanotube channel element 4370-1. Nanotube element 4345-2 of nanotube channel element 4370-2 includes sidewall contacts to lower layer contact 4330-2 and upper layer contact 4365-2 of cell 2. Nonvolatile nanotube switch 4305-2 is formed from lower contact 4330-2 and upper contact 4365-2, both of which are in contact with nanotube element 4345-2 of nanotube channel element 4370-2. In the X direction, cell 1 and cell 2 are both larger than the minimum dimension F, but the overall cell period remains 2F and the array density remains unchanged.

FIG. 43B shows cross-section 4300 ' in which a nonvolatile nanotube channel element storage device is positioned within isolation trench B ', as shown by nonvolatile channel elements 4370-1 ' (positioned on a sidewall of a region of cell 1 ') and 4370-2 ' (positioned on a region of cell 2 '), which correspond to nonvolatile channel elements 4270 and 4270 ', respectively, shown in cross-section 4275 of FIG. 42H. Section 4300 ' shown in FIG. 43B shows relatively thick nanotube elements 4345-1 ' and 4345-2 ', which may be 15nm thick, for example. Nanotube element 4345-1 ' of nanotube channel element 4370-1 ' includes sidewall contacts to lower layer contact 4330-1 ' and upper layer contact 4365-1 ' of cell 1 '. Nonvolatile nanotube switch 4305-1 ' is formed from lower contact 4330-1 ' and upper contact 4365-1 ', both of which are in contact with nanotube element 4345-1 ' of nanotube channel element 4370-1 '. Nanotube element 4345-2 ' of nanotube channel element 4370-2 ' includes sidewall contacts to lower layer contact 4330-2 ' and upper layer contact 4365-2 ' of cell 2 '. Nonvolatile nanotube switch 4305-2 ' is formed from lower contact 4330-2 ' and upper contact 4365-2 ', both of which are in contact with nanotube element 4345-2 ' of nanotube channel element 4370-2 '. In the X direction, cell 1 'and cell 2' are both larger than the minimum dimension F, but the period of the entire cell remains 2F and the array density remains unchanged.

FIG. 43C shows cross-section 4300 "in which the nonvolatile nanotube channel element storage device is positioned within isolation trench A", trench B ", and trench C", as shown by nonvolatile channel elements 4370-1 "and 4370-3 (positioned on the sidewalls of the cell 1" region) and nonvolatile channel elements 4370-2 "and 4370-4 (positioned on the sidewalls of the cell 2" region). Section 4300 "shown in FIG. 43C shows relatively thick channel elements 4345-1", 4345-2 ", 4345-3, and 4345-4, which may be 15nm thick, for example. The nanotube elements of nanotube channel elements 4370-1 "and 4370-3 include sidewall contacts to lower contact 4330-1" and upper contact 4365-1 "of cell 1". Nonvolatile nanotube switch 4305-1 "is formed by lower contact 4330-1" and upper contact 4365-1 ", both contacts being in contact with nanotube elements 4345-1" and 4345-3, respectively, of nanotube channel elements 4370-1 "and 4370-3, respectively, for an effective channel element thickness of, for example, 30 nm. The nanotube elements of nanotube channel elements 4370-2 "and 4370-4 include sidewall contacts to lower contact 4330-2" and upper contact 4365-2 "of cell 2". Nonvolatile nanotube switch 4305-2 "is formed by lower contact 4330-2" and upper contact 4365-2 "that contact nanotube elements 4345-2" and 4345-4, respectively, of nanotube channel elements 4370-2 "and 4370-4, respectively, for an effective channel element thickness of, for example, 30 nm. In the X direction, cell 1 "and cell 2" are larger than the minimum dimension F, but 2F is maintained for the entire cell period and the array density remains unchanged. As the cell becomes smaller (e.g., 22nm) or even smaller, the number of nanotubes between contacts decreases and the resistance rises. The achievable density of the nanotubes per layer is limited. Therefore, it may be helpful to find ways to add layers of nanotubes by placing more layers of parallel nanotubes to try to keep the number of nanotubes nearly the same, if possible. In other words, nanotube elements can be scaled to keep pace with the size reduction of semiconductors.

Non-volatile 3D memory using vertically oriented non-volatile nanotube switches with nanotube element stacks on steering (select) diodes and in trench isolation regions

Nanotube elements included in the non-volatile nanotube switches can be incorporated within cell boundaries defined by isolation trenches as described above with reference to fig. 37 and 39 and also with respect to the structures shown in fig. 28A-28C and 31A-31C and with respect to the fabrication methods described with reference to fig. 34A-34FF and 36A-36 FF. In addition, nanotube elements included in the non-volatile nanotube switches can also be incorporated within the isolation trench regions and outside the cell boundaries, as further described above with reference to the fabrication methods of fig. 43A-43C and with reference to fig. 42A-42H. However, it is possible to combine nanotube elements within the cell boundaries with other nanotube elements in the isolation trenches and outside the cell boundaries to form a non-volatile nanotube switch that includes both types of nanotube configurations. As the cells become smaller (e.g., 22nm) and even smaller, the number of nanotube elements between contacts decreases and the resistance rises. The achievable density of the nanotubes per layer is limited. Thus, finding ways to add layers of nanotubes may be helpful by placing more layers of parallel nanotubes to try to keep the number of nanotubes nearly the same, if possible. In other words, nanotube elements can be scaled to keep pace with the size reduction of semiconductors.

Fig. 44A shows cell 1 and mirror cell 2 with nonvolatile nanotube switches 4405 and 4405'. Since cell 2 is a mirror image of cell 1, only cell 1 will be described in detail. Non-volatile nanotube switch 4405 is formed by combining non-volatile nanotube switch 4468 (corresponding to non-volatile nanotube switch 3905 shown in figure 39) and nanotube channel element 4470 (corresponding to nanotube channel element 4370-3 shown in figure 43C). The non-volatile nanotube switch 4405 may be formed by first forming the non-volatile nanotube switch 4468 using the fabrication methods described further above with reference to fig. 34A-34 FF. Next, nanotube channel element 4470 is formed using the fabrication method described with reference to fig. 42A-42H. The nanotube element 4445 of the nanotube channel element 4470 shares a lower contact 4430 with the nanotube element 4445 'and shares sidewall contacts 4440 and an upper contact 4465 with the nanotube element 4445'. The two nanotube elements 4445 and 4445' have substantially the same channel length L_SW-CHRanging, for example, from less than 5nm to greater than 250 nm. The thickness values of nanotube elements 4445 and 4445' may be different. In this example, the minimum dimension F is assumed to be 32nm and the thickness of each nanotube element may be 15nm for an effective thickness of 30nm for combined nanotube elements 4445 and 4445'. The effective thickness 30nm of the combined nanotube element 4445 and 4445' is approximately equal to the cell dimension F32 nm because the nanotube element is used not only within the cell boundary but also outside the cell boundary within the isolation trench region. Although this example illustrates a NT upper cathode type unit, a NT upper anode unit may also be formed.

Nanotube elements included in the non-volatile nanotube switch can be incorporated within cell boundaries defined by isolation trenches, as further described above with reference to fig. 40. In addition, nanotube elements included in the non-volatile nanotube switches can also be incorporated within the isolation trench regions and outside the cell boundaries, as further described above with reference to the fabrication methods described with reference to fig. 43A-43C and with reference to fig. 42A-42H. However, it is possible to combine nanotube elements within the cell boundaries with other nanotube elements in the isolation trenches and outside the cell boundaries to form a non-volatile nanotube switch that includes both types of nanotube arrangements.

Fig. 44B shows cell 1 and cell 2 with nonvolatile nanotube switches 4405 "and 4405'". Since unit 2 is identical to unit 1, only unit 1 will be described in detail. Non-volatile nanotube switch 4405 "is formed by the combination of non-volatile nanotube switch 4469 (corresponding to non-volatile nanotube switch 4050 shown in figure 40) and nanotube channel elements 4470-1 and 4470-2 (corresponding to nanotube channel elements 4370-3 and 4370-1, respectively, shown in figure 43C). The non-volatile nanotube switch 4405 "may be formed using a fabrication method similar to that of fig. 40 by first forming the non-volatile nanotube switch 4469. Next, nanotube channel elements 4470-1 and 4470-2 are formed using the fabrication method described with reference to FIG. 42. Nanotube element 4445-1 of nanotube channel element 4470-1 and nanotube element 4445-2 of nanotube channel element 4470-2 share a lower contact 4430 with nanotube element 4445-3 and an upper contact 4465 with nanotube element 4445-3. Nanotube elements 4445-1, 4445-2 and 4445-3 have substantially the same channel length L _SW-CHRanging, for example, from less than 5nm to greater than 150 nm. The thickness values of nanotube elements 4445-1, 4445-2, and 4445-3 may be different. In this example, minimum dimension F is assumed to be 22nm and for a combined effective thickness of 34nm for combined nanotube elements 4445-1, 4445-2, and 4445-3, the thickness of nanotube elements 4445-1 and 4445-2 may each be 6nm and nanotube element 4445-3 may be 22 nm. The effective thickness 34nm of the combined nanotube element 4445-1, 4445-2, and 4445-3 is greater than about 50% of the cell dimension F22 nm because the nanotube element is used not only within the cell boundary but also outside the cell boundary within the isolation trench region. Although this example illustrates a NT upper cathode type unit, a NT upper anode unit may also be formed. As the cells become smaller (e.g., 22nm) and even smaller, the number of nanotube elements between contacts decreases and the resistance rises. The achievable density of the nanotubes per layer is limited. Therefore, finding ways to add layers of nanotubes may be helpful by placing more layers of parallel nanotubes to try to keep the number of nanotubes nearly the same, if possible. In other words, the nanotube elementThe device can be scaled to keep pace with the size reduction of semiconductors.

Non-volatile 3D memory storing two bits per cell using two vertically oriented non-volatile nanotube switches sharing a single steering (select) diode

Fig. 33A-33D show two stacked memory arrays, one array of cathode type on NT and one array of anode type on NT, to double the bit density. Each cell in the stack has a select (steering) diode and a non-volatile nanotube switch. As with the cells described above with reference to FIGS. 43C and 44A-44B, each cell uses two nanotube elements connected in parallel to increase the effective nanotube element thickness. However, with two nanotube elements per cell, it is possible to double the bit density by storing two data states (bits) in the same cell in two nanotube elements (sharing one select (steering) diode without having to stack two arrays), as further described above with reference to FIGS. 33A-33D.

The memory array cross-section 4500 shown in fig. 45 shows cell 1 and cell 2 having the same non-volatile nanotube switch. Since cell 1 and cell 2 are identical, only cell 1 will be described in detail. FIG. 45 shows cell 1 storing two bits. A select (steering) diode 4525 is connected to word line WL0 and lower contact 4530. Cell 1 includes two non-volatile nanotube switches 4505-1 and 4505-2 that share a select (steering) diode 4525.

Nanotube channel element 4570-1 is formed within trench a and is similar to nanotube channel element 4370-3 shown in figure 43C. Nanotube element 4545-1 makes contact with shared lower contact 4530 and upper contact 4565-1. The upper contact 4565-1 makes contact with the bit line BL 0-a. Nanotube element 4545-1 may store information via its resistive state.

Nanotube channel element 4570-2 is formed within trench B. Nanotube element 4545-2 makes contact with shared lower contact 4530 and upper contact 4565-2. Upper contact 4565-2 makes contact with via 4567, and via 4567 makes contact with bit line BL 0-B. Nanotube element 4545-2 may also store information via its resistive state.

Cell 1 includes a nonvolatile nanotube switch 4505-1 that stores, for example, one bit, while nonvolatile nanotube switch 4505-2 also stores, for example, one bit, such that cell 1 stores, for example, two bits. Cross section 4500 of FIG. 45 shows a 3D memory array storing two bits per cell, one in non-volatile nanotube switch 4505-1 and one in non-volatile nanotube switch 4505-2. The memory array cross-section 4500 shown in fig. 45 has the same density as the stacked array shown in fig. 33A-33C, without the need to stack two separate arrays. While this example illustrates an NT upper anode type cell, an NT upper cathode cell may be used instead.

Fig. 45 illustrates a variation of fig. 43C in which sub-minimum upper contacts 4565-1 and 4565-2 and contact via 4567 are formed using fabrication methods corresponding to self-aligned spacer techniques, sacrificial shapes, and fill and planarization techniques to form sub-minimum insulator and conductor regions, as further described above with reference to fig. 36A-36 FF. More specifically, the self-aligning spacer technique is further described above with reference to fig. 36E and 36F; forming the sub-minimum sacrificial layer is described with reference to fig. 36P to 36S; while forming the minimum and sub-minimum contact areas is described with reference to fig. 36Y, 36Z, and 36 AA.

Fig. 33A-33C show two stacked arrays, one of cathode-on-NT type and the other of anode-on-NT type, to double the bit density. Each cell in the stack has a select (steering) diode and a non-volatile nanotube switch. As with the cells described above with reference to FIGS. 43C and 44A-B, each cell uses two nanotube elements connected in parallel to increase the effective nanotube element thickness. However, in the case of two nanotube elements per cell, it is possible to double the bit density by storing two data states (bits) in the same cell in two nanotube elements (sharing one select (steering) diode without having to stack two arrays), as further described above with reference to FIGS. 33A-33C.

Memory array cross-section 4600 of fig. 46 shows cell 1 and cell 2 having the same nonvolatile nanotube switch configuration. Since cell 1 and cell 2 are identical, only cell 1 will be described in detail. FIG. 46 shows cell 1 storing, for example, two bits. A select (steering) diode 4625 is connected to the word line WL0 and the lower contact 4630. Cell 1 includes two nonvolatile nanotube switches 4605-1 and 4605-2 that share a select (steering) diode 4625.

Nanotube channel element 4670-1 is formed within trench A and is similar to nanotube channel element 4470 shown in FIG. 44A. Nanotube element 4645-1 is in contact with shared lower layer contact 4630 and upper layer contact 4665-1. The upper contact 4665-1 is in contact with the bit line BL 0-A. Nanotube element 4645-1 may store information via its resistive state.

Nanotube element 4645-2 is part of a non-volatile nanotube switch 4605-2, which is formed within the cell 1 boundaries as further described above with respect to the non-volatile nanotube 4468 shown in fig. 44A, except that the upper contact structure is modified as further described below. Nanotube element 4645-2 is in contact with shared lower layer contact 4630 and upper layer contact 4665-2. Upper contact 4665-2 is in contact with via 4667, and via 4667 is in contact with bit line BL 0-B. Nanotube element 4645-2 may also store information via its resistive state.

Cell 1 includes a non-volatile nanotube switch 4605-1, which stores, for example, one bit, and a non-volatile nanotube switch 4605-2, which also stores, for example, one bit, so that cell 1 stores, for example, two bits. Section 4600 shown in fig. 46 shows a 3D memory array that can store two bits per cell, e.g., one bit in nonvolatile nanotube switch 4605-1 and another bit in nonvolatile nanotube switch 4605-2. Memory array cross-section 4600 shown in fig. 46 has the same density as the stacked arrays shown in fig. 33A-33C without the need to stack two separate arrays. Although this example illustrates an NT upper anode type cell, an NT upper cathode cell may be used instead.

Fig. 46 illustrates a variation of fig. 44A-44B in which sub-minimum upper contacts 4665-1 and 4665-2 and contact vias 4667 are formed using fabrication methods corresponding to self-aligned spacer techniques, sacrificial shapes, and fill and planarization techniques to form sub-minimum insulator and conductor regions, as further described above with reference to fig. 36A-36 FF. More specifically, the self-aligning spacer technique is further described above with reference to fig. 36E and 36F; forming the sub-minimum sacrificial layer is described with reference to fig. 36P to 36S; while forming the minimum and sub-minimum contact areas is described with reference to fig. 36Y, 36Z, and 36 AA.

Non-volatile 3D memory using horizontally oriented self-aligned end-contacted nanotube element stack on steering (select) diode

Fig. 40 shows a cross section 4000 including nanotube switch 4005 where nanotube element 4050 may have a thickness equal to cell dimension F. In general, the thickness of the nanotube element need not be related in any way to the lateral cell dimension F. In this example, nanotube element 4050 can be deposited by a manufacturing method such as spray coating. For a technology node (generation) with a F of about 22nm and a nanotube element with a thickness of, for example, about 22nm, the nanotube region fills the available cell area. Sidewall contacts are eliminated and lower layer contact 4030 and upper layer contact 4065 form a two terminal (contact) area to nanotube 4050. Vertical channel length L_SW-CHDetermined by the spacing between upper contact 4065 and lower contact 4030. Although the cross-section 4000 reaches a high level of 3D cell density, the channel length L_SW-CHIs limited because nanotube element 4050 is porous. In some embodiments, L_SW-CHA spacing of several hundred nanometers must be maintained to ensure that no short circuit occurs between upper contact 4065 and lower contact 4030 through the nanotube element. However, various methods and configurations may be used to reduce the thickness of the nanotube element, and thereby reduce L _SW-CHWhile still avoiding short circuits between the upper and lower contacts. Some exemplary methods and configurations for achieving this are described in more detail below.

Cross-section 4785 shown in FIG. 47 shows a horizontally oriented non-volatile nanotube element that passes through insulationThe edge region is separated from the upper layer contact and the lower layer contact. Nanotube element terminal-contacts are used to connect nanotube elements with corresponding upper contacts on one terminal and corresponding lower contacts on the other terminal using trench sidewall routing. This structure allows the nanotube element channel length (L) of the cell_SW-CH) Channel width (W)_SW-CH) And the height (thickness) can be reduced. The method of fabricating a NT top cathode 3D memory array is described in FIGS. 48A-48 BB.

FIG. 49 shows a non-volatile nanotube switch using terminal-contacts. FIG. 50 illustrates the operation of the terminal-contacted non-volatile nanotube switch depicted in FIG. 49.

Fig. 51 and 52 show cross-sections of nanotube element termination contact switches used in an anode 3D memory array on NT.

FIGS. 53 and 54A and 54B illustrate a dual-high memory stack using NT upper cathode and nanotube upper anode-3D memory arrays based on the new 3D cell shown in FIGS. 47, 48A-48BB, 51, and 52.

Fig. 55A-55F illustrate a structure of trench sidewall wiring and corresponding method of fabrication, the trench sidewall wiring being formed using a conformal conductor in a trench region. The manufacturing method used in fig. 48A-48BB uses a conductor trench filling method in forming trench sidewall wiring.

Three-dimensional cell structure of non-volatile cell of NVNT device with vertically oriented diode and horizontally oriented self-aligned NT switch filling conductor trench for NT on-NT cathode switch connection

FIG. 47 illustrates cross section 4785 of a 3-D memory embodiment including cells C00 and C01. The nanotube layer is deposited horizontally on a flat insulator surface that is located on a predefined diode-forming layer (as shown in fig. 34A and 34B, further shown above). A self-alignment method similar to the self-alignment method described further above with reference to fig. 34A-34FF and 36A-36FF determines the size and location of the trenches used to define the cell boundaries. Self-aligned trench sidewall routing connects horizontally oriented nanotube elements to vertically oriented diodes and also to array routing.

A method 2710, as further described above with reference to fig. 27A, is used to define the support circuitry and interconnects 3401.

Next, method 2730 shown in fig. 27B deposits and planarizes insulator 3403. Interconnect means (not shown at section 4785, but shown above with respect to section 2800 "of fig. 28C) through the planar insulator 3403 may be used to connect metal array lines in the 3-D array to the respective support circuitry and interconnects 3401. As an example, bit line drivers in the BL driver and readout circuitry 2640 may be connected to bit lines BL0 and BL1 in the array 2610 of the memory 2600 (as shown in fig. 26A and the cross-section 4785 shown in fig. 47, described further above). At this point in the fabrication process, method 2740 can be used to form a memory array on the surface of insulator 3403, which is interconnected to memory array support structure 3405-1 as shown in FIG. 47.

Method 2740 shown in fig. 27B deposits and planarizes metal, polysilicon, insulator, and nanotube elements to form a nonvolatile nanotube diode, which in this example includes a plurality of vertically oriented diodes and horizontally oriented serial pairs of nonvolatile nanotube switches. To eliminate the accumulation of layer alignment tolerances that substantially increase the cell area, the boundaries of the cells are formed in a single etching step, each cell having a single NV NT diode defined by a single trench etching step after the layers (except the WL0 layer) have been deposited and planarized. The size of a single cell in the X direction is F (1 minimum feature) as shown in fig. 47, while the size in the Y direction (not shown) perpendicular to the X direction is also F, with a period of 2F in both the X and Y directions. Thus, each cell occupies an area of about 4F ²。

Vertically oriented (Z-direction) trench sidewall cell routing on the first cell sidewall connects the vertically oriented diode with one end of the horizontally oriented nanotube element; and vertically oriented trench sidewall cell wiring on the second cell sidewall connects the other end of the horizontally oriented nanotube element to the array wiring. Exemplary methods of forming vertically oriented trench sidewall cell routing can be modified from methods of patterning shapes on trench sidewalls, such as disclosed in U.S. patent 5,096,849, which is incorporated herein by reference in its entirety. The dimensions in the X and Y directions of the horizontally oriented NV NT switching elements (nanotube elements) are defined by the trench etch. In the X or Y direction, the nanotube element has no alignment requirement. The nanotube element thickness (Z-direction) is typically in the range of 5 to 40 nm. However, the nanotube element thickness can be any desired thickness, such as less than 5nm or greater than 40 nm.

Horizontally oriented nanotube elements can be formed using a single nanotube layer, or can be formed using multiple layers. Such nanotube element layers can be deposited using, for example, spin-on coating techniques or spray-on coating techniques, as described in more detail in the incorporated patent references. Fig. 47 illustrates a 3-D memory array cross-section 4785 in the X-direction and corresponds to the method of fabrication illustrated with reference to fig. 48. Nanotube element length dimension L _SW-CHAnd a width dimension W_SW-CHDetermined by the etched trench wall spacing. If the trench wall pitch is substantially equal to the minimum technology node dimension F in the X and Y directions, L is for technology nodes 90nm, 65nm, 45nm, and 22nm, for example_SW-CHAnd W_SW-CHWill be, for example, about 90nm, 65nm, 45nm, and 22 nm.

The method fills the trench with an insulator; the method then planarizes the surface. The method then deposits and patterns word lines on the planarized surface.

Fabrication of the vertically oriented 3D cell shown in fig. 47 proceeds as follows. The method deposits a bit line wiring layer on the surface of insulator 3403, having a thickness of, for example, 50 to 500nm, as described further below with reference to fig. 48. Fabrication of the vertically oriented diode portion of structure 4785 is the same as fig. 34A and 34B, described further above, and is incorporated into the fabrication method described with reference to fig. 48. The method etches the bit line wiring layer and defines the individual bit lines, such as bit line conductors 3410-1(BL0) and 3410-2(BL 1). Bit lines, such as BL0 and BL1, are used as array wiring conductors, and may also be usedAnd the anode terminal of the Schottky diode is taken. Alternatively, Schottky diode junctions 3418-1 and 3418-2 may be formed using metal or silicide contacts (not shown) in contact with N-polysilicon regions 3420-1 and 3420-2 and also in ohmic contact with bit line conductors 3410-1 and 3410-2, and the N-polysilicon regions 3420-1 and 3420-2 may be doped with arsenic or phosphorous in the range of 10 ¹⁴To 10¹⁷Dopant atom/cm³For example, and may have a thickness in the range of, for example, 20nm to 400 nm.

Fig. 47 shows a cathode-to-NT type NV NT diode formed with a schottky diode. However, PN or PIN diodes may be used in place of schottky diodes, as described further below with reference to fig. 48A.

By controlling the material properties of the polysilicon, such as depositing and patterning the polysilicon to form polysilicon regions 3420-1 and 3420-2, the electrical characteristics of the schottky (and PN, PIN) diode may be improved (e.g., low leakage). . The polysilicon region may have a relatively large or relatively small grain boundary size as determined by the method used in the semiconductor region. For example, SOI deposition methods used in the semiconductor industry may be used, which result in a polycrystalline silicon region that is monocrystalline (no longer polycrystalline), or nearly monocrystalline, for further enhancement of electrical properties, such as low diode leakage current.

Examples of contact and conductor materials include elemental metals such as Al, Au, W, Cu, Mo, Pd, Ni, Ru, Ti, Cr, Ag, In, Ir, Pb, Sn, and metal alloys such as TiAu, TiCu, TiPd, Pbin, and TiW, other suitable conductors, or conductive nitrides, oxides, or silicides such as RuN, RuO, TiN, TaN, CoSi _xAnd TiSi_x. The insulator can be SiO₂、SiN_x、Al₂O₃BeO, polyimide, mylar, or other suitable insulating material.

In some examples, conductors such as Al, Au, W, Cu, Mo, Ti, and others may be used as both contacts and conductor materials as well as the anode of the schottky diode. However, in other examples, the needleIt is advantageous to optimize the anode material for low forward voltage drop and low diode leakage. Schottky diode anode material (not shown) may be added between conductors 3410-1 and 3410-2 and polysilicon regions 3420-1 and 3420-2, respectively. Such anode materials may include Al, Ag, Au, Ca, Co, Cr, Cu, Fe, Ir, Mg, Mo, Na, Ni, Os, Pb, Pd, Pt, Rb, Ru, Ti, W, Zn, and other elemental metals. In addition, silicides, e.g., CoSi, may be used₂、MoSi₂、Pd₂Si、PtSi、RbSi₂、TiSi₂、WSi₂And ZrSi₂. Schottky diodes formed using such metals and silicides are disclosed in NG, k.k. "compact Guide to Semiconductor Devices", Second Edition, John Wiley&Sons, 2002m pp.31-41, the entire contents of which are incorporated herein by reference.

Next, after the schottky diode select device is completed, the method forms N + polysilicon regions 3425-1 and 3425-2 to contact N polysilicon regions 3420-1 and 3420-2, respectively, and also forms contact regions to make ohmic contacts to contacts 3430-1 and 3430-2. The N + polysilicon is typically doped with arsenic or phosphorous to, for example, 10 ²⁰Dopant atom/cm³And has a thickness of, for example, 20 to 400 nm. The N and N + polysilicon region sizes are defined by the trench etch near the end of the fabrication flow.

Next, the process forms planar insulating regions 4735-1 and 4735-2, typically, for example, SiO, on the surfaces of underlying contacts 3430-1 and 3430-2, respectively₂Having a thickness of, for example, 20 to 500nm, and X and Y dimensions defined by trench etching towards the end of the fabrication flow.

Next, the method forms horizontally oriented nanotube elements 4740-1 and 4740-2 on the surfaces of insulator regions 4735-1 and 4735-2, respectively, the length and width of the nanotube elements being defined near the end of the fabrication flow by trench etching, and the nanotube elements being insulated from direct contact with underlying contacts 3430-1 and 3430-2. To improve the density of cells C00 and C01, nanotube elements 4740-1 and 4740-2 shown in FIG. 47 are horizontally oriented, and trench-defining termination contacts 4764 and 4779 are in contact with nanotube element 4740-1, and termination contacts 4764 'and 4779' are in contact with nanotube element 4740-2, as described further below. Horizontally oriented nanotube elements and methods for making them are described in more detail in the incorporated patent references.

The method then forms protective insulators 4745-1 and 4745-2 on the surfaces of conformal nanotube elements 4740-1 and 4740-2, respectively, with X and Y dimensions defined by trench etching near the end of the fabrication flow. Exemplary methods of forming the protective insulators 4745-1 and 4745-2 are further described below with reference to fig. 48B.

Next, the method forms upper contacts 4750-1 and 4750-2 on the surfaces of protective insulators 4745-1 and 4745-2, respectively, with X and Y dimensions defined near the end of the fabrication process by trench etching.

Next, the method forms (etches) a trench opening of width F that forms cells C00 and C01 and corresponding upper and lower contacts, nanotube element, and outer sidewalls of the insulator, as further described above.

Next, vertical wirings 4762 and 4762' of sidewalls are formed by a method. Vertical sidewall routing 4762 forms and connects terminal-contact 4764 of nanotube element 4740-1 with terminal-contact 4766 of underlying contact 3430-1; vertical sidewall routing 4762 ' forms and connects terminal-contact 4764 ' of nanotube element 4740-2 with terminal-contact 4766 ' of underlying contact 3430-2.

Next, the method completes trench formation (etching) to the surface of insulator 3403.

Next, the method fills the trench opening with an insulator such as TEOS and planarizes the surface to complete trench fill 4769.

The method then forms (etches) a trench opening of width F that forms cells C00 and C01 and the corresponding upper and lower layer contacts, nanotube elements, and the outer sidewalls of the insulator, as further described above.

Next, the method forms the vertical wiring 4776 and 4776' of the sidewall. Vertical sidewall routing 4776 forms and connects terminal-contact 4778 of nanotube element 4740-1 with a terminal-contact region of upper level contact 4750-1; vertical sidewall routing 4776 'forms and connects terminal-contact 4778' of nanotube element 4740-2 with a terminal-contact region of upper contact 4850-2.

Next, the method completes trench formation (etching) to the surface of insulator 3403.

Next, the method fills the trench openings with an insulator such as TEOS and planarizes the surface to complete trench fills 4882 and 4882'.

Next, the method directionally etches and forms wordline contacts 4784C-1 and 4784C-2 on the surfaces of upper contacts 4750-1 and 4750-2, respectively, by depositing and planarizing the wordline layer.

Next, the method patterns the word line 4784.

The nonvolatile nanotube diode forming cells C00 and C01 corresponds to the nonvolatile nanotube diode 1200 of fig. 12, one for each of cells C00 and C01. Cells C00 and C01 of cross-section 4785 shown in fig. 47 correspond to respective cells C00 and C01 of memory array 2610 schematically shown in fig. 26A, while bit lines BL0 and BL1 and word line WL0 correspond to the array lines schematically shown in memory array 2610.

Method 2700 shown in FIGS. 27A and 27B can be used to fabricate a memory using a memory having a cathode-to-NT switch connectionHorizontally orientedThe NV NT diode device of a self-aligned NV NT switch (such as shown in section 4785 of fig. 47) as further described below with reference to fig. 48. A structure such as cross-section 4785 may be used to fabricate memory 2600, shown schematically in fig. 26A.

Using diodes with vertical orientation and conducting trench-fill as cathode-to-NT switch connectionHorizontally oriented self-alignedNV NT device for NT switch fabrication of three-dimensional cell junction of non-volatile cellMethod of construction

The method 2710 of fig. 27A is used to define support circuits and interconnects, which are similar to those described further above with respect to the memory 2600 of fig. 26A. The method 2710 applies well known semiconductor industry technology design and fabrication techniques to fabricate support circuits and interconnects 3401 in and on a semiconductor substrate, as shown in fig. 48A. The support circuits and interconnects 3401 include FET devices in a semiconductor substrate and interconnects, such as vias and wires, on the semiconductor substrate. Fig. 48A corresponds to fig. 34A, showing a schottky diode structure, except that the optional conductive schottky anode contact layer 3415 shown in fig. 34A is not shown in fig. 48A. Note that fig. 34A 'may be initially used in place of fig. 34A' if a PN diode structure is desired. If the N polysilicon layer 3417 in fig. 34A' is replaced with an intrinsic doped polysilicon layer (not shown), a PIN diode will be formed instead of a PN diode. Thus, although the structure shown in fig. 48A illustrates a schottky diode structure, the structure may also be manufactured using a PN diode or a PIN diode.

Methods of fabricating the elements and structures of the support circuitry and interconnects 3401, insulator 3403, memory array support structure 3405, conductor layer 3410, N polysilicon layer 3420, N + polysilicon layer 3425, and underlying contact layer 3430 shown in fig. 48 are further described above with reference to fig. 34A and 34B.

Next, the manufacturing method deposits an insulator layer 4835 on the surface of the lower layer contact layer 3430 as shown in fig. 48B. Insulator layer 4835 is typically SiO₂With a thickness in the range of, for example, 20 to 500 nm.

Next, the method deposits a horizontally oriented nanotube layer 4840 on the planar surface of the insulator layer 4835 as shown in fig. 48B. The horizontally-oriented nanotube layer 4840 can be formed using a single nanotube layer, or can be formed using multiple nanotube layers. Such a nanotube layer can be deposited using, for example, spin-on coating techniques or spray-on coating techniques, as described in more detail in the incorporated patent references.

Then, the method isA protective insulator layer 4845 is formed on the surface of the nanotube layer 4840 as shown in fig. 48B. The protective insulator layer 4845 can be formed using suitable materials known in the CMOS industry, including but not limited to: PVDF (polyvinylidene fluoride), polyimide, PSG (phosphosilicate glass) oxide, orlon (Orion) oxide, LTO (planarizing low temperature oxide), sputtered oxide or nitride, flow-fill (flowfill) oxide, ALD (atomic layer deposition) oxide. CVD (chemical vapor deposition) nitrides may also be used, and these materials may be used in combination with each other, for example, a PVDF layer or PVDF blends and other copolymers may be placed on top of the nanotube layer 4840, and this composite (complex) may be covered with ALD Al ₂O₃Layer, however any high temperature polymer that does not contain oxygen can be used as the passivation layer. In some embodiments, a passivation material such as PVDF may be mixed or formulated with other organic or dielectric materials such as PC7 to produce specific passivation properties, for example to provide extended lifetime and reliability. Various materials and methods are described in U.S. patent application No.11/280,786.

At this point in the manufacturing process, the method deposits an upper layer contact layer 4850 on the surface of insulator layer 4845, as shown in fig. 48B. The thickness of the upper layer contact layer 4850 may be, for example, 10 to 500 nm. The upper layer contact 4850 can be formed using: al, Au, W, Cu, Mo, Pd, Ni, Ru, Ti, Cr, Ag, In, Ir, Pb, Sn, and metal alloys such as TiAu, TiCu, TiPd, Pbin, and TiW, other suitable conductors, or conductive nitrides, oxides, or silicides such as RuN, RuO, TiN, TaN, CoSi_xAnd TiSi_x。

Next, the method deposits a sacrificial layer 4852 (sacrificial layer 1) on the upper layer contact layer 4850, as shown in fig. 48C. The sacrificial layer 4852 can have a thickness in the range of 10 to 500nm and be formed using a conductive, semiconductor, or insulator material, such as the materials described further above with respect to the underlying contact layer 3430, semiconductor layers 3420 and 3425, and insulator layers 4835 and 4845.

Next, the process deposits and patterns a mask layer (not shown) deposited on the top surface of the sacrificial layer 4852 using known industry methods. The mask openings can be aligned to, for example, alignment marks in the planar insulating layer 3403; this alignment is non-critical.

The process then directionally etches the sacrificial layer 4852 using known industry methods to form openings of size DX1 that stop at the surface of the upper layer contact layer 4850 through the sacrificial layer 4852, as shown in fig. 48D. As described further below, two memory cells are formed, including horizontal nanotube channel elements that are self-aligned and positioned with respect to the vertical edges of sacrificial cap layer (cap)1 region 4852' and sacrificial cap layer 1 region 4852 ". Dimension DX1 is about 3F, where F is the minimum lithographic dimension. For a 65nm technology node, DX1 is about 195 nm; for the 45nm technology node, DX1 is about 135 nm; whereas for the 22nm technology node DX1 is about 66 nm. These DX1 dimensions are much larger than the technology minimum dimension F and therefore are non-critical dimensions for any technology node.

Next, the method deposits a second conformal sacrificial layer 4853 (sacrificial layer 2), as shown in fig. 48E. The thickness of the conformal sacrificial layer 4853 is selected to be F. In this example, if F is 45nm, the thickness of the conformal sacrificial layer 4853 is about 45 nm; if F is 22nm, the thickness of the conformal sacrificial layer 4853 is about 22 nm. Conformal sacrificial layer 4853 may be formed using a conductor, semiconductor, or insulator material, i.e., similar to the materials used to form sacrificial layer 4852 described further above.

Next, the method directionally etches the conformal sacrificial layer 4853 using known industry methods such as Reactive Ion Etching (RIE), forming openings 4855 with a size of about F, which in this example may be in the range 22 to 45nm, as shown in fig. 48F. The inner sidewalls of the second sacrificial cover layer 2 region 4853 'and the second sacrificial cover layer 2 region 4953 "in the opening 4855 are self-aligned to the inner walls of the sacrificial regions 4852' and 4852" and are separated by a distance of about F.

At this point in the process, sacrificial regions 4853' and 4853 "may be used as a mask layer to directionally etch trenches using a method that defines the cell boundaries of a 3D cell in the X-direction using an NV NT diode with an internal cathode-to-nanotube connection per cell. U.S. patent 5,670,803 to Bertin, which is incorporated herein by reference in its entirety, discloses a 3-D array (3D-SRAM in this example) structure having sidewall dimensions that are simultaneously trench-defined. The structure includes vertical sidewalls simultaneously defined by trenches cut through the multi-layer doped silicon and insulating regions to avoid multiple alignment steps. This trench-directed selective etch process can cut through multiple layers of conductor, semiconductor, and oxide layers as further described above with respect to the trench formation of FIGS. 34A-34FF and 36A-36 FF. In this example, a selective directional trench etch (RIE) removes the exposed areas of the upper contact layer 4850 to form upper contact regions 4850' and 4850 "; removing the exposed regions of the protective insulator layer 4845 to form protective insulator regions 4845' and 4845 "; removing the exposed areas of the nanotube layer 4840 to form nanotube regions 4840' and 4840 "; removing the exposed region of the insulating layer 4835 to form insulating regions 4835' and 4835 ″; removing exposed regions of the lower contact layer 3430 to form lower contact regions 3430' and 3430 "; and a selective directional etch stops on the top surface of the N + polysilicon layer 3425 to form trench openings 4857, as shown in fig. 48G.

Next, a method such as evaporation or sputtering fills the trench 4857 with a conductor material 4858 as shown in fig. 48H. Examples of conductor layer materials are elemental metals, such as Al, Au, W, Cu, Mo, Pd, Ni, Ru, Ti, Cr, Ag, In, Ir, Pb, Sn, and metal alloys, such as TiAu, TiCu, TiPd, PbIn, and TiW, other suitable conductors, or conductive nitrides, oxides, or silicides, such as RuN, RuO, TiN, TaN, CoSi_xAnd TiSi_x. A conductive material is formed into the sidewall wiring regions as described further below. Since the wiring distance is short, there is no fear of sheet resistance of the trench sidewall wiring. The nanotube contact resistance value, nanotube contact resistance difference, and nanotube contact resistance reliability between the trench sidewall routing and the ends of nanotube regions 4840' and 4840 "are criteria used in selecting the conductor type. Because of a plurality of nano-meters connected in parallelThe large cross-sectional area of the nanotube area of the tube generally results in a reduction in the overall contact resistance. Trench sidewall contacts to the nanotube termination region and underlying metal sidewall regions are used to form cell cathode-to-NT connections. A non-volatile nanotube switch with terminal unique contacts is described further below with reference to fig. 49 and 50.

Next, the method selectively directionally etches the conductor 4858 to a depth DZ1 below the top surface of the sacrificial cap layer 2 regions 4853' and 4853 ", as shown in FIG. 48I. The DZ1 is selected to ensure complete contact with the nanotube termination region and not with the upper contact region. At this point in the process, the sidewall of conductor 4858 ' is in electrical contact with one terminal of nanotube region 4840 ' and one terminal of underlying conductor 3430 ', and is also in electrical contact with one terminal of nanotube region 4840 "and one terminal of underlying conductor 3430". Two separate sidewall routing regions may be formed, as described further below.

Next, the method deposits a conformal insulator layer 4860, as shown in fig. 48J. Conformal insulator 4860 can be, for example, 5-50 nm thick, and can be formed of any suitable known insulator material in the CMOS industry or the packaging industry, such as SiO₂、SiN、Al₂O₃BeO, polyimide, PSG (phosphosilicate glass), photoresist, PVDF (polyvinylidene fluoride), sputtered glass, epoxy glass, and other dielectric materials and combinations of dielectric materials, such as Al-coated₂O₃PVDF of the layer, as described in U.S. patent application No.11/280,786. Insulator 4860 is deposited to a film thickness that determines the thickness of the trench sidewall wiring, as described further below.

Next, the method directly etches the conformal insulator 4860 using RIE and removes the conformal layer material on the top horizontal surface and on the bottom horizontal surface at the bottom of the trench opening to form trench opening 4861 having sidewall insulators 4860 'and 4860 "and conductor 4858', as shown in fig. 48K.

Next, the method directionally etches conductor 4858 'using sidewall insulators 4860' and 4860 "as mask regions and stopping on the surface of N + polysilicon layer 3425, as shown in fig. 48L. The thickness of sidewall insulators 4860' and 4860 "determines the thickness of the trench sidewall routing region, as described below. Trench sidewall wire 4862 is formed which forms contact 4864 between trench sidewall wire 4862 and one terminal end of nanotube region 4840'. Trench sidewall wiring 4862 also forms contact 4866 having one sidewall (terminal end) of underlying contact 3430'. Trench sidewall wire 4862 ' is formed which forms contact 4864 ' between trench sidewall wire 4862 ' and one terminal end of nanotube region 4840 ". Trench sidewall wiring 4862 'also forms contact 4866' having one sidewall (terminal end) of underlying contact 3430 ".

Next, the method directionally etches the exposed regions of the N + polysilicon layer 3425 to form N + polysilicon regions 3425' and 3425 "; etching exposed regions of the polysilicon layer 3420 to form N polysilicon regions 3420' and 3420 "; and the exposed regions of conductor layer 3410 are etched to form conductor regions 3410' and 3410 "stopping at the surface of insulator 3403. Sidewall insulators 4860 'and 4860 "and trench sidewall conductors 4862 and 4862' are used as masks. The directional etch stops on the top surface of insulator 3403, forming trench openings 4867', as shown in fig. 48M.

Next, the method fills the trench openings 4867' with an insulator 4869, such as TEOS, and planarizes as shown in fig. 48N.

At this point in the process, a second cell boundary is formed along the X-direction of the 3D memory cell. The process removes (etches) the sacrificial cap layer 1 regions 4852 'and 4852 ", exposing portions of the surface of the upper contact regions 4850' and 4850", as shown in fig. 48O.

At this point in the process, sacrificial regions 4853' and 4853 "may be used as a mask layer for directionally etching trenches using a method that defines another cell boundary of the 3D cell in the X-direction using one NV NT diode with one interior cathode-to-nanotube connection per cell, as further described above with reference to fig. 48F. The structure includes vertical sidewalls simultaneously defined by trenches cut through the multi-layer doped silicon and insulating regions to avoid multiple alignment steps. This trench-directed selective etch process can cut through multiple layers of conductors, semiconductors, and oxide layers as further described above with respect to the trench formation of fig. 48F and fig. 34A-34FF and 36A-36 FF. In this example, a selective directional trench etch (RIE) removes exposed areas of the upper contact regions 4550' and 4850 "to form upper contacts 4850-1 and 4850-2, respectively; removing exposed regions of protective insulator regions 4845' and 4845 "to form protective insulators 4845-1 and 4845-2, respectively; removing exposed areas of nanotube regions 4840' and 4840 "to form nanotube elements 4840-1 and 4840-2, respectively; and a selective directional etch stops on the top surfaces of the insulator regions 4835 'and 4835 "to form trench openings 4871 and 4871', as shown in figure 48P.

Next, the trenches 4871 and 4871' are filled with a conductor material 4872, such as by evaporation or sputtering, as shown in fig. 48Q, and also as further described above with reference to fig. 48H.

Next, the method selectively directionally etches conductor 4872 to a depth DZ2 below the top surface of sacrificial cap layer 2 regions 4853' and 4853 ", as shown in fig. 48R. The DZ2 is adjusted to ensure complete contact to the nanotube termination region while also contacting the upper contacts. At this point in the process, the sidewalls of conductors 4872' and 4872 "are in electrical contact with one terminal of each nanotube element 4840-1 and 4840-2, respectively, and with one terminal of upper conductors 4850-1 and 4850-2, respectively. Sidewall routing regions may be formed as described further below.

Next, the method deposits a conformal insulator layer 4874 as shown in fig. 48. Conformal insulator 4874 can be, for example, 5 to 50nm thick, and can be formed from any insulator material known in the CMOS industry or the packaging industry, e.g., SiO₂、SiN、Al₂O₃BeO, polyimide, PSG (phosphosilicate glass), photoresist, PVDF (polyvinylidene fluoride), sputtered glass, epoxy glass, and other dielectric materials and combinations of dielectric materials, such as Al-coated₂O₃PVDF of layers, e.g. American As described in national patent application No.11/280,786. Insulator 4874 is deposited to a film thickness that determines the thickness of the trench sidewall wiring, as described further below.

Next, the method directly etches the conformal insulator 4874 using RIE and removes the conformal layer material on the top horizontal surface and on the bottom horizontal surface at the bottom of the trench opening to form a trench opening having sidewall insulators 4874 'and 4874 "and conductors 4872' and 4872", as shown in fig. 48T.

Next, the method directionally etches conductors 4872 ' and 4872 ", respectively, using sidewall insulators 4874 ' and 4874", respectively, and the corresponding insulators (not shown) on the other sides of trenches 4880A and 4880B as mask regions and stopping on the top surfaces of insulator regions 4835 ' and 4835 ", respectively, as shown in fig. 48U. The thickness of the sidewall insulators 4874' and 4874 "determines the thickness of the trench sidewall routing regions, as described below. Trench sidewall wiring 4876 is formed which in turn forms contact 4879 between trench sidewall wiring 4876 and one terminal of nanotube element 4840-1. Trench sidewall routing 4876 also forms contact 4878 having one sidewall (terminal) of upper layer contact 4850-1. Trench sidewall routing 4876 ' is formed, which in turn forms contact 4879 ' between trench sidewall routing 4876 ' and one terminal of nanotube element 4840-2. Trench sidewall routing 4876 'also forms contact 4878' having one sidewall (terminal) of upper layer contact 4850-2.

Next, the method directionally etches exposed areas of the insulator regions 4835' and 4835 "to form insulators 4835-1 and 4835-2, respectively; directionally etching lower contact regions 3430' and 3430 "to form lower contacts 3430-1 and 3430-2, respectively; directionally etching N + polysilicon regions 3425' and 3425 "to form N + polysilicon regions 3425-1 and 3425-2, respectively; directionally etching exposed regions of polysilicon regions 3420' and 3420 "to form N polysilicon regions 3420-1 and 3420-2; and directionally etching exposed regions of conductor regions 3410' and 3410 "to form conductors 3410-1 and 3410-2, respectively, stopping at the surface of insulator 3403. Sidewall insulators 4874 'and 4874 "and trench sidewall conductors 4876 and 4876' are used as masks. The directional etch stops on the top surface of insulator 3403, forming trench openings 4880A 'and 4880B', as shown in fig. 48V.

Next, the method fills trench openings 4880A 'and 4880B' with insulator 4882, e.g., TEOS, and planarizes as shown in fig. 48W.

Next, the process removes (etches) the sacrificial cap 2 regions 4853 'and 4853 "to form openings 4883 and 4883', respectively, exposing the top surfaces of the upper contacts 5850-1 and 5850-2, respectively, as shown in FIG. 48X.

Next, a conductor layer 4884 is deposited and planarized, and conductor layer 4884 also forms contacts 4884C-1 and 4884C-2 that contact upper contacts 4850-1 and 4850-2, respectively, as shown in FIG. 48Y.

Next, conductor layer 4884 is patterned to form word lines perpendicular to conductors (bit lines) 3410-1 and 3410-2, as described further below.

At this point in the process, cross-section 4885 shown in FIG. 48Y has been fabricated and includes NV NT diode cells of size F (where F is the minimum feature size) and a corresponding array bit line with an X-direction upper limit cell period of 2F. Next, cell dimensions to define dimensions in the Y-direction are formed by a directional trench etch process, similar to that described further above with respect to section 4885 shown in fig. 48Y. The trench to define the dimension in the Y direction is substantially perpendicular to the trench to define the dimension in the X direction. In this example, the cell characteristics in the Y-direction relative to the X-direction dimension do not require self-alignment techniques as described further above. The cross-section of the structure in the Y (bit line) direction is illustrated with respect to the cross-section X-X' shown in fig. 48Y.

Next, the method deposits and patterns a mask layer, such as mask layer 4884A, on the surface of word line layer 4884, as shown in fig. 48Z. The mask layer 4884A can be non-critically aligned to alignment marks in the planar insulator 3403. The opening in mask layer 4884A determines the location of the trench directional etch region, which in this case is substantially perpendicular to the bit line, such as conductor 3410-1(BL 0).

At this point in the process, the openings in mask layer 4884A may be used for directional etching of trenches using a method to define new cell boundaries in the Y-direction of the 3D cell using one NV NT diode with an internal cathode-to-nanotube connection per cell. All trenches and corresponding cell boundaries may be formed simultaneously. The structure includes vertical sidewalls simultaneously defined by the trenches. This trench-oriented selective etch method can cut through multiple layers of conductors, semiconductors, and oxide layers as described further below and also as described further above with respect to the trench formation in fig. 48F-48M and also in fig. 34A-34FF and 36A-36 FF. In this example, a selective directional trench etch (RIE) removes the exposed areas of conductive layer 4884 to form word line conductors 4884-1(WL0) and 4884-2(WL 1); removing exposed areas of contact area 4884C-1 to form contacts 4884C-1' and 4884C-1 "; the exposed areas of the upper contact regions 4850-1 and 4850-2 are removed to form upper contacts 4850-1' and 4850-1 "; the exposed regions of protective insulator regions 4845-1 and 4845-2 are removed to form protective insulators 4845-1' and 4845-1 "; removing exposed areas of nanotube regions 4840-1 and 4840-2 to form nanotube elements 4840-1' and 4840-1 "; removing exposed areas of the insulator regions 4835-1 and 4835-2 to form insulators 4835-1' and 4835-1 "; the exposed areas of the lower contact regions 3430-1 and 3430-2 are removed to form lower contacts 3430-1' and 3430-1 "; removing exposed regions of N + polysilicon regions 3425-1 and 3425-2 to form N + polysilicon regions 3425-1' and 3425-1 "; and the exposed regions of polysilicon regions 3420-1 and 3420-2 are removed to form N polysilicon regions 3420-1' and 3420-1 ". The directional etch stops on the top surface of conductor 3410-1, forming trench openings 4886, as shown in fig. 48 AA.

The method then fills the trenches 4886 with an insulator 4888, such as TEOS, and planarizes the surface as shown in cross-section 4885' of fig. 48 BB. Cross-section 4885' shown in fig. 48BB and cross-section 4885 shown in fig. 48Y are representative of two cross-sections of the same 3D non-volatile memory array having cells formed from NV NT diodes with vertically oriented steering (select) diodes and horizontally oriented nanotube elements routed at each termination contact. The cross-section 4885 shown in fig. 48Y corresponds to the cross-section 4785 shown in fig. 47.

At this point in the process, cross-sections 4885 and 4885' shown in FIGS. 48Y and 48BB are fabricated, respectively, and the horizontally-oriented channel length L of the nonvolatile nanotube element is determined_SW-CHIs defined to include NV NT diode cells having overall dimensions of 1F in the X-direction and 1F in the Y-direction, as well as corresponding bit line and word line array lines. Cross section 4885 is a cross section in the X direction of two adjacent cathode-to-nanotube type nonvolatile nanotube diode-based cells, while cross section 4885' is a cross section in the Y direction of two adjacent cathode-to-nanotube type nonvolatile nanotube diode-based cells. Sections 4885 and 4885' include respective word line and bit line array lines. The nonvolatile nanotube diode forms steering and storage elements in each cell shown in cross-sections 4885 and 4885', and each cell has dimensions of 1F by 1F. The pitch between adjacent cells is 1F, so the cell period is 2F in both the X and Y directions. So that one bit occupies an area of 4F ². At the 45nm technology node, the unit area is less than 0.01um²。

Non-volatile nanotube switch with nanotube element having channel-region terminal contact

Fig. 49 shows NV NT switch 4900 including patterned nanotube element 4910 on insulator 4920, the insulator 4920 being supported by substrate 4930. Patterned protective insulator 4935 contacts the top surface of nanotube element 4910. Examples of nanotube element 4910 and protective insulator 4935 are further described above with reference to fig. 48A-48 BB. Terminals (conductor elements) 4940 and 4950 are deposited adjacent to the termination-area of nanotube element 4910 and form terminal-to-nanotube termination-area contacts 4960 and 4965, respectively. Examples of terminal-area contacts to nanotube elements are further described above with reference to fig. 48L and 48U. Non-volatile nanotube switch channel length L_SW-CHTerminal-area contacts 4960 and 496 for nanotube element5, in the space between them. Substrate 4930 may be an insulator such as ceramic or glass, a semiconductor, or an organic rigid or flexible substrate. The insulator 4920 may be SiO2, SiN, Al₂O₃Or other insulator material. The terminals (conductor elements) 4940 and 4950 may be formed using various contact and interconnect element metals, such as Ru, Ti, Cr, Al (Cu), Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn, and metal alloys, such as TiAu, TiCu, TiPd, PbIn, and TiW, other suitable conductors, or conductive nitrides, oxides, or silicides, such as RuN, RuO, TiN, TaN, CoSi _xAnd TiSi_x。

Curve 5000 of fig. 50 shows experimental test results for a single non-volatile nanotube switch 4900 having a nanotube element 4910 channel length of about 250nm and terminals (conductive elements) 4940 and 4950 formed from TiPd. Switching results for 100ON/OFF cycles of non-volatile nanotube switch 4900 show that most ON resistance values are in the range of 10 kilo-ohms to 100 kilo-ohms, some ON resistance values are 800 kilo-ohms as shown by resistance 5010, and OFF resistance values are in the range of 500 mega-ohms to 100 giga-ohms as shown by resistance 5020. In some examples 5030, the ON resistance value is greater than 100 megaohms.

If the 3D memory array is used for non-volatile flash applications, a flash architecture can be used to detect instance 5030 with an ON resistance greater than OFF resistance 5010 and apply one or more additional cycles as needed to ensure that the ON resistance is less than 1 megaohm, as shown by curve 5000.

The ON/OFF resistance value of nonvolatile nanotube switch 4900 shows that the spread of ON resistance values decreases and the distribution of ON resistance values concentrates after tens (or hundreds) of cycles. Curves 5010 and 5020 of the 80 to 100ON/OFF cycle range show ON resistance values between, for example, 10 kOhms and less than 1 megaohm, and OFF resistance values greater than 80 megaohms. The non-volatile nanotube switch can be used in any memory architecture. Non-volatile nanotube switch 4900, which applies tens or hundreds of cycles to the fabrication state, may be used as part of a memory array burn-in operation. Examples of the cycling between the ON and OFF resistance values resulting from the application of voltages and currents are further described above with reference to fig. 11A and 11B.

Using diodes with vertical orientation and conductor trench-fill as anode switch connection on NTHorizontally oriented self-alignedThree-dimensional cell structure of non-volatile cell of NV NT device of NT switch

FIG. 51 shows a cross-section 5185 including cells C00 and C10 in a 3-D memory embodiment. The nanotube layer is deposited horizontally on a flat insulator surface that is located on a predefined diode-forming layer (as further shown in fig. 36A and 36B above). Self-alignment methods similar to those described further above with reference to fig. 34A-34FF, 36A-36FF, and 48A-48BB determine the size and location of trenches used to define cell boundaries. Self-aligned trench sidewall routing connects horizontally oriented nanotube elements to vertically oriented diodes and also to array routing.

A method 3010, as described further above with reference to fig. 30A, is used to define the support circuits and interconnects 3601.

Next, method 3030 shown in fig. 30B deposits and planarizes insulator 3603. An interconnect device (not shown in section 5185, but further shown above with respect to section 2800 "of fig. 28C) through the planar insulator 3603 may be used to connect metal array lines in the 3-D array to respective support circuits and interconnects 3601. As an example, the word line drivers in WL driver and sensing circuit 2930 may be connected to word lines WL0 and WL1 in array 2910 of memory 2900 (as shown in fig. 29A and in section 5185 shown in fig. 51, described further above). At this point in the fabrication process, method 3040 may be used to form a memory array on the surface of insulator 3603, interconnected to memory array support structure 3605-1 shown in FIG. 51.

The exemplary method 3040 illustrated in FIG. 30B deposits and planarizes metal, polysilicon, insulator, and nanotube elements to form non-volatile nanotube diodes, which in this case include a plurality of vertically oriented diodes anda horizontally oriented series pair of non-volatile nanotube switches. To eliminate the accumulation of individual layer alignment tolerances that substantially increase the cell area, individual cell boundaries are formed in a single etching step, each cell having an individual NV NT diode defined by a single trench etching step after the layers (except the BL0 layer) have been deposited and planarized. The size of a single cell in the Y direction is F (1 minimum feature) as shown in fig. 51, while in the X direction (not shown) perpendicular to the Y direction is also F with periodicity 2F in the X and Y directions. Thus, each cell occupies an area of about 4F²。

Vertically oriented (Z-direction) trench sidewall cell wiring on the first cell sidewall connecting the vertically oriented diode with one terminal of the horizontally oriented nanotube element; and vertically oriented trench sidewall cell wiring on the second cell sidewall connects the other terminal of the horizontally oriented nanotube element with the array wiring. Exemplary methods of forming vertically oriented trench sidewall cell routing can be modified from methods of patterning shapes on trench sidewalls, such as the method disclosed in U.S. patent 5,096,849. The dimensions of the horizontally oriented NV NT switching elements (nanotube elements) in the X and Y directions are defined by the trench etch. In the X or Y direction, the nanotube element has no alignment requirements. The thickness (Z-direction) of the nanotube element is typically in the range of 5 to 40 nm. However, the thickness of the nanotube element can be any desired thickness, such as less than 5nm or greater than 40 nm.

Horizontally oriented nanotube elements can be formed using a single nanotube layer, or can be formed using multiple layers. Such nanotube element layers can be deposited, for example, using spin-on coating techniques or spray-on coating techniques, as described more fully in the incorporated patent references. Fig. 51 shows a 3-D memory array cross-section 5185 in the Y-direction and corresponds to the fabrication method described with reference to fig. 48A-48BB, but with a minor modification in that fig. 36A and 36B replace fig. 34A and 34B to form an NT upper anode 3D memory cell (rather than an NT upper cathode memory cell). The NV NT switch is formed using the same manufacturing method as further described above with reference to fig. 48A-48 BB. Nanotube element length dimension L_SW-CHAnd a width dimension W_SW-CHDetermined by the etched trench wall spacing. If the trench wall pitch is equal to the minimum technology node dimension F in the X and Y directions, L is equal to the minimum technology node dimension F for technology nodes such as 90nm, 65nm, 45nm, and 22nm_SW-CHAnd W_SW-CHWill be, for example, about 90nm, 65nm, 45nm, and 22 nm.

The method fills the trench with an insulator; the method then planarizes the surface. The method then deposits and patterns bit lines on the planarized surface.

Fabrication of the vertically oriented 3D cell shown in fig. 51 proceeds as follows. The method deposits a word line wiring layer on the surface of insulator 3603, having a thickness of, for example, 50 to 500nm, as further illustrated above with reference to fig. 48A-48BB (the word line wiring layer in fig. 51 corresponds to the bit line wiring layer of fig. 48A-48 BB). Fabrication of the vertically oriented diode portion of structure 5185 is the same as fig. 36A and 36B, described further above, and is incorporated into the fabrication method described with reference to fig. 51. The method etches the word line wiring layer and defines individual word lines, such as word line conductors 3610-1(WL0) and 3610-2(WL 1). Word lines, such as WL0 and WL1, are used as array wiring conductors and may also be used as contacts to N + regions 3620-1 and 3620-2, which are in contact with N regions 3625-1 and 3625-2 which form the cathodes of schottky diodes. The N + polysilicon regions 3620-1 and 3620-2 may be doped with As or P to 10 ²⁰Dopant atom/cm³Or more, and the N-polysilicon regions 3625-1 and 3625-2 may be doped with arsenic or phosphorous, for example, in the range of 10¹⁴To 10¹⁷Dopant atom/cm³And may have a thickness in the range of, for example, 20nm to 400 nm.

Fig. 51 shows an anode-to-NT type NV NT diode, which is formed with a schottky diode. However, PN or PIN diodes may be used in place of schottky diodes.

By controlling the material properties of the polysilicon, such as depositing and patterning the polysilicon to form polysilicon regions 3625-1 and 3625-2, schottky (and PN, PIN) diode electrical characteristics may be improved (e.g., low leakage). The polysilicon regions may have a relatively large or relatively small grain boundary size, which is determined by the method used in the semiconductor region. For example, to further enhance electrical properties, such as low diode leakage, SOI deposition methods in the semiconductor industry may be used, which result in the polysilicon region being monocrystalline (no longer polysilicon), or nearly monocrystalline.

Methods form lower contacts 3630-1 and 3630-2. Examples of contact conductor materials include elemental metals such as Al, Au, W, Cu, Mo, Pd, Ni, Ru, Ti, Cr, Ag, In, Ir, Pb, Sn, and metal alloys such as TiAu, TiCu, TiPd, Pbin, and TiW, other suitable conductors, or conductive nitrides, oxides, or silicides such as RuN, RuO, TiN, TaN, CoSi _xAnd TiSi_x. The insulator can be SiO₂、SiN_x、Al₂O₃BeO, polyimide, mylar, or other suitable insulating material.

Lower layer contacts 3630-1 and 3630-2 also form the anodes of schottky diodes having schottky diode junctions 3618-1 and 3618-2. In some examples, conductors such as Al, Au, W, Cu, Mo, Ti, and others may be used as both the contact conductor material and the anode of the schottky diode. However, in other examples, it is advantageous to optimize the anode material for low forward voltage drop and low diode leakage. Schottky diode anode material (not shown) may be added between underlying contacts (and schottky diode anodes) 3630-1 and 3630-2 and polysilicon regions 3625-1 and 3625-2, respectively. Such anode materials may include Al, Ag, Au, Ca, Co, Cr, Cu, Fe, Ir, Mg, Mo, Na, Ni, Os, Pb, Pd, Pt, Rb, Ru, Ti, W, Zn, and other elemental metals. In addition, silicides, e.g., CoSi, may be used₂、MoSi₂、Pd₂Si、PtSi、RbSi₂、TiSi₂、WSi₂And ZrSi₂. Schottky diodes formed using such metals and silicides are disclosed in NG, k.k. "compact Guide to Semiconductor Devices", Second Edition, John Wiley&Sons, 2002m pp.31-41, the entire contents of which are incorporated herein by reference.

Next, the process forms planar insulating regions 4735-1 and 4735-2, typically, for example, SiO, on the surface of underlying contacts 3630-1 and 3630-2, respectively₂Having a thickness of, for example, 20 to 500nm, and X and Y dimensions defined by trench etching towards the end of the fabrication flow.

Next, the method forms horizontally oriented nanotube elements 4740-1 and 4740-2 on the surfaces of insulator regions 4735-1 and 4735-2, respectively, the nanotube elements length and width being defined near the end of the fabrication process by trench etching, while the nanotube elements are insulated from direct contact with underlying contacts 3430-1 and 3430-2, respectively. To maximize the density of cells C00 and C10, nanotube elements 4740-1 and 4740-2 shown in fig. 51 are horizontally oriented, trench-defining terminal contacts 4764 and 4779 are in contact with nanotube element 4740-1, and terminal contacts 4764 'and 4779' are in contact with nanotube element 4740-2, as described in greater detail in the incorporated patent references.

The method then forms protective insulators 4745-1 and 4745-2 on the surfaces of conformal nanotube elements 4740-1 and 4740-2, respectively, with X and Y dimensions defined by trench etching near the end of the fabrication flow. Exemplary methods of forming the protective insulators 4745-1 and 4745-2 are further described above with reference to fig. 48B.

Next, the method forms upper contacts 4750-1 and 4750-2 on the surfaces of protective insulators 4745-1 and 4745-2, respectively, with X and Y dimensions defined by trench etching near the end of the fabrication flow.

The method then forms (etches) a trench opening of width F that forms the cells C00 and C10 and the corresponding upper and lower layer contacts, nanotube elements, and the inner sidewalls of the insulator, as further described above.

Next, vertical wirings 4762 and 4762' of sidewalls are formed by a method. Vertical sidewall wire 4762 forms and connects terminal-contact 4764 of nanotube element 4740-1 with terminal-contact 4766 of lower level contact 3630-1; vertical sidewall routing 4762 ' forms and connects terminal-contact 4764 ' of nanotube element 4740-2 with terminal-contact 4766 ' of underlying contact 3630-2.

Next, the method completes trench formation (etching) to the surface of insulator 3403.

Next, the method fills the trench opening with an insulator such as TEOS and planarizes the surface to complete trench fill 4769.

The method then forms (etches) a trench opening of width F that forms cells C00 and C10 and the corresponding upper and lower layer contacts, nanotube elements, and the outer sidewalls of the insulator, as further described above.

Next, the method forms the vertical wiring 4776 and 4776' of the sidewall. Vertical sidewall routing 4776 forms and connects terminal-contact 4779 of nanotube element 4740-1 with terminal-contact region 4778 of upper contact 4750-1; vertical sidewall routing 4776 ' is formed to connect terminal-contact 4779 ' of nanotube element 4740-2 with terminal-contact region 4778 ' of upper contact 4850-2.

Next, the method completes trench formation (etching) to the surface of insulator 3403.

Next, the method fills the trench openings with an insulator such as TEOS and planarizes the surface to complete trench fills 4882 and 4882'.

Next, by depositing and planarizing the bit line layer, the method directionally etches and forms bit line contacts 5184C-1 and 5184C-2 on the surfaces of upper layer contacts 4750-1 and 4750-2, respectively.

Next, the method patterns the bit line 5184.

The nonvolatile nanotube diode forming cells C00 and C10 corresponds to the nonvolatile nanotube diode 1300 of fig. 13, one for each of cells C00 and C10. Cells C00 and C10 of cross-section 5185 shown in fig. 51 correspond to respective cells C00 and C10 of memory array 2910 schematically shown in fig. 29A, while word lines WL0 and WL1 and bit line BL0 correspond to the array lines schematically shown in memory array 2910.

After the cross-section 5185 shown in fig. 51 is fabricated, the 3D memory cell boundaries in the X-direction are formed by simultaneous trench etching, trench filling with insulator and planarization. The bitlines and bitline contacts to the upper level contacts are then formed to complete the cross-section 5185' in fig. 52 (corresponding to the cross-section 5185 of fig. 51).

The cross-section 5185' shown in fig. 52 illustrates support circuitry and interconnects 3601 and insulators 3603, as further described above with reference to fig. 51. The cross section 5185' is along the word line WL0 in the X direction.

The N + polysilicon regions 3620-1 'and 3620-1 "form contacts between the word lines 3610-1(WL0) and the N polysilicon regions 3625-1' and 3625-1", respectively, to form diode cathode regions. Lower contacts 3430-1 ' and 3430-1 "serve as anodes to form schottky diode junctions 3618-1 ' and 3618-1" and contacts to nanotube elements 4840-1 ' and 4840-1 ", respectively. The contact between the nanotube element and the underlying contact is shown in the corresponding cross-section 5185 in fig. 51.

Insulators 4835-1 ' and 4835-1 ' are used to separate nanotube elements 4840-1 ' and 4840-1 ', respectively, to avoid electrically contacting lower contacts 3630-1 ' and 3630-1 ".

Protective insulators 4845-1 'and 4845-1 "provide a protective region over the nanotube element and also electrically separate nanotube elements 4840-1' and 4840-1 ', respectively, to prevent electrical contact with upper contacts 4850-1' and 4850-1". The contacts between the nanotube element and the upper layer contacts are shown in the corresponding cross-section 5185.

Bit line contacts 5184-1 ' and 5184-1 ' connect upper layer contacts 4850-1 ' and 4850-1 "to bit lines 5184-1(BL0) and 5184-2(BL1), respectively.

The corresponding cross-sections 5185 and 5185' of fig. 51 and 52 show an anode-to-NT 3D memory array having horizontally oriented nanotube elements, respectively. Nanotube channel length and channel width (W)_SW-CH) NV NT dipolar corresponding to dimension 1F in X-direction and 1F in Y-directionA pipe unit, and corresponding bit lines and word line array lines. Cross section 5185 is a cross section in the Y direction of two adjacent cells of an anode-to-nanotube type based nonvolatile nanotube diode, while cross section 5185' is a cross section in the X direction of two adjacent cells of an anode-to-nanotube type based nonvolatile nanotube diode. Sections 5185 and 5185' include corresponding word lines and bit line array lines. The nonvolatile nanotube diode forms a steering and storage element in each cell shown in cross-sections 5185 and 5185', and each cell has dimensions of 1F by 1F. The pitch between adjacent cells is 1F, so the cell period is 2F in both X and Y directions. So that one bit occupies an area of 4F². At the 45nm technical node, the unit area is less than 0.01um ²。

The fabrication methods of the respective cross-sections 5185 and 5185' shown in fig. 51 and 52 correspond to the fabrication methods described with reference to fig. 48A-48BB, except that the vertical positions of the N polysilicon and N + silicon layers are interchanged. The manufacturing process for making NV NT switches is the same. The only difference is that when forming trenches in sections 5185 and 5185', the N polysilicon layer is etched before the N + polysilicon layer.

Non-volatile memory using NV NT diode device with NV NT switch having both anode-to-NT switch connection and cathode-to-NT switch connection and horizontally oriented self-aligned terminal contact

Fig. 32 illustrates a method 3200 of fabricating an embodiment having two memory arrays stacked on top of each other with support circuitry formed on an insulating layer over the support circuitry under the insulating layer and the stacked arrays, and with a communication device through the insulating layer. Although method 3200 is further described below in relation to nonvolatile nanotube diodes 1200 and 1300, method 3200 is sufficient to encompass the fabrication of many nonvolatile nanotube diodes as described further above. It is also noted that although method 3200 is described in a 3D memory embodiment, method 3200 can also be used to form a 3D logic embodiment based on NV NT diodes arranged as a logic array, such as NAND and NOR arrays with logic support circuitry (rather than memory support circuitry) when used in PLAs, FPGAs, and PLDs.

Fig. 53 illustrates a 3D perspective view 5300 including a dual-high stacked three-dimensional array, a lower array 5302, and an upper array 5304. Lower array 5302 includes nonvolatile nanotube diode cells C00, C01, C10, and C11. The upper array 5304 includes nonvolatile nanotube diode cells C02, C12, C03, and C13. Word lines WL0 and WL1 are oriented along the X-direction, while bit lines BL0, BL1, BL2, and BL3 are oriented along the Y-direction and are substantially perpendicular to word lines WL1 and WL 2. Nanotube element channel length L_SW-CHHorizontally oriented as shown in 3D perspective view 5300. The cross-sections of cells C00, C01, C02, and C03 are further illustrated in fig. 54A as follows, while cells C00, C02, C12, and C10 are further illustrated in fig. 54B as follows.

Generally, method 3210 manufactures support circuitry and interconnects in and on a semiconductor substrate. This includes NFET and PFET devices having drains, sources, and gates interconnected to form memory (or logic) support circuits. Such structures and circuits may be formed using known techniques, which are not described herein. Some embodiments of method 3210 are used to form the support circuitry and interconnect 5401 layers as part of cross-sections 5400 and 5400' (fig. 54A and 54B) using known fabrication methods, wherein the nonvolatile nanotube diode controls and circuitry are fabricated in and on the support circuitry and interconnect 5401 layers. Support circuits and interconnects 5401 are similar to, for example, support circuits and interconnects 3401 in FIG. 47 and 3601 in FIG. 51, but modified to accommodate two stacked memory arrays. Note that although a dual-high stack memory array is shown in fig. 54, more than a dual-high 3D array stack may be formed (fabricated), including but not limited to, for example, 4-high and 8-high stacks.

Method 3210 is then also used to fabricate intermediate structures comprising a planarized insulator, such as insulator 5403 shown in cross-sections 5400 and 5400' in fig. 54A and 54B, and similar to insulator 3403 shown in fig. 47 and insulator 3601 shown in fig. 51, but modified to accommodate two stacked memory arrays, with interconnects and non-volatile nanotube array structures on the planarized insulator surface. The interconnect means includes vertically oriented fill contacts, or studs, for interconnecting memory support circuitry in and on the semiconductor substrate below the planarized insulator, and having an array of non-volatile nanotube diodes above and on the surface of the planarized insulator. The planarization insulator 5403 is formed using a method similar to method 2730 shown in fig. 27B. Interconnect means (not shown in cross-section 5400) through planar insulator 5403 are similar to contacts 2807 shown in fig. 28C and may be used to connect array lines in first and second memory arrays 5410 and 5420 to respective support circuitry and interconnects 5401. The support circuitry and interconnects 5401 and insulator 5403 form memory array support structure 5405-1.

Next, method 3220, which is similar to method 2740, is used to fabricate first memory array 5410 using a diode cathode-to-nanotube switch based on a non-volatile nanotube diode array similar to that illustrated in section 4785 of FIG. 47 and the corresponding fabrication methods.

Next, a second memory array 5420 is fabricated on the planar surface of first memory array 5410 similar to method 3230 of method 3040 of FIG. 30B, but using a diode anode-to-nanotube switch based on a non-volatile nanotube diode array similar to that illustrated in section 5185 of FIG. 51 and the corresponding fabrication method.

FIG. 54A shows cross-section 5400, which includes first memory array 5410 and second memory array 5420, both arrays sharing common word line 5430. Word lines, e.g., 5430, are defined (etched) during a trench etch that defines the memory array (cells) in forming array 5420. Cross section 5400 shows first memory array 5410 and second memory array 5420 in combination in the word line or X-direction with shared word line 5430(WL0), four bit lines BL0, BL1, BL2, and BL3, and corresponding cells C00, C01, C02, and C03. The period of the array in the X direction is 2F, where F is the minimum size of a technology node (generation).

FIG. 54B shows a cross-section 5400 'including a first memory array 5410' and a second memory array 5420 ', both arrays sharing common word lines 5430' and 5432. Word line 5430' is a cross section of word line 5430. Word lines, such as 5430 'and 5432, can be defined (etched) during a trench etch that defines the memory array (cells) when array 5420' is formed. Cross section 5400 'shows first and second memory arrays 5410', 5420 'of combinations in bit lines or in the Y-direction, with shared word lines 5430' (WL0) and 5432(WL1), two bit lines BL0 and BL2, and corresponding cells C00, C10, C02, and C12. The period of the array in the Y direction is 2F, where F is the minimum size of the technology node (generation).

Because of the 2F period in the X and Y directions, a memory array cell area of 1 bit is 4F for array 5410²,. Because of the 2F period in the X and Y directions, the memory array cell area of 1 bit is 4F for array 5420². Because memory arrays 5420 and 5410 are stacked, the memory array cell area per bit is 2F². If four memory arrays (not shown) are stacked, the memory array cell area per bit is 1F²。

In some embodiments, method 3240 completes fabrication of the semiconductor chip using industry standard fabrication techniques by adding additional wiring layers as needed, and passivating the chip and adding package interconnects.

In operation, memory section 5400 of FIG. 54A and corresponding memory section 5400 ' of FIG. 54B correspond to the operation of memory section 3305 shown in FIG. 33B and corresponding memory section 3305 ' shown in FIG. 33B '. Operation of the memory cross-section 5400 and corresponding memory cross-section 5400' is the same as described with respect to waveform 3375 shown in FIG. 33D.

Method of forming trench sidewall wiring using conformal conductor deposition as an alternative to trench fill

Fig. 48G shows trench opening 4857, which is then filled with conductor 4858, as shown in fig. 48H. Trench sidewall routing is then formed as further described in the fabrication method of fig. 48A-48 BB.

Conformal conductor deposition may be used in place of trench fill conductor to create trench sidewall routing, as shown in fig. 55A-55F. The exemplary manufacturing method shown in fig. 55A-55F is based on a variation of U.S. patent 5,096,849 (shown in fig. 41A-41B).

Some methods deposit conformal conductor layer 5510 in opening 4857 (fig. 48G), as shown in fig. 55A, and form trench opening 5515. Examples of conductor layer materials are elemental metals, such as Al, Au, W, Cu, Mo, Pd, Ni, Ru, Ti, Cr, Ag, In, Ir, Pb, Sn, and metal alloys, such as TiAu, TiCu, TiPd, PbIn, and TiW, other suitable conductors, or conductive nitrides, oxides, or silicides, such as RuN, RuO, TiN, TaN, CoSi_xAnd TiSi_x. A conductive material is formed into the sidewall wiring regions as described further below. Because the wiring distance is short, it is not necessary to consider the sheet resistance of the resulting trench sidewall wiring.

Next, the method fills the trench opening 5515 with a sacrificial material 5520, as shown in fig. 55B. The sacrificial material 5520 can be a conductor, a semiconductor, or an insulator. If an insulator is selected, the sacrificial material 5520 can be formed of any insulator material known in the CMOS industry or the packaging industry, such as, for example, SiO ₂、SiN、Al₂O₃BeO, polyimide, PSG (phosphosilicate glass), photoresist, PVDF (polyvinylidene fluoride), sputtered glass, epoxy glass, and other dielectric materials.

The method then etches (RIE) the sacrificial material 5520 to a depth DZ10 below the bottom of the upper contacts 4850 'and 4850 ", as shown in fig. 55C, leaving the sacrificial material 5520'.

Next, the method removes (etches) the exposed regions of the conformal trench sidewall conductors using known industry methods, as shown in fig. 55D, and leaves the sacrificial material 5520'.

Next, the method removes (etches) the remaining sacrificial material 5520' using known industry methods, as shown in fig. 55E.

Next, the remaining conformal conductor is RIE to form trench sidewall wirings 5535 and 5535'. The method then directionally etches the remaining semiconductor and metal layers to form trench sidewall wires 5535 and 5535 'corresponding to sidewall wires 4862 and 4862' in fig. 48L and to form trench 5550.

The fabrication methods using conformal conductor instead of conductive trench fill deposition and as described with reference to fig. 55A-55F may be applied to the fabrication methods described with reference to fig. 48A-48BB to form 3D memory cross-section 4885 shown in fig. 48Y and 3D memory cross-section 4885' shown in fig. 48 BB.

Fabrication methods using conformal conductor deposition and as described with reference to fig. 55A-55F can also be used to form the 3D memory cross-section 5185 shown in fig. 51 and the 3D memory cross-section 5185' shown in fig. 52.

Non-volatile nanotube block

Non-volatile nanotube switches (NV NT switches) are described in detail in U.S. patent application No.11/280,786, and switch examples and operation are summarized in this application, as shown in fig. 3-11B above. Fig. 3-6B show NV NT switches 300, 400, 500, and 600 oriented horizontally, while fig. 7B shows NV NT switch 750 oriented vertically. These switches are formed by nanotube elements having a thickness in the range of, for example, 0.5 to 10nm, which contact the metal terminals (in contact with the surface areas at the opposite ends of the patterned nanotube element).

Fig. 26A and 29A illustrate a nonvolatile nanotube diode-based memory array and circuit using NT over cathode and NT over anode type nonvolatile nanotube diodes, respectively, as further described above with reference to fig. 12 and 13. It is desirable to fabricate the highest density memory array possible at each technology node, F, where F is the minimum technology node lithographic dimension. If each timeA cell is FxF and is separated from neighboring cells by a dimension F, the cell-to-cell period is 2F and the minimum cell area for technology node F is 4F ². An active memory cell may be, for example, 2F if a single cell can store more than one bit, or if arrays can be stacked on top of each other²Or 1F²。

Fig. 28C shows a cross-section 2800 "where the NV NT diode cell includes a vertically oriented diode steering (select) device in contact with a horizontally oriented nanotube that is larger than the minimum feature size F in the X-direction because horizontally placed nanotube element contacts at opposite ends of nanotube element 2850 extend beyond the minimum feature F. Fig. 28A and 28B and 31A, 31B, and 31C show vertically aligned nanotubes with bottom and side/top contacts compatible with the minimum feature size F.

However, even with vertically oriented nanotubes, scaling to small dimensions in some embodiments, such as a technology node F of 22nm (or less), may be limited by the nanotube structure density of the nanotube element, which is the number of individual nanotubes available in the width direction of the element. Another way to express the density of the nanotube structure is to measure the size of the void region as shown in fig. 38. Fig. 39 illustrates a nanotube element with increased thickness to increase the number of available nanotubes for a device with a minimum feature width F, which may be, for example, 45nm, 35nm, or 22 nm. Fig. 40 illustrates a high density memory cell in which nanotube element 4050 has cross-section FxF. Nanotube thickness determines channel length L _SW-CHDefined by the spacing between upper contact 4065 and lower contact 4030 of nanotube switch 4005. The upper level contacts may also be referred to as top contacts and the lower level contacts may also be referred to as bottom contacts. The thicker nanotube element, such as nanotube element 4050, may be referred to as a non-volatile nanotube block. Fabrication of NV NT diode arrays using NV nanotube blocks, such as nanotube element 4050 with upper and lower level contacts as further shown above in fig. 40 and as further described below with reference to fig. 57, 67, and 68, results in relatively simple self-aligned three-dimensional NV memoryA reservoir array structure.

The non-volatile nanotube block ("NV NT block") may be considered a nanotube element comprising a 3-D volume nanotube structure. The term NV NT block is used to distinguish relatively thicker nanotube elements from relatively thinner nanotube elements (such as shown in fig. 3-7B). For example, the NV NT block has a thickness in a range, e.g., from about 10nm to 200nm (or more), e.g., from about 10 to 50 nm. Thus, the thickness of the block is typically substantially greater than the diameter of the individual nanotubes in the block, e.g., at least 10 times greater than the diameter of the individual nanotubes, forming a 3-D volumetric nanotube. In contrast, some other types of nanotube elements are relatively thin, e.g., having a thickness approximately equal to the nanotube diameter itself (e.g., about 1nm), forming a monolayer. In many instances, the relatively thin elements may be referred to as "2-D" in nature (although 3-D features may of course be observed with nanoscale instruments). Typically, relatively thin nanotube structures as well as relatively thick NV NT blocks (e.g., having a thickness in a wide range, such as from less than about 1nm to 200nm or more) include nanotube networks.

In many embodiments, the NV NT block is shaped, sized, and/or formed with a high enough density so that the terminals can contact the block on any surface(s), including the bottom, top, sides, and ends, or any combination of surfaces. The size and/or density of the structures forming the blocks substantially prevents the terminals from contacting each other and shorting through the structures. In other words, the size and/or density of the structures physically separate the terminals from each other. As discussed above with respect to fig. 38, one method of ensuring a sufficiently high density of structures forming NV NT blocks controls the distribution of hole sizes within the structures. As will be discussed in more detail below, the density of the structures of the NV NT block may be controlled by selecting appropriate deposition parameters. For example, nanotubes forming the structure can be deposited with high density using a spray coating technique or by coating multiple layers onto each other using spin coating. Alternatively, as described in more detail below, thinner layers may be formed by bonding a sacrificial material to the nanotube structures, for example, during or after deposition of the nanotube structures. This sacrificial material substantially prevents the terminals from contacting each other when the terminals are formed, i.e., physically separates the terminals. The sacrificial material may be substantially removed later, leaving the nanotube structure. The nanotube structures need not be as dense or thick as in other embodiments because the terminals have been formed with a given physical spacing between them.

In some embodiments, a number of nanotubes within a nanotube structure forming the NV NT block are substantially parallel to a surface on which they are disposed. In some embodiments, at least some of the nanotubes may also generally extend laterally in a given direction if the nanotubes are, for example, spun on a surface, although their orientation is not limited to that direction. If another layer of nanotubes is spun on top of this layer, the nanotubes may generally extend in the same direction as the previous layer or in a different direction. Additionally, while many of the nanotubes of the additional layer will also generally be parallel to the surface, some of the nanotubes may be bent down to fill holes in the previous layer of nanotubes. In other embodiments, if the nanotubes are, for example, sprayed onto a surface, the nanotubes will be generally parallel to the surface on which they are disposed, although they may have generally random orientations relative to one another in the lateral direction. In other embodiments, the nanotubes may extend randomly in all directions.

In many embodiments, the NV NT block has a thickness or height on the order of one or more lateral dimensions thereof. For example, as described in more detail below, one or more dimensions of the NV NT block may be defined by lithography, while one dimension is defined by the as-deposited thickness of the nanotube structures forming the NV NT block. The lithographically defined dimensions shrink with technology node (F) enabling the fabrication of devices having a minimum lateral dimension of about F, for example, about 65nm (for F ═ 65nm), about 45nm (for F ═ 45nm), about 32nm (for F ═ 32nm), about 22nm (for F ═ 22nm), or below. For example, for F ═ 22nm, the NV NT block may have a size of about 22nmx22nmx35nm, assuming that the nanotube structure forming the NV NT block is about 35nm thick. Other dimensions and thicknesses are possible. Depending on the arrangement of the terminals and the formation of NV N The thickness of the nanotube structure and the deposition state characteristics of the T-block, the distance between the terminals (i.e., the switch channel length) can be defined by the lithographically defined dimensions of the NV NT block. Alternatively, the distance between the terminals may be defined by the thickness of the structure forming the NV NT block, which in some cases may be sub-lithographic. Alternatively, the switch channel length may be defined by providing an arrangement of terminals that is not directly related to the size of the NV NT block itself, but by patterning the terminals to have features that are separated from each other by a certain distance. Generally, the NV NT block enables the switching element to be fabricated with at least a drop to 1F as described in more detail below²The area of (a).

Note that the "NV NT block" need not be square, e.g., all of approximately equal sized volumes, or even have parallel sides, although some embodiments will have these features. For example, in particular embodiments, the shape of the mask layer defined at the smallest dimension may have rounded corners, such that the depicted square shape may be substantially circular in the as-fabricated state, or may be generally square but have rounded corner features. The substantially circular mask layer results in a substantially cylindrical non-volatile nanotube element, also referred to herein as a NV NT block. Thus, if the mask layer used to define the trench boundaries is FxF square, nanotube element 4050, as illustrated by section 4000 of FIG. 40, may have a as-fabricated square cross-section FxF, as further illustrated in FIG. 57A below. Alternatively, nanotube element 4050 of cross-section 4000 can have a cross-section that is substantially F in diameter, substantially circular in the as-manufactured state, and is part of a cylindrical NV NT block element, as further shown in FIG. 57A' below.

The size of the single NT-to-NT overlap region was estimated to be between 0.5x0.5nm to 10x10nm, which is below the available SEM resolution limit. Fig. 3 shows NV NT switch 300, which corresponds to NV NT switch 600/600' shown in fig. 6A and 6B. Referring to fig. 6A, NV NT switch 600 is in the ON state, causing a voltage applied to terminal 620 to be transmitted to terminal 610 through patterned nanotube element 630 with NV NT mesh in an electrically continuous ON state (as shown in SEM voltage contrast). FIG. 6B shows NV NT switch 600' corresponding to NV NT switch 600 but in the OFF state. In the OFF state, patterned nanotube element 630 forms an NV NT network in an electrically discontinuous state and does not electrically connect terminals 610 and 620. The SEM voltage contrast plot of NV NT switch 600 'of fig. 6B shows a patterned nanotube element 630, wherein patterned nanotube element region 630' is electrically connected to terminal 620 (the light region), and patterned nanotube element region 630 "is electrically connected to terminal 610 '(the dark region), but wherein patterned nanotube element regions 630' and 630" are not electrically connected to each other. Because of the electrical discontinuity of the NV NT network between patterned nanotube element regions 630 ' and 630 ", the voltage applied to terminal 620 does not reach terminal 610 ', so terminal 610 ' is dark. Note that terminal 610 'is identical to terminal 610 except that it is not electrically connected to terminal 620 of NV NT switch 600'. While electrical discontinuities of NV NT mesh are observable from the bright portions of region 630 'and the dark portions of region 630', individual nanoscale NV NT switches forming the NV NT mesh are not observable due to SEM resolution limitations.

In operation, the switch 300 switches between ON and OFF states as further illustrated above in FIGS. 9A-9B and with the test voltages and timing illustrated in FIGS. 11A-11B. In the ON state, the resistance measured during the read operation is near-ohmic. NV NT elements fabricated in various thicknesses and terminal (contact) configurations as described above with reference to fig. 49 and 50 and as further described below with reference to fig. 56A-65, produce electrical switching characteristics similar to those shown in fig. 9A-9B when test conditions similar to those of fig. 11A-11B are applied. Nanotube element switches are apparently relatively less sensitive to variations in geometry, with the possible exception of shorter switch channel lengths L_SW-CHUpper is operated at a lower voltage as shown in fig. 10.

56A-56F and 57A-57C further illustrate various relatively thin NV nanotube elements and relatively thick NV nanotube elements (NV NT blocks) in three-dimensional perspective, and with various terminal contact location configurations.

58A-65 illustrate non-volatile switches fabricated using various non-volatile nanotube elements, and corresponding measured electrical switching characteristics. These non-volatile nanotube element and terminal contact configurations correspond to FIGS. 56A-56F and 57A-57C.

Fig. 66A-66C illustrate various methods of fabricating various non-volatile nanotube blocks, such as those shown in fig. 40, 47, 49, 56A-56F, 57A-57C, and 58A-65.

FIGS. 67 and 68A-68I illustrate a structure and method of fabricating a memory cell, as described above with respect to section 4000 in FIG. 40. FIGS. 67 and 68A-68I are described with respect to NT upper cathode NV NT diode configurations. FIGS. 69 and 70 show the structure of a memory cell based on an anode-to-NT NV NT diode configuration.

FIGS. 71 and 72A-72B show a 2-high stack array of 3-D NV NT diode based cells, including shared array lines (e.g., shared word lines). FIGS. 73 and 74 show a 2-high stack array of 3-D NV NT diode based cells that do not share array lines (e.g., share word lines).

FIGS. 75 and 76A-76D illustrate a 3-D NV NT diode based structure and corresponding simplified fabrication method. The simplified manufacturing method enables multi-layer arrays of 4, 8, 16 and greater numbers of layers, as shown in the perspective view shown in fig. 77.

Fabricating NVNT switches with non-volatile nanotube blocks, different terminal locations, and switching characteristics thereof

NV NT switch 5600A, shown in perspective 3-D view in FIG. 56A, shows an NV NT switch with a relatively thin (e.g., about 0.5 to less than 10nm) nonvolatile nanotube element 5602A and top contact locations 5605A and 5607A. Contact locations show where a terminal (not shown) contacts the surface of nanotube element 5602A. NV NT switch 5600A corresponds to NV NT switch 300 shown in FIG. 3, where nanotube element 5602A corresponds to nanotube element 330, contact position 5605A corresponds to the position of terminal 310, and contact position 5607A corresponds to the position of terminal 320.

NV NT switch 5600B, shown in perspective 3-D view in FIG. 56B, shows a NV NT switch with thin nonvolatile nanotube element 5602B and bottom contact positions 5605B and 5607B. Contact locations show where a terminal (not shown) contacts a surface of nanotube element 5602B. NV NT switch 5600B corresponds to NV NT switch 500 shown in FIG. 5, where nanotube element 5602B corresponds to nanotube element 530, contact position 5605B corresponds to the position of terminal 510, and contact position 5607B corresponds to the position of terminal 520.

NV NT switch 5600C, shown in perspective 3-D in FIG. 56C, shows a NV NT switch having a thin non-volatile nanotube element 5602C and top and bottom contact positions 5605C and 5607C. Contact locations show where a terminal (not shown) contacts a surface of nanotube element 5602B. NVNT switch 5600C combines top and bottom contacts to the same nanotube element.

NV NT switch 5600D, shown in perspective view 3-D in FIG. 56D, shows a NV NT switch having a NV NT block (thick NV NT element) 5610 and contact positions 5612 and 5614. The NV NT switch 5600D corresponds to NV NT switches 5800/5800'/5870 having the structure and electrical switching results as further described below with reference to fig. 58A-58D and 59, respectively. In the illustrated embodiment, the corresponding switch 5800 is scaled down to the technology node for lithographically defining lateral dimensions. For example, a technology node F-22 nm for this embodiment may provide a switching channel length of about 22nm, and a width of about 22 nm. As discussed above, in many embodiments it is desirable to make the switch channel length as small as possible, for example, as small as the technology node allows, although in other embodiments a larger channel length may be desirable. The thickness of the NV NT block defines the height of the switch 5600D, which in a particular embodiment is about 10nm, although other thicknesses are possible as discussed elsewhere. Contact position 5612 in fig. 56D includes side contact positions 5612-1 and 5612-2, top contact position 5612-3, and terminal contact positions (not visible) and corresponds to contacts 5830-1 and 5830-2 in fig. 58A-58D. Contact position 5614 includes a side contact position 5614-1, a second side contact position (not visible), a top contact position 5614-2, and a terminal contact 5614-3, and corresponds to contacts 5840-1 and 5840-2.

NV NT switch 5600E, shown in perspective view 3-D of fig. 56E, shows a NV NT switch having NV NT section 5620 and terminal-contact positions 5622 and 5625. NV NT block 5620 corresponds to nanotube element 4910, terminal-contact position 5622 corresponds to terminal-zone contact 4965, and terminal-contact position 5625 corresponds to terminal-zone contact 4960, as further described above with respect to NV NT switch 4900 shown in fig. 49. The switching operation is shown in fig. 50. As also described further below with respect to NV NT switches 6000/6000'/6050 shown in fig. 60A-60C, NV NT block 5620 corresponds to nanotube element 6010, terminal-contact position 5622 corresponds to terminal-region contact 6040, and terminal-contact position 5625 corresponds to terminal-region contact 6030. The electrical switching characteristics are described with reference to fig. 61.

NV NT switch 5600F, shown in perspective view 3-D in fig. 56F, shows an NV NT switch having NV NT block 5630, bottom contact position 5638, and combined terminal-contact position 5634 (including combined terminal-contact position 5634-1 and top contact position 5634-2). NV NT switch 5600F corresponds to NV NT switch 6200/6200' as further described below with reference to FIGS. 62A-62B. NV NT block 5630 corresponds to NV NT block 6210, bottom contact position 5632 corresponds to bottom contact 6230, and combined termination contact position 5631-1 and top contact position 5634-2 correspond to combined termination contacts 6240-1 and 6240-2, respectively. The electrical switching characteristics are described with reference to fig. 63A-63B.

NV NT switch 5700A, shown in perspective view in FIG. 57A from 3-D, shows a NV NT switch having NV NT block 5710 and bottom contact location 5715 and top contact location 5720. NV NT switch 5700A corresponds to NV NT switches 6400/6400'/6450, the structure and electrical switching results of which are further described below with reference to fig. 64A-64C and 65, respectively. NV NT block 5710 corresponds to NV NT block 6410, bottom contact location 5715 corresponds to bottom contact 6427, and top contact location 5720 corresponds to top contact 6437 shown in fig. 64B. The switching results for switch 6400 show that although the NV NT block is a given thickness, e.g., 35nm, there is no short circuit at the top contact-to-bottom contact.

NV NT switch 5700A also corresponds to nanotube element 4050 shown in FIG. 40 if FxF mask layer is used at the time of manufacture. NV NT switch 5700A ', shown in perspective view 3-D in fig. 57A', is formed with a generally circular mask layer of diameter F, which is caused by the rounding of the drawing in the mask layer, as further described above. NV NT block 5710 ' is generally cylindrical in shape having a circular cross-section with a diameter of about F and bottom contact location 5715 ' and top contact location 5720 '. The corresponding diode region in cross-section 4000 is formed concurrently with nanotube element 4050 and may have a square cross-section FxF or a circular cross-section with a diameter of about F. In other words, the 3-D NVNT diode forming the storage cell in cross-section 4000 forms a stack of NVNT block switches on top of the steering (select) diode, the cross-sectional shape of the stack being either substantially square or substantially circular.

A sufficiently small size and number of hole regions, as further described above with respect to the nanotube layer 3800 shown in fig. 38, can be used to fabricate NV NT block 6410, as further shown in fig. 64A-64C, below, without shorting between bottom contact 5425 and top contact 6435 separated by a given distance, e.g., about 35 nm. NV NT block 6410 corresponds to NV NT block 5710 shown in the 3-D perspective view of FIG. 57A.

FIG. 57B shows a 3-D perspective view showing NV NT switch 5700B, where the spacing between bottom contact position 5735 and top contact position 5740 is smaller in block 5730 as compared to the corresponding spacing between the corresponding contact positions shown in FIG. 57A. The block volume is also shaded, showing that it is fabricated differently than block 5710. The manufacturing differences are further described below with reference to fig. 66A-66C. However, a short summary of the significant differences will be provided. NV NT block described with reference to fig. 56A-56F, 57A and 57A', and corresponding figures further illustrated above, can be fabricated using carbon nanotubes deposited from standard dispersions of CMOS compatible, non-trace metals in aqueous or non-aqueous solvents, as described in more detail in the incorporated patent references. Such nanotube element layers may be deposited using spin-coating techniques or spray-coating techniques. Block 5730 shown in fig. 57B can be made with a sacrificial polymer (e.g., polypropylene carbonate) dissolved in an organic solvent such as NMP or cyclohexanone, as further described below with reference to fig. 66A-66C. The top terminals are formed to contact the top contact areas 5740. The presence of the sacrificial polymer in the NV NT block 5730 structure enables the top and bottom contacts to be made relatively close, such as less than about 35nm, such as about 22nm or less, such as about 10nm (e.g., about 10-22 nm). After patterning and insulation, or before insulation, a sacrificial polymer (e.g., polypropylene carbonate) is evaporated through an insulating layer at an evaporation temperature range, e.g., 200 to 400 ℃, leaving substantially no residue. NV NT switch 5700B ' shown in fig. 57B ' shows block 5730 ' after sacrificial polymer material removal (e.g., after evaporation), and having bottom contact regions 5735 ' and top contact regions 5740 '. NVNT block 5730B' is similar to NV NT block 5700A except that the top and bottom contact areas can be more closely located.

FIG. 57C shows a 3-D perspective view showing NV NT switch 5700C, where NV NT block 5750 includes a shaded area, showing NV NT block 5750 including additional material between individual nanotubes, as further described below with reference to FIGS. 66A-66C. Bottom contact area 5755 is formed prior to NV NT block 5750 deposition, and top contact area 5760 is formed after NV NT block 5750 deposition. This additional material may improve the performance characteristics of NV NT block 5750. Such additional material, which may be a polymer, such as polypropylene carbonate, is not evaporated and may remain as part of the NV NT block 5750 structure. Alternatively, the polypropylene carbonate may be evaporated, as shown in fig. 57B ', and NV NT block 5730' is then filled with a porous dielectric material prior to top contact formation to improve the switching characteristics of NV NT switch 5700C.

Fabricating NVNT switches with non-volatile nanotube area block sizes reduced to technology nodes

FIG. 58A shows a top view of NV NT switch 5800, while FIG. 58B shows a section 5800 'corresponding to section Z1-Z1' shown in FIG. 58A. In a particular embodiment, the non-volatile nanotube block 5810 on the substrate 5820 has an overall dimension of about 800nm, a width of about 24nm, and a thickness of about 10 nm. As discussed above, the cross-sectional dimension is typically determined by the technology node, whereas the thickness dimension perpendicular to the cross-section may not correspond to the technology node. Terminal 5825 contacts NV NT block 5810 at terminal-contact (terminal-area contact) 5830-1 and top contact 5830-2. Side contacts (not shown) are also used as shown in the corresponding 3-D view of fig. 56D. Terminal 5835 contacts NV NT block 5810 at terminal-contact 5840-1 and top contact 5840-2. Side contacts (not shown) are also used as shown in the corresponding 3-D view of fig. 56D. NV NT switch 5800/5800' channel length L _SW-CHDetermined by the spacing of terminals 5825 and 5835, which is, for example, about 22 nm. Switch channel width W_SW-CHFor example about 24nm, and is determined by etching. Film thickness H_SW-CHFor example about 10nm at the time of deposition. The electrical performance of block 5810 is determined in part by the NV NT network, which in some embodiments is included at about 22nm (L)_SW-CH)x24nm(W_SW-CH)x10nm(H_SW-CH) And corresponds to NV NT switches formed with NV NT blocks reduced in size to technology node F22 nm. In this example, terminals 5825 and 5835 are formed using Ti/Pd, however, the terminals can be formed using various contact and interconnect element metals, such as Ru, Ti, Cr, Al (Cu), Au, Pd, Pt, Ni, Ta, W, Cu, Mo, Ag, In, Ir, Pb, Sn, and metal alloys, such as TiAu, TiCu, TiPd, Pbin, and TiW, other suitable conductors, or conductive nitrides, oxides, or silicides, such as RuN, RuO, TiN, TaN, CoSi_xAnd TiSi_x. The substrate 5820 may be an insulator (e.g., ceramic or glass), a semiconductor having an insulating surface, a metal having an insulating surface, or an organic rigid or flexible substrate.

Fig. 58C shows an SEM image of an exemplary non-volatile nanotube switch 5850 prior to passivation, and corresponds to non-volatile nanotube switch 5800/5800' shown in fig. 58A and 58B. Non-volatile Exemplary nanotube switch 5850 includes NV NT block 5855 corresponding to NV NT block 5810, terminal 5860 corresponding to terminal 5825, terminal 5865 corresponding to terminal 5835, and substrate 5868 corresponding to substrate 5820. Nonvolatile nanotube switch 5850 is fabricated with a terminal-to-terminal channel length L_SW-CH21.9nm, a channel width W_SW-CH24.4nm as shown in fig. 58C, and a thickness of about 10nm (not shown in fig. 58C). Fig. 58D shows an SEM image of the nanotube layer 5875 used to form NV NT block 5855. The nanotube layer 5875 was deposited using a spin-on deposition of nanotubes 18 in an aqueous solvent and had a four point probe (four point probe) resistance measurement of 150 ohms. SEM of nanotube layer 5875 cannot resolve individual nanotubes, which are typically in the range of about 0.5nm to about 10nm in diameter depending on the nanotube type, e.g., SWNT, DWNT, and MWNT, or combinations thereof. The nanotubes in the SEM image are clearly much larger than their actual diameter. The nanotube layer 5875 is formed using semiconductor and metal-type nanotubes.

The results of experimental testing of the non-volatile nanotube switch 5850 are shown by curve 5900 of fig. 59. The switching results for 100 cycles of the ON/OFF cycle of the non-volatile nanotube switch 5850 show that most of the ON resistance value 5910 is in the range of 50 kilo-ohms to 75 kilo-ohms, while the OFF resistance value 5920 is greater than 500 megaohms. The experimental tests are similar to those described further above with reference to fig. 11A-11B.

NVNT switch for fabricating non-volatile nanotube block with terminal contacts

Fig. 60A shows a top view of NV NT switch 6000, while fig. 60B shows a section 6000 'corresponding to section Z2-Z2' shown in fig. 60A, which includes NV NT block 6010 with only terminal contacts. The non-volatile nanotube block 6010 on the substrate 6020 also includes a protective insulator 6015. In an exemplary embodiment, the protective insulator 6015 is SiO with a thickness of 100nm and a size of 250nmx250nm₂Oxide, although other sizes and insulating materials may generally be used. The protective insulator 6015 may be used as a mask layer to pattern the NV NT block 6010 to a desired size, which in the illustrated embodiment is, for example, 250x250nm, the lateral dimension. NV NT 6010 has a given thickness, for example about 50 nm. Terminal 6025 contacts NV NT block 6010 at terminal-contact (terminal-area contact) 6030. Terminal 6035 contacts NV NT block 6010 at terminal-contact 6040. In the embodiment shown in FIGS. 60A and 60B, NV NT switch channel length L_SW-CHAnd W_SW-CHThe lateral dimensions directly associated with the NV NT block 6010, for example using the exemplary block dimensions provided above, are all about 250 nm. The terminals 6025 and 6035 overlap the protective insulator 6015 in the as-manufactured state, however the overlapping regions have substantially no effect on electrical operation. NV NT switch 5600E is a 3-D representation of FIG. 56E corresponding to NV NT switch 6000/6000' of FIGS. 60A and 60B, with NV NT switch 5620 corresponding to NV NT block 6010. The electrical properties of block 6010 are determined by the NV NT network contained in the volume of the block, for example, about 250nm (L) using the exemplary dimensions provided above _SW-CH)x250nm(W_SW-CH)x50nm(H_SW-CH). In this example, terminals 6025 and 6035 are formed using Ti/Pd, however, the terminals can be formed using various contact and interconnect element metals, such as Ru, Ti, Cr, Al (Cu), Au, Pd, Pt, Ni, Ta, W, Cu, Mo, Ag, In, Ir, Pb, Sn, and metal alloys, such as TiAu, TiCu, TiPd, Pbin, and TiW, other suitable conductors, or conductive nitrides, oxides, or silicides, such as RuN, RuO, TiN, TaN, CoSi_xAnd TiSi_x. The substrate 6020 may be an insulator (e.g., ceramic or glass), a semiconductor having an insulating surface, a metal having an insulating surface, or an organic rigid or flexible substrate.

Fig. 60C shows an SEM image of non-volatile nanotube switch 6050 before passivation, and corresponds to non-volatile nanotube switch 6000/6000' shown in fig. 60A and 60B. The non-volatile nanotube switch 6050 includes an NV NT block 6010 (not visible in this top view), the exposed portion of the protective insulator 6055 corresponds to the protective insulator 6015, the terminal 6065 and the overhang (overlap) region 6060 correspond to the terminal 6025, the terminal 6075, the overhang region 6070 corresponds to the terminal 6035, and the substrate 6080 corresponds to the substrate 6020. Non-volatile nanotube switch 6050 is fabricated with its terminals -to-terminal channel length L_SW-CHAbout 250nm, a channel width W_SW-CHAbout 250nm and a thickness of about 50nm (not shown in fig. 60C).

NV NT switch 6000/6000' corresponds to NV NT switch 4900 as further described above with reference to fig. 49, but provides more detail of the NV NT switch structure, including SEM pictures. NV NT block 6010 corresponds to nanotube element 4910, protective insulator 6015 corresponds to protective insulator 4935, and terminals 6025 and 6035 correspond to terminals 4940 and 4950, respectively, except that terminals 6025 and 6035 also include regions where protective insulator 6015 is overlapped. Terminal contacts (terminal-area contacts) 6030 and 6040 correspond to terminal-area contacts 4960 and 4965, respectively, while substrate 6020 corresponds to the combination of insulator 4920 and substrate 4930.

The experimental ON/OFF switch test results for nanotube switch 6050 with only terminal-to-field contacts correspond to the electrical characteristics of NV NT switch 4900, as further described above with respect to curve 5000 shown in fig. 50. The switching results for 100 ON/OFF cycles of non-volatile nanotube switch 4900 show that most ON resistance values are in the range of 10 kilo-ohms to 100 kilo-ohms, some ON resistance values are 800 kilo-ohms, as shown by resistance 5010, and OFF resistance values are in the range of 500 mega-ohms to 100 giga-ohms, as shown by resistance 5020. In a few examples 5030, the ON resistance value is greater than 100 megaohms. The I-V characteristic of NV NT switch 6050 in the ON state is shown by curve 6100 in FIG. 61, showing a near-ohmic ON resistance characteristic.

NVNT switch for fabricating non-volatile nanotube block with bottom and terminal/top contacts

FIG. 62A shows a top view of NV NT switch 6200, while FIG. 62B shows a cross-section 6200 'corresponding to cross-sections Z3-Z3' shown in FIG. 62A. In one embodiment, the dimensions of non-volatile nanotube patch 6210 on substrate 6220 are about 100x80nm in cross-section and 50nm high, although other dimensions are possible. Bottom terminals 6225 form bottom contacts 6230 and terminals 6235 form combined terminal contacts 6240-1 and top contacts 6240-2. Bottom contact 6230 and top contact 62402 overlap by about 150 nm. NV NT switch 6200 channel length L_SW-CHIs not well defined in this configuration because terminals 6225 and 6235 are placed in contact with NVNT block 6210. Switch 6200 is shown in respective 3-D perspective views shown in fig. 56F, where NV NT block 5630 corresponds to NV NT block 6210, bottom contact position 5632 corresponds to bottom contact 6225, terminal contact position 5631-1 corresponds to terminal contact 6240-1, and top contact position 5634-2 corresponds to top contact 6240-2. In this example, terminals 6225 and 6235 are formed using Ti/Pd, however, the terminals can be formed using various contact and interconnect element metals, such as Ru, Ti, Cr, Al (Cu), Au, Pd, Pt, Ni, Ta, W, Cu, Mo, Ag, In, Ir, Pb, Sn, and metal alloys, such as TiAu, TiCu, TiPd, Pbin, and TiW, other suitable conductors, or conductive nitrides, oxides, or silicides, such as RuN, RuO, TiN, TaN, CoSi _xAnd TiSi_x. The substrate 6220 may be an insulator (e.g., ceramic or glass), a semiconductor having an insulating surface, a metal having an insulating surface, or an organic rigid or flexible substrate.

The results of the experimental ON/OFF switch testing of nanotube switch 6200/6200' are described with respect to curve 6300 shown in FIG. 63A and curve 6350 shown in FIG. 63B. The test conditions are similar to those described further above with reference to FIGS. 11A-11B; write 0 corresponds to erase, and write 1 corresponds to program. Curve 6300 tests applied one write 0 voltage pulse of 6 volts, one write 1 voltage pulse of 6V, and measured the ON resistance for 100 cycles per ON/OFF cycle. The ON resistance value 6310 is in the range of 120 kilo-ohms to 1 megaohm and the OFF resistance value 6320 exceeds 100 megaohms. In both instances, the ON resistance value 6330 exceeds 1G ohms, indicating a failure to switch to the ON state. Curve 6350 tests an application of one write 0 voltage pulse of 6 volts and five write 1 voltage pulses of 6V and measures the ON resistance for 100 cycles per ON/OFF cycle. The ON resistance 6360 is in the range of 130 kilo-ohms to 1 megaohm and the OFF resistance 6370 exceeds 800 megaohms. In one example, the ON resistance value 6380 exceeds 1G ohms, indicating a switch to ON state failure.

Fabricating non-volatile nano-scale with top and bottom contactsNVNT switch for a bank of transistors

FIG. 64A shows a top view of NV NT switch 6400, while FIG. 64B shows a cross-section 6400 'of NV NT block 6410 having top and bottom contacts (corresponding to cross-sections Z4-Z4' shown in FIG. 64A). Non-volatile nanotube block 6410 is formed on the surface of insulator 6415 on substrate 6420 and overlaps bottom terminal 6425 embedded in insulator 6415 to form bottom contact 6427. The bottom terminal 6425 is formed of Ti/Pd with a thickness of 25 nm. The horizontal dimensions of terminals 6425 are not critical. NV NT block 6410 can be etched from large nanotube structure 6410'. In one embodiment, insulator 6430 is about 50nm thick and width W_INSUL(W_Insulator) SiO of about 200nm₂Oxide, and overlapping a portion of the nanotube structure 6410'. Other embodiments may have other suitable insulators having other suitable dimensions. Width W_{TOP CONTACT}(W_{Top contact}) Top terminal 6435, e.g., 100nm, overlaps a portion of insulator 6430 and extends beyond insulator 6430 to overlap a portion of nanotube structure 6410' beyond the edge of insulator 6430 to form top contact region 6440 having dimensions C1 and C2 and to form top contact 6437. Exposed regions 6445 of nanotube structure 6410 'outside the boundary defined by top terminal 6435, insulator 6430, and nanotube structure 6410' are etched using nanotube etching techniques (described in the incorporated references) to form NV NT block 6410. The ON/OFF switching of NV NT block 6410 occurs mostly in the area defined by dimensions C1 and C2 in the top contact area that forms top contact 6437 ON bottom contact 6427. Top contact 6437 and bottom contact 6427 are separated by a thickness of NV NT block 6410, which in one example is about 35nm, although other thicknesses are possible. In one embodiment, C1 is substantially in the range 40 to 80nm and C2 is about 100 nm. A portion of NV NT mesh that switches between ON and OFF states is mostly between top and bottom contacts 6437 and 6427, respectively, of approximate size, for example using the volume of NV NT block 6410 of the example size provided above of about 100x40x35nm (some sizes not visible in fig. 64A-64C). Channel length L _SW-CHIs the distance between the top and bottom contacts, which in one embodiment is about 35 nm. NVNT switch 5700A shown in FIG. 57A is a 3-D representation corresponding to NV NT switch 6400/6400' in FIGS. 64A and 64B, with NV NT block 5710 corresponding to NV NT block 6410. Bottom contact location 5715 corresponds to bottom contact 6427 and top contact location 6720 corresponds to top contact 6437. The electrical performance of block 6410 is determined by NV NT mesh, which is largely contained within a volume of about 100nmx40nmx35nm, as further described above using example dimensions. In this example, terminals 6425 and 6435 are formed using Ti/Pd, however, the terminals can be formed using various contact and interconnect element metals, such as Ru, Ti, Cr, Al (Cu), Au, Pd, Pt, Ni, Ta, W, Cu, Mo, Ag, In, Ir, Pb, Sn, and metal alloys, such as TiAu, TiCu, TiPd, Pbin, and TiW, other suitable conductors, or conductive nitrides, oxides, or silicides, such as RuN, RuO, TiN, TaN, CoSi_xAnd TiSi_x. Insulator 64156430 may be SiO₂、AL₂O₃SiN, polyimide, and other compatible insulator materials. The substrate 6420 may be an insulator (e.g., ceramic or glass), a semiconductor having an insulating surface, a metal having an insulating surface, or an organic rigid or flexible substrate.

Fig. 64C shows an SEM image of the non-volatile nanotube switch 6450 just before final etching and passivation, which corresponds to the non-volatile nanotube switch 6400/6400' shown in fig. 64A and 64B. The final etch defines the dimensions of the block 6410. Non-volatile nanotube switch 6450 shows: the exposed portion of insulator 6455 just prior to NVNT block 6410 formation corresponds to insulator 6415, nanotube structure 6460 corresponds to nanotube structure 6410', insulator 6465 corresponds to insulator 6430, top terminal 6470 corresponds to top terminal 6435, and top contact region 6475 corresponds to top contact region 6440 before final etching. Non-volatile nanotube switch 6450 is fabricated with its channel length L_SW-CHAbout 35nm, corresponding to the thickness of the NV NT block between the top and bottom contacts.

A plot 6500 of the switching results for 100 ON/OFF cycle periods of non-volatile nanotube switch 6450 is shown in fig. 65. The ON resistance value 6510 indicates that most of the ON resistance value is in the range of 100 kilo-ohms to 1 megaohms, while the OFF resistance value 6520 is about 1 giga-ohms or higher. The test conditions are similar to those described further above with reference to fig. 11; writing 0 corresponds to erasing and writing 1 corresponds to programming. Plot 6500 shown in FIG. 65 uses one 7 volt write 0 pulse, five 6 volt write 1 pulses, and switches the NV NT switch between the ON and OFF states for 100 cycles. No short circuit was observed between the overlapping top and bottom contacts.

NV NT switches, which use NV NT blocks as switching elements, show ON/OFF switching of fabricated devices covering a wide range of horizontal dimensions, e.g., from 22nm to 300nm, and contact schemes including various combinations of bottom, top, terminal, and side contacts. The NV NT block can be used in a variety of integration schemes to form a variety of three-dimensional nonvolatile nanotube diode-based memory arrays. For example, cross-section 4000 shown in FIG. 40 shows a NV NT block, referred to as nanotube element 4050, having a top contact, referred to as upper contact 4065, and a bottom contact, referred to as lower contact 4030, forming nonvolatile nanotube switch 4005. Section 4785 of FIG. 47 shows NV NT block having terminal contacts referred to as nanotube element 4740-1, which has terminal contacts 4779 and 4764, and nanotube element 4740-2 has terminal contacts 4779 'and 4764'.

The flexibility of the NV NT block enables integration into a variety of structures and product applications. For example, NV NT switches formed using NV NT blocks can be used as scalable non-volatile nanotube switches in structures and circuits, such as those described in U.S. patent provisional application No.60/836,343. In addition, NV NT switches formed using NV NT blocks can be used in memory arrays such as those described in U.S. patent application nos. 11/280,786 and 11/274,967. In addition, NV NT switches formed using NV NT blocks may be used for non-volatile shadow latches to form register files used in logic circuits, such as the register file described in U.S. patent application No.11/280,599. These scalable NV NT switches formed using NV NT blocks can be used to replace stacked capacitors in DRAM cells to create less complex scalable non-volatile storage structures.

Method for fabricating NVNT switch using non-volatile nanotube block

Some embodiments of methods of depositing and patterning Carbon Nanotubes (CNTs) of one or more CNT layers from CNTs dispersed in an aqueous or non-aqueous solution may be used to fabricate non-volatile nanotube blocks, as described in the incorporated patent references. Examples of such NV NT blocks are shown in the 3-D diagrams of fig. 56D, 56E, 56F, 57A, and 57A'. This method can be used to fabricate a non-volatile nanotube switch using NV NT blocks, as further described above with reference to fig. 58A-65. This method can also be used to fabricate 3-D memory cells using NV NT blocks, such as section 4000 shown in FIG. 40, where nanotube element 4050 is an NV NT block having top and bottom contacts, and section 4785 shown in FIG. 47, where nanotube elements 4740-1 and 4740-2 have NVNT blocks with terminal contacts.

Some embodiments of NV NT block fabrication methods can be extended to include depositing a CNT layer (or layers) from CNTs dispersed in a sacrificial polymer dissolved in an organic solvent, as described with respect to fabrication method 6600A shown in fig. 66A. Such an approach may be used in some embodiments to improve electrical performance, such as cyclability (number of ON/OFF cycles) and/or enable NV NT block manufacturing, e.g., having better tightly arranged top and bottom contact locations, as illustrated by comparing NV NT block 5730 (shown in 3-D view of FIG. 57B) with NV NT block 5710 (shown in 3-D view of FIG. 57A). Shorter NV NT switch channel length L _SW-CH(corresponding to the top-to-bottom contact spacing) may lower the NV NT switch operating voltage, as further described above with reference to fig. 10. The sacrificial polymer may remain in the NV NT structure 5730 (shown in the 3-D diagram of FIG. 57B), or may be removed from the NV NT block by evaporation, such as NV NT block 5, typically at a temperature range of 200 ℃ to 400 ℃730 '(shown in the 3-D view of figure 57B').

Some embodiments of NV NT block fabrication methods may also be extended to include the addition of performance enhancing materials, such as porous dielectrics, as described with respect to fabrication method 6600B in fig. 66B and fabrication method 6600C in fig. 66C. Block 5750 (shown in the 3-D view of FIG. 57C) shows the NV NT block incorporating a performance enhancing material, such as a porous dielectric.

Method for fabricating non-volatile nanotube block using sacrificial polymer

Fig. 66A illustrates some methods of manufacturing 6600A of an elevated NV NT block. Generally, method 6605 separately manufactures support circuitry and interconnects in and out of a semiconductor substrate, for example, using method 2710 as described further above with reference to fig. 27A-27B. Exemplary method 6605 deposits and patterns semiconductor, metal, and insulating layers and forms structures before the CNT layer is deposited.

Next, method 6608 deposits a CNT layer (or layers) from a CNT dispersion in a sacrificial polymer dissolved in an organic solvent. For example, the sacrificial Polymer Polypropylene Carbonate (PPC) is dissolved in one or more organic solvents, such as NMP or cyclohexanone, which are available in the industry. A description of the properties of polypropylene carbonate can be found in reference technical data, for example, from the company enbauer Materials (Inc). Although the sacrificial polymer PPC is used in this example, other sacrificial polymers may also be used, such as union (Unity) sacrificial polymers and polyethylene carbonate sacrificial polymers. At this point in the process, the CNT layer may be patterned, continuing with fabrication flow 1A shown in fig. 66A. Alternatively, additional layers may be added prior to patterning the multiple layers (including the CNT layer), continuing with fabrication flow 2A shown in fig. 66A. An exemplary method will first be described with respect to CNT layer patterning (fabrication flow 1A), and then a method of patterning a plurality of layers including a CNT layer (fabrication flow 2A).

Continuing with the description of manufacturing method 6600A using manufacturing flow 1A, then, method 6610 uses the nano-scale described in the incorporated patent referenceThe tube etching technique then patterns (etches) the CNT layer. In certain embodiments, the method includes substantially removing (e.g., etching) the sacrificial polymer, such as polypropylene carbonate (PPC), in the exposed regions. Such removal may be performed, for example, using anisotropic physical etching, such as Ar ion cut etching; or Reactive Ion Etching (RIE) including O ₂Plasma; or a combination of both.

Next, method 6612 completes NV NT block fabrication. Such methods include depositing and patterning a conductor layer to form terminals that contact the NV NT blocks at the top, side, or termination areas, or combinations of contacts thereof, as shown, for example, in fig. 58A-58D. Alternatively, the method may include depositing and patterning an insulating layer followed by depositing and patterning a conductive layer, as shown in FIGS. 60A-60C.

At this point in the process, NV NT switches incorporating NV NT blocks have been formed and method 6680 completes the fabrication of the chip including passivation and packaging of the interconnect devices using known industrial fabrication methods. The encapsulated NV NT block includes a sacrificial polymer as shown with respect to block 5730 (shown in the 3-D diagram of fig. 57B).

Alternatively, method 6615 can substantially remove (e.g., evaporate) a sacrificial polymer, such as polypropylene carbonate, by heating the wafer to a temperature in the range of 200C to 400C. In this example, NV NT block 5730 becomes similar to NV NT block 5730 '(shown in 3-D view in FIG. 57B'), which has CNT structures formed substantially only from a single nanotube.

Method 6680 then completes fabrication of the chip including passivation and package interconnects using known industrial fabrication methods (,. NV NT block of package does not substantially include sacrificial polymer as shown with respect to block 5730' (3-D view of fig. 57B). at this point in the process, fabrication method 6600A using fabrication flow 1A ends.

In an alternative fabrication procedure, fabrication method 6600A includes fabrication flow 2A, which deposits an additional fabrication layer, added to the CNT layer (or layers), using method 6620 (deposited at a previous step using fabrication method 6608).

Next, method 6622 patterns a plurality of layers (including CNT layers). Known industrial methods remove (etch) exposed areas of the metal, insulator, and semiconductor layers. Exemplary methods of CNT layer etching are described in the incorporated patent references. Some methods remove (etch) sacrificial polymers, such as polypropylene carbonate (PPC), in the exposed areas. Exemplary methods may include anisotropic physical etching, such as Ar ion cut etching; or Reactive Ion Etching (RIE) including O₂Plasma; or a combination of both.

By way of example, NV NT switch 6400/6400' shown in fig. 64A-64C shows the formation of NV NT block 6410, which uses the top contact (and terminal) conductor and insulating layer as a mask to remove (etch) the underlying CNT layer. Section 4000 shown in FIG. 40 also shows NV NT patch, referred to as nanotube element 4050, formed by patterning an additional layer on the surface of the NV NT patch. However, substantially removing the exposed areas of the sacrificial polymer is not described in these two examples.

At this point in the process, NV NT switches incorporating NV NT blocks have been formed, and method 6680 completes fabrication of the chip including passivation and packaging of the interconnect devices using known industrial fabrication methods. The encapsulated NV NT block includes a sacrificial polymer as shown with respect to block 5730 (shown in the 3-D diagram of fig. 57B).

Alternatively, method 6615 substantially removes (e.g., evaporates) a sacrificial polymer, such as polypropylene carbonate, by heating the wafer to a temperature in the range of 200 ℃ to 400 ℃. In this example, NV NT block 5730 becomes similar to NV NT block 5730 '(shown in the 3-D view of fig. 57B'), which has CNT structures formed substantially from only a single nanotube.

Method 6680 then completes the fabrication of the chip including passivation and packaging of the interconnection means using known industrial fabrication methods. The encapsulated NV NT block includes substantially no sacrificial polymer, as shown with respect to block 5730 '(shown in the 3-D view of fig. 57B'). At this point in the process, fabrication method 6600A using fabrication flow 2A ends.

First manufacturing method of nonvolatile nanotube block with porous dielectric

Fig. 66B illustrates a method 6600B of fabricating an elevated NV NT block. In general, method 6605 manufactures support circuitry and interconnects in and out of a semiconductor substrate, for example, using method 2710 as described further above with reference to fig. 27. Method 6605 deposits and patterns semiconductor, metal, and insulating layers and forms structures before the CNT layer is deposited.

Next, method 6608 deposits a CNT layer (or layers) from a CNT dispersion in a sacrificial polymer dissolved in an organic solvent. For example, the sacrificial Polymer Polypropylene Carbonate (PPC) is dissolved in an organic solvent, such as NMP or cyclohexanone, which are available in the industry. At this point in the process, method 6600B of the manufacturing flow may continue with manufacturing flow 1B. Alternatively, method 6600B of the manufacturing flow may continue with manufacturing flow 2B. An exemplary fabrication method 6600B will first be described with respect to fabrication flow 1B, followed by a description of the fabrication method with respect to fabrication flow 2A.

The description of fabrication method 6600B is continued using fabrication flow 1B, then method 6625 uses nanotube etching techniques described in the incorporated patent references followed by patterning (etching) of the CNT layer. In some embodiments, the method substantially removes (e.g., etches) the sacrificial polymer, such as polypropylene carbonate (PPC), in the exposed regions. Exemplary methods include anisotropic physical etching, such as Ar ion cut etching; or Reactive Ion Etching (RIE) including O₂Plasma; or a combination of both.

Next, method 6628 substantially removes (e.g., evaporates) the sacrificial polymer, such as polypropylene carbonate, by heating the wafer to a temperature in the range of 200 ℃ to 400 ℃. In this example, NV NT block 5730 becomes similar to NV NT block 5730 '(shown in the 3-D view of fig. 57B'), which has CNT structures formed substantially from only a single nanotube.

Next, method 6630 forms a performance enhancing material, such as a porous dielectric. Porous dielectrics can be formed using Spin-On glass (SOG) and Spin-On low- κ (low- κ) organic dielectrics as described in the document "Reduction in the efficient Dielectric Constant of Integrated interconnected structures Through-line-On structure" available from Honeywell electronic materials of Honeywell International, Inc., Santo Industcoat 94089, USA, by Thanawa et al. Alternatively, the individual nanotubes forming the non-volatile nanotube bulk structure may be derivatized, covalently or non-covalently, to produce a modified surface, as described in U.S. patent publication No.2006/0193093, which includes the co-inventor Bertin and is incorporated herein by reference in its entirety. The derivatized individual nanotubes may include atoms such as oxygen, fluorine, chlorine, bromine, iodine (or others), thereby forming a non-volatile nanotube block that includes a porous dielectric for performance enhancement purposes.

Next, method 6632 completes the NV NT block fabrication. Such methods include depositing and patterning a conductor layer to form terminals that contact the NV NT blocks at the top, side, or termination areas, or combinations of contacts thereof. In this example, the NV NT block of the package having top and bottom contacts includes a performance enhancing material, such as a porous dielectric, as shown with respect to block 5750 (shown in 3-D view in fig. 57C).

At this point in the process, NV NT switches incorporating NV NT blocks have been formed, and method 6680 completes fabrication of the chip including passivation and packaging of the interconnect devices using known industrial fabrication methods. The NV NT block of the package includes a performance enhancing material, such as a porous dielectric, as shown with respect to block 5750 (shown in 3-D view in fig. 57C).

In an alternative fabrication sequence, fabrication method 6600B includes fabrication flow 2B, which uses method 6635 to substantially remove (e.g., evaporate) a sacrificial polymer, such as polypropylene carbonate, from the CNT layer by heating the wafer to a temperature in the range of 200 ℃ to 400 ℃.

Next, method 6638 forms a performance enhancing material, such as a porous dielectric. Porous dielectrics can be formed using Spin-On glass (SOG) and Spin-On low- κ (low- κ) organic dielectrics as described in the document "Reduction in the efficient Dielectric Constant of Integrated interconnected structures Through-line-On structure" available from Honeywell electronic materials of Honeywell International, Inc., Santo Industcoat 94089, USA, by Thanawa et al. Alternatively, the individual nanotubes forming the non-volatile nanotube block structure may be derivatized, either covalently or non-covalently, to produce a modified surface, as described in U.S. patent publication No. 2006/0193093. The derivatized individual nanotubes may include atoms such as oxygen, fluorine, chlorine, bromine, iodine (or others), thereby forming a non-volatile nanotube block that includes a porous dielectric for performance enhancement purposes.

Next, fabrication method 6640 deposits additional fabrication layers added to the CNT layer(s), such as conductor, insulator, or semiconductor layers deposited using industrial fabrication methods.

Next, method 6642 patterns a plurality of layers (including CNT layers). Known industrial methods remove (etch) exposed areas of the metal, insulator, and semiconductor layers. Exemplary methods of CNT layer etching are described in the incorporated patent references. Exemplary methods remove (etch) exposed portions of the performance enhancing material, such as the porous dielectric, using known industrial methods of etching dielectric materials.

At this point in the process, NV NT switches incorporating NV NT blocks have been formed, and method 6680 completes fabrication of the chip including passivation and packaging of the interconnect devices using known industrial fabrication methods. The NV NT block of the package includes a performance enhancing material, such as a porous dielectric, as shown with respect to block 5750 (shown in 3-D view in fig. 57C).

Second method for fabricating non-volatile nanotube block with porous dielectric

Fig. 66C shows a method 6600C of manufacturing an elevated NV NT block. In general, method 6605 fabricates support circuits and interconnects in and out of a semiconductor substrate, for example, using method 2710 as described further above with reference to fig. 27. In some embodiments, method 6605 deposits and patterns semiconductor, metal, and insulating layers and forms structures before the CNT layer is deposited.

Next, method 6650 deposits a CNT layer (or layers) from the CNT dispersion in an aqueous or non-aqueous solution, which is used to fabricate non-volatile nanotube blocks, as described in the incorporated patent references. At this point in the process, method 6600C of the manufacturing flow may continue with manufacturing flow 1C. Alternatively, method 6600C of the manufacturing flow may continue with manufacturing flow 2C. Exemplary fabrication method 6600C will first be described with respect to fabrication flow 1C, followed by a description of fabrication method 6600C with respect to fabrication flow 2C.

The description of fabrication method 6600C is continued using fabrication flow 1C, then method 6655 uses nanotube etching techniques described in the incorporated patent references followed by patterning (etching) of the CNT layer.

Next, method 6658 forms a performance enhancing material, such as a porous dielectric. Porous dielectrics can be formed using Spin-On glass (SOG) and Spin-On low- κ (low- κ) organic dielectrics as described in the document "Reduction in the efficient Dielectric Constant of Integrated interconnected structures Through-line-On structure" available from Honeywell electronic materials of Honeywell International, Inc., Santo Industcoat 94089, USA, by Thanawa et al. Alternatively, the individual nanotubes forming the non-volatile nanotube block structure may be derivatized, either covalently or non-covalently, to produce a modified surface, as described in U.S. patent publication No. 2006/0193093. The derivatized individual nanotubes may include atoms such as oxygen, fluorine, chlorine, bromine, iodine (or others), thereby forming a non-volatile nanotube block that includes a porous dielectric for performance enhancement purposes.

Next, method 6660 completes NV NT block fabrication. Such methods include depositing and patterning a conductor layer to form terminals that contact the NV NT blocks at the top, side, or termination areas, or combinations of contacts thereof. In this example, the NV NT block of the package having top and bottom contacts includes a performance enhancing material, such as a porous dielectric, as shown with respect to block 5750 (shown in 3-D view in fig. 57C).

At this point in the process, NV NT switches incorporating NV NT blocks have been formed, and method 6680 completes fabrication of the chip including passivation and packaging of the interconnect devices using known industrial fabrication methods. The NV NT block of the package includes a performance enhancing material, such as a porous dielectric, as shown with respect to block 5750 (shown in 3-D view in fig. 57C).

In an alternative fabrication sequence, fabrication method 6600C includes fabrication flow 2C, which uses method 6665 to form a performance enhancing material, such as a porous dielectric. Porous dielectrics can be formed using Spin-On glass (SOG) and Spin-On low- κ (low- κ) organic dielectrics as described in the document "reduced the efficient Dielectric Constant of Integrated Interconnect Structures through silicon-On Structures" by Thanawala et al (available from Honeywell electronic materials, Inc., Honeywell 94089, Calif.). Alternatively, the individual nanotubes forming the non-volatile nanotube block structure may be derivatized, either covalently or non-covalently, to produce a modified surface, as described in U.S. patent publication No. 2006/0193093. The derivatized individual nanotubes may include atoms such as oxygen, fluorine, chlorine, bromine, iodine (or others), thereby forming a non-volatile nanotube block that includes a porous dielectric for performance enhancement purposes.

Next, fabrication method 6670 deposits additional fabrication layers added to the CNT layer(s), such as conductor, insulator, or semiconductor layers deposited using industrial fabrication methods.

Next, method 6675 patterns a plurality of layers (including CNT layers). Known industrial methods remove (etch) exposed areas of the metal, insulator, and semiconductor layers. Exemplary methods of CNT layer etching are described in the incorporated patent references. In some embodiments, exposed portions of the performance enhancing material, such as the porous dielectric, are removed (etched) by using known industrial methods of etching dielectric materials, particularly oxygen plasma and reactive ion etching with gases, which are capable of removing carbon nanotubes that are not protected by photoresist or other process materials. Such etching may be isotropic or anisotropic depending on the desired orientation.

At this point in the process, NV NT switches incorporating NV NT blocks have been formed and method 6680 completes the fabrication of the chip including passivation and packaging of the interconnect devices using known industrial fabrication methods. The NV NT block of the package includes a performance enhancing material, such as a porous dielectric, as shown with respect to block 5750 (shown in 3-D view in fig. 57C).

Will have vertically oriented diodes andnon-volatile nanotube blockNV NT deviceBy usingFor forming on NT using top and bottom contactsCathode electrodeThree-dimensional cell structure for non-volatile cells of non-volatile NT switch of switch

FIG. 67 shows a cross-section 6700 including cells C00 and C01 in a 3-D memory embodiment. The nanotube layer is deposited by coating, spraying, or other means on a flat contact surface on a predefined diode-forming layer (as exemplified by fig. 40 shown further above). Section 6700 shown in fig. 67 corresponds to structure 4000 shown in fig. 40, and some additional details are associated with having NT upper cathode implementation and number of elements to facilitate description of the fabrication method. The trench etch after deposition of the insulator, semiconductor, conductor, and nanotube layers forms sidewall boundaries that define the nonvolatile nanotube-diode based 3-D memory cell of the nonvolatile nanotube block and define the nonvolatile nanotube block size, diode size, and the size of all other structures in the three-dimensional nonvolatile memory cell. The horizontal 3-D cell dimensions (X and Y are approximately vertical) of all cell structures are formed by trench etching and are therefore self-aligned at the time of fabrication. The vertical dimension (Z) is determined by the thickness and number of vertical layers used to form the 3-D cell. Fig. 67 shows a cross section 6700 along the word line (X) direction. The series-connected vertically oriented stacked steering diodes and the non-volatile nanotube block switches are symmetrical and have approximately the same cross-sectional dimensions in both the X and Y directions. Cross section 6700 shows an array cell in which the steering diode is connected to the bottom (lower) contact of the non-volatile nanotube block of the NT upper cathode arrangement. The word lines are oriented along the X-axis and the bit lines (along the Y-axis) as shown in the perspective view of fig. 33A.

Some embodiments of the method 2710, described further above with reference to fig. 27A, are used to define the support circuitry and interconnects 6701.

Next, method 2730 shown in fig. 27B deposits and planarizes insulator 6703. Interconnect means (not shown at section 6700, but shown above with reference to section 2800 "of fig. 28C) through the planar insulator 6703 can be used to connect the metal array lines in the 3-D array to the respective supporting circuitry and interconnects 6701. As an example, bit line drivers in BL driver and sense circuit 2640 may be connected to bit lines BL0 and BL1 in array 2610 of memory 2600 shown in fig. 26A and in section 6700 of fig. 67, described further above. At this point in the fabrication process, method 2740 may be used to form a memory array on the surface of insulator 6703, interconnected with memory array support structure 6705 of fig. 67. Memory array support structure 6705 corresponds to memory array support structure 3405 shown in fig. 47, support circuitry and interconnects 6701 correspond to support circuitry and interconnects 3401, and insulator 6703 corresponds to insulator 3403, with some modifications to accommodate new memory array structures including 3-D memory cells having non-volatile nanotube blocks with top (upper) and bottom (lower) contacts.

Exemplary method 2740 shown in fig. 27B deposits and planarizes metal, polysilicon, insulator, and nanotube element layers to form a non-volatile nanotube diode, which in this example includes a plurality of vertically oriented diodes and non-volatile nanotube block (NV NT block) switch NT upper cathode series pairs. To eliminate the accumulation of individual layer alignment tolerances that would substantially increase cell areaFor the X-direction, a single cell boundary is formed in a single etch step (and for the Y-direction a separate single etch), each cell having a single NV NT diode defined by a single trench etch step after the layers (except the WL0 layer) have been deposited and planarized. The single cell size is F (1 minimum feature) in the X direction as shown in fig. 40 and corresponding fig. 67, and also F in the Y direction (not shown) substantially perpendicular to the X direction, with a period of 2F in the X and Y directions. Thus, each cell occupies an area of about 4F²。

NV NT block with top (upper) and bottom (lower) contacts, as further illustrated above in fig. 40 and corresponding fig. 67 (via nanotube elements 4050-1 and 4050-2), is further illustrated above in the perspective views of fig. 57A-57C. The NV NT block device structure and electrical ON/OFF switch results are further described above with reference to FIGS. 64A-64C and 65. Methods of fabricating NV NT blocks with top and bottom contacts are described with respect to methods 6600A, 6600B, and 6600C shown in fig. 66A, 66B, and 66C, respectively. Channel length L of NV NT block with top and bottom contacts _SW-CHApproximately equal to the spacing between the top and bottom contacts, e.g., 35 nm. The NV NT block switch cross-section X by Y may be formed as X-Y-F, where F is the minimum technology node size. For a 35nm technology node, the NVNT tile may have a size of 35x35x35 nm; the NV NT block may have a size, for example, 22x22x35nm for a 22nm technology node.

The method fills the trench with an insulator; the method then planarizes the surface. The method then deposits and patterns word lines on the planarized surface.

Fabrication of the vertically oriented 3D cell shown in fig. 67 proceeds as follows. In some embodiments, the method deposits a bit line wiring layer on the surface of insulator 6703 having a thickness, for example, of 50 to 500nm, as described further below with reference to fig. 68A-68I. Fabrication of the vertically oriented diode portion of structure 6700 can be the same as further illustrated above in fig. 34A and 34B and incorporated into the fabrication method described with reference to fig. 68A-68I. Methods etch the bit line wiring layer and define individual bit lines, e.g.Bit line conductors 6710-1(BL0) and 6710-2(BL 1). Bit lines, such as BL0 and BL1, are used as array wiring conductors and may also be used as anode terminals of schottky diodes. Alternatively, more optimized Schottky diode junctions may be formed using metal or silicide contacts (not shown) in contact with N-polysilicon regions 6720-1 and 6720-2, while also forming ohmic contacts to bit line conductors 6710-1 and 6710-2. The N-poly regions 6720-1 and 6720-2 may be doped with arsenic or phosphorous in the range of, for example, 10 ¹⁴To 10¹⁷Dopant atom/cm³And may have a thickness in the range of, for example, 20nm to 400 nm.

Fig. 67 shows a cathode-to-NT type NV NT diode formed with a schottky diode. However, PN or PIN diodes may be used in place of schottky diodes, as further described below with reference to fig. 68A.

By controlling the material properties of the polysilicon, such as depositing and patterning the polysilicon to form polysilicon regions 6820-1 and 6820-2, the electrical characteristics of the schottky (and PN, PIN) diode may be improved (e.g., low leakage). The polysilicon region may have a relatively large or relatively small grain boundary size, depending on the fabrication process, such as annealing (anneal) time and temperature. In some embodiments, SOI deposition methods in the semiconductor industry may be used, which result in the polysilicon region being monocrystalline (no longer polysilicon), or nearly monocrystalline, for further enhancing electrical properties, such as low diode leakage current.

Examples of contact and conductor materials include elemental metals such as Al, Au, Pt, W, Ta, Cu, Mo, Pd, Ni, Ru, Ti, Cr, Ag, In, Ir, Pb, Sn, and metal alloys such as TiAu, TiCu, TiPd, Pbin, and TiW, other suitable conductors, or conductive nitrides such as TiN, oxides, or silicides such as RuN, RuO, TiN, TaN, CoSi _xAnd TiSi_x. In some examples, conductors such as Al, Au, W, Cu, Mo, Ti, and others may be used as both contacts and conductor materials as well as the anode of the schottky diode. In other examples, however, for low forward voltage drop and low diode leakage,it is advantageous to optimize the anode material. Schottky diode anode material (not shown) may be added between conductors 6710-1 and 6710-2 and polysilicon regions 6720-1 and 6720-2, respectively. Such anode materials may include Al, Ag, Au, Ca, Co, Cr, Cu, Fe, Ir, Mg, Mo, Na, Ni, Os, Pb, Pd, Pt, Rb, Ru, Ti, W, Ta, Zn, and other elemental metals. In addition, silicides, e.g., CoSi, may be used₂、MoSi₂、Pd₂Si、PtSi、RbSi₂、TiSi₂、WSi₂And ZrSi₂. Schottky diodes formed using such metals and silicides are disclosed in NG, k.k. "CompleteGuide to Semiconductor Devices", Second Edition, John Wiley&Sons, 2002, pp.31-41, the entire contents of which are incorporated herein by reference.

Next, after the schottky diode select device is completed, the method forms N + polysilicon regions 6725-1 and 6725-2 to contact N polysilicon regions 6720-1 and 6720-2, respectively. The N + polysilicon is typically doped with arsenic or phosphorous to, for example, 10 ²⁰Dopant atom/cm³And has a thickness of, for example, 20 to 400 nm. The N and N + polysilicon region sizes are defined by the trench etch near the end of the fabrication flow.

Next, the method forms bottom (lower) contact regions 4030-1 and 4030-2, respectively, having ohmic or near-ohmic contacts to polysilicon regions 6725-1 and 6725-2. Examples of contact and conductor materials include elemental metals such as Al, Au, W, Ta, Cu, Mo, Pd, Ni, Ru, Ti, Cr, Ag, In, Ir, Pb, Sn, and metal alloys such as TiAu, TiCu, TiPd, Pbin, and TiW, other suitable conductors, or conductive nitrides such as TiN, oxides, or silicides such as RuN, RuO, TiN, TaN, CoSi_xAnd TiSi_x。

Next, the method forms NV NT blocks 4050-1 and 4050-2 on the surface of contact areas 4030-1 and 4030-2, respectively, with the nanotube element length of the NV NT blocks defined by the nanotube thickness in the vertical Z direction and the X-Y cross section defined by the trench etch near the end of the fabrication flow. Note that NV NT block 4050-1 in FIG. 67 corresponds to nanotube element 4050 in FIG. 40. To increase the density of cells C00 and C01, NV NT blocks 4050-1 and 4050-2 in FIG. 67 include simple top and bottom contacts within the trench-defining cell boundaries.

Next, the method forms top (upper) contacts 4065-1 and 4065-2 on the top surface of NV NT blocks 4050-1 and 4050-2, respectively, with X and Y dimensions defined by a trench etch near the end of the fabrication process.

Next, the method forms (etches) trench openings 4075, 4075A, and 4075B each having a width F, thereby forming cells C00 and C01 and corresponding top (upper) and bottom (lower) contacts, nanotube elements, and the inside and outside walls of the insulator. Bottom (lower) contacts 4030-1 and 4030-2 form electrical connections between NV NT blocks 4050-1 and 4050-2 and the corresponding lower steering diode cathode terminals, respectively, and form bit lines 6710-1 and 6710-2. The trench formation (etching) stops at the surface of the insulator 6703.

Next, the method fills the trench openings 4075, 4075A, and 4075B with insulators 4060, 4060A, and 4060B, respectively, such as TEOS, and planarizes the surface. All trenches may be formed simultaneously.

Next, the method deposits and planarizes the wordline layer.

Next, the method patterns the word lines 6770.

Next, method 2750 of FIG. 27A completes the fabrication of a semiconductor chip having a non-volatile memory array using a non-volatile nanotube diode cell structure including passivation and packaging interconnect means using known industry methods.

The nonvolatile nanotube diode forming cells C00 and C01 corresponds to nonvolatile nanotube diode 1200 shown in fig. 12, and is also schematically shown by NV NT diode 6780 in fig. 67, one for each of cells C00 and C01. Cells C00 and C01 of cross-section 6700 shown in fig. 67 correspond to respective cells C00 and C01 of memory array 2610 schematically shown in fig. 26A, while bit lines BL0 and BL1 and word line WL0 correspond to the array lines schematically shown in memory array 2610.

The embodiment of method 2700 shown in fig. 27A and 27B can be used to fabricate non-volatile memories using NV NT diode devices having a cathode-to-NT switch connected to an NV NT block switch, such as section 6700 shown in fig. 67 and as further described below with reference to fig. 68A-68I. Structures, such as cross-section 6700, may be used to fabricate memory 2600, which is schematically illustrated in fig. 26A.

Will have vertically oriented diodes andof non-volatile nanotube blocksNV NT devices used for forming on NT using top and bottom contactsOf cathode switchesMethod for fabricating three-dimensional cell structure of nonvolatile cell by nonvolatile NT switch

The embodiment of the method 2710 shown in fig. 27A can be used to define support circuits and interconnects similar to those further described above with respect to the memory 2600 shown in fig. 26A. The method 2710 applies well-known semiconductor industry technology design and fabrication techniques to fabricate support circuits and interconnects 6801 in and on a semiconductor substrate, as shown in fig. 68A. The support circuits and interconnects 6801 include FET devices in the semiconductor substrate and interconnects, such as vias and wires, on the semiconductor substrate. Fig. 68A corresponds to fig. 34A showing a schottky diode structure except that an optional conductive schottky anode contact layer 3415 is shown in fig. 34A but not in fig. 68A. Note that fig. 34A ' may be used initially instead of fig. 34A ', ' if a PN diode structure is desired. If the N polysilicon layer 3417 in fig. 34A' is replaced with an inherently doped polysilicon layer (not shown), a PIN diode is formed instead of a PN diode. Thus, while the structure shown in fig. 68A shows a schottky diode structure, the structure may also be fabricated using a PN diode or a PIN diode.

The method of fabricating the elements and structures of support circuitry and interconnects 6801, insulator 6803, memory array support structure 6805, conductor layer 6810, N polysilicon layer 6820, N + polysilicon layer 6825, and bottom (lower) contact layer 6830 shown in fig. 68A is further described above with reference to fig. 34A and 34B, in which support circuitry and interconnects 6801 correspond to support circuitry and interconnects 3401; the insulator 6803 corresponds to the insulator 3403; memory array support structure 6805 corresponds to memory array support structure 3405; the conductive layer 6810 corresponds to the conductive layer 3410; the N polysilicon layer 6820 corresponds to the N polysilicon layer 3420; the N + polysilicon layer 6825 corresponds to the N + polysilicon layer 3425; and the bottom (lower) contact layer 6830 corresponds to the bottom (lower) contact layer 3430.

Next, the method deposits a nanotube layer 6835 on the flat surface of contact layer 6830 using multiple layers of spin coating, spray coating, or other means, as shown in fig. 68B. The nanotube layer 6835 can be in the range of, for example, 10-200 nm. An exemplary device having a thickness of 35nm was fabricated and switched between ON/OFF states as shown in fig. 64A-64C and 65. Methods of fabricating NV NT blocks with top and bottom contacts are described with respect to methods 6600A, 6600B, and 6600C shown in fig. 66A, 66B, and 66C, respectively.

At this point in the fabrication process, the method deposits a top (upper) contact layer 6840 on the surface of the nanotube layer 6835, as shown in fig. 68B. The top (upper) contact layer 6840 may be, for example, 10 to 500nm thick. The top (upper) contact layer 6840 may be formed using the following: al, Au, Ta, W, Cu, Mo, Pd, Pt, Ni, Ru, Ti, Cr, Ag, In, Ir, Pb, Sn, and metal alloys such as TiAu, TiCu, TiPd, PbIn, and TiW, other suitable conductors, or conductive nitrides such as TiN, oxides, or silicides such as RuN, RuO, TiN, TaN, CoSi_xAnd TiSi_x。

Next, the process deposits and patterns a mask layer 6850 on the top (upper) contact layer 6840 using known industry methods, as depicted in fig. 68C. The mask layer 6850 may have a thickness in the range of 10 to 500nm, and may be formed using a resist, such as a photoresist, an electron beam (e-beam) resist, or a conductor, semiconductor, or insulator material. Openings 6855, 6855A, and 6855B of mask layer 6850 expose underlying regions for trench etch purposes. The mask openings may be aligned to, for example, alignment marks in the planar insulating layer 6803; this alignment is non-critical. To achieve the minimum unit size, the openings 6855, 6855A, and 6855B of the mask layer 6850 are approximately equal to the minimum allowable technology dimension F. F may be, for example, 90nm, 65nm, 45nm, 35nm, 25nm, 12nm, or sub-10 nm.

At this point in the process, mask layer 6850 openings 6855, 6855A, and 6855B may be used for directional etching of the trenches using a method that defines cell boundaries along the X-direction of a 3D cell using one NV NT diode with one internal cathode-to-nanotube connection per cell. U.S. patent 5,670,803 to Bertin, which is incorporated herein by reference in its entirety, discloses a 3-D array (3D-SRAM in this example) structure having sidewall dimensions that are simultaneously trench-defined. The structure includes vertical sidewalls simultaneously defined by trenches cut through the multi-layer doped silicon and insulating regions to avoid multiple alignment steps. This trench-directed selective etch process can cut through multiple layers of conductor, semiconductor, oxide, and nanotube layers as further described above with respect to the trench formation of FIGS. 34A-34FF and 36A-36 FF. In this example, a selective directional trench etch (RIE) removes exposed regions of the top (upper) contact layer 6840 to form upper contact regions 6840-1 and 6840-2; removing exposed regions of nanotube layer 6835 to form nanotube regions 6835-1 and 6835-2; removing exposed regions of bottom (lower) contact layer 6830 to form bottom (lower) contact regions 6830-1 and 6830-2; directionally etching away the exposed regions of the N + polysilicon layer 6825 to form N + polysilicon regions 6825-1 and 6825-2; removing the exposed regions of the polysilicon layer 6820 to form N polysilicon regions 6820-1 and 6820-2; and removing the exposed regions of conductor layer 6810 to form conductor regions 6810-1 and 6810-2, stopping on the surface of insulator 6803 and simultaneously forming trench openings 6860, 6860A, and 6860B, as shown in fig. 68D.

Next, the method fills the trench openings 6860, 6860A, and 6860B with insulators 6865, 6865A, and 6865B, such as TEOS, respectively, and planarizes, as shown in fig. 68E.

Next, the method deposits and planarizes conductor layer 6870 contacting top (upper) contacts 6840-1 and 6840-2, as shown in fig. 68F.

Next, the conductor layer 6870 is patterned to form word lines that are substantially perpendicular to the conductors (bit lines) 6810-1 and 6810-2, as further illustrated below.

At this point in the process, the cross-section 6875 shown in FIG. 68F has been fabricated and includes NV NT diode cells of size F (where F is the minimum feature size) and a cell period defined as 2F in the X direction, as well as the corresponding array bit lines. Next, cell dimensions for defining dimensions in the Y-direction are formed by a directional trench etch process, similar to that described further above with respect to cross-section 6875 shown in FIG. 68F. The trenches defining a dimension in the Y direction are substantially perpendicular to the trenches defining a dimension in the X direction. A cross section of the structure in the Y (bit line) direction is shown with respect to the cross section Y-Y' shown in fig. 68F.

Next, the method deposits and patterns a mask layer, such as mask layer 6880 having openings 6882, 6882A, and 6882B on the surface of word line layer 6870, as shown in fig. 68G. The mask layer 6880 openings can be non-critically aligned to alignment marks in the planar insulator 6803. Openings 6882, 6882A, and 6882 in mask layer 6880 determine the location of trench-directed etch regions, which in this example are substantially perpendicular to a bitline, such as bitline 6810-1(BL 0).

At this point in the process, the openings 6882, 6882A, and 6882B in the mask layer 6880 can be used for directional etching of the trenches using a method that defines new cell boundaries along the Y-direction of the 3D cells using an NV NT diode with an internal cathode-to-nanotube connection per cell. Using the fabrication method for forming X-direction trenches as described with reference to fig. 68D, all trenches and corresponding cell boundaries can be formed simultaneously (e.g., using one etching step). The structure includes vertical sidewalls, which are simultaneously defined by trenches; the dimensions and materials in the X and Y directions are the same. In this example, a selective directional trench etch (RIE) method removes the exposed regions of the conductive layer 6870 to form word lines 6870-1(WL0) and 6870-2(WL1) (substantially perpendicular to bit lines 6810-1(BL0) and 6810-2(BL 1)); removing top (upper) contact layer 6840-1 to form upper contact regions 6840-1' and 6840-1 "; removing exposed regions of the nanotube layer 6835-1 to form nanotube regions 6835-1' and 6835-1 "; removing exposed regions of bottom (lower) contact layer 6830-1 to form bottom (lower) contact regions 6830-1' and 6830-1 "; selectively directional etch removes the exposed regions of the N + polysilicon layer 6825-1 to form N + polysilicon regions 6825-1' and 6825-1 "; removing the exposed regions of the polysilicon layer 6820-1 to form N polysilicon regions 6820-1' and 6820-1 "; and the etching stops on the surface of the exposed region of the conductor layer 6810-1, as shown in fig. 68H.

Next, the method fills, for example, trench openings 6884, 6884A, and 6884B with insulator 6885, 6885A, and 6885B (e.g., TEOS) and planarizes, as shown in cross-section 6890 in fig. 68I. At this point in the process, the nonvolatile nanotube diode based cell is fully formed and interconnected with the bit line and substantially perpendicular to the word line. Section 6875 shown in FIG. 68F and section 6890 shown in FIG. 68I are two cross-sectional views of the same 3D nonvolatile memory array whose cells are formed with NV NT diodes having vertically oriented steering (select) diodes and nonvolatile nanotube blocks. The cathode terminal of the diode contacts the lower surface of the block located within the cell boundary. The anode side of the diode is in contact with a bit line, such as bit line 6810-1(BL0), while the top surface of the block is in contact with a substantially vertical word line, such as word line 6870-1(WL0), as shown by cross-section 6890 in FIG. 68I.

Cross-sections 6875 and 6890 shown in FIGS. 68F and 68I, respectively, at this point in the process correspond to cross-section 6700 shown in FIG. 67 and are fabricated with cells having a vertically oriented steering diode and corresponding non-volatile nanotube block switch in series, with a vertically oriented (Z-direction) channel length L _SW-CHIs defined to include: overall NV NT diode cell size with X-direction 1F and Y-direction 1F, and corresponding bit and word line array lines. Cross-section 6875 is a unit of two adjacent cathode-to-nanotube type based non-volatile nanotube diodesCross-section in the X-direction, and cross-section 6890 is the cross-section in the Y-direction of two adjacent cells based on a cathode-to-nanotube type nonvolatile nanotube diode. Sections 6875 and 6890 include corresponding word lines and bit line array lines. The non-volatile nanotube diode forms the steering and storage elements in each cell shown in cross-sections 6875 and 6890, and each cell has dimensions of 1F by 1F. The pitch between adjacent cells is 1F, so the cell period is 2F in both X and Y directions. So that one bit occupies an area of 4F². At the 45nm technical node, the unit area is less than 0.01um²Or in this case about 0.002um²。

Using diodes with vertical orientation andnon-volatile nanotube blockAs a method of using top and bottom contacts to form on NTAnodeThree-dimensional cell structure for non-volatile cells of non-volatile NT switch of switch

FIG. 69 shows a cross-section 6900 including cells C00 and C10 in a 3-D memory embodiment. The nanotube layer is deposited by coating, spraying, or other means on a flat contact surface on a predefined diode-forming layer (as shown in fig. 40, further shown above). The cross-section 6900 shown in fig. 69 corresponds to the structure 4000 shown in fig. 40, and some additional details are associated with the cathode implementation and number of elements on the NT in order to describe the manufacturing method. The trench etch after deposition of the insulator, semiconductor, conductor, and nanotube layers forms sidewall boundaries that define the nonvolatile nanotube-diode based 3-D memory cell of the nonvolatile nanotube block and define the nonvolatile nanotube block size, diode size, and the size of all other structures in the three-dimensional nonvolatile memory cell. The horizontal-D cell dimensions (X and Y are approximately vertical) of all cell structures are formed by trench etching and are therefore self-aligned at the time of fabrication. The vertical dimension (Z) is determined by the thickness and number of vertical layers used to form the 3-D cell. Fig. 69 shows a cross section 6900 along the bit line (Y) direction. The series-connected vertically oriented stacked steering diodes and the non-volatile nanotube block switches are symmetrical and have approximately the same cross-sectional dimensions in both the X and Y directions. Cross section 6900 shows an array cell with a steering diode connected to the bottom (lower) contact of the non-volatile nanotube block of the anode arrangement on the NT. The word lines are arranged along the X-axis and the bit lines are arranged along the Y-axis, as shown in the perspective view of fig. 33A.

In some embodiments, a method 3010, as further described above with reference to fig. 30A, is used to define the support circuitry and interconnects 6901.

Next, a method 3030 shown in fig. 30B deposits and planarizes the insulator 6903. An interconnect means (not shown in cross-section 6900, but shown above with respect to cross-section 2800 "in fig. 28C) through the planar insulator 6903 can be used to connect the metal array lines in the 3-D array to corresponding support circuitry and interconnects 6901. As an example, a word line driver of the word line drivers 2930 may be connected to word lines WL0 and WL1 (shown in the array 2910 of the memory 2900 of fig. 29A and the cross-section 6900 shown in fig. 69, further illustrated above). At this point in the fabrication process, method 3040 may be used to form a memory array on the surface of insulator 6903, interconnected with memory array support structure 6905 of fig. 69. Memory array support structure 6905 corresponds to memory array support structure 3605 shown in fig. 51, support circuitry and interconnects 6901 correspond to support circuitry and interconnects 3601, and insulator 6903 corresponds to insulator 3603, except with some changes to accommodate new memory array structures that include 3-D memory cells with non-volatile nanotube blocks having top (upper) and bottom (lower) contacts.

In some embodiments, the method 3040 of FIG. 30B deposits and planarizes metal, polysilicon, insulator, and nanotube element layers to form a non-volatile nanotube diode, which in this case includes a plurality of vertically oriented diode and non-volatile nanotube block (NVNT block) switch anode series pairs. To eliminate the accumulation of individual layer alignment tolerances that would substantially increase the cell area, individual cell outer dimensions are formed in a single etch step, each cell having a single NV NT diode etched from a single trench after the layers (except for the BL0 layer) have been deposited and planarizedThe steps are defined. The single cell size is F (1 minimum feature) in the X direction as shown in fig. 40 and corresponding fig. 67, and also F in the Y direction substantially perpendicular to the X direction as shown in fig. 69, with a period of 2F in the X and Y directions. Thus, each cell occupies an area of about 4F²。

NV NT block with top (upper) and bottom (lower) contacts as shown above in fig. 69 by nanotube elements 4050-1 and 4050-2 is further shown in the perspective view of fig. 57 above. NV NT block device structure and electrical ON/OFF switching results, as described further above with reference to FIGS. 64 and 65. Methods of fabricating NV NT blocks with top and bottom contacts are described with respect to methods 6600A, 6600B, and 6600C shown in fig. 66A, 66B, and 66C, respectively. Channel length L of NV NT block with top and bottom contacts _SW-CHApproximately equal to the spacing between the top and bottom contacts, e.g., 35nm, as further described above with reference to fig. 64A-64C. The NV NT block switch cross-section X by Y may be formed as X-Y-F, where F is the minimum technology node size. For a 35nm technology node, the NV NT block may have a size of 35x35x35 nm; for a 22nm technology node, the NV NT block may have, for example, a size of 22x22x35 nm. The thickness of the nanotube element need not be related to F in any particular manner.

The method fills the trench with an insulator; the method then planarizes the surface. The method then deposits and patterns bit lines on the planarized surface.

Fabrication of the vertically oriented 3D cell shown in fig. 69 proceeds as follows. In some embodiments, the method deposits the word line wiring layer on the surface of the insulator 6903 with a thickness of, for example, 50 to 500 nm. Fabrication of the vertically oriented diode portion of structure 6900 is the same as that of fig. 36A, as described further above. In some embodiments, the method etches a word line routing layer and defines a single word line, such as word line conductors 6910-1(WL0) and 6910-2(WL 1). Word lines, such as WL0 and WL1, are used as array wiring conductors and may also be used as near-ohmic contacts to the N + polysilicon cathode terminals of the schottky diodes.

Examples of contact and conductor materials include elemental metals such as Al, Au, W, Ta, Cu, Mo, Pd, Pt, Ni, Ru, Ti, Cr, Ag, In, Ir, Pb, Sn, and metal alloys such as TiAu, TiCu, TiPd, Pbin, and TiW, other suitable conductors, or conductive nitrides such as TiN, oxides, or silicides such as RuN, RuO, TiN, TaN, CoSi_xAnd TiSi_x. The insulator can be SiO₂、SiN_x、Al₂O₃BeO, polyimide, mylar, or other suitable insulating material.

Next, N + polysilicon regions 6920-1 and 6920-2 are formed to contact word line regions 6910-1 and 6920-2, respectively. The N + polysilicon is typically doped with arsenic or phosphorous to, for example, 10²⁰Dopant atom/cm³And has a thickness of, for example, 20 to 400 nm.

Next, N polysilicon regions 6925-1 and 6925-2 are formed to contact N + polysilicon regions 6920-1 and 6920-2, respectively, and may be doped with arsenic or phosphorous, for example, in the range of 10¹⁴To 10¹⁷Dopant atom/cm³And may have a thickness in the range of, for example, 20nm to 400 nm. N polysilicon regions 6925-1 and 6925-2 form the cathode regions of the corresponding schottky diodes. The N and N + polysilicon region sizes are defined by the trench etch near the end of the fabrication flow.

Next, the method forms contact regions 6930-1 and 6930-2 on N-poly regions 6925-1 and 6925-2, respectively. Contact regions 6930-1 and 6930-2 form anode regions, which complete the formation of a vertically oriented steering diode structure. Contact areas 6930-1 and 6930-2 also form bottom (lower) contacts to NV NT blocks 4050-1 and 4050-2, respectively. Fabrication of the vertically oriented diode portion of structure 6900 is similar to the fabrication method described further above with reference to fig. 36A. Although fig. 69 shows NV NT diodes of the anode-on-NT type formed with schottky diodes, PN or PIN diodes may be used in place of schottky diodes, as further described above with reference to fig. 36A'.

In some examples, such as Al, Au, W, Cu, Mo,Ti, and other conductors, may be used as both NV NT block contacts and anodes of schottky diodes. However, in other examples, it is advantageous to optimize the anode material for low forward voltage drop and low diode leakage. In this example (not shown), a sandwich structure (sandwich) may be formed by contacting the schottky diode anode material with the N-poly region and NV NT block contact material (forming the bottom (lower region) contact). The anode material may include Al, Ag, Au, Ca, Co, Cr, Cu, Fe, Ir, Mg, Mo, Na, Ni, Os, Pb, Pd, Pt, Rb, Ru, Ta, Ti, W, Zn, and other elemental metals. In addition, silicides, e.g., CoSi, may be used ₂、MoSi₂、Pd₂Si、PtSi、RbSi₂、TiSi₂、WSi₂And ZrSi₂. Schottky diodes formed using such metals and silicides are disclosed in NG, k.k. "compact Guide to semiconductor Devices", Second Edition, John Wiley&Sons, 2002, pp.31-41, the entire contents of which are incorporated herein by reference. Examples of NV NT block contacts and materials that also contact the anode material include elemental metals such as Al, Au, W, Ta, Cu, Mo, Pd, Ni, Ru, Ti, Cr, Ag, In, Ir, Pb, Sn, and metal alloys such as TiAu, TiCu, TiPd, PbIn, and TiW, other suitable conductors, or conductive nitrides such as TiN, oxides, or silicides such as RuN, RuO, TiN, TaN, CoSi_xAnd TiSi_x。

Next, the method forms NV NT blocks 4050-1 and 4050-2 on the surface of contact regions 6930-1 and 6930-2, respectively, with nanotube element lengths defined by nanotube thickness in the vertical Z direction and X-Y cross sections defined by trench etching near the end of the fabrication process. Note that NV NT block 4050-1 in FIG. 69 corresponds to nanotube element 4050 in FIG. 40. To maximize the density of cells C00 and C10, NV NT blocks 4050-1 and 4050-2 shown in FIG. 69 include simple top and bottom contacts within the trench-defining cell boundaries.

Next, the method forms top (upper) contacts 4065-1 and 4065-2 on the top surface of NV NT blocks 4050-1 and 4050-2, respectively, with the X and Y dimensions being defined near the end of the fabrication process by trench etching.

Next, the method forms (etches) trench openings 6975, 6975A, and 6975B each having a width F, thereby forming cells C00 and C10 and corresponding top (upper) and bottom (lower) contacts, nanotube elements, and inner and outer sidewalls of the insulator. Bottom (lower) contacts 6930-1 and 6930-2 form electrical connections between NV NT blocks 4050-1 and 4050-2, respectively, and also form lower steering diode anode terminals, and word lines 6910-1 and 6910-2. The trench formation (etch) stops at the surface of insulator 6903.

Next, the method fills the trench openings 6975, 6975A, and 6975B with insulators 6960, 6960A, and 6960B (e.g., TEOS), and planarizes the surface. All trenches may be formed simultaneously.

Next, the method deposits and planarizes the bit line layer.

Next, the method patterns the bit lines 6970.

The nonvolatile nanotube diode forming cells C00 and C10 corresponds to nonvolatile nanotube diode 1300 shown in fig. 13, which is also schematically illustrated by NV NT diode 6980 in fig. 69, one for each of cells C00 and C10. Cells C00 and C10 of cross-section 6900 shown in fig. 69 correspond to respective cells C00 and C10 schematically shown in memory array 2910 in fig. 29A, while word lines WL0 and WL1 and bit line BL0 correspond to the array lines schematically shown in memory array 2910.

At this point in the process, corresponding structures in the X direction are formed to complete the NV NT diode based cell structure. Fig. 70 shows cross section 7000 along word line WL0, with word line WL0 along the word line (X-axis) direction. The series-connected vertically oriented stacked steering diodes and the non-volatile nanotube block switches are symmetrical and have substantially the same cross-section in both the X and Y directions. Cross section 7000 shows an array cell with steering diodes connected to the bottom (lower) contact of the non-volatile nanotube block of the anode arrangement on the NT. The word lines are oriented along the X-axis and the bit lines are oriented along the Y-axis, as shown in the perspective view of fig. 33A.

The cross section 7000 shown in fig. 70 shows the support circuitry and interconnects 6901 and insulators 6903, as further described above with reference to fig. 69. Section 7000 is along word line 6910-1(WL0) in the X direction.

The N + polysilicon regions 6920-1 'and 6920-1 "form contacts between word lines 6910-1(WL0) and N polysilicon regions 6925-1' and 6925-1" (forming the diode cathode regions), respectively. Bottom (lower) contacts 6930-1 ' and 6930-1 "serve as anodes to form N-polysilicon regions 6925-1 ' and 6925-1", respectively, of the schottky diode and contact non-volatile nanotube blocks 4050-1 ' and 4050-1 ", respectively, as illustrated by cross-section 7000 shown in fig. 70.

NVNT blocks 4050-1 'and 4050-1 "on the surface of contact regions 6930-1' and 6930-1", respectively, have nanotube element lengths L of NV NT blocks_SW-CHDefined by the nanotube thickness in the vertical Z-direction, while the X-Y cross section is defined by the trench etch near the end of the fabrication flow. Note that NV NT block 4050-1' in FIG. 70 corresponds to NV NT block 4050-1 shown in FIG. 69. To maximize the density of cells C00 and C01 shown in fig. 70, NV NT blocks 4050-1' and 4050-1 "include simple top and bottom contacts within the trench-defining cell boundaries.

Contacts to the top surface of the NV NT block are shown in fig. 70 by top (upper) contacts 4065-1 'and 4065-1 "on the top surface of NV NT blocks 4050-1' and 4050-1", respectively.

The bit lines 6970-1(BL0) and 6970-2 are in direct contact with top (upper) contacts 4065-1' and 4065-1 ", respectively, as shown in FIG. 70.

Next, method 3050, shown in fig. 30A, completes fabrication of a semiconductor chip having a non-volatile memory array using a non-volatile nanotube diode cell structure including passivation and packaging interconnects using known industry methods.

Respective cross sections 6900 and 7000 of fig. 69 and 70 show anode-to-NT 3D memory arrays with nonvolatile nanotube block based switches, respectively. Nanotube channel length L _SW-CHCorresponding to the NV NT diode cell size in the Z-direction, and having an X-Y cross-section with X-Y-F, and corresponding bit and word line array lines. Cross-section 6900 is a cross-section in the Y-direction of two adjacent cells of an anode-to-nanotube type based nonvolatile nanotube diode (including NV NT block based switches), while cross-section 7000 is a cross-section in the X-direction of two adjacent cells of an anode-to-nanotube type based nonvolatile nanotube diode (including NV NT block based switches). Cross sections 6900 and 7000 include respective word line and bit line array lines. The non-volatile nanotube diode forms steering and storage elements in each cell shown in cross-sections 6900 and 7000, and each cell has dimensions of 1F by 1F. The spacing between adjacent cells is 1F, so the cell period is 2F in both the X and Y directions. So that one bit occupies an area of 4F². At a 45nm technology node, the unit area is less than about 0.01um²Or in this case about 0.002um²。

The fabrication methods of the respective cross-sections 6900 and 7000 shown in fig. 69 and 70 correspond to the fabrication method described with reference to fig. 68, except that the vertical positions of the N polysilicon and N + silicon layers are interchanged. The manufacturing method for fabricating NV NT block switches is the same. The only difference is that when the trenches are formed in cross-sections 6900 and 7000, the N polysilicon layer is etched before the N + polysilicon layer.

Non-volatile memory using NVNT diode devices with shared array lines and unshared array line stacks and cathode-to-NT switch connections and non-volatile nanotube blocks with top and bottom contacts forming 3-D NVNT switches

FIG. 32 illustrates a method 3200 of fabricating an embodiment having two memory arrays stacked on top of each other and stacked on an insulating layer over support circuitry formed under the insulating layer and the stacked arrays and having vias through the insulating layer. Although method 3200 is further described below with respect to nonvolatile nanotube diodes 1200 and 1300, method 3200 is sufficient to encompass the fabrication of many nonvolatile nanotube diodes as described further above. It is also noted that while method 3200 is described in terms of a 3D memory embodiment, method 3200 can also be used to form a 3D logic embodiment based on NV NT diodes arranged as a logic array, such as NAND and NOR arrays with logic support circuitry (rather than memory support circuitry) for PLA, FPGA, and PLD, for example.

Fig. 71 shows a 3D perspective view 7100 comprising a dual-high stacked three-dimensional array, a lower array 7102 and an upper array 7104. The lower array 7102 includes nonvolatile nanotube diode cells C00, C01, C10, and C11. The upper array 7104 includes nonvolatile nanotube diode cells C02, C12, C03, and C13. Word lines WL0 and WL1, which are shared between the upper and lower arrays, are oriented along the X-direction, while bit lines BL0, BL1, BL2, and BL3 are oriented along the Y-direction and are substantially perpendicular to word lines WL1 and WL 2. Nanotube element channel length L _SW-CHOriented vertically as shown in 3D perspective 7100. The cross-section 7200 corresponding to cells C00, C01, C02, and C03 is further shown below in fig. 72A, and the cross-section 7200' corresponding to cells C00, C02, C12, and C10 is further shown below in fig. 72B.

Generally, method 3210 manufactures support circuitry and interconnects in and on a semiconductor substrate. This includes NFET and PFET devices having drains, sources, and gates interconnected to form memory (or logic) support circuits. Such structures and circuits may be formed using known techniques, which are not described herein. In some embodiments, method 3210 is used to form the support circuitry and interconnect 7201 layers using known fabrication methods as part of the cross-sections 7200 and 7200' shown in fig. 72A and 72B, where the nonvolatile nanotube diode control and circuitry is fabricated in and on the support circuitry and interconnect 7201 layers. The support circuits and interconnects 7201 are similar to, for example, the support circuits and interconnects 6701 shown in FIG. 67 and 6901 shown in FIG. 69, but modified to accommodate two stacked memory arrays. Note that although a dual-high stacked memory array is shown in fig. 72A-72B, more than a dual-high 3D array stack may be formed (fabricated), including but not limited to, for example, 4-high and 8-high stacks.

Next, method 3210 is also used to fabricate intermediate structures, including a planarized insulator with interconnects and non-volatile nanotube array structures on the planarized insulator surface, such as insulator 7203 shown in cross-sections 7200 and 7200' in fig. 72A and 72B, respectively, and similar to insulator 6703 shown in fig. 67 and insulator 6901 shown in fig. 69, but modified to accommodate two stacked memory arrays. The interconnect means includes vertically oriented fill contacts, or studs, for interconnecting memory support circuitry in and on the semiconductor substrate below a planarized insulator having an array of non-volatile nanotube diodes above and on the surface of the planarized insulator. The planarization insulator 7203 is formed using a method similar to method 2730 shown in fig. 27B. The interconnect means (not shown in cross-section 7200) through planar insulator 7203 is similar to contacts 2807 shown in fig. 28C and can be used to connect array lines in first and second memory arrays 7210 and 7220 to corresponding support circuits and interconnects 7201. Support circuits and interconnects 7201 and insulator 7203 form memory array support structure 7205.

Next, method 3220, which is similar to method 2740, is used to fabricate first memory array 7210 using a diode cathode-to-nanotube switch based on a non-volatile nanotube diode array similar to that shown in section 6700 in FIG. 67 and the corresponding fabrication method.

Next, second memory array 7220 is fabricated on the planar surface of first memory array 7210 similar to method 3230 of method 3040 shown in FIG. 30B, but using a diode anode-to-nanotube switch based on a non-volatile nanotube diode array similar to that shown in cross-section 6900 of FIG. 69 and the corresponding fabrication method.

Fig. 72A shows a cross section 7200 that includes a first memory array 7210 and a second memory array 7220, both of which share a common word line 7230. Word lines, e.g., 7230, are defined (etched) during a trench etch, which defines the memory array (cells) when array 7220 is formed. Cross section 7200 shows first and second memory arrays 7210 and 7220 combined in a word line or X direction, having shared word line 7230(WL0), four bit lines BL0, BL1, BL2, and BL3, and corresponding cells C00, C01, C02, and C03. The array has a period of 2F in the X direction, where F is the minimum size of a technology node (generation).

FIG. 72B shows a cross-section 7200 'including a first memory array 7210' and a second memory array 7220 ', both sharing common word lines 7230' and 7232. Word line 7230' is a cross-section of word line 7230. Word lines, such as 7230 'and 7232, are defined (etched) during a trench etch that defines the memory array (cells) when array 7220' is formed. Cross section 7200 'shows first and second memory arrays 7210', 7220 'in combination in the bit line or Y-direction, with shared word lines 7230' (WL0) and 7232(WL1), two bit lines BL0 and BL2, and corresponding cells C00, C10, C02, and C12. The array has a period of 2F in the Y direction, where F is the minimum size of a technology node (generation).

Because of the 2F period in the X and Y directions, the memory array cell area of 1 bit is 4F for array 7210². Because of the 2F period in the X and Y directions, the memory array cell area of 1 bit is 4F for array 7220². Because memory arrays 7220 and 7210 are stacked, the memory array cell area per bit is 2F². If four memory arrays (not shown) are stacked, the memory array cell area per bit is 1F ²。

Exemplary method 3240 completes fabrication of the semiconductor chip using industry standard fabrication techniques by adding additional wiring layers as needed, and passivating the chip and adding package interconnects.

In operation, memory section 7200 shown in FIG. 72A and the corresponding memory section 7200 ' shown in FIG. 72B correspond to the operation of memory section 3305 shown in FIG. 33B and the corresponding memory section 3305 ' shown in FIG. 33B '. Operation of memory section 7200 and corresponding memory section 7200' is the same as described with respect to waveform 3375 shown in FIG. 33D.

FIG. 71 shows a 3D perspective view 7100 of an array having a 2-high stack sharing word lines WL0 and WL 1. Fig. 72A shows a corresponding 2-height section 7200 in the X direction, while fig. 72B shows a corresponding 2-height section 7200' in the Y direction. The cells C00 and C01 in the lower array are formed using cathode-to-NTNV NT diodes, while the cells C02 and C03 in the upper array are formed using anode-to-NTNV NT diodes. Alternative stacked array structures do not share array routing (e.g., word lines) as shown in fig. 73 and 74. A stack array that does not share a word line may use the same NV NT diode type. For example, both the upper and lower arrays of fig. 73 and 74 use NT upper cathode NV NT diodes. However, an NT on anode NV NT diode cell may be used instead. The stack can continue to use a mix of NV NT diode cells with a cathode on NT and an anode on NT, if desired. By not sharing array lines between the upper and lower arrays, greater manufacturing and interconnect flexibility is possible, as described further below with reference to fig. 75, 76A-76D, and 77.

Fig. 73 shows a 3D perspective view 7300 that includes a dual-high stacked three-dimensional array, a lower array 7302 and an upper array 7304, with no shared array lines between upper array 7204 and lower array 7302. The X-oriented word lines WL0 and WL1 and the Y-oriented bit lines BL0 and BL1 interconnect the cells C00, C01, C10, and C11 to form the array interconnect of the lower array 7302. The cells C00, C01, C10, and C11 of the lower array 7302 are formed by NT upper cathode NV NT diodes, however, NT upper anode NV NT diodes may be used instead. Word lines WL2 and WL3 oriented in the X-direction and bit lines BL2 and BL3 oriented in the Y-direction interconnect cells C22, C32C23, and C33 to form an array interconnect of the upper array 7304. The upper array 7304 cells C22, C32, C23, and C33 are formed by NT upper cathode NV NT diodes, however, NT upper anode NV NT diodes may be used instead. The bit lines are substantially parallel, the word lines are substantially parallel, and the bit lines and word lines are substantially perpendicular. Nanotube element channel length L_SW-CHIs vertically oriented as shown in 3D perspective 7300. The cross-section 7400 shown in fig. 74 corresponds to the cells C00, C01, C22, and C23 further shown in fig. 74 as follows.

Fig. 74 shows a cross section 7400 that includes a first memory array 7410 and a second memory array 7420, the first memory array 7410 including cells C00 and C01, bit lines BL0 and BL1, and word line WL0, while the second memory array 7420 includes cells C22 and C23, bit lines BL2 and BL3, and word line WL 2. The lower array 7410 and upper array 7420 are separated by insulator and interconnect regions 7440 and do not share word lines. Cross section 7400 shows first and second memory arrays 7210 and 7220 stacked in the word line or X direction, having word lines WL0 and WL2, four bit lines BL0, BL1, BL2, and BL3, and corresponding cells C00, C01, C22, and C23. The array has a period of 2F in the X direction, where F is the minimum size of a technology node (generation). A cross section in the Y direction corresponding to the X-direction cross section 7400 is not shown. However, the NV NT diode cells are symmetrical in both the X and Y directions, so the NV NT diode cells look identical. Due to the 90 degree rotation, only the bit line and word line orientations change.

Because of the 2F period in the X and Y directions, the memory array cell area for 1 bit is 4F for array 7410². Because of the 2F period in the X and Y directions, the memory array cell area of 1 bit is 4F for array 7420 ². Because the memory arrays 7420 and 7410 are stacked, the memory array cell area per bit is 2F². If four memory arrays (not shown) are stacked, the memory array cell area per bit is 1F²。

Will have vertically oriented diodes andnon-volatilityNanotube blockUsed to form on NT using top and bottom contactsCathode electrodeThree-dimensional cell structure of non-volatile cells of non-volatile NT switch of switchSimplified alternatives

FIG. 75 shows a 3-D perspective view of nonvolatile memory array 7500, which includes four 3-D nonvolatile memory cells C00, C01, C10, and C11, each cell including a 3-D nonvolatile nanotube diode, and cell interconnects formed by bit lines BL0 and BL1 and word lines WL0 and WL 1. Non-volatile memory array 7500 shown in FIG. 75 corresponds to section 4000 shown in FIG. 40, section 6700 shown in FIG. 67, and sections 6875 and 6890 shown in FIG. 68F and FIG. 68I, respectively, as further described above. The 3-D NV NT diode dimensions used to form the cells in sections 6700, 6875, and 6890 are defined in two mask steps. First, a first masking method defines a trench boundary for forming a cell boundary using a directional trench etching method. In some embodiments, cell boundaries are formed in the X-direction, trenches are filled with insulator, and the surface is planarized, as in the fabrication methods described further above with reference to fig. 68A-68I. The second masking method then defines the trenches, and then forms cell boundaries in the Y-direction, fills the trenches with insulator, and planarizes the surface as further described above with reference to the fabrication methods described above with reference to fig. 68A-68I. The cell boundaries are substantially perpendicular in the X and Y directions.

The memory block structures shown in fig. 40, 67, and 68A-68I, having top (upper) and bottom (lower) contacts, are symmetric in the X and Y directions. A3-D memory array formed of NV NT blocks with top (upper) and bottom (lower) contacts enables 3-D symmetric cells that can be used to enable simplified fabrication methods to pattern and simultaneously fabricate memory arrays of 3-D NV NT diodes. The X and Y dimensions can be simultaneously defined and a selective directional etch can be used to simultaneously define the 3-D NV NT diode cell, then fill the opening with insulator and planarize the surface. Thus, for example, the manufacturing method (corresponding to the manufacturing method described in relation to the structure shown in fig. 68D) also forms the structure shown in fig. 68H at the same time. This simplified fabrication method facilitates stacking of the multi-layer array because each layer is fabricated with fewer process steps. In this example, X ═ Y ═ F, where the minimum technology size is for the selected technology node F. For example, for a technology node where F is 45nm, X is 45 nm. The design of the array mask as described further below with respect to 76C shows a plan view of FxF shapes (as depicted), each FxF shape being stepped in the X and Y directions by a distance F. During the process of exposing the mask layer pattern on the chip surface, the fillet typically occurs at the minimum technology node dimension F, and the mask layer pattern approximates a circle of about diameter F, as further illustrated below in the plan view of fig. 76D. The 3-D NV NT diode forming the cells of memory array 7500 will be approximately cylindrical in shape due to the rounding effect, as shown in FIG. 75. The memory array 7500 shown in FIG. 75 uses 3-D NV NT diodes of the type with a cathode on NT. However, a 3-D NV NT diode of the anode-on-NT type, such as shown in FIGS. 69 and 70, may be formed instead.

The method of manufacturing the non-volatile memory array corresponds to the method of manufacturing as further described above with reference to fig. 68A-68I. However, the bit line dimensions are defined prior to the formation of the 3-D NV NT diode cell because the bit line is no longer defined by the etch process step at the same time as defining the cell boundary, and FIG. 68A is modified as shown in FIG. 76A. In addition, the size of the mask 6850 shown in fig. 68C is equal to F only in the X direction. However, the Y direction is then as long as the memory array or the memory sub-arrays used to form the memory array. A simplified fabrication method (further illustrated below with reference to fig. 76C and 76D) shows the mask having the same dimensions in the X and Y directions. In some embodiments, a fabrication method corresponding to the fabrication methods described with reference to fig. 68D, 68E, and 68F may be used to complete the fabrication of the memory array 7500 structure.

The mask needs to be aligned to the predefined bit lines BL0 and BL1 before the 3-D NV NT diode is formed to define the bit lines BL0 and BL 1. Using semiconductor industry processes, alignment can be achieved in the range of about + -F/3. Thus, for example, for the F-45 nm node, the alignment would be within ± 15nm, and the bit lines BL0 and BL1 would thus be in contact with most of the anode region of the 3-D NV NT diode memory cell, as further illustrated below with reference to fig. 76B.

Support circuits and interconnects 7501 (illustrated in non-volatile memory array 7500 shown in FIG. 75) correspond to support circuits and interconnects 6701 (shown in cross-section 6700 in FIG. 67).

The planarizing insulator 7503 (shown in fig. 75) corresponds to the planarizing insulator 6703 (shown in fig. 67). An interconnect arrangement (not shown in cross-section 7500, but shown above with respect to cross-section 2800 "of fig. 28C) through a planar insulator 7503 can be used to connect the metal array lines in the 3-D array to the corresponding support circuitry and interconnects 7501. As an example, bit line drivers in the BL driver and sense circuit 2640 may be connected to bit lines BL0 and BL1 (in the array 2610 of the memory 2600 shown in fig. 26A, and in the non-volatile memory array 7500 shown in fig. 75, described further above).

The bit lines 7510-1(BL0) and 7510-2(BL1) are patterned as further described below with reference to FIG. 76A. Cells C00, C01, C10, and C11 are formed by corresponding 3-D NV NT diodes that include NV NT blocks with top (upper) and bottom (lower) contacts, as further described below with reference to fig. 76A-76D.

Cell C00 includes a corresponding 3-D NV NT diode formed from a steering diode having a cathode-to-NT series connection to the bottom (lower) contact of the NV NT block. Anode 7515-1 makes contact with bit line 7510-1(BL0) and the top (upper) contact 7565-1 of NV NT block 7550-1 makes contact with word line 7570-1(WL 0). The NV NT diode corresponding to cell C00 includes an anode 7515-1 in contact with a bit line 7510-1(BL0) and also in contact with an N polysilicon region 7520-1. N polysilicon region 7520-1 is in contact with N + polysilicon region 7525-1. Anode 7515-1, N polysilicon region 7520-1, and N + polysilicon region 7525-1 form a Schottky-type steering diode. Note that PN or PIN diodes (not shown) may be used instead. N + polysilicon region 7525-1 makes contact with bottom (lower) contact 7530-1, which also forms a bottom (lower) contact for NV NT block 7550-1. NV NT block 7550-1 is also associated with The top (upper) contact 7565-1, which in turn makes contact with the word line 7570-1(WL 0). NV NT block 7550-1 channel length L_SW-CHIs vertically oriented and is approximately equal to the distance between top (upper) contact 7565-1 and bottom (lower) contact 7530-1, which can be defined by the thickness of the NV NT block.

Cell C01 includes a corresponding 3-D NV NT diode formed from a steering diode having a cathode-to-NT series connection to the bottom (lower) contact of the NV NT block. Anode 7515-2 makes contact with bit line 7510-2(BL1) and the top (upper) contact 7565-2 of NV NT block 7550-2 makes contact with word line 7570-1(WL 0). The NV NT diode corresponding to cell C01 includes an anode 7515-2 in contact with a bit line 7510-2(BL1) and also in contact with an N polysilicon region 7520-2. The N polysilicon region 7520-2 is in contact with the N + polysilicon region 7525-2. Anode 7515-2, N poly region 7520-2, and N + poly region 7525-2 form a Schottky-type steering diode. Note that PN or PIN diodes (not shown) may be used instead. N + polysilicon region 7525-2 makes contact with bottom (lower) contact 7530-2, which also forms a bottom (lower) contact for NV NT block 7550-2. NV NT block 7550-2 also makes contact to top (upper) contact 7565-2, which in turn makes contact to word line 7570-1(WL 0). NV NT block 7550-2 channel length L _SW-CHIs vertically oriented and approximately equal to the distance between top (upper) contact 7565-2 and bottom (lower) contact 7530-2, and can be defined by the thickness of the NV NT block.

Cell C10 includes a corresponding 3-D NV NT diode formed from a steering diode having a cathode-to-NT series connection to the bottom (lower) contact of the NV NT block. Anode 7515-3 makes contact with bit line 7510-1(BL0) and the top (upper) contact 7565-3 (not visible, behind word line 7570-1) of NV NT block 7550-3 makes contact with word line 7570-2(WL 1). The NV NT diode corresponding to cell C10 includes an anode 7515-3 in contact with a bit line 7510-1(BL0) and also in contact with an N polysilicon region 7520-3. N polysilicon region 7520-3 is in contact with N + polysilicon region 7525-3. An anode 7515-3, an N polysilicon region 7520-3, and an N + polyThe crystalline silicon region 7525-3 forms a schottky-type steering diode. Note that PN or PIN diodes (not shown) may be used instead. N + polysilicon region 7525-3 makes contact with bottom (lower) contact 7530-3, which also forms a bottom (lower) contact for NV NT block 7550-3. NV NT block 7550-3 also makes contact to top (upper) contact 7565-3, which in turn makes contact to word line 7570-2(WL 1). NV NT block 7550-3 channel length L _SW-CHIs vertically oriented and approximately equal to the distance between top (upper) contact 7565-3 and bottom (lower) contact 7530-3, and can be defined by the thickness of the NV NT block.

Cell C11 includes a corresponding 3-D NV NT diode formed from a steering diode having a cathode-to-NT series connection to the bottom (lower) contact of the NV NT block. Anode 7515-4 makes contact with bit line 7510-2(BL1) and the top (upper) contact 7565-4 (not visible, behind word line 7570-1) of NV NT block 7550-4 makes contact with word line 7570-2(WL 1). The NV NT diode corresponding to cell C11 includes an anode 7515-4 in contact with a bit line 7510-2(BL1) and also in contact with an N polysilicon region 7520-4. The N polysilicon region 7520-4 is in contact with the N + polysilicon region 7525-4. Anode 7515-4, N polysilicon region 7520-4, and N + polysilicon region 7525-4 form a Schottky-type steering diode. Note that PN or PIN diodes (not shown) may be used instead. N + polysilicon region 7525-4 makes contact with bottom (lower) contact 7530-4, which also forms a bottom (lower) contact for NV NT block 7550-4. NV NT block 7550-4 also makes contact to top (upper) contact 7565-4, which in turn makes contact to word line 7570-2(WL 1). NV NT block 7550-4 channel length L _SW-CHIs vertically oriented and approximately equal to the distance between top (upper) contact 7565-4 and bottom (lower) contact 7530-4, and can be defined by the thickness of the NV NT block. The openings 7575 between the cells C00, C01, C10, and C11 of the 3-D NV NT diode based cell are filled with an insulator (not shown), such as TEOS.

The nonvolatile nanotube diode forming the cells C00, C01, C10, and C11 corresponds to the nonvolatile nanotube diode 1200 (shown in fig. 12). The cells C00C01, C10, and C11 of the nonvolatile memory array 7500 shown in fig. 75 correspond to the corresponding cells C00, C01, C10, and C11 (schematically shown in the memory array 2610 in fig. 26A), and the bit lines BL0 and BL1 and the word lines WL0 and WL1 correspond to the array lines schematically shown in the memory array 2610.

Will have vertically oriented diodes andnon-volatile nanotube blockNV NT deviceBy usingActing as top and bottom contacts to form on NTCathode switchThe non-volatile NT switch of (1) manufacturing a three-dimensional cell structure of a non-volatile cellAlternative simplified method

In some embodiments, the method 2710 shown in fig. 27A is used to define support circuits and interconnects, similar to as described further above with respect to the memory 2600 shown in fig. 26A. The exemplary method 2710 applies well-known semiconductor industry technology design and fabrication techniques to fabricate support circuits and interconnects 7601 in and on a semiconductor substrate, as shown in fig. 76A. Support circuits and interconnects 7601 include FET devices in a semiconductor substrate and interconnects, such as vias and wires, on a semiconductor substrate. Fig. 76A corresponds to fig. 34A showing a schottky diode structure, including an optional conductive schottky anode contact layer 3415 (shown in fig. 34A and 76A) as the anode contact layer 7615. Note that fig. 34A 'may be initially used in place of fig. 34A' if a PN diode structure is desired. If the N polysilicon layer 3417 in fig. 34A' is replaced with an inherently doped polysilicon layer (not shown), a PIN diode, rather than a PN diode, may be formed. Thus, while the structure shown in fig. 76A shows a schottky diode structure, the structure may also be fabricated using a PN diode or a PIN diode.

The fabrication methods of elements and structures forming support circuitry and interconnects 7601 and insulator 7603 of memory array support structure 7605 correspond to the fabrication methods as described further above with reference to fig. 34A and 34B, where support circuitry and interconnects 7601 correspond to support circuitry and interconnects 3401; the insulator 7603 corresponds to the insulator 3403. The fabrication methods of the elements and structures that form support circuitry and interconnects 7601 and insulator 7603 for memory array support structure 7605 also correspond to support circuitry and interconnects 6801, and insulator 7603 corresponds to insulator 6803, as shown in fig. 68A, and also corresponds to support circuitry and interconnects 7501 and insulator 7503, respectively, in fig. 75.

At this point in the process, the fabrication method patterns the conductor layer 7610 to form bit lines 7610-1 and 7610-2 and other bit lines separated by isolation regions 7612, as shown in fig. 76A. Bit lines 7610-1 and 7610-2 correspond to bit lines 7510-1(BL0) and 7510-2(BL1), respectively, as shown in FIG. 75. The insulating region 7612 corresponds to the insulating region 7512 shown in fig. 75. In some embodiments, the method forms a masking layer (not shown) using masking methods well known in the semiconductor industry. Next, a process (e.g., directional etching) defines bit lines 7610-1 and 7610-2 using methods well known in the semiconductor industry. The method then deposits and planarizes the insulating regions (e.g., TEOS) using methods well known in the semiconductor industry, forming insulating regions 7612.

Examples of conductor (and contact) materials include elemental metals such as Al, Au, Pt, W, Ta, Cu, Mo, Pd, Ni, Ru, Ti, Cr, Ag, In, Ir, Pb, Sn, and metal alloys such as TiAu, TiCu, TiPd, Pbin, and TiW, other suitable conductors, or conductive nitrides such as TiN, oxides, or silicides such as RuN, RuO, TiN, TaN, CoSi_xAnd TiSi_x。

In some instances, materials such as those used in the conductor layer 7610 may also be used as the anode of the schottky diode, in instances where a separate layer such as the contact (anode) layer 7615 may not be needed. In other examples, a separate contact (anode) layer 7615 may be used to improve diode characteristics. For example, the contact layer 3415 shown in fig. 34A corresponds to the contact (anode) layer 7615 in fig. 76A for forming an anode of a schottky diode.

In some embodiments, the method may deposit a schottky diode anode material to form a contact (anode) layer 7615 having a thickness in a range, for example, 10 to 500nm on the conductor layer 7610 as in fig. 76A. The anode material may comprise Al, Ag, Au, Ca, Co,Cr, Cu, Fe, Ir, Mg, Mo, Na, Ni, Os, Pb, Pd, Pt, Rb, Ru, Ti, W, Ta, Zn and other elemental metals. In addition, silicides, e.g., CoSi, may be used ₂、MoSi₂、Pd₂Si、PtSi、RbSi₂、TiSi₂、WSi₂And ZrSi₂. Schottky diodes formed using such metals and silicides are disclosed in NG, k.k. "compact Guide to Semiconductor Devices", Second Edition, John Wiley&Sons, 2002, pp.31-41, the entire contents of which are incorporated herein by reference.

At this point in the process, the method deposits an N polysilicon layer 7620 on the contact (anode) layer 7615; depositing an N + polysilicon layer 7625 on the N polysilicon layer 7620; and a bottom (lower) contact layer 7630 is deposited over the N + polysilicon layer 7625, as shown in fig. 76A.

The exemplary method of fabricating the N-polysilicon layer 7620 shown in fig. 76A is further described above with respect to the corresponding N-polysilicon layer 6820 (shown in fig. 68A) and the corresponding N-polysilicon layer 3420 (shown in fig. 34A); the N + polysilicon layer 7625 corresponds to the N + polysilicon layer 6825 (shown in fig. 68A) and the N + polysilicon layer 3425 (shown in fig. 34A); the bottom (lower) contact layer 7630 corresponds to the bottom (lower) contact layer 6830 (shown in fig. 68A) and the bottom (lower) contact layer 3430 (shown in fig. 34B).

Next, the method uses multi-layer spin coating, spray coating, or other means to deposit a nanotube layer 7650 on the planar surface of the contact (anode) layer 7630, as shown in fig. 76B. Nanotube layer 7650 can be, for example, in the range of 10-200 nm. Nanotube layer 7650 corresponds to nanotube layer 6835 (shown in figure 68B). An exemplary device having a thickness of 35nm was fabricated and switched between ON/OFF states as shown in fig. 64 and 65. Methods of fabricating NV NT blocks with top and bottom contacts are described with respect to methods 6600A, 6600B, and 6600C (shown in fig. 66A, 66B, and 66C), respectively.

At this point in the manufacturing process, the method deposits a top (upper) contact layer 7665 on the surface of nanotube layer 7650, as shown in fig. 76B. The thickness of the top (upper) contact layer 7665 can be, for exampleSuch as 10 to 500 nm. The top (upper contact) layer 7665 can be formed using: al, Au, Ta, W, Cu, Mo, Pd, Pt, Ni, Ru, Ti, Cr, Ag, In, Ir, Pb, Sn, and metal alloys such as TiAu, TiCu, TiPd, PbIn, and TiW, other suitable conductors, or conductive nitrides such as TiN, oxides, or silicides such as RuN, RuO, TiN, TaN, CoSi_xAnd TiSi_x. Top (upper) contact layer 7665 corresponds to top (upper) contact layer 6840 (shown in fig. 68B).

Next, the process deposits and patterns a mask layer 7672 on top (upper) contact layer 7650 using known industry methods, as shown in fig. 76B. Mask layer 7672 may be in the range of 10 to 500nm thick and formed using a resist, such as photoresist, e-beam resist, or a conductor, semiconductor, or insulator material. Mask layer 7672 is opened to expose underlying regions for trench etch purposes. The mask openings may be aligned to alignment marks in the conductor layer 7610 using known semiconductor methods to align the mask openings to an alignment accuracy AL of + F/3 or better. For technology nodes where F is 45nm, the alignment AL is equal to or better than ± 15nm with respect to the bit line edge, such as the edge of bit line 7610-1 shown in fig. 76B. To achieve a reduced cell size, the mask layer 7672 openings can be arranged to be approximately equal to the minimum allowed technology dimension F. F may be, for example, 90nm, 65nm, 45nm, 35nm, 25nm, 12nm, or sub-10 nm.

Fig. 76C shows a plan view of mask layer 7672 having the shape as depicted on top (upper) contact layer 7665. The shape of each mask map 7672-1, 7672-2, 7672-3, and 7672-4 is about FxF (as depicted), and all shapes are separated from each other by a distance F.

Fig. 76D illustrates the corner rounding effect when the method patterns the mask area on the surface of the top (upper) contact layer 7665 at the technology node minimum dimension F using known semiconductor industry methods. The as-drawn shape 7672-1 becomes a patterned generally circular shape 7672-1R, about F in diameter; the as-drawn shape 7672-2 becomes a patterned generally circular shape 7672-2R, about F in diameter; the as-drawn shape 7672-3 becomes a patterned generally circular shape 7672-3R, about F in diameter; and the as-depicted shape 7672-4 becomes a patterned, generally circular shape 7672-4R, about F in diameter.

At this point in the process, the method selectively orients the exposed areas between etch mask shapes 7672-1R, 7672-2R, 7672-3R, and 7672-4R, starting at the top (upper layer) contact layer 7665, ending at the surface of conductor layer 7610, located on the top surface of the bit lines (e.g., bit lines 7610-1 and 7610-2), thereby forming an opening 7675 (not shown) and simultaneously forming all surfaces (boundaries) of the 3-D NV NT diode (forming cells C00, C01, C10, and C11 in FIG. 75). In some embodiments, the method fills the opening 7675 with an insulator (e.g., TEOS) (not shown) and planarizes the surface. Opening 7675 corresponds to opening 7575 of fig. 75. If a rectangular (e.g., square) cross-section is desired, mask shapes 7672-1, 7672-2, 7672-3, and 7672-4 can be used instead of 7672-1R, 7672-2R, 7672-3R, and 7672-4R.

U.S. patent 5,670,803 to Bertin, which is incorporated herein by reference in its entirety, discloses a 3-D array (3D-SRAM in this example) structure having simultaneous trench-defined sidewall dimensions. The structure includes vertical sidewalls simultaneously defined by trenches cut through the multi-layer doped silicon and insulating regions to avoid multiple alignment steps. This trench-oriented selective etch process can cut through multiple layers of conductor, semiconductor, oxide, and nanotube layers, as described above with respect to the trench formation of, for example, FIGS. 34A-34FF, 36A-36FF, and 68A-68I. In this example, a selective directional trench etch (RIE) removes exposed areas of top (upper) contact layer 7665 to form top (upper) contacts 7565-1, 7565-2, 7565-3, and 7565-4 (shown in FIG. 75); removing exposed areas of nanotube layer 7650 to form NV NT blocks 7550-1, 7550-2, 7550-3, and 7550-4 (shown in FIG. 75); removing the exposed regions of bottom (lower) contact layer 7630 to form bottom (lower) contacts 7530-1, 7530-2, 7530-3, and 7530-4 (shown in FIG. 75); the exposed regions of the N + polysilicon layer 7625 are removed by directional etching to form N + polysilicon regions 7525-1, 7525-2, 7525-3, and 7525-4, as shown in FIG. 75; the exposed regions of polysilicon layer 7620 are removed to form N polysilicon regions 7520-1, 7520-2, 7520-3, and 7520-4, as shown in fig. 75. An exemplary method of selective directional etching stops on the top surface of the conductor layer 7610 and the top surfaces of the bit lines 7610-1 and 7610-2, as shown in fig. 76B and 75.

An exemplary method of selectively directionally etching the exposed regions between mask shapes 7672-1R, 7672-2R, 7672-3R, and 7672-4R, corresponding to the directional etching method for forming the trench regions in fig. 68D, is shown in fig. 76B, except that the etch stops at the surfaces of bit lines BL0 and BL1 because bit lines BL0 and BL1 have been patterned in an earlier step.

Next, the method fills the trench opening 7675 with an insulator such as TEOS and planarizes filling the area 7575 shown in fig. 75 (the fill is not shown). An exemplary method of filling and planarizing the trench opening 7675 corresponds to the method of filling and planarizing the trench openings 6860, 6860A, and 6860B as described with reference to fig. 68E.

Next, the process deposits, planarizes, and patterns (forms) conductors, such as word lines 7570-1(WL0) and 7570-2(WL1) as shown in FIG. 75. The exemplary method of forming word lines 7570-1 and 7570-2 corresponds to the method of forming word lines WL0 and WL1 as further described above with reference to FIG. 68I.

Alternative simplified non-volatile memory using stacked three-dimensional cell structures with non-shared array lines

The simplified three-dimensional non-volatile memory array 7500 makes it possible to stack multiple layers of sub-arrays based on the memory array 7500 to achieve high density bit storage per unit area. Non-volatile memory array 7500 has a cell area of 4F ²And 4F²Bit density per bit. However, 2-high stacks at the same 4F²Two bits are saved in area and up to 2F²Bit density per bit. Likewise, a 4-high stack implements 1F²Bit density per bit, 8-high Stack implementation 0.5F²Density of a/bit, and16-high Stack implementation 0.25F²Density per bit.

Fig. 77 shows a diagram of a stacked non-volatile memory array 7700 based on the non-volatile memory array 7500 shown in fig. 75. Support circuitry and interconnects 7701 of stacked non-volatile memory array 7700 (shown in FIG. 77) correspond to support circuitry and interconnects 7501 (shown in cross-section 7500 in FIG. 75), except that the circuitry is modified to accommodate the stacked array. BL driver and sense circuits 7705, a subset of support circuits and interconnects 7701, are used to interface to bit lines in stacked volatile memory array 7700.

The planarizing insulator 7707 (shown in fig. 77) corresponds to the planarizing insulator 7503 (shown in fig. 75). Interconnection means through planar insulator 7707 (not shown in stacked non-volatile memory array 7700, but further shown in cross-section 2800 "of fig. 28C above) may be used to connect metal array lines (bit lines in this example) in the 3-D array to corresponding BL driver and readout circuitry 7705 and other circuitry (not shown). As an example, bit line drivers in BL driver and sense circuit 2640 may be connected to bit lines BL0 and BL1 (in array 2610 of memory 2600 shown in fig. 26A, and in stacked non-volatile memory array 7700 shown in fig. 77, described further above).

The left and right 3-D sub-arrays of the three stacked layers correspond to non-volatile memory array 7500 in FIG. 75, with the above additional memory stacks (not shown). Memories having 8, 16, 32, and 64 and more non-volatile memory stacks may be formed. In this example, a first stack memory layer is formed, including non-volatile memory array 7710L, which includes mxn NV NT diode cells (interconnected by m word lines WL0_ LA to WLM _ LA and n bit lines BL0_ LA to BLN _ LA), and non-volatile memory array 7710R includes mxn NV NT diode cells (interconnected by m word lines WL0_ RA to WLM _ RA and n bit lines BL0_ RA to BLN _ RA). Next, a second stacked memory layer is formed, including non-volatile memory array 7720L, which includes mxn NV NT diode cells (interconnected by m word lines WL0_ LB to WLM _ LB and n bit lines BL0_ LB to BLN _ LB), and non-volatile memory array 7720R, which includes mxn NV NT diode cells (interconnected by m word lines WL0_ RB to WLM _ RB and n bit lines BL0_ RB to BLN _ RB). Next, a third stacked memory layer is formed, including nonvolatile memory array 7730L, which includes mxn NV NT diode cells (interconnected by m word lines WL0_ LC through WLM _ LC and n bit lines BL0_ LC through BLN _ LC), and nonvolatile memory array 7730R, which includes mxn NV NT diode cells (interconnected by m word lines WL0_ RC through WLM _ RC and n bit lines BL0_ RC through BLN _ RC). Additional stacked non-volatile memory arrays are included (but not shown in figure 77).

The sub-array bit line segments are interconnected by vertical interconnects and then fanned out to BL driver and readout circuitry 7705, as shown in stacked non-volatile memory array 7700 in fig. 77. For example, BL0_ L interconnects bit lines BL0-LA, BL0_ LB, BL0-LC segments, and other bit line segments (not shown), and connects these to BL driver and sense circuitry 7705. In addition, BLN _ L interconnects bit lines BLN-LA, BLN _ LB, BLN-LC segments, and other bit line segments (not shown), and connects these bit line segments to BL driver and sense circuitry 7705. In addition, BL0_ R interconnects bit line BL0-RA, BL0_ RB, BL0-RC segments, and other bit line segments (not shown), and connects these to BL driver and sense circuit 7705. In addition, BLN _ R interconnects bit line BLN-RA, BLN _ RB, BLN-RC sections, as well as other bit line sections (not shown), and connects these bit line sections to BL driver and sense circuit 7705.

BL driver and sense circuitry 7705 can be used to read or write to character locations (on any of the stacked layers in stacked non-volatile memory array 7700 shown in fig. 77). The word lines may also be selected by support circuitry and interconnects 7701 (not shown in this example).

When forming a non-volatile memory array, it may be necessary to anneal the polysilicon layer for about an hour in a temperature range of 700 to 800 ℃ to control the grain boundary size and achieve desired electrical parameters, such as the forward voltage drop and breakdown voltage of the steering diode. For 3-D arrays, this anneal may be performed before or after NV NT block switch formation. When stacking memory arrays to form stacked non-volatile memory array 7700, an anneal at a temperature range of 700 to 800 ℃ for one hour may be required to improve the steering diode electrical properties after NV NT block switch formation, as the diode layers may be disposed over the NV NT block. The bottom (lower) and top (upper) contact materials may need to withstand temperatures up to 800 ℃ without forming carbides (note that nanotubes are subjected to temperatures well in excess of 800 ℃). The selection of the block contact material, such as Pt, may help ensure that carbides do not form because Pt is insoluble in carbon. In addition, carbide formation can also be avoided by selecting high melting point materials, such as Mo, Cr, and Nb. Mo and Nb carbides form at temperatures in excess of 1000 ℃ and Cr carbides form at temperatures in excess of 1200 ℃. Other high-melting point metals may also be used. By selecting a contact metal that does not form carbides or forms carbides at temperatures in excess of 800 ℃, annealing of a stacked non-volatile memory array (where the diode is placed above and/or below the NV NT block and its associated contacts) can be performed without causing contact-to-nanotube degradation. Thus, at least some embodiments of the present invention are resilient to high temperature processes without degradation. Phase diagrams for various metals and carbons can be found in various references.

The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The provided embodiments are, therefore, to be considered in all respects as illustrative and not restrictive. For example, the 3D example as further shown above may be used to form a free standing memory array. Alternatively, the 3D example as further shown above may be used as an embedded memory in a logic chip. Furthermore, the 3D example as further shown above may be stacked on one or more microprocessors on a logic chip, resulting in the address, timing, and data line lengths being mostly vertically oriented and short distances to reduce power boost performance. Furthermore, for example, many of the embodiments described above are described with respect to a minimum technology node F. However, it may be used to fabricate memory elements with the minimum dimensions allowed by the minimum technology node, and embodiments may be fabricated with any dimensions allowed by the minimum technology node (e.g., greater than the minimum feature size).

Incorporated patent reference data

The following commonly owned references, referred to herein as "incorporated patent references," describe various techniques for fabricating nanotube elements (nanotube fabric articles and switches), such as creating and patterning nanotube fabrics, the entire contents of which are incorporated herein by reference:

U.S. patent application No.09/915,093, now U.S. patent No.6,919,592, filed on 25/7/2001, entitled "electromechanical memory array using nanotube ribbon elements and method of making same";

U.S. patent application No.09/915,173, filed on 25/7/2001, now U.S. patent No.6,643,165, entitled "electromechanical memory with cell selection circuit constructed using nanotube technology";

U.S. patent application No.09/915,095, filed on 25/7/2001, now U.S. patent No.6,574,130, entitled "hybrid circuit with nanotube electromechanical memory";

U.S. patent application No.10/033,323, filed 12, month 28, 2001, now U.S. patent No.6,911,682, entitled "electromechanical three trace junction device";

U.S. patent application No.10/033,032, filed 12/28/2001, now U.S. patent No.6,784,028, entitled "method of manufacturing an electromechanical three trace junction device";

U.S. patent application No.10/128,118, filed 4/23/2002, now U.S. patent No.6,706,402, entitled "nanotube films and articles";

U.S. patent application No.10/128,117, filed 4/23/2002, now U.S. patent No.6,835,591, entitled "method of nanotube films and articles";

U.S. patent application No.10/341,005, filed on 13/1/2003, entitled "methods for manufacturing carbon nanotube films, layers, tissues, ribbon-like elements, and articles";

U.S. patent application No.10/341,055, filed on 13/1/2003, entitled "method for fabricating carbon nanotube films, layers, structures, ribbon elements, and articles using thin metal layers";

U.S. patent application No.10/341,054, filed on 13/1/2003, entitled "method for manufacturing carbon nanotube films, layers, tissues, ribbon elements, and articles using pre-formed nanotubes";

U.S. patent application No.10/341,130, entitled "carbon nanotube films, layers, tissues, ribbon-like elements, elements and articles", filed on 13/1/2003;

U.S. patent application No.10/864,186, now U.S. patent No.7,115,901, filed on 9.6.2004, entitled "nonvolatile electromechanical field effect device and circuit and method of forming the same";

U.S. patent application No.10/776,059, now U.S. patent publication No.2004/0181630, filed 2/11/2004, entitled "device with horizontally disposed nanostructured articles and method of making the same";

U.S. patent application No.10/776,572, now U.S. patent No.6,924,538, filed 2/11/2004, entitled "article with vertically disposed nanostructures and method of making the same"; and

U.S. patent application No.10/936,119, filed on 8.9.2004, now U.S. patent publication No.2005/0128788, entitled "patterned nanoscale article and method of making same".

Claims (16)

1. A non-volatile nanotube diode device, comprising:

a first terminal and a second terminal;

a semiconductor element including a cathode and an anode and capable of forming a conductive path between the cathode and the anode in response to an electrical stimulus applied to the first terminal; and

a nanotube switching element comprising a nanotube fabric article in electrical communication with the semiconductor element, the nanotube fabric article being disposed between the semiconductor element and the second terminal and capable of forming an electrically conductive path between the semiconductor element and the second terminal;

wherein electrical stimuli applied to the first and second terminals cause a first logic state and a second logic state;

wherein the nanotube fabric article is comprised of nanotube elements of a non-woven mesh; and is

Wherein the nanotube elements of the non-woven web provide at least one conductive path through the nanotube fabric article.

2. The non-volatile nanotube diode device of claim 1, wherein in the first logic state, a conductive path between the first and second terminals is substantially disabled, and wherein in the second logic state, a conductive path between the first and second terminals is enabled.

3. The non-volatile nanotube diode device of claim 2, wherein the nanotube article has a relatively high resistance in the first logic state and a relatively low resistance in the second logic state.

4. The non-volatile nanotube diode device of claim 3, wherein the nanotube fabric article comprises a non-woven network of misaligned nanotubes.

5. The non-volatile nanotube diode device of claim 4, wherein in the second logic state, the non-woven network of unaligned nanotubes comprises at least one electrically conductive path between the semiconductor element and the second terminal.

6. The non-volatile nanotube diode device of claim 4, wherein the nanotube fabric article comprises a multilayer structure.

7. The non-volatile nanotube diode device of claim 1, wherein the semiconductor element is capable of allowing current to flow from the anode to the cathode above a threshold voltage between the first and second terminals, and wherein the semiconductor element is incapable of allowing current to flow from the anode to the cathode below the threshold voltage between the first and second terminals.

8. The non-volatile nanotube diode device of claim 2, wherein in the first logic state a conductive path between the anode and the second terminal is disabled.

9. The non-volatile nanotube diode device of claim 2, wherein in the second logic state, a conductive path between the anode and the second terminal is enabled.

10. The non-volatile nanotube diode device of claim 2, wherein the nanotube switching element further comprises a conductive contact disposed between the nanotube fabric article and the semiconductor element and providing an electrical communication path between the nanotube fabric article and the semiconductor element.

11. The non-volatile nanotube diode device of claim 10, wherein the first terminal is in electrical communication with the anode and the cathode is in electrical communication with the conductive contact of the nanotube switching element.

12. The nonvolatile nanotube diode device of claim 11, wherein the nonvolatile nanotube diode device is capable of substantially carrying current from the first terminal to the second terminal when in the second logic state.

13. The non-volatile nanotube diode device of claim 10, wherein the first terminal is in electrical communication with the cathode and the anode is in electrical communication with the conductive contact of the nanotube switching element.

14. The non-volatile nanotube diode device of claim 13, wherein the element is capable of substantially driving current to flow from the second terminal to the first terminal when in the second logic state.

15. The non-volatile nanotube diode device of claim 1, wherein the anode comprises a conductive material and the cathode comprises an n-type semiconductor material.

16. The non-volatile nanotube diode device of claim 10, wherein the anode comprises a p-type semiconductor material and the cathode comprises an n-type semiconductor material.