HK1118975B - System and method for channel identification and system for electronic dispersion compensation - Google Patents

Description

Channel identification system and method and system for electronic dispersion compensation

Technical Field

The present invention relates to digital integrated circuits and signal processing, and more particularly, to performing electronic dispersion compensation (dispersion compensation), employing an interleaved architecture, and performing timing recovery using channel identification information.

Background

The radio communication system comprises a transmitter for encoding information to be transmitted into electromagnetic waves; the transmission medium provides a channel for the transmission of electromagnetic waves; and a receiver for receiving and processing the electromagnetic waves carrying the information. Radio communication systems may utilize waveguides (waveguides) as the transmission medium. A waveguide is a structure that guides or confines the propagation of electromagnetic radiation. The waveguide may comprise a material boundary (material boundary) system in the form of a solid dielectric. In radio communication systems, optical fibers are commonly used as waveguides.

It is desirable to increase the bandwidth or transmission rate of a radio communication system for a number of reasons. First, greater bandwidth is needed to support current radio communication devices, such as those used in data centers, or devices for live video and audio, as well as other ultra-wideband devices. Secondly, there is a need to increase the bandwidth of radio communication systems for efficiency and cost reasons. Therefore, it is very important to solve the physical condition limitation of the waveguide for transmitting the high bandwidth electromagnetic signal.

Dispersion is an important physical phenomenon that limits the ability to successfully transmit and recover electromagnetic waves carrying information over a communication channel. The phase velocity of any spectral component in the transmission medium will depend on the refractive index of the physical medium. In general, the refractive index of a transmission medium depends on the frequency. Waveguide dispersion occurs when the wave velocity in a waveguide, such as an optical fiber, depends on its frequency. The transverse modes (transverse modes) of a wave confined by a waveguide typically have different velocities depending on the frequency. A similar phenomenon is modal dispersion (modal dispersion) caused by a waveguide having multiple modes at a given frequency, each mode of the waveguide propagating at a different speed.

Waveguide dispersion causes signal attenuation in radio communication systems because changing the delay in arrival time between different components of the signal significantly reduces the pulse characteristics of the pulses transmitted through the waveguide. This phenomenon is commonly referred to as intersymbol interference (ISI). Adjacent symbols, denoted as pulses, clearly "bleed" into each other, and at a particular sampling instant of a symbol there may be energy that is actually included with the energy associated with the adjacent symbol.

Therefore, error sources, such as chromatic dispersion and associated ISI, introduced in the received signal transmitted over the communication channel must be corrected. Typically, the receiver will be equipped with a signal processing system to correct for the effects of dispersion introduced by the communication channel. These signal processing systems often analyze the statistical properties of the communication channel to remove ISI. Signal processing systems typically utilize one or more equalizers to perform these corrections. One commonly used equalizer is a Feed Forward Equalizer (FFE) that corrects for the pre-cursor ISI, where the current symbol is affected by the next symbol. FFE is typically combined with a Decision Feedback Equalizer (DFE) that corrects post-cursor ISI (where the current symbol is affected by the previous symbol).

Various technical challenges may arise in constructing a signal processing system to correct for dispersion and ISI, and these challenges become especially acute in communication systems that use high baud rates or symbol rates. First, it is desirable to perform signal processing operations in the digital domain because it is generally easier to achieve higher SNR than an equivalent analog system. Secondly, digital systems have the advantage of being less complex in terms of signal layout and design, and offer the opportunity to easily modify the signal processing procedures used.

Digital signal processing systems must convert received analog signals to digital signals. In general, it is difficult and expensive to operate a series of ADCs at baud rates in excess of 1.5-2 GHz. This is problematic because it is often necessary to construct communication systems that operate at least around 10 GHz. Similar problems exist for designing and constructing equalizers that operate at high data rates.

A second technical problem relates to the time-varying nature of the communication channel, which has an impact on the performance of the timing recovery operation of the receiver. The transmitter typically includes a clock for encoding the data signal into a carrier signal for transmission over the channel. The transmitter clock determines the rate at which symbols are transmitted over the communication channel.

The receiver also typically requires a clock, which is preferably phase locked to the transmitter clock, to accurately recover the symbols transmitted by the transmitter over the communication channel. However, the transmitter and receiver clocks typically drift relative to each other, which results in a frequency offset between the two. The phase is a fraction of the frequency and therefore the phase between the transmitter and receiver clocks can be shifted. Therefore, receivers in communication systems typically include timing recovery circuits for synchronizing the transmitter clock with the receiver clock.

Digital communication systems may use a method known as baud rate or symbol rate sampling, in which a received signal is sampled at the baud rate. Sampling at the Nyquist rate (Nyquist rate) is not necessary since the entire analog signal does not have to be recovered in the communication system. However, baud rate sampling significantly constrains the accuracy with which timing recovery operations can be performed in the receiver to effectively stabilize signal samples.

As mentioned above, communication systems require a physical medium to transport communication signals. The characteristics of the physical medium in a communication system often change over time. This time dependency is usually on a relatively long time scale (time scale) compared to the baud rate. Where the communication channel is approximated by its first order activity, the higher order contribution is small, the channel characteristics do not change over time and the initial state is known, the effect of the channel on the transmitted signal can be characterized by an impulse response or Green's function, which describes the response of the channel to an impulse signal. In conventional timing recovery systems utilizing conventional algorithms, the time-varying nature of the channel characteristics is not accounted for, which reduces the ability of the signal processing system to perform accurate baud rate sampling to effectively cancel the effects of undesired ISI.

Disclosure of Invention

According to one general aspect of the present invention, embodiments of the present invention include a system for performing electronic dispersion compensation on an information-bearing signal transmitted over a communication channel. The system includes a channel identification module for receiving a first digitized version of an information-bearing signal and an equalized version of the information-bearing signal and for determining therefrom an impulse response of the communication channel. The system includes a time-varying phase detector for receiving the equalized version of the information-bearing signal, the second digitized version of the information-bearing signal, and the impulse response, and for generating a reference waveform from the impulse response and the equalized version of the information-bearing signal. The time-varying phase detector is operable to generate a phase signal from a reference waveform and an error signal determined from the reference waveform and a second digitized version of the information-bearing signal.

In accordance with another general aspect, the present invention provides a Channel Identification (CID) system for identifying characteristics of a communication channel over which an information-bearing signal is transmitted. The CID system comprises: a filter computation module that computes a plurality of impulse response signals for a communication channel, wherein each of the plurality of impulse response signals is associated with a different phase; an optimal phase calculation module that determines an optimal impulse response signal of a plurality of impulse response signals of a communication channel; a reference waveform generator for generating a reference waveform from the optimal impulse response signal; and a time-varying phase detector for determining an error signal from the reference waveform and the digitized version of the information-bearing signal and for generating a phase signal from the error signal and the reference waveform to control timing recovery of the information-bearing signal.

According to another general aspect, there is provided a method of performing channel identification of a communication channel, comprising calculating a plurality of impulse responses of the communication channel, wherein each of the plurality of impulse response signals is associated with a different phase; determining an optimal impulse response signal of a plurality of impulse response signals of a communication channel; determining an error signal between the reference waveform and a corresponding portion of the information-bearing signal transmitted over the communication channel based on the optimal impulse response signal; and determining a phase signal for controlling the timing recovery circuit based on the reference waveform and the error signal.

According to one aspect of the present invention, there is provided a Channel Identification (CID) system for identifying characteristics of a communication channel over which an information-bearing signal is transmitted, the channel identification system comprising:

a filter computation module that computes a plurality of impulse response signals for the communication channel, wherein each of the plurality of impulse response signals is associated with a different phase;

an optimal phase calculation module that determines an optimal impulse response signal of a plurality of impulse response signals of the communication channel;

a reference waveform generator for generating a reference waveform from the optimal impulse response signal; and

a time-varying phase detector for determining an error signal from the reference waveform and the digitized version of the information-bearing signal and for generating a phase signal from the error signal and the reference waveform to control timing recovery of the information-bearing signal.

Preferably, the channel identification system receives as inputs: an information bearing signal, at least one decision signal representative of a characteristic of the information bearing signal, and a phase information signal.

Preferably, each impulse response signal is characterized by a plurality of coefficients.

Preferably, the filter computation module computes coefficients of a current impulse response signal, the coefficients being a function of an error signal between the information-bearing signal and the decision signal.

Preferably, the current impulse response coefficient is calculated according to the following relation:

preferably, the phase signal comprises a dc offset parameter.

Preferably, the dc offset parameter controls the timing recovery circuit using a Mueller Muller timing recovery procedure.

Preferably, the phase information signal is used to set a current phase for estimating one of the plurality of impulse response signals.

Preferably, the system further comprises an analog-to-digital converter.

Preferably, the analog-to-digital converter operates at a sampling rate below a critical sampling rate of data transmitted over the channel.

Preferably, the optimal impulse response is determined by calculating a metric for each impulse response and selecting an impulse response that minimizes and maximizes the metric.

Preferably, the time-varying phase detector determines the phase signal from the error signal and a slope of the reference waveform.

According to one aspect of the present invention, there is provided a method of performing channel identification of a communication channel, comprising:

calculating a plurality of impulse responses of the communication channel, wherein each of the plurality of impulse response signals is associated with a different phase;

determining an optimal impulse response signal of a plurality of impulse response signals of the communication channel;

determining a reference waveform according to the optimal impulse response signal;

determining an error signal between the reference waveform and a corresponding portion of an information-bearing signal transmitted over the communication channel; and

a phase signal for controlling a timing recovery circuit is determined from the reference waveform and the error signal.

Preferably, the method further comprises receiving as inputs: an information-bearing signal transmitted over the communication channel, at least one decision signal representative of a characteristic of the information-bearing signal, and a phase information signal.

Preferably, the method further comprises calculating coefficients of the current impulse response signal, the coefficients being a function of an error signal between the information-bearing signal and the decision signal filtered by the previous impulse response signal.

Preferably, the coefficients of the current impulse response signal are calculated using the following relation:

preferably, the output signal includes a dc offset parameter, wherein the dc offset parameter controls the timing recovery circuit using a Mueller Muller timing recovery procedure.

According to one aspect of the invention, there is provided a system for performing electronic dispersion compensation on an information-bearing signal transmitted over a communication channel, the system comprising:

a channel identification module for receiving a first digitized version of an information-bearing signal and an equalized version of the information-bearing signal and determining therefrom an impulse response of the communication channel;

a time-varying phase detector for receiving the equalized version of the information-bearing signal, the second digitized version of the information-bearing signal, and the impulse response, and generating a reference waveform from the impulse response and the equalized version of the information-bearing signal;

wherein the time-varying phase detector generates a phase signal from the reference waveform and an error signal determined from the reference waveform and a second digitized version of the information-bearing signal.

Preferably, said first digitised form is sampled at a rate lower than the baud rate of the information bearing signal and said second digitised form is sampled at said baud rate.

Preferably, the time-varying phase detector determines the phase signal from the slip error signal and a slope of the reference waveform.

The details of one or more embodiments are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims.

Drawings

The invention will be further described with reference to the accompanying drawings and examples, in which:

fig. 1 is a block diagram of a radio communication system;

FIGS. 2a-2c are timing diagrams illustrating the effects of dispersion on an electromagnetic signal transmitted through a communication channel;

FIG. 3a is a block diagram of a signal processing system for correcting signal distortion in a signal received by a receiver of a communication system;

FIG. 3b is a detailed schematic diagram of a signal processing system;

FIG. 4 is a schematic illustration of a signal flow through a signal processing system for correcting signal distortion introduced by a communication channel;

FIG. 5a is a schematic diagram of the operation of an interleaved ADC according to one embodiment;

FIG. 5b is a more detailed schematic diagram of an ADC architecture according to one embodiment;

FIG. 5c is an overall operational schematic of an interleaved ADC according to one embodiment;

FIG. 6a is a schematic diagram of the signal path of an interleaved FFE;

fig. 6b is a schematic diagram of a serial DFE unit according to one embodiment;

FIG. 7a is a schematic diagram of the operation of a channel identification filter update module according to one embodiment;

FIG. 7b is an operational diagram of a channel identification module determining channel characterization information to assist in timing recovery operations, according to one embodiment;

FIG. 7c is a schematic diagram of the operation of the optimal phase calculation module according to one embodiment;

FIG. 8 is a schematic diagram of the operation of a baud rate phase detector;

FIG. 9 is a workflow diagram of a signal processing system according to one embodiment;

FIG. 10 is a flowchart of the work performed by a signal processing system according to one embodiment;

FIG. 11 is a flowchart of the operation of a start-up state machine of an embodiment.

Detailed Description

Fig. 1 is a block diagram of a radio communication system. Communication system 100 includes any number of stations in which information may be exchanged via any number of communication channels 182. Fig. 1 shows two stations 102(1), 102(2), one of which includes a transmitter 108 and serves as a transmitting station and the other of which includes a receiver 116 and serves as a receiving station. This is merely exemplary, and it is understood that the communication system may include any number of stations 102, each of which may provide separate transmit capabilities, separate receive capabilities, or a combination of transmit and receive capabilities.

The stations 102(1), 102(2) within the radio communication system 100 may be, for example, data centers. Alternatively, each site 102 may be a special structure within a data center, such as a data archive system or mass storage device (e.g., a disk storage array), server, or other head-end system. In data center applications, it is important to access and transfer large amounts of data at high data rates.

Each transmitting station 102(1) includes a data source 104, and the data source 104 may be any system for archiving or generating data to be transmitted to the receiving station 102 (2). The information transmitted between transmitting station 102(1) and receiving station 102(2) may include any type of data, such as multimedia information, including audio and video information, text information, and may be stored in any suitable format. The data source 104 may archive data for transmission from the transmitting station 102(1) to the receiving station 102 (2). Alternatively, the data source 104 may provide real-time or near real-time data for transmission. For example, the data source 104 may be a multimedia device, such as a video camera or microphone, that generates video and audio signals, respectively. Alternatively, the data source 104 may be an archived multimedia file, such as an MPEG file. The data source 104 may include any combination of analog and digital information. The data source 104 may include data stored in any format, including raw data or compressed data.

The transmitting station 102(1) may transmit information from the data source 101 to the receiving station 102(2) over a communication channel 182 using electromagnetic signals. The electromagnetic signals transmitted over the communication channel 182 may utilize optical wavelengths or other wavelengths as necessary to achieve the desired symbol rate. Thus, communication channel 182 may be, for example, a fiber optic cable or other physical medium suitable for transmitting optical wavelength electromagnetic signals. According to one embodiment, the communication channel 182 may be a multi-mode fiber optic cable through which a bit rate of 10 gigabits per second (gbps) may be achieved between the transmitting station 102(1) and the receiving station 102 (2). In a more specific exemplary embodiment, the bit rate is 10.3125 gbps.

The transmitting station 102 may also include a transmitter 108. The transmitter 108 further includes a Transmitter Optical Sub Assembly (TOSA) 106, the TOSA106 providing an interface to an optical physical layer (e.g., an optical communication channel). The TOSA106 may include a laser (not shown). In particular, the TOSA106 may modulate an electromagnetic carrier signal generated by the laser using information provided by the data source 104 and provide the modulated signal to the communication channel 182. Since the transmitting station 102(1) and the receiving station 102(2) may exchange digital information, the TOSA106 may perform digital modulation of the optical carrier signal. Thus, the TOSA106 may provide a number of electromagnetic signals for transmission over the communication channel 180 that correspond to the data provided by the data source 104.

In the case of digital communication between the transmitting station 102(1) and the receiving station 102(2), the data source 107 may provide a plurality of numbers representing information to be transmitted between the transmitting station 102(1) and the receiving station 102 (2). These numbers can be represented as a bit stream (0 or 1) in binary or radix-2. For each bit to be transmitted, transmitter 108 may generate a first pulsed electromagnetic signal to represent a digital 1 and a second pulsed electromagnetic signal to represent a digital 0.

The transmitter 108 may also be equipped with a transmit clock 110, the transmit clock 110 controlling the symbol rate at which the transmitter 108 transmits information over the communication channel 182. According to one embodiment, transmit clock 110 may operate at 10 Gbps.

The receiving station 102(2) includes a network device 112 connected to a communication channel 182, which provides a system for receiving and processing signals transmitted by the transmitting station 102(1) over the communication channel 182. In particular, the network device 112 may include a receiver 116, the receiver 116 including various functional modules for receiving and processing signals transmitted by the transmitting station 102(1) over the communication channel 182.

Receiver 116 may include a Receiver Optical Sub Assembly (ROSA). The ROSA includes a photodiode (not shown) that converts an optical signal to an electrical signal. In particular, a photodiode can convert an optical signal into a current. A transimpedance amplifier (not shown) in the ROSA may further convert the current into a voltage, which may be further processed. The receiver 116 may include a receiver clock 142, the receiver clock 142 designed to operate at the same frequency as the transmitter clock 110. However, typically the receiver clock 142 will not be perfectly synchronized with the transmitter clock 110 (i.e., there will be a drift or phase offset), which must be corrected by the receiver. To correct for drift between the transmitter clock 110 and the receiver clock 142, the receiver 116 is provided with a timing recovery module 134.

The receiver 116 may also include a Variable Gain Amplifier (VGA), an analog-to-digital converter (ADC)120, an equalizer module 132, a channel identification module 124, a timing recovery module 134, a state machine 126, and a microcontroller 138. The overall operation of receiver 116 is controlled by microcontroller 138, and microcontroller 138 may coordinate the interaction between the various functional modules on receiver 116. The state machine 126 controls the start-up and convergence actions of the receiver. Other embodiments of the EDC system 410, including the operation of the above-mentioned components, will be described in detail in subsequent sections.

Fig. 2a-2c illustrate the dispersion effect of electromagnetic signals transmitted through a communication channel on a physical medium, such as a multimode fiber optic cable. Fig. 2a shows an idealized pulse train comprising a plurality of pulses 206(1) -206 (6). Each pulse is ordered into a characteristic frequency and phaseThe bit(s) (phi (f,) ) of the transmitter clock signal 202. As shown in fig. 2a, each pulse corresponds to either a +1 or a-1, depending on whether the pulse is positive or negative. Thus, pulses 206(1), 206(3), and 206(5) correspond to a +1, while pulses 206(2), 206(4), and 206(6) correspond to a-1. The +1/-1 pulses can be converted to 0 or 1 at the receiver, respectively.

In the ideal case shown in fig. 2a, a receiver clock (not shown in fig. 2a-2 c) that completely follows the transmitter clock signal 202 in frequency and phase may be implemented in the receiver. Furthermore, in such an ideal situation, the burst 210 generated at the transmitter may be transmitted to the receiver without any signal distortion or fading. The receiver may use the receiver clock signal 208 to time samples of the signal received from the transmitter. In particular, the receiver may perform baud rate sampling on the received signal to recover the bits encoded at the transmitter.

These ideal conditions are not practically achievable. Fig. 2b shows some non-idealities that may occur during transmission of electromagnetic signals between a transmitter and a receiver. In particular, FIG. 2b shows a frequency and phase characteristicOf the receiver clock signal 208. The receiver clock signal 208 may be phase offset and frequency offset relative to the transmitter clock signal 210. This frequency and associated phase offset occurs due to drift between the two clocks.

A second condition limiting the operation of digital communication systems is associated with imperfections in the transmission medium itself, including dispersion effects and associated intersymbol interference. Figure 2b also shows the pulse characteristics of a plurality of pulses transmitted by a receiver over a communication channel such as a fibre optic cable. In particular, the received pulses 204(1) -204(6) correspond to the transmitted pulses 206(1) -206(6), respectively. Each transmitted pulse 206(1) -206(6) suffers from chromatic dispersion due to the characteristics of the communication channel. In particular, the refractive index of the communication channel is frequency dependent, which results in different frequency components of each pulse propagating at different velocities. In the case where the communication channel 182 is a multimode fiber, the transmitted pulses may be subject to dispersion. As shown in fig. 2b, the received pulses 204(1) -204(6) are spread or smeared in the temporal direction.

Fig. 2c shows the linearly superimposed composite signal of pulses 204(1) -204 (6). Such a composite signal may represent the actual communication signal received by the receiver. The characteristic transmission signal of the transmitted burst 210 is received by the receiver. Due to this linear superposition, each individual pulse signal (e.g., 206(1) -206(6)) is distorted. This phenomenon is commonly referred to as intersymbol interference (ISI). In order to recover the transmitted signal and/or perform efficient baud rate sampling, the ISI introduced by the communication channel must be significantly reduced.

Fig. 3a is a block diagram of a signal processing system for correcting signal distortions, such as waveguide dispersion and associated ISI, in a signal received by a receiver of a communication system. The pulse signal 206 is generated at the transmitter 108, and the transmitter 108 encodes data at a baud rate that is a function of the transmitter clock 110 that generates the transmitter clock signal 202. The pulse signal is provided to the communication channel by the TOSA106 at the transmitter 108. The communication channel may be implemented using a multimode fiber optic cable.

The transmitter 108 may generate an information-bearing signal 396, the information-bearing signal 396 including a plurality of pulses synchronized with a transmitter clock 110, the transmitter clock 110 generating a transmitter clock signal 202. The transmitter clock signal 202 may define a bit rate or symbol rate that defines the number of different signal variations provided to the communication channel 182 per second. The transmitter clock may encode data at any baud rate. For example, according to one embodiment, the baud rate is 10 Gbps.

The TOSA at the transmitter 108 may cause the transmission of an information-bearing signal 396 over the communication channel 182, which communication channel 182 may be a multimode fiber optic cable communication channel. Due to the channel characteristics of the communication channel 182, the information-bearing signal 396 may undergo various transformations and/or distortions. These distortions and transformations can result in signal 304 received at ROSA107 being significantly different from information-bearing signal 396 generated at transmitter 108. These distortions include ISI and dispersion. The channel is characterized by an impulse response of the communication channel 182. These distortions can result in difficulty in recovering the information originally encoded in the information-bearing signal 396.

The received signal 304 may be provided to the signal processing system 140 to compensate for signal distortion introduced by the communication channel 182. In particular, the signal processing system 140 may perform signal conditioning on the received signal to correct for signal distortion introduced by the communication channel 182. In general, the signal processing system 140 may perform analog and digital domain processing on the received signal 304. To perform digital processing, signal processing system 140 may perform analog-to-digital conversion on signals derived from received signal 304.

Since the information bearing signal 396 may encode data at a high baud rate, the signal processing system 140 may include one or more interleaved structures that individually operate at a clock rate lower than the baud rate. This facilitates the processing to be performed in the digital domain. Thus, as shown in fig. 3a, the signal processing system 140 may include an interleaved ADC module 118 and an interleaved equalizer module 132. As will be described in more detail below, the interleaved ADC module 118 may include a plurality of ADCs, each operating at a clock rate lower than the baud rate. Similarly, the interleaved equalizer module 132 includes a plurality of equalizer structures, each operating at a clock rate lower than the baud rate. The interleaved ADC module 118 and the interleaved equalizer module 132 may run at the same clock rate or different clock rates relative to each other.

The interleaved ADC block 118 may utilize baud rate sampling such that the combined operation of the plurality of ADCs comprising the interleaved ADC block 118 effectively samples the received signal 396 at the baud rate. The receiver may include a receiver clock 142 that generates a receiver clock signal 208. Ideally, the receiver clock 142 may be precisely locked in frequency with the transmitter clock 110 to allow precise sampling of the received signal 396 at the baud rate. In practice, however, the receiver module 142 will typically drift in frequency relative to the transmitter module 110, which results in a phase offset between the transmitter module 110 and the receiver module 142. To compensate for this frequency drift, the signal processing system 140 may include a baud rate phase detector 198. Baud rate phase detector 198 may operate to recover timing information associated with received signal 396. This timing information may be used to force the conditions at each sampling instant (at which time interleaved ADC samples received signal 396) to correspond to valid, stable symbol conditions when encoded at transmitter 108. The timing recovery operation performed by the baud rate phase detector 198 facilitates the use of baud rate sampling by the interleaved ADC module 118 and helps to ensure that the samples obtained at that baud rate correspond to valid symbols. According to one embodiment, baud rate phase detector 198 may utilize an algorithm derived from the Mueller-Muller algorithm. The interleaved ADC module 118 may utilize the receiver clock signal 208 to trigger the sampling operation.

As described above, the baud-rate phase detector 198 may perform various Mueller-Muller algorithms to perform timing recovery operations. To perform such an algorithm, the baud rate phase detector may assume that the communication channel 182 has a particular channel characteristic, which may be represented as an impulse response of the communication channel 182. However, due to the varying physical conditions, the channel characteristics of the communication channel 182 actually change over time. Typically, the time-varying rate of the channel characteristics is significantly slower than the baud rate. For example, in a multimode fiber, the channel characteristics may be time-varying due to physical movement or vibration of the fiber (which is rare relative to the baud rate).

To account for the time-varying nature of the channel characteristics, the signal processing system 140 may include a time-varying phase detector (TVPD) 196. The TVPD196 may periodically determine a channel characteristic of the time-varying communication channel 182. The channel characteristic may be an estimated impulse response of the communication channel 182. As described below, the TVPD196 or associated circuitry within the CID module 102 may calculate an estimated impulse response of the communication channel 182 for each of a plurality of sampling phases. These multiple sampling phases may be used to provide an estimate of the impulse response that is oversampled compared to the baud rate. The best phase of the multiple phases may be periodically calculated by TVPD196 or associated circuitry within CID module 102 using a metric (metric). The timing information data 372 may then be calculated by the TVPD196 or associated circuitry within the CID module 102 and provided to a Phase Locked Loop (PLL) (not shown in fig. 3 a) for controlling the sampling operation of the interleaved ADC module 118.

Referring to fig. 3a, a received signal 304, after being received by the ROSA107 at the receiver 116, is provided to a data path 712 including a splitter 134, an analog processing block, an interleaved ADC block 18, an interleaved equalizer block 132, and a Multiplexer (MUX) 150. The splitter 134 splits the received signal into parallel analog signals 348 comprising a plurality of analog signals. The parallel analog signals 348 are then provided to an analog processing module 398. Analog processing module 398 performs various signal conditioning on parallel analog signals 348 to generate processed analog signals 384. The nature of the signal conditioning performed by the analog processing module 398 will be described in detail below. Typically, however, signal conditioning includes gain adjustment or analog filtering. The analog processing module 398 then generates a processed analog signal 384, which may be provided to the interleaved ADC module 118. The interleaved ADC module 118 may effectively perform analog-to-digital conversion on the processed analog signal 384 at the baud rate. As will be described in greater detail below, the interleaved ADC module 118 may include a plurality of ADCs, each operating at a clock rate that is lower than the baud rate, such that the combined operation of the plurality of ADCs samples the processed analog signal 384 at the baud rate.

The interleaved ADC module 118 may output a digital signal 386, and the digital signal 386 is then provided to the interleaved equalizer module 132. As will be described in greater detail below, the digital signal 386 provided by the interleaved ADC module 118 to the interleaved equalizer module 132 may include a plurality of digital signals, each corresponding to a separate ADC on the interleaved ADC module 118. Interleaved equalizer module 132 may perform a digital equalization process on digital signal 386. As will be described below, the equalization performed by the interleaved equalizer module 132 may correct for dispersion and ISI introduced by the communication channel 182. Interleaved equalizer module 132 may include a Feed Forward Equalizer (FFE), a Decision Feedback Equalizer (DFE), a sequential DFE, and various combinations thereof, as will be described.

Interleaved equalizer module 132 may generate decision signal 388 that is provided to Multiplexer (MUX) 150. The MUX150 may generate a multiplexed output as shown.

The decision signal 388 may also be provided to the TVPD 196. The processed analog signal 384 is provided to the auxiliary ADC394, and the auxiliary ADC394 may sample the processed analog signal 384 to generate the digital signal 374 for processing by the TVPD196 along with the decision signal 388. The auxiliary ADC394 may operate at a sampling rate that is significantly lower than the baud rate. According to one embodiment, the auxiliary ADC may operate at 10 MHz.

As described below, the CID module 102 may calculate an estimated impulse response of the communication channel 182 for each of a plurality of sampling phases and periodically calculate the best phase of the plurality of phases using a metric. The TVPD196 may therefore use the calculated optimal phase information to determine a regeneration or reference waveform, such that timing recovery may be performed (e.g., by the PLL804 shown in fig. 7 b) based on an error calculation performed between the regeneration or reference waveform and the actual output 386 of the interleaved ADC module 118.

Fig. 3b is a detailed schematic diagram of the signal processing system 140. As shown in fig. 1, the signal processing system 140 may include a microcontroller 138 for coordinating the operation and internal operation of various components including the signal processing system 140. For example, the microcontroller 138 may trigger various functional modules on the signal processing system 140 at different points in time.

To handle high data rates, the signal processing system 140 may utilize one or more interleaving components. The interleaved architecture allows certain components to operate at a clock rate that is lower than the symbol rate. For example, to the extent that the signal processing system performs a portion of the signal processing in the digital domain, the signal processing system 140 may include an interleaved analog-to-digital converter (ADC) module 118. According to one embodiment, the signal processing system 140 may utilize baud rate sampling, wherein the received signal is sampled at the symbol rate. Thus, for example, if the symbol rate is 10Gbps, signal processing system 140 may utilize interleaved ADC module 118 to achieve the desired baud rate sampling of 10Gbps, where interleaved ADC module 118 may use a parallel array of ADCs (not shown in FIG. 3), each operating at a sampling rate of 1.25 Gbps. The bandwidth of each ADC in the parallel array of ADCs may be set to approximately 5 GHz.

In addition, signal processing system 140 may include an interleaved equalizer module 132 to correct various signal distortions, including chromatic dispersion and ISI. Both the interleaved equalizer module 132 and the interleaved ADC118 utilize the same or different number of parallel substructures. For example, according to one embodiment, interleaved ADC118 includes eight parallel ADCs, each operating at a sampling rate of approximately 1.25 GHz. The interleaved equalizer module 132 may comprise a parallel array of 16 equalizer segments (slices) each operating at a clock rate of approximately 625 MHz. In general, interleaved ADC module 118 and interleaved equalizer module 132 may each utilize any number of parallel substructures and operate individually at any suitable clock rate. Further, the above values are for exemplary purposes only and adjustments may be made as necessary, for example, if the actual data rate deviates from 10Gbps (e.g., 10.3125Gbps or some other desired value).

The signal processing system 140 may also include a timing recovery module 105 to perform symbol synchronization or timing recovery. The receiver clock (not shown in fig. 3) may continuously adjust its frequency and phase to optimize the sampling instants of the received signal 304 and compensate for frequency drift between the transmitter clock and the oscillator used in the receiver clock circuit (not shown in fig. 3). The timing recovery module 105 may provide timing information to the interleaved ADC module to ensure that the interleaved ADC module 118 performs its sampling operations accurately. In practice, for example, if the signal processing system 1410 performs baud rate sampling, the timing recovery module 105 causes the interleaved ADC module 118 to perform sampling at the symbol rate.

More specifically, the timing recovery module 105 may output timing information to the splitter 134 to cause the splitter 134 to split the inbound signal from the coarse PGA130 into multiple signals separated from each other by a suitable distance (e.g., 100ps apart). In addition, the timing recovery module 105 may output to the interleaved ADC module via a plurality of interpolators, so that the interleaved ADC may sample the baud in very fine steps (e.g., 1.5ps, 10ps baud intervals, 64 phase interpolators). Additional details regarding an exemplary embodiment of the timing recovery module 105 are provided below with reference to fig. 5 a.

The timing recovery module 105 may include a coarse timing recovery module 142 and a fine timing recovery module 144. The purpose of these two structures will be described in detail below. In general, however, the coarse timing recovery module 142 may control the optimal sampling rate of the channel, while the fine timing recovery module 144 may correct timing mismatches caused by the presence of multiple ADCs within the interleaved ADC module 118 and/or due to the presence and operation of the splitter 134 in splitting the received amplified signal from the coarse PGA130 into multiple signals corresponding to the multiple interleaved ADCs.

The signal processing system 140 may include a channel identification (channel ID) module 102. as shown, the channel identification module 102 may output to the TVPD of fig. 3 a. The structure and function of the channel ID module 102 will be described in detail below. In general, however, the channel ID module 102 may determine real-time representations of the communication channel characteristics at different times. The channel characteristics may include, for example, an impulse response of the communication channel. As shown in fig. 3b, the channel ID module 102 may provide information to the timing recovery module 105 to enable timing recovery operations that allow for more efficient and accurate. In particular, as shown in fig. 3b, the channel ID module 102 may provide a parameter 312, referred to herein as a DC offset, to the timing recovery module 105.

Channel ID module 102 may be provided with a channel ID ADC104 (similar to or related to ADC394 in fig. 3 a) to sample the input signal provided to channel ID 102. Since the role of channel ID102 is to determine channel characteristics that change at a rate significantly lower than the symbol rate, channel ID ADC104 operates at a different sampling rate than the ADC including interleaved ADC 11. According to one embodiment, the channel ID ADC104 may operate at a sampling rate of 10 MHz.

As will be described in greater detail below, channel ID102 may establish a representation of the channel characteristics at any number of different stages. A representation of each phase may be stored in the channel ID module 102 and an optimal phase may be determined periodically. According to one embodiment, the best representation of the channel is selected to be the one that maximizes the signal energy after resolving chromatic dispersion and ISI.

The data path of the signal processing system 140 will now be described. The received analog signal 304 is first received by the coarse Programmable Gain Amplifier (PGA) block 130. The PGA may be a variable gain amplifier. The coarse PGA block 130 may amplify the received signal 304 to achieve a desired uniform amplitude level of the received signal 304. A digital control circuit (not shown in fig. 3) may receive one or more values for controlling the overall gain of coarse PGA circuit 130. The PGA circuit 130 may utilize any combination of passive and active circuit elements to achieve gain correction.

Next, the received signal 304, which has been processed by the PGA block 130, may be provided to the splitter 134, and the splitter 134 generates an appropriate number of copies of the signal received from the PGA block 130. The splitter 134 may be used to prepare the necessary number of inputs for the interleaved ADC module 118. For example, according to one embodiment, the interleaved ADC module 118 includes eight parallel ADCs. In this case, the splitter generates eight copies from the signal received from the PGA block 130. The set of signals generated by splitter 134 do not have uniform amplitudes due to component mismatches in the splitter 134 circuitry. To correct for this discrepancy, each signal generated by the splitter 134 is passed to the fine PGA block 114. The fine PGA block 114 may include a plurality of fine PGA (not shown in fig. 3) each providing separate amplitude amplification for each signal generated by the splitter 134.

The set of parallel signals is then passed to the interleaved ADC module 118. In particular, each fine PGA including fine PGA block 114 passes a respective signal to a respective ADC in interleaved ADC block 118. The interleaved ADC module 118 may perform baud rate sampling using the set of received signals from the fine-tuning PGA 114. The structure and function of the interleaved ADC module 118 will be described in detail below. Typically, the ADC module 118 may comprise a plurality of ADCs, each operating at a sampling rate significantly lower than the overall symbol rate of the radio communication system. For example, according to one embodiment, the symbol rate of the channel may be 10Gbps, and the interleaved ADC118 includes 8 parallel ADCs, each operating at a sampling rate of 1.25 Gbps.

As mentioned above and described in more detail below, the CID module 102 may use the decision signal 310 and the output of the CID ADC104 to determine information related to optimal phase information for the communication channel. Next, for example, the TVPD196 in the coarse timing recovery module 142 provides a regenerated or reference waveform based on the optimal phase information, and the coarse timing recovery module 142 compares the reference waveform to the actual output of the interleaved ADC module 118 to determine error information therebetween, and then controls the sampling of the amplified received signal at the splitter 134 and at the interleaved ADC118, e.g., by outputting a phase signal for use by a phase locked loop (in a conventional manner), to assist in performing timing recovery.

Fig. 4 is a schematic diagram of a signal flow through a signal processing system for correcting signal distortion introduced by a communication channel. The received signal 304 is provided to a coarse Programmable Gain Amplifier (PGA) 130. The coarse PGA130 provides overall gain adjustment for the received signal 304. The output of the coarse PGA130 is then provided to a splitter circuit 134. The splitter circuit 134 may generate multiple copies of the gain-adjusted signal, each copy being provided to the fine PGA block 114, respectively. In particular, the outputs of the splitter module 134 are provided to the parallel fine tuning PGA circuits 116(1) - (116 (N), respectively. Each of the parallel fine PGA circuits 116(1) -116(N) may perform a separate gain adjustment on the received signal 304 under the control of a digital control circuit, such as the fine PGA controller 134. The parallel fine tuning PGA circuits 116(1) -116(N) implement gain adjustments necessary to correct for inconsistent signal levels in the interleaved structure including the signal processing system 140.

Each of the parallel fine-tuning PGA circuits 116(1) -116(N) may provide an output to a respective ADC120(1) -120(N) including an interleaved ADC 118. Each ADC120(1) -120(N) may convert the analog signal provided by the corresponding fine PGA circuit 116(1) -116(N) to a digital signal. The structure and function of interleaved ADC118 will be described in detail below. In general, however, each ADC120(1) -120(N) may sample the input signal from the fine PGA block 14 at a clock rate lower than the baud rate. Thus, the effective sampling rate of the combined ADCs 120(1) -120(N) is the baud rate. This may be accomplished by introducing a phase offset to each ADC120(1) -120(N) relative to each other, as described below. For example, according to one embodiment, the baud rate is 10Gbps, while the interleaved ADC block 118 includes 8 ADCs, each operating at a sampling rate of 1.25Gbps, which results in an effective sampling rate of 10 Gbps. Each ADC120(1) -120(N) may also operate at a particular bit resolution. According to one embodiment, each ADC120(1) -120(N) provides 6-bit resolution.

The output of interleaved ADC module 118 may be provided to interleaved equalizer module 132, where interleaved equalizer module 132 includes interleaved FFE424, interleaved parallel decision feedback equalizers 428(1), 428(2), and sequential DFE module 142. Interleaved FFE module 424 may perform signal processing operations to correct for pre-cursor ISI. Interleaved FFE module 424 may include a plurality of FFE cells 124(1) -124 (M). The number of FFE cells (M) corresponds to or differs from the number of parallel ADCs 120(1) -120 (N). Thus, each interleaved FFE cell 124(1) -124(M) may operate at a different clock rate than the clock rate of each ADC120(1) -120 (N). Buffering circuitry (not shown in fig. 4) may enable coordination between the N output streams of interleaved ADC modules 118(120(1) -120(N)) and the M inputs provided to interleaved FFE modules 424(124(1) -124 (M)). According to one embodiment, interleaved FFE module 424 comprises 16 FFE cells 124(1) -124(M), each operating at a clock rate of 625 MHz. The structure and function of each FFE cell 124(1) -124(M) will be described in detail below.

The interleaved PDFE blocks 428(1) and 428(2) are operable to correct for pre-cursor ISI. Each PDFE block 428(1) and 428(2) may include a plurality of summing blocks, each summing block summing the output signals of the respective interleaved FFE units 124(1) -124(M) and the PDFE units 128(1) -128(M) and 132(1) -132(M), respectively.

The output of each summing block may be provided to a respective slicer (slicer)142(1) -142(M), 144(1) -144(M) in a sequential DFE block 144. Each slicer (slicer)142(1) -142(M), 144(1) -144(M) may receive an input signal from each PDFE unit 128(1) -128(M) and 132(1) -132(M), compare the input signal to a threshold, and output a decision signal(k) Indicating whether the signal value is below or above the threshold. According to one embodiment, each decision signal(k) May be a signal of one bit representing a +1 or-1 value. Each decision signal(k) May be routed back to each PDEF unit 128(1) -128(M), 132(1) -132 (M). Each PDFE cell 128

(1) 128(M), 132(1) -132(M) may receive decision signals from respective slicers 142(1) -142(M), 144(1) -144(M)(k) And outputs values to the summing modules. According to one embodiment, the output value of each PDFE cell 128(1) -128(M), 132(1) -132(M) may be a 16-bit value.

Decision logic 480 in the sequence DFE block 142 may select a currently active PDFE from among the PDFEs 428(1) and 428(2) as the valid and correct data to provide. More specifically, for example, when the output of FFE424 falls within an indeterminate range, interleaved PDFEs 428(1) and 428(2) are forced to different values (e.g., 1 and-1), the decision logic module may aggregate the error measurements for each PDFE428(1) and 428(2) over a number of next (e.g., subsequent) bit periods, and then select the PDFE with the lower error over the number of bit periods.

Any number of the plurality of decision signals from each slicer of a currently active PDFE (e.g., 142(1) -142(M) or 144(1) -144(M)) may be routed to the CID module 102 and/or the timing recovery module 105. As described with reference to fig. 3b, the CID module 102 may provide optimal phase information for TVPD functions, and the timing recovery module 105 may also provide baud rate phase monitor functions.

The CID module may include CID ADC104, and CID ADC104 may sample received signal 304 (after being processed by coarse PGA 130). CID since channel characteristics change at a rate lower than the baud rate

The ADC104 operates at a clock rate that is much lower than the baud rate. According to one embodiment, for example, CID ADC104 may operate at 10 MHz. Since the CID module 102 operates at a rate significantly lower than the baud rate, according to one embodiment, there is only a subset of decision signals(k) Is routed to the CID module 102 and the timing recovery module 105. This may be accomplished using a multiplexer or buffer 497, which selects one or more decision signals(k) And routed to the CID module 102 and/or the timing recovery module 105.

CID module 102 may also include CID filter update module 106, CID filter 701, update circuitry 729, cache 474, and CID best phase calculation module 108. The CID filter update module 106 may receive a decision signal from the currently active PDFE(k) Based on this information and the sampled received signal 304, the CD filter 701 may update the current channel characteristics of the channel, which are parameterized as phase, as will be described in detail below with reference to fig. 7a and 7 b. Generally, as described above, CThe ID module 102 may calculate the channel characteristics for multiple phases. According to one embodiment, the CID module calculates the channel characteristics for 16 different phases. The timing recovery module 105 may send a CID phase update signal 112 to the CID ADC104 to control the sampling phase of the multiple channel characteristic phase calculation operations. According to one embodiment, CID phase update signal 112 may be updated periodically to cause the CID module to begin generating channel characteristics for the new phase.

The channel characteristics for each phase may be cached in the CID module 102 using the cache 474. CID optimal phase calculation module 108 may periodically calculate the optimal phase of a plurality of different channel characteristics that have been stored in cache and provide this channel characteristic to update circuitry 729 (described in more detail below with reference to fig. 7 c), so update circuitry 729 provides optimal phase information associated with the channel characteristic to TVPD module 196. The TVPD module 196 may perform TVPD operations using the channel characteristics provided by the CID optimal phase calculation module 108. The TVPD module 196 may also receive the plurality of decision signals 310 and generate a reference waveform (e.g., using the reference waveform generator 703 of fig. 7 b) based thereon (and the optimal phase information/channel characteristics), which is compared to the output of the interleaved ADC118 to obtain error information therebetween for determining a phase signal for controlling a PLL (e.g., the PLL804 of fig. 7 b).

The fine timing recovery module 138 may receive the outputs of the interleaved ADCs 120(1) -120 (N). Due to processing variations, the multiple ADCs 120(1) -120(N) and circuitry associated with driving the ADCs and/or the splitter 134 may experience clock differences. Based on the inputs provided by the interleaved ADCs 120(1) -120(N), the fine timing recovery may provide a plurality of output signals to correct for the time variations of the ADCs 120(1) -120 (N).

Finally, in fig. 4, a signal-to-noise ratio (SNR) monitor 498 is shown that represents any suitable technique for detecting a performance level or characteristic of EDC system 140. For example, EDC system 140 may be required to maintain a certain level of bit error rate or other performance characteristic to remain in a steady-state mode of operation, and if a certain error threshold is exceeded, EDC system 140 may return to a startup state to recalibrate various settings of the EDC system, as described in more detail herein (e.g., with reference to startup state machine 126 and with reference to fig. 11).

Although fig. 4 illustrates certain functional operations associated with a particular architecture, this is by way of example only, and those skilled in the art will appreciate that the organization and performance of certain operations and functions may be practiced with any combination of the architectures in fig. 4. For example, although fig. 4 shows a TVPD in relation to the timing recovery module 105, the TVPD operation or a portion thereof may actually be implemented in the CID module 102.

Fig. 5a is a schematic diagram of the operation of an interleaved ADC according to an embodiment. As described with reference to fig. 3a, 3b and 4, interleaved ADCs may be provided in data path 172 for correcting waveguide dispersion and ISI. The data path may include coarse PGA130, splitter 134, fine PGA114, interleaved ADC118, DEMUX 512, and other such components.

Interleaved ADC118 may be used to achieve a sample rate comparable to the baud rate or symbol rate of received signal 304. For example, according to one embodiment, the baud rate of received signal 304 may be 10 Gbps. As described with reference to fig. 4, the interleaved ADC118 may include a plurality of ADCs 120(1) -120 (n). Each ADC120(1) -120(n) may be driven by a common sampling clock signal that may be adjusted by the timing recovery module 105 to correct for clock drift between the receiver and transmitter clocks such that the ADCs 120(1) -120(n) have their own sampling clock.

In particular, the timing recovery module 105 may generate a phase signal p (n), which is provided to the PLL804 as described with reference to fig. 7a-7 c. The PLL804 may generate an output signal to control the sampling phase of the plurality of ADCs 120(1) -120 (n). According to one embodiment, PLL804 controls a single clock phase, which may operate at 2.5GHz according to one embodiment. The single clock may be replicated by a plurality of phase interpolators 514(1) -514 (n). Each phase interpolator may generate an interpolated version of the single clock signal and may control a particular ADC120(1) -120(n), respectively. In addition, as shown, each phase interpolator 514(1) -514(n) may control a corresponding circuit (e.g., a sample-handling circuit, as shown in fig. 5) in splitter 134. Between each phase interpolator 514(1) - (514 (n)), a corresponding drive circuit 530(1) - (530 (n) may be used to drive or operate the separator 134. For example, the driver circuitry may include buffering, amplification, or timing circuitry (e.g., a clock) used by splitter 134 and/or ADC 118. Furthermore, since the splitter 134 includes digital circuitry, the drive circuitry will include an analog-to-digital converter. Furthermore, there may be relatively long signal paths on-chip between the interpolator and splitter 134/ADC 118. Thus, these mentioned factors, or others, may result in non-ideal operation of the splitter 134 and, thus, of the interleaved ADC 118. The fine timing recovery module 144 in the timing recovery module 105 may be used to individually adjust each of the phase interpolators 514(1) -514(n) to account for the time-varying problems associated with these imperfections so that the interleaved ADC118 may operate as a single ADC at the baud rate for a particular purpose. For example, a first phase interpolator/ADC pair may be selected as a reference, and the remaining phase interpolator/ADC pairs are adjusted relative to this reference pair. Thus, a first phase interpolator/ADC pair 514(1)/120(1) may operate on the basis of p (N), each phase interpolator/ADC pair, except for the reference pair, operating on the basis of the corresponding difference between p (N) and the phase required to maintain the relative timing of each pair, or delta (i.e., [ p Δ (N) ] (2) - [ p Δ (N) ] (N)).

Fig. 5b is a more detailed schematic diagram of an ADC architecture according to one embodiment. In fig. 5b, the splitter 134 includes a plurality of sample-and-hold circuits 522(1) -522(N) that individually drive the PGAs 116(1) -116(N), as shown. Circuit 532 provides an example of a gain circuit in which a variable impedance is used to vary the overall gain of PGA116 (N). Also, circuit 534 provides an example of an ADC circuit using a flash ADC. Circuits 532 and 534 are merely exemplary and other suitable circuits may be used. As shown in fig. 5b, sample-and-hold circuits 522(1) -522(N) are designed to receive a 1.25GHz clock signal (e.g., the sample-and-hold circuits may receive 2 non-superimposed clock signals) to sample the input signal at 100ps intervals. As described above, the fine timing recovery module 144 adjusts the timing information provided to the phase interpolator of fig. 5a such that a 100ps interval is maintained regardless of whether there are relative imperfections in the respective drive circuits 530(1) - (530 (N) (e.g., due to temperature, process, or other mismatches in their design and manufacturing processes).

Fig. 5c is an overall operation diagram of an interleaved ADC according to an embodiment. As described above, the interleaved ADC118 may include a plurality of ADCs 120(1) -120 (n). Each ADC120(1) -120(n) may be triggered by the receiver clock 208 over a particular period. The efficiency of the receiver clock 208 is the baud rate of the transmitted signal. However, the clock rate of a particular ADC120(1) -120(n) may be significantly lower than the baud rate.

Fig. 6a is a schematic diagram of the signal path of an interleaved FFE. According to one embodiment, interleaved FFE utilizes a parallel structure to receive 16 input signals X (n) -X (n +15) and generate 16 output signals Y (n) -Y (n + 15). This is merely exemplary, and an interleaved ADC may include any number of input signals and any number of output signals. For example, a serial FFE with 8 taps (taps) can be implemented as a convolution of the input signal with the FIR.

According to one embodiment, interleaved FFE118 generates 16 outputs y (n) -y (n +15) that are a function of the 16 inputs x (n) -x (n +15), with the following relationship:

y(n)＝c(0)x(n)+c(1)x(n-2)+c(2)x(n-2)+c3x(n-3)+...+c(7)x(n-7)

y(n+1)＝c(0)x(n+1)+c(1)x(n)+c2x(n-1)+c3x(n-2)+...+c(6)x(n-6)

y(n+15)＝c(0)x(n+15)+c(1)x(n+14)+c2x(n+13)+c3x(n+12)+...+c(7)x(n+8)

referring to fig. 6a, interleaved FFE424 may receive a plurality of inputs x (n) -x (n +15) on a plurality of individual input lines 615(1) -615 (16). FFE424 may generate a plurality of outputs y (n) -y (n +15) on a plurality of output lines 617(1) -617 (16). Each input line 615(1) -615(16) may include a plurality of Multiply and Accumulate (MAC) modules 623(1) -623 (n). Each MAC module 623(1) -623(n) may include a respective multiplication module 533 and summation module 534. Each MAC module 623(1) -623(n) is connected to a respective input line 615(1) -615(16) through its multiplication module 533, the multiplication module 533 providing an input port for the MAC module. Each MAC module 623 may be connected to different output lines 617(1) -617(16) via respective summing modules 534, the summing modules 534 serving as output ports for the MAC modules 623.

The inputs (x (n) -x (n +15)) of a particular input line 615(1) -615(16) may be provided to a plurality of MAC modules connected to the input line by their multiplication modules 533, where the inputs are each multiplied by a coefficient CX and then provided to the respective summation modules 534 of the MAC modules 623. The output of each summation module 534 is combined with the output of the other MAC module 623, which is connected to a different input line.

Fig. 6b is a schematic diagram of a serial DFE unit according to one embodiment. The arrangement shown in fig. 6 represents one channel in a parallel array of interleaved PDEFs 428(1), 428 (2). The input signal x (n) is provided to a summing module 542 where the input signal x (n) is summed and combined with the output of the PDFE unit 128. The output of the summing block 542 is then provided to the slicer 142. The limiter 142 generates a binary signal (e.g., +1, -1) depending on whether the input to it is less than or greater than zero. The output of slicer 142 is provided to a plurality of delay units, e.g., 548(1) -548(4), which generate respective delay signals y (n) -y (n-4). The delayed output signals y (n) -y (n-4) are provided to the PDFE unit 128, and the PDFE unit 128 generates output signals F (y (n), y (n-1), y (n-2), y (n-3), y (n-4)). The output signals F (y (n), y (n-1), y (n-2), y (n-3), y (n-4)) may be a linear combination of the delayed signals y (n) -y (n-4). According to one embodiment, each binary signal y (n) -y (n-4) may be multiplied by a 16-bit coefficient to generate a 16-bit value. These 16-bit values are then linearly combined by the PDFE unit 128.

Fig. 7a is a partial operation diagram of the CID filter update module 106 according to one embodiment. More detailed examples of timing recovery and channel identification operations are given below with reference to fig. 7b and 7 c. In fig. 7a, the CID filter update module 106 may be included within the TVPD196 or the CID102 to update the estimated channel characteristics of the communication channel 182. As described above, the channel characteristic may be an impulse response of the communication channel 182. The CID filter update module 106 may calculate a plurality of channel characteristics for a plurality of different sampling phases of the communication channel 182. Thus, for example, where the channel characteristic is an impulse response, CID filter update module 106 may calculate a plurality of estimated channel impulse responses parameterized by a phase parameter (p) and an iteration parameter (n) as. As described below, the CID optimal phase calculation module 108 may calculate an optimal phase channel characteristic based on the plurality of channel characteristics, which is used to provide a timing recovery assistance signal to the timing recovery module 105 to assist timing recovery (not shown in fig. 7). The CID filter update module 106 may update the given phase by calculating the error signal e (n)The next iteration of estimating the channel impulse response. By taking the sampled received signal 304 and the decision signal processed by CID filter 701The difference between these, an error signal e (n) can be calculated. For example, CID filter update module 106 may update each phaseIs provided to CID filter 701 with coefficient "hThereby generating a waveform that is compared to the delayed output of CID ADC104, as shown, and then determining e (n).

Referring again to fig. 7a, the received signal 304 is provided to the data path 172 (described above with reference to fig. 3a, 3b, and 4). After processing via data path 172, a decision signal may be generated. As described above with reference to fig. 4, the data path 172 may generate (render) a plurality of decision signals, wherein only a subset of the decision signals are selected for routing through the multiplexer or router to the CID module 102. This is highly likely because the CID module can operate at a clock rate lower than the baud rate. Decision signal 310 is then provided to CID filter update module 106 at CID module 102.

As shown in fig. 7a, the received signal 304 is also provided to the CID ADC104, and the CID ADC104 performs analog-to-digital conversion on the received signal. CID ADC104 may operate at a clock rate sufficient to track the time-varying characteristics of the channel characteristics. According to one embodiment, for example, CID ADC104 may operate at 10 MHz. The timing recovery module 105 may provide the CID phase update signal 112 to the CID ADC104 to control the sampling phase of the CID ADC 104. The timing recovery module 105 may periodically update the CID phase update signal 112. According to one embodiment, the CID module 102 may calculate 16 different phasesThe estimated channel impulse response.

After sampling by CID ADC104, the sampled version of the received signal is provided to delay block 502. The delay module is necessary to compensate for the delay of the signal 304 received over the data path 172. The delayed version of the sampled version of received signal 304 is then provided to summing block 702, and summing block 702 calculates the difference between the sampled and delayed received signal 304 and the output of CID filter 701 to generate error signal e (n). The error signal e (n) is provided to the CID filter update module 106 to process the next iteration of estimating the channel impulse response.

According to one embodiment, the CID filter update module 106 may utilize the decision signalError signal e (n), estimated channel impulse responseAnd the parameter mu to calculate a next iteration of estimating the channel impulse response. According to one embodiment, CID filter update module 106 may calculate the next iteration of the estimated channel impulse response using the following relationship:

fig. 7b is a diagram illustrating operation of a CID module to determine channel characteristic information to assist in timing recovery operations, according to one embodiment. In general, the best estimate of the impulse response h_opt(n) and decision signal may be used by reference waveform generator 703 to regenerate an estimate of received signal y (n) for use as a timing recovery aid signalTiming recovery assistance signal312 may be provided to assist in timing recovery operations. In particularThe coarse timing recovery module 142 in the timing recovery module 105 may receive the timing recovery assistance signal312 and performs a timing recovery operation using the timing recovery auxiliary signal 312 in the Mueller-Muller algorithm, which may generate a phase signal p (n) to drive the PLL804 to control the sampling phase of the interleaved ADC 118.

Although fig. 7b depicts specific functional modules performing certain functions and/or operations, those skilled in the art will appreciate that this is merely exemplary. Utilizing channel characteristics (e.g., estimated impulse response of a communication channel) to assist and/or perform timing recovery operations of a communication system may also be performed by a single functional unit or multiple functional units. Furthermore, the operations attributed to TVPD196 may also be performed by CID module 102 instead of timing recovery module 105. As another example, CID filter 701 may be performed by the same or similar modules as reference waveform generator 703.

According to an example embodiment, CID module 102 may include CID ADC104, delay module 502, summing module 702, CID filter update module 106, cache 474, and update circuitry 729. Received signal 304 is provided to data path 172, data path 172 including analog front end 739, interleaved ADC118, FFE424, DFE428, and sequence DFE142 in a signal processing system. Analog front end 739 may perform analog processing on received signal 304, including amplitude adjustment of the received signal. The output of analog front end 739 may be provided to CID ADC104 in CID 102. CID ADC104 may perform analog-to-digital conversion on the output of analog front end 739. CID ADC104 can operate at data rates significantly lower than the baud rate.

The output of analog front end 739 may also be provided to interleaved ADC118, interleaved ADC118 being followed by interleaved FFE424, interleaved DFE428, and sequential DFE 142. The sequential DFE142 may output a decision signal 310 that is provided to the CID filter update module 106 in the CID102 and to the reference waveform generator 703. The operation of the CID filter update module 106 has been described with reference to fig. 7 a. That is, after CID ADC104 completes the analog-to-digital conversion, the output of CID ADC104 is provided to delay block 502. The output of delay block 502 is provided to a summation block 702 where a difference signal (e (n)) is calculated using the output of CID filter update block 106, and then returned to CID filter update block 106 for provision to CID filter 701.

CID102 may also include cache 474. The updated estimated channel impulse response calculated by the CID filter update module 106 is provided and stored in the cache 474. As will be described in more detail below, the cached estimated channel response may be parameterized as a phase parameter (p) that is periodically analyzed by an optimal phase calculation module 108, which optimal phase calculation module 108 calculates the best estimated channel impulse response (i.e., the best phase) using a predetermined metric.

Best estimate channel impulse responseMay be provided to an update circuit 729 (described in detail below with reference to fig. 7 c) and, in turn, to a reference waveform generator in the TVPD196, as shown. The TVPD196 can thus utilize the best estimated channel impulse response h_opt(n) to perform a TVPD operation to generate a timing recovery assistance signal312, timing recovery assistance signal312 may be used to assist in timing recovery operations. In particular, the TVPD196 may also receive a decision signal 310 and use the decision signal 310 to utilize the currently estimated optimal impulse response h_opt(n) to generate a reconstructed or regenerated version of the received signal y (n). Regenerated form of received signal y (n)) Which may be used as a timing recovery assistance signal, is provided to the timing recovery module 105 for timing recovery operations. According to one embodiment, the timing recovery assistance signal is based on312 is the current best estimate impulse response h_opt(n) convolution with decision signal 310: (the assignment of the following equation isRather than h (n)

Upon receiving the timing recovery assistance signal 310, the timing recovery module 105 may perform a timing recovery operation using the Mueller-Muller algorithm. In particular, the timing recovery operation 105 may calculate a regeneration waveform) And multiplying the slope by the actual data and regenerated waveform received by the data ADC y (n)The error between. To perform this operation, the timing recovery module may include a plurality of delay units to arrange the actual data signal and the reproduced signal. Referring to fig. 7b, the timing recovery module 105 may include a coarse timing recovery module 142. Coarse timing recovery module 142 generates phase signals p (n) to control the overall sampling phase of the various ADCs, including interleaved ADC118 (described in detail below).

The coarse timing recovery module may include a delay module 502, a summation module 711, a first delay unit 715, a second delay unit 717, and a multiplication module 719. A plurality including interleaved ADC118At least one output of the ADC is provided to a delay block 502 in the coarse timing recovery block 140, which is coupled to the reconstructed signalAnd (4) combining. The output of the delay block 502 is provided to a summation block 711 where it is summed with a timing recovery assistance signal312 are combined to generate a difference signal e' (n). The difference signal e' (n) can be calculated by:

the difference signal e' (n) is provided to a delay unit 715, and the delay unit 715 generates a sampled delayed version e (n-1) of the error signal, which is provided to a multiplication module 719. Timing recovery assistance signal312 may also be provided to a second delay unit 717, the second delay unit 717 generating the timing recovery assistance signalAnd a twice-sampled delayed timing recovery auxiliary signal312 delayed version. The outputs of the first and second delay units 715 and 717 are provided to a multiplication module 719, and the multiplication module 719 multiplies the two signals to generate as an output a phase signal p (n). Thus, the phase signal p (n) is the product of the error signal e' (n) and the slope of the (regenerated) waveform:

in other words, as can be appreciated from the above explanation,represents the convolution of the impulse response of the calculated DFE (or sequential DFE) decisions, so the expected value y (n) of the impulse response is assumed to be valid. Thus, the error signal e' (n) is multiplied by the reproduction waveformIs shown as) And according to the Mueller-Muller algorithm, a phase signal p (n) is obtained. The phase signal p (n) is provided to PLL804 for controlling the sampling phase of the interleaved ADC comprising interleaved ADC module 118.

Fig. 7c is a schematic diagram of the operation of the optimal phase calculation module according to one embodiment. An optimal phase calculation module 108, which may be included in CID module 102, may determine an optimal estimated impulse channel characteristic of the plurality of channel characteristics parameterized as phase312. As described above, the CID filter update module 106 may store a plurality of estimated impulse responses h in the cache 474⁰[0:I]-hⁱ[0:I]Each of which is parameterized to a different phase from 0-i. According to one embodiment, each estimated impulse response h stored in the cache⁰[0:I]-hⁱ[0:I]Are associated with a plurality of taps (tap), for example i may be 6.

CID optimum phase calculation modeBlock 108 may respond from multiple pulses h⁰[0:I]-hⁱ[0:I]In which the optimum impulse response is determined periodicallyWherein each estimated impulse response h⁰[0:I]-hⁱ[0:I]Are associated with each phase and stored in cache 474. The CID best phase calculation module 108 may attempt to minimize or maximize a particular metric to determine. That is, the CID optimal phase calculation module 108 periodically applies the metric scale to the plurality of impulse response signals h stored in the cache 474⁰[0:I]-hⁱ[0:I]. For example, the CID may include a timer 798. According to the operation of the timer 798, a signal is sent to the CID optimal phase calculation module 108 to calculate the optimal phase according to h⁰[0:I]-hⁱ[0:I]Determining. Once determinedThe timer is reset and the process is reinitialized. According to one embodiment, the CID optimal phase calculation module 108 minimizes ISI energy with respect to the estimated channel impulse response signal of the main tap (main tap) using a metric. For example, according to one embodiment, the metric that is maximized is: (where the first term h (3) is for the main tap and the other terms are ISI terms):

[h^p(3)]²-[h^p(2)]²-[h^p(1)]²-[h^p(0)]²-[h^p(4)]²-[h^p(5)]²

once determined using the minimum ISI energy scale described above312，May be provided to the TVPD196 for timing recovery assistance in conjunction with the timing recovery module 105Do (i.e., generate the phase signal p (n)). However, according to one embodiment, the method will be describedH is updated by the update circuit 729 before being provided to the TVPD196_opt(n) performing treatment. This is required because the tracking error does not update the phase of the TVPD196 too quickly. Update circuit 729 causes h provided to TVPD196 to be slowly updated_opt(n), wherein the provided update parameter is denoted herein as h_opt(n)。

The update circuit 729 may include a cache 752, a ramp circuit 754, a multiplexer 756, and a multiplication module 758.May be provided to cache 752, providing a plurality of CID best phase calculation modules 108Cache 752 stores the plurality. The threshold circuit 756 may determine the current optimum phase at each clock instantAnd h stored in cache 752_opt(n) difference between (n). In particular, only atThe update circuit is operative to update the cache when the change in (c) exceeds a programmable threshold. The error may be divided by a larger value, and the divided value may be slowly updated as provided to the TVPD196

Fig. 8 describes the operation of the baud rate phase detector. The signal path shown in fig. 8 may be in operation before CID102 determines the estimated channel impulse response (i.e., when signal processing system 140 is in a startup mode). As shown in fig. 8, the timing recovery module 105 may include a coarse timing recovery module 142 and a fine timing recovery module 138. The coarse timing recovery module 142 may include a baud rate phase detector 198. The baud rate phase detector, in turn, includes a delay module 802, a first multiplication module 804, a second multiplication module 806, a delay unit 810, and a summation module 808.

Received signal 304 may be provided to data path 172, data path 172 including analog front end 739, interleaved ADC118, interleaved FFE424, interleaved DFE428, and sequential DFE 142. Received signal 304 may be provided to analog front end 739, which analog front end 739 may perform analog signal processing on the received signal. The processed output from analog front end 739 is provided to interleaved ADC118, and ADC118 may perform analog-to-digital conversion on the processed analog signal. The output of interleaved ADC118 is provided to interleaved FFE 424. The output of interleaved FFE424 is provided to interleaved DFE 428. The output of interleaved DFE428 is provided to sequential DFE 142. Sequential DFE142 generates decision signals310. Decision signal310 may also be provided to the channel ID module 102, and the channel ID module 102 may generate a timing recovery auxiliary signal 312, referred to herein as a dc _ offset signal (i.e., the auxiliary signal 312 in the startup mode, including at least the dc _ offset value).

At least one digital output of interleaved ADC118 is provided to a delay block 802 in baud rate phase detector 198. Decision signal generated by sequential DFE140310 are provided to a first multiplication block 804 and a delay unit 810 in the baud rate phase detector 198. The output of the delay block 802 is also provided to a first multiplying unit 804, where it is multiplied by a decision signal310. The delay unit 810 may generate a decision signal310 and provided for a second multiplicationBlock 806, decision signal delayed in the second multiplying block 806310 is multiplied by the output of the delay block 802. The output of the second multiplication module is then provided to the summation module 806 where it is combined with the timing recovery assistance signal 312(dc _ offset) provided by the channel ID module 102.

Summation module 808 may combine the output of first multiplication module 804 with the output of second multiplication module 806 to generate phase signal p (n) using the following relationship, where a & B are scalar constants, which relationship may be referred to herein as a dc phase detector relationship:

fig. 9 is a flow diagram of the operation of a signal processing system according to one embodiment. The process begins at step 902. An electromagnetic signal is received at step 909. The electromagnetic signal may be received by a receiver over a communication channel 182. In step 904, the sampling phase of the interleaved ADC is updated. As described herein, the interleaved ADC may be controlled by a timing recovery operation performed by the baud rate phase detector, the TVPD, or a combination of both. As previously described, the phase detector (TVPD or baud rate) may generate a phase signal p (n) that is provided to the PLL to control the sampling clock of the interleaved ADC. Although fig. 9 shows this step to occur sequentially, the update of the ADC sampling phase 904 may be performed in parallel with the other steps described in fig. 9.

In step 906, analog signal processing is performed on the received signal. According to one embodiment, the analog signal processing may include variable gain amplification or other processing. In step 907, analog to digital conversion is performed on the processed analog signal. According to one embodiment, the analog-to-digital conversion may be performed in an interleaved manner using interleaved ADCs. In step 908, digital equalization is performed on the output of the ADC. According to one embodiment, the equalization process may be performed in an interleaved manner using an interleaved equalizer module. According to one embodiment, the interleaved equalizer may include an interleaved FFE, an interleaved DFE, and a sequential DFE. In step 910, the interleaved signals provided by the interleaved structures (ADC and equalizer) are combined to generate a composite signal. The process ends at step 912.

Fig. 10 is a flowchart of the work performed by the signal processing system according to one embodiment. The process shown in fig. 10 may be performed in a steady state operation of the signal processing system (i.e., after the start-up operation is completed). Thus, assume that h _ opt (n) has determined that the system has stabilized (i.e., the filter has converged). The flow begins in step 1002. In step 1007, a timer is initialized. In step 1004, a test is performed to determine if the timer is running. If not ("no" branch of step 1004), in step 1010, a filter update is performed. The filter update may be a procedure that estimates the impulse response of the communication channel.

In step 1012, received signal 304 is provided to a data path and CID module of signal processing system 140. In step 1014, the data path may process the EM signal to generate decision signal 310. In step 1016, a regenerated signal is generated using the decision signal 310To determine the best pulse of the communication channelImpulse response h _ opt (n). According to one embodiment, the regeneration signal may be generated by a TVPD. In step 1018, the regenerated signal may be usedA timing recovery operation is performed. According to one embodiment, the timing recovery operation may use a morphing algorithm of the Mueller-Muller algorithm. Flow then continues to step 1004.

If the timer has been running ("yes" branch of step 1004), the best phase calculation operation is performed in step 1006. The optimal phase calculation operation may determine the best estimated impulse response of the communication channel using a predetermined metric. In step 1011, the best estimated impulse response is provided to the TVPD. Flow then continues to step 1012.

FIG. 11 is a flowchart of the operation of a startup state machine of an embodiment, such as the startup state machine of FIG. 1. In general, FIG. 11 depicts the initiation, execution, or other management of the states of EDC system 140 in FIG. 1. Also, FIG. 11 is used to describe the boot state machine 126 of FIG. 1, but is not an exhaustive or comprehensive description. For example, conventional functions or techniques of the startup state machine that may be performed by the startup state machine 126 are not described in detail herein. For example, a plurality of registers or timers (not explicitly shown or described in fig. 11) may be used for storing and controlling the various states of EDC system 140. In addition, the startup state machine 126 may perform some or all of the functions described with reference to FIGS. 1-10, or equivalent functions, although not all of these functions are fully described in FIG. 11.

In fig. 11, state machine 126 is typically enabled to find the best settings for the blocks, including ADC120, equalizer 132, coarse and fine PGA132/134, CID102, and timing recovery block 105. In this way, startup state machine 126 may implement many known settings from which to select the most appropriate value to achieve the desired performance of EDC system 140. Once the desired performance level is reached, the startup state machine 126 is then responsible for monitoring that performance level, and when such performance level must be maintained and restored, the startup state machine 126 is responsible for recalibration and restart.

Thus, in fig. 11, in an initial state, PLL804 may be converged using a default initial value (e.g., 1) of the dc _ offset value from baud rate phase detector 198 (step 1102). Next, the coarse PGA130 is stabilized (step 1104), for example, to a preset value within the range of available gains. A LOSs of signal (LOS) module (not shown) may be activated (step 1106) to detect LOSs or lack of signal (e.g., by monitoring the condition of the ADC signal relative to a reference threshold).

Next, dc _ off is selected (step 1108), and is performed for three available phase detectors (step 1110). For example, referring to fig. 8, certain initial values of dc _ off may be selected, baud rate phase detector 198 may be implemented as a dc phase detector, e.g., as one or more of a forward phase detector, a backward phase detector, and/or a symmetric phase detector. That is, a setting can be made for the channel characteristics and the channel impulse response determined accordingly. Next, a channel impulse response is selected that is relatively close to the actual channel impulse response when the timing recovery converges.

In one example, baud rate phase detector 198 may set dc _ off values within certain ranges (e.g., -5), which may be passed through in predetermined increments. For each increment value, some or all of the dc phase detectors may be performed until timing recovery convergence occurs and/or some performance threshold is reached, and/or until all values are exhausted (those values from which the best value is selected). For example, in the phase detector relationship described above, certain settings (e.g., with forward, backward, or symmetric ISI) regarding the channel characteristics allow one or more terms to be known or set, and the phase signal can be calculated therefrom.

In the example of fig. 11, and somewhat similarly, equalizer 132 may be initialized (step 1112) by selecting a tap value from a pool of available values. With the selected values in place, coarse tune TR142, FFEs 124(1) -124(n), and DFEs 128(1) -128(M) may be turned on and held in steady state based on a preset timer value, and the coarse tune PGA may also (re-) hold in steady state 1114. These operations (steps 1112, 1114) may be repeated until an acceptable tap value is determined, from which the fine TR and fine PGA loops are turned on and allowed to remain steady-state (step 1116).

In fig. 11, the outer loop may continue with the next value of dc _ off (step 1118), or, if appropriate dc _ off has been determined, then the channel ID and timing recovery start (step 1120), e.g., as described with reference to fig. 10. In this operation, if the SNR monitor 498 determines that the current SNR value is not acceptable (step 1122), the sequential DFE142 is turned on for additional performance gains. In other embodiments, sequential DFE142 may be continuously turned on. If the performance gain is not sufficient to maintain the SNR at an acceptable level, the dc phase detector, equalizer, and other components are re-initialized (step 1108-. Of course, other metrics besides SNR may be additionally or alternatively monitored to determine whether to reinitialize. Clock and Data Recovery (CDR) will lock as long as an acceptable SNR level is achieved, CID and timing recovery may continue (step 1120).

Embodiments of the various techniques described herein may be implemented in digital electronic circuitry, or in computer hardware, firmware, software, or in combinations of them. Embodiments may be implemented as a computer program product, i.e., may be embodied in an information carrier (e.g., in a machine-readable storage device or in a propagated signal) for execution by, or to control the operation of, data processing apparatus, e.g., a programmable processor, a computer, or multiple computers. A computer program, such as the one described above, may be written in any form of programming language, including compiled or interpreted languages, and it may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interacting across a communication network.

Method steps can also be performed by, or apparatus can be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit).

Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read-only memory or a random access memory or both. Elements of a computer include at least one processor for executing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto-optical disks, or optical disks. Information carriers suitable for embodying computer program instructions and data include all forms of non-volatile memory, including semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory, magnetic disks such as internal hard disks or removable disks, magneto-optical disks, and CD-ROM and DVD-ROM optical disks. The processor and the memory can be implemented by, or incorporated in, special purpose logic circuitry.

While certain features of the embodiments have been described herein, many modifications, substitutions, changes, and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the embodiments of the invention.

Claims (10)

1. A channel identification system for identifying characteristics of a communication channel transmitting an information-bearing signal, said channel identification system comprising:

a filter computation module that computes a plurality of impulse response signals for the communication channel, wherein each of the plurality of impulse response signals is associated with a different phase;

an optimal phase calculation module that determines an optimal impulse response signal of a plurality of impulse response signals of the communication channel;

a reference waveform generator for generating a reference waveform from the optimal impulse response signal; and

a time-varying phase detector for determining an error signal from the reference waveform and the digitized version of the information-bearing signal and for generating a phase signal from the error signal and the reference waveform to control timing recovery of the information-bearing signal.

2. The system of claim 1, wherein the channel identification system receives as inputs: an information bearing signal, at least one decision signal representative of a characteristic of the information bearing signal, and a phase information signal.

3. The system of claim 2, wherein each impulse response signal is characterized by a plurality of coefficients.

4. The system of claim 3 wherein the filter computation module computes coefficients of a current impulse response signal, the coefficients being a function of an error signal between the information bearing signal and the decision signal.

5. The system of claim 4, wherein the current impulse response coefficient is calculated according to the following relationship:

wherein the content of the first and second substances,is the next iteration of estimating the channel impulse response,is the previous time of estimating the channel impulse responseIteration, μ is a parameter, e (n) is an error signal,is a decision signal; where p is the phase parameter and n is the iteration parameter.

6. The system of claim 2 wherein the phase signal includes a dc offset parameter.

7. A method of performing channel identification of a communication channel, comprising:

calculating a plurality of impulse response signals for the communication channel, wherein each of the plurality of impulse response signals is associated with a different phase;

determining an optimal impulse response signal of a plurality of impulse response signals of the communication channel;

determining a reference waveform according to the optimal impulse response signal;

determining an error signal between the reference waveform and a corresponding portion of an information-bearing signal transmitted over the communication channel; and

a phase signal for controlling a timing recovery circuit is determined from the reference waveform and the error signal.

8. The method of claim 7, further comprising receiving as inputs: an information-bearing signal transmitted over the communication channel, at least one decision signal representative of a characteristic of the information-bearing signal, and a phase information signal.

9. A system for performing electronic dispersion compensation on an information-bearing signal transmitted over a communication channel, the system comprising:

a channel identification module for receiving a first digitized version of an information-bearing signal and an equalized version of the information-bearing signal and determining therefrom an impulse response of the communication channel;

a time-varying phase detector for receiving the equalized version of the information-bearing signal, the second digitized version of the information-bearing signal, and the impulse response, and generating a reference waveform from the impulse response and the equalized version of the information-bearing signal;

wherein the time-varying phase detector generates a phase signal from the reference waveform and an error signal determined from the reference waveform and a second digitized version of the information-bearing signal.

10. The system of claim 9, wherein said first digitized version is sampled at a rate that is lower than a baud rate of the information bearing signal and said second digitized version is sampled at said baud rate.