HK1112112B - Semiconductor power device having a top-side drain using a sinker trench - Google Patents

Description

Semiconductor power device with top drain using sinker trench

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. provisional application No.60/598,678 filed on 3.8.2004, the contents of which are incorporated herein by reference. Further, the present application relates to application No.11/026,276 entitled "power semiconductor device and method of manufacturing the same" filed on 29.12.2004, the contents of which are incorporated herein by reference.

Technical Field

The present invention relates generally to semiconductor power devices and, more particularly, to power devices with top drain contacts using sinker trenches (sinker trenches).

Background

Unlike Integrated Circuits (ICs) which have a lateral structure, all of which interconnections are available on the top chip surface, many power semiconductor devices have a vertical structure, in which the backside of the chip is an active electrical connection. For example, in a vertical power MOSFET structure, the source and gate connections are located at the top surface of the chip, while the drain connection is located at the back side of the chip. For some applications it is desirable to achieve that the drain connection is available at the top. A sinker trench structure is used for this purpose.

In a first technique, a diffusion sinker extending from the top of the chip down to the substrate (which forms the drain contact region of the device) is used to make the drain contact available at the chip top surface. A disadvantage of this technique is that lateral diffusion during the formation of the diffusion sinker causes consumption of a significant amount of silicon area.

In a second technique, metal-filled vias extending from the top of the chip through the back side of the chip are used to connect the back side to the top of the chip. Although this technique does not result in active area (active area) loss as in the diffusion sinker technique, it requires deep trenches to be formed, which increases the complexity of the fabrication process. Furthermore, during conduction, the current needs to travel a long distance along the substrate before it reaches the drain contact, resulting in a device with a high on-resistance Ron.

Therefore, there is a need for an improved trench structure so that a back contact can be obtained at the top.

Disclosure of Invention

According to an embodiment of the present invention, a semiconductor power device includes a substrate of a first conductivity type and an epitaxial layer of the first conductivity type over and in contact with the substrate. The first trench extends into and terminates within the epitaxial layer. A sinker trench extends through the epitaxial layer from a top surface of the epitaxial layer and terminates within the substrate. The sinker trench is laterally spaced from the first trench and is wider and extends deeper than the first trench. The sinker trench is lined with an insulator only along the sinker trench sidewalls so that the conductive material filling the sinker trench makes electrical contact with the substrate along the bottom of the trench and makes electrical contact with the interconnect layer along the top of the trench.

According to another embodiment of the present invention, a semiconductor power device is formed as follows. An epitaxial layer is formed over and in contact with the substrate. The epitaxial layer and the substrate are of a first conductivity type. A first opening for forming the first trench and a second opening for forming the sinker trench are defined such that the second opening is wider than the first opening. A silicon etch is performed to simultaneously etch through the first and second openings to form a first trench and a sinker trench such that the first trench terminates within the epitaxial layer and the sinker trench terminates within the substrate. The sidewalls and bottom of the sinker trench are lined with an insulator. The sinker trench is filled with a conductive material such that the conductive material makes electrical contact with the substrate along the bottom of the sinker trench. An interconnect layer is formed over the epitaxial layer such that the interconnect layer makes electrical contact with the conductive material along a top surface of the sinker trench.

In accordance with yet another embodiment of the present invention, a semiconductor power device includes a plurality of sets of strip trenches extending in a silicon region above a substrate. The contiguous sinker trench completely surrounds each of the plurality of sets of strip-shaped trenches to insulate the plurality of sets of strip-shaped trenches from each other. A contiguous sinker trench extends from a top surface of the silicon region through the silicon region and terminates within the substrate. The contiguous sinker trench is lined with an insulator only along sinker trench sidewalls so that conductive material filling the contiguous sinker trench makes electrical contact with the substrate along the bottom of the contiguous sinker trench and makes electrical contact with the interconnect layer along the top of the contiguous sinker trench.

In accordance with yet another embodiment of the present invention, a semiconductor power device includes a plurality of sets of strip gate trenches extending in a silicon region above a substrate. Each of the plurality of stripe sinker trenches extends between two adjacent ones of the plurality of groups of stripe gate trenches. A plurality of strap sinker trenches extend through the silicon region from a top surface of the silicon region and terminate within the substrate. The plurality of stripe-shaped sinker trenches are lined with an insulator only along sinker trench sidewalls so that the conductive material filling each sinker trench makes electrical contact with the substrate along the bottom of the sinker trench and makes electrical contact with the interconnect layer along the top of the sinker trench.

According to another embodiment of the present invention, a semiconductor package device houses a chip including a power device. The chip includes a silicon region over a substrate. Each of the plurality of first trenches extends in the silicon region. A contiguous sinker trench extends along the perimeter of the chip so as to completely surround the plurality of first trenches. A contiguous sinker trench extends from the top surface of the die through the silicon region and terminates within the substrate. The continuous sinker trench is lined with an insulator only along the sinker trench sidewalls so that the conductive material filling the continuous sinker trench makes electrical contact with the substrate along the bottom of the continuous sinker trench and makes electrical contact with the interconnect layer along the top of the continuous sinker trench. The plurality of interconnect balls disposed in the grid array includes an outer set of the plurality of interconnect balls electrically connected to the conductive material in the contiguous sinker trench.

Drawings

Fig. 1 shows a simplified cross-sectional view of an exemplary vertical power device according to an embodiment of the present invention;

2-4 illustrate various top layout views of a vertical power device having one or more sinker trenches according to an exemplary embodiment of the invention; and

fig. 5 is a top view illustrating the location of interconnect balls in a ball grid array package relative to sinker trenches extending along the perimeter of a chip located in the ball grid array package, according to an exemplary embodiment of the invention.

Detailed Description

According to an embodiment of the present invention, a sinker trench terminating within a silicon substrate is filled with a highly conductive material such as doped polysilicon or a metallic material. The sinker trench is laterally spaced a predetermined distance from the active region in which the gate trench is formed. The sinker trench is wider than and extends deeper than the gate trench and is lined with insulator only along its sidewalls. This technique eliminates area loss due to side diffusion of the diffusion sinker approach and increases on-resistance due to the use of more conductive materials compared to diffusion. Moreover, this technique requires a trench that is much shallower than the trench required in a technique in which a metal-filled trench extends from the top of the chip to its bottom. The on-resistance is increased since the current does not need to travel the full depth of the substrate to reach the drain contact.

Fig. 1 shows a simplified cross-sectional view of a vertical trench-gate power MOSFET structure 100 according to an exemplary embodiment of the invention. An n-type epitaxial layer 104 extends over the n-type substrate 102 forming the back drain. Sinker trench 106 extends from the top surface of epitaxial layer 104 through epitaxial layer 104 and terminates within substrate 102. Dielectric layer 110 lines the sidewalls of the sinker trench. The dielectric layer 110 may be made of any one of the following: oxide, silicon nitride, silicon oxynitride, a multilayer structure of oxide and nitride, any well-known low-k insulating material, and any well-known high-k insulating material. "oxide" as used in this disclosure refers to chemical vapor deposited oxide (Si)_xO_y) Or thermally grown (thermally grown) silicon dioxide (SiO)₂). Sinker trench 106 is filled with a conductive material 108, such as doped polysilicon, selective epitaxial Silicon (SEG), a metal, or a metal compound. Conductive material 108 makes electrical contact with substrate 102 along the bottom of sinker trench 106. Thus, the conductive material 108 makes back side drains available along the top to facilitate interconnection. Since the drain contact moves to the top surface, the backside metal for contacting the substrate 102 is no longer needed, but can be used in conjunction with the top contact. The backside metal layer may be included for other purposes, such as preventing die cracking and improving the heat transfer characteristics of the device.

A well region (well region)114 of P-type conductivity extends along an upper portion of the epitaxial layer 104. Gate trench 112 is laterally spaced a predetermined distance S1 from sinker trench 106 and extends vertically from the top surface through P-type well region 114, terminating at a predetermined depth within epitaxial layer 104. Sinker trench 106 is wider and deeper than gate trench 112. Gate trench 112 is lined with a dielectric layer 116. The dielectric along the bottom of gate trench 112 may optionally be made thicker than the dielectric along the sidewalls of the gate trench. Each gate trench 112 includes a gate electrode 118 and a dielectric layer 120, the dielectric layer 120 being located on top of the gate electrode 118 for reducing gate-to-drain capacitance. Source regions 122 of n-type conductivity extend along an upper portion of the well region 114. The source region 122 overlaps the gate electrode 118 in the vertical direction. It can be seen that well region 114 terminates a distance away from sinker trench 106. In one embodiment, the distance is controlled by the device blocking voltage rating. In another embodiment, well region 114 terminates at and abuts sinker trench 106. In this embodiment, to achieve a higher blocking voltage rating, the thickness of the dielectric layer along the sidewalls of the sinker trench needs to be made thicker since the sinker dielectric layer needs to withstand higher voltages. If the conductive material 108 is required to have a minimum width for current handling purposes, a wider sinker trench may be required.

In the on state, a conduction channel from the source region 122 to the epitaxial layer 104 is formed in the well region 114 along the gate trench sidewalls. Thus, current flows vertically from the drain terminal 124 through the conductive material 108 of the sinker trench 106, then laterally through the substrate 102, and finally vertically through the epitaxial layer 104, the conduction channel in the well region 114, and the source region 122 to the source terminal 126.

While the width of the gate trench is typically kept at a level of small width corresponding to the maximum packing density allowed by the fabrication technology, a wider sinker trench is often more desirable. Wider sinker trenches are easier to fill, have lower resistance, and can be extended more easily deeper if desired. In one embodiment, sinker trench 106 and gate trench 114 are formed simultaneously. This facilitates self-alignment of the sinker trench with the active region. In this embodiment, the widths of the sinker trench and the gate trench and the spacing S1 between sinker trench 106 and the active area need to be carefully selected taking into account a number of factors. First, the ratio of the width Ws of sinker trench 106 to the width Wg of gate trench 112 needs to be selected so that once the trench etch step is complete, sinker trench 106 and gate trench 112 terminate at the desired depth. Second, the width ratio and the spacing S1 need to be carefully selected to minimize micro-loading effects (micro-loading effects) that occur when trenches having different characteristics are etched simultaneously. If not handled correctly, the micro-loading effect may cause the trench with the wide opening to have a wider bottom than the top. This may cause problems such as the formation of pinholes in the conductive material in the sinker trench. The micro-loading effect can also be minimized by selecting an appropriate etching material. Third, the width of the trench and the spacing S1 affect the on-resistance Ron of the device. In an article entitled "a new integrated silicon gate technology incorporating bipolar linear, CMOS logic and DMOS power components", published by a.andreini et al, ieee (transacton Electron device) vol.ed-33, No.12, pp2025-2030, 12, andreini et al, at 12 months 1986, a formula is presented in section IV-B, page 2028, which can be used to determine the optimum trench width and spacing S1 for the desired Ron. Although the power device described in this article uses diffusion sinking, the same principles relating to optimizing Ron can be applied in the present invention. This article is incorporated herein by reference.

The ratio of the sinker trench width to the gate trench width also depends on the type of conductive material used in the sinker trench. Typically, it is desirable that the ratio of the sinker trench width to the gate trench width be less than 10: 1. In one embodiment using doped polysilicon as the conductive material, it is desirable that the ratio of the sinker trench width to the gate trench width be less than 5: 1. For example, for a gate trench width of 0.5 μm, the sinker trench width will be selected in the range of about 0.7 μm to 2.5 μm. A higher ratio (e.g., 3: 1) is more desirable if metal or other highly conductive material is used in the sinker trench. In addition to the relative width of the trenches, the spacing S1 between the sinker trench and the active region also affects the micro-loading effect. Smaller pitches generally result in less micro-loading effects.

In one embodiment, the depth of the gate trenches in the epitaxial layer is selected to be close to the interface between substrate 102 and epitaxial layer 104 so that a slightly wider sinker trench will penetrate to contact substrate 102. In an alternative embodiment, both the gate trenches and the sinker trenches terminate within substrate 102.

In another embodiment, the sinker trench and the gate trench are formed at different times. Although the sinker trench will not be self-aligned to the active region, the spacing S1 is not a critical dimension. Advantages of forming two trenches at different times include: elimination of micro-loading effects and the ability to individually optimize each trench.

In accordance with an embodiment of the present invention, the following is a method of forming the power transistor shown in fig. 1, wherein the sinker trench and the gate trench are formed simultaneously. An epitaxial layer 104 is formed over the substrate 102. The gate trench and sinker trench openings are then patterned using a mask layer. The silicon is etched using conventional plasma etching techniques to form the sinker trench and the gate trench. An insulating layer (e.g., oxide) is then formed along the sidewalls and bottom of the gate trench and sinker trench. Since some of the voltage from the lossy layer will be carried by the insulating layer, reducing the silicon area consumed by the use of sinker trenches, increasing the insulating thickness or increasing the dielectric constant of the insulating material will facilitate the minimization of the area between the lossy region and the sinker trench, as well as the distance S1.

A nitride layer is formed over the oxide layer in all trenches. The oxide and nitride layers are then removed from the bottom of the sinker trench using conventional photolithography and anisotropic etching techniques, leaving a bilayer of oxide-nitride along the sinker trench inner walls. Alternatively, a combination of anisotropic and isotropic etching or only isotropic etching may be used. A combination of anisotropic and isotropic etching may be advantageously used to remove the nitride and oxide layers, respectively, from the lower sidewall portions of the trench sinker (e.g., those extending in the substrate or even the epitaxial layer, which would advantageously reduce on-resistance). The resulting thicker dielectric bi-layer along the sinker trench sidewalls is advantageously able to withstand higher drain voltages. The sinker trench and gate trench are then filled with in-situ (in-situ) doped polysilicon. The doped polysilicon is then etched back to planarize the top of the polysilicon in the trench with respect to the top surface of the epitaxial layer 104. The dual layer of polysilicon and oxide-nitride is then removed from the gate trench using a mask layer to cover the sinker trench. The gate trench is then lined with a gate oxide layer and filled with a gate polysilicon material. The excess gate polysilicon over the sinker trench is removed using conventional photolithography and etching processes to pattern the gate electrode. The remaining process steps for forming the insulating layer over the gate electrode, well region, source and drain metal contact layers, as well as other steps to complete the device, are performed according to conventional methods.

In an alternative method, after forming the trenches, a thick oxide layer is formed along the sidewalls and bottom of the gate trenches and sinker trenches (as described above to reduce the sinker trench to well region spacing). The thick oxide layer is then removed from the bottom of the sinker trench using conventional photolithography and anisotropic etching techniques, thereby leaving the sidewalls of the sinker trench lined with thick oxide while protecting the gate trench. Alternatively, a combination of anisotropic and isotropic etching may also be used to remove the thick oxide from the lower portion of the trench sinker sidewalls. The oxide layer may serve as a sacrificial (sacrificial) insulating layer for the gate trench to improve gate oxide integrity. The sinker trench and gate trench are then filled with in-situ doped polysilicon. The doped polysilicon is then etched back to planarize the top of the polysilicon in the trenches with respect to the top surface of epitaxial layer 104. The sinker trench is then covered with a masking layer, and the polysilicon and insulating layer are removed from the gate trench. The gate trench is then lined with a gate insulation layer and filled with a gate polysilicon material. The excess gate polysilicon over the sinker trench is removed using conventional photolithography and etching processes to pattern the gate electrode. The remaining process steps for forming the insulating layer over the gate electrode, well region, source and drain metal contact layers, as well as other steps to complete the device, are performed according to conventional methods.

In another approach, once the trenches are formed, an insulating layer (e.g., gate oxide) is formed (grown or deposited) along the sidewalls and bottom of the gate trenches and sinker trenches. The gate oxide layer is then removed from the bottom of the sinker trench using conventional photolithography and anisotropic etching techniques, leaving the oxide layer lining the sinker trench sidewalls while protecting the gate trench. Alternatively, a combination of anisotropic and isotropic etching or only isotropic etching may be used. A combination of anisotropic and isotropic etching may be advantageously used to remove the gate oxide layer from the lower sidewall portions of the trench sinker (e.g., those extending in the substrate or even the epitaxial layer, which would advantageously reduce on-resistance). The sinker trench and gate trench are then filled with in-situ doped polysilicon. The doped polysilicon is then patterned using conventional photolithographic techniques and etched to form the sinker (drain) electrode and the gate electrode. The remaining process steps for forming the insulating layer over the gate electrode, well region, source and drain metal contact layers, as well as other steps to complete the device, are performed according to conventional methods.

In yet another method, the sinker trench and the gate trench are formed separately by using separate masking steps. For example, a first set of masks and process steps are used to define and etch the gate trench, lined with gate oxide, and filled with polysilicon. A second set of masks and process steps are used to define and etch the sinker trench, lined with a dielectric layer along its sidewalls, and filled with a conductive material. The order of forming the sinker trench and the gate trench may be reversed.

Fig. 2 shows a simplified top layout view of a power device with a sinker trench according to an exemplary embodiment of the invention. The layout of fig. 2 shows a band-shaped cell structure. The strip gate trench 212a extends vertically and terminates in a horizontally extending gate trench 212 b. As shown, three sets of stripe gate trenches are surrounded by a contiguous sinker trench 206. In an alternative embodiment shown in fig. 3, sinker trenches 306 are disposed between groups of gate trenches (only two are shown) and repeated at a frequency and spacing controlled by the desired Ron. In a variation of this embodiment, to achieve the same Ron as the backside drain contact method, the spacing between adjacent sinker trenches needs to be twice the wafer thickness. For example, for a 4 mil (mil) thick wafer, the sinker trenches may be spaced apart from each other by about 8 mils. The sinker trenches can be placed closer together even for lower Ron. In yet another embodiment shown in fig. 4, the stripe-shaped gate trenches 412 extend horizontally, while the vertically extending sinker trench 406 is spaced apart from a different set of gate trenches. Sinker trenches 406 are interconnected by metal interconnects 432. An enlarged metal interconnect is shown along the right side of the view, forming a drain pad for bond-wire connection. In addition, a gate pad 430 is also shown in the cut-away corner of a set of gate trenches.

Fig. 5 shows a top view of a chip housing a power device having a sinker trench according to an embodiment of the invention. The small circles represent the balls in the ball grid array package. Peripheral region 506 includes a sinker trench and thus the balls in peripheral region 506 provide the drain connection. The central region 507 represents the active region and the balls inside this region provide the source connection. A small square area 530 at the lower left corner of central region 508 represents the gate pad and the ball inside area 530 provides the gate connection.

It is apparent that the sinker trench structure 106 in fig. 1 can be used to bring the backside connections of any power device to the top surface and is not limited to use with vertical trench gate power MOSFETs. The same or similar sinker trench structures can be similarly integrated with other vertically conducting power devices such as planar gate MOSFETs (i.e., MOSFETs with a gate and its underlying channel region extending above and parallel to the silicon surface) and power diodes so that an anode or cathode contact region is available along the top for interconnection. Many other variations and alternatives are possible, including the use of shielded gate and dual gate structures in different combinations with various charge balance techniques, many of which are described in detail in the above-referenced, commonly assigned patent application entitled "power semiconductor device and method of manufacturing the same", filed 12/29/2004, the entire contents of which are incorporated herein by reference. Also, although fig. 2 to 5 show layout embodiments according to the structure of the open cell, the present invention is not limited thereto. The structure shown in fig. 1 may also be implemented in any of a number of well-known disclosed cell structures. Finally, the dimensions in the cross-sectional view of fig. 1 and the top layout views in fig. 2-5 are not to scale, but are primarily illustrative.

Claims (37)

1. A semiconductor power device comprising:

a first conductive type substrate;

an epitaxial layer of a first conductivity type over and in contact with the substrate;

a first trench extending into and terminating within the epitaxial layer;

a sinker trench extending through the epitaxial layer from a top surface of the epitaxial layer and terminating within the substrate, the sinker trench laterally spaced from the first trench, the sinker trench being wider and extending deeper than the first trench, the sinker trench being lined with an insulator only along sidewalls of the sinker trench such that conductive material filling the sinker trench makes electrical contact with the substrate along a bottom of the sinker trench and makes electrical contact with an interconnect layer along a top of the sinker trench.

2. The semiconductor power device of claim 1, further comprising:

a well region of a second conductivity type in the epitaxial layer;

a source region of the first conductivity type located in the well region, the source region being at a side of the first trench;

a gate dielectric layer lining at least sidewalls of the first trench; and

a gate electrode at least partially filling the first trench,

wherein a gate electrode contact layer in electrical contact with the gate electrode, a source contact layer in electrical contact with the source region, and a drain contact layer in electrical contact with the substrate are along one surface of the semiconductor power device.

3. The semiconductor power device of claim 1, wherein the conductive material comprises one or more of: doped polysilicon, selective epitaxial Silicon (SEG), metals, and metal compounds.

4. The semiconductor power device of claim 1 wherein the insulator comprises one of: oxides, silicon nitrides, silicon oxynitrides, multilayers of oxides and nitrides, low-k insulating materials, and high-k insulating materials.

5. A semiconductor power device comprising:

a first conductive type substrate;

an epitaxial layer of a first conductivity type over and in contact with the substrate;

a well region of a second conductivity type in the epitaxial layer;

a gate trench extending through the epitaxial layer and the well region and terminating within the substrate, the gate trench including a gate dielectric layer lining at least sidewalls of the gate trench, and a gate electrode at least partially filling the gate trench;

a source region of a first conductivity type in the well region, the source region being at a side of the gate trench; and

a sinker trench extending through the epitaxial layer from a top surface of the epitaxial layer and terminating within the substrate, the sinker trench laterally spaced from the gate trench, the sinker trench being wider than the gate trench, the sinker trench being lined with an insulator only along the sinker trench sidewalls such that conductive material filling the sinker trench makes electrical contact with the substrate along the bottom of the sinker trench and makes electrical contact with an interconnect layer along the top of the sinker trench.

6. The semiconductor power device of claim 5, wherein the conductive material comprises one or more of: doped polysilicon, selective epitaxial Silicon (SEG), metals, and metal compounds.

7. The semiconductor power device of claim 5 wherein the insulator comprises one of: oxides, silicon nitrides, multiple layers of oxides and nitrides, silicon oxynitrides, low-k insulating materials, and high-k insulating materials.

8. A method of forming a semiconductor power device, comprising:

forming an epitaxial layer over and in contact with a substrate, the epitaxial layer and the substrate being of a first conductivity type;

defining a first opening for forming a first trench and a second opening for forming a sinker trench, the second opening being wider than the first opening;

performing a silicon etch simultaneously through the first and second openings to form the first trench and the sinker trench such that the first trench terminates within the epitaxial layer and the sinker trench terminates within the substrate;

lining sidewalls of the sinker trench with an insulator;

filling the sinker trench with a conductive material such that the conductive material makes electrical contact with the substrate along a bottom of the sinker trench; and

an interconnect layer is formed over the epitaxial layer, the interconnect layer making electrical contact with the conductive material along a top surface of the sinker trench.

9. The method of claim 8, wherein a ratio of the sinker trench width to the first trench width is less than 10: 1.

10. The method of claim 9, wherein the ratio is less than 4: 1.

11. The method of claim 9, wherein the conductive material comprises polysilicon and the ratio is 2: 1.

12. The method of claim 8 wherein the insulator in the lining step is a bilayer of nitride-oxide.

13. The method of claim 8, wherein the insulator comprises one of:

oxides, silicon nitrides, multiple layers of oxides and nitrides, silicon oxynitrides, low-k insulating materials, and high-k insulating materials.

14. The method of claim 8, further comprising:

forming a well region of a second conductivity type in the epitaxial layer;

forming a source region of a first conductivity type in the well region such that the source region is on a side of the first trench;

forming a gate dielectric layer lining at least sidewalls of the first trench; and

forming a gate electrode at least partially filling the first trench,

wherein a gate electrode contact layer in electrical contact with the gate electrode, a source contact layer in electrical contact with the source region, and a drain contact layer in electrical contact with the substrate are along one surface of the semiconductor power device.

15. The method of claim 8, wherein a plasma etch is used to perform the silicon etch.

16. The method of claim 8 wherein, in the lining step, sidewalls of the first trench are also lined with the insulator, the method further comprising:

removing the insulator only from the bottom of the sinker trench such that the substrate is exposed along the bottom of the sinker trench.

17. The method of claim 8, further comprising:

removing the insulator from the lower portion of the sinker trench using an anisotropic etch prior to the filling step.

18. The method of claim 8, wherein,

the lining step includes lining sidewalls and a bottom of the sinker trench and the first trench simultaneously with the insulator, and

the filling step includes simultaneously filling the sinker trench and the first trench with in-situ doped polysilicon;

the method further comprises:

removing the insulator from only the bottom of the sinker trench prior to the filling step;

removing the polysilicon and the insulator from at least an interior of the first trench;

forming a gate dielectric lining sidewalls and a bottom of the first trench; and

and forming a gate electrode in the first trench.

19. The method of claim 8, wherein:

the lining step includes lining sidewalls and bottom of the sinker trench and the first trench simultaneously with a gate dielectric; and

the filling step includes simultaneously filling the sinker trench and the first trench with in-situ doped polysilicon,

the method further comprises:

prior to the filling step, removing the gate dielectric from only the bottom of the sinker trench.

20. A method of forming a field effect transistor, the method comprising:

forming an epitaxial layer over and in contact with a substrate, the epitaxial layer and the substrate being of a first conductivity type;

defining a first opening for forming a gate trench and a second opening for forming a sinker trench, the second opening being wider than the first opening;

performing a silicon etch through the first and second openings simultaneously to form the gate trench and the sinker trench such that the gate trench terminates within the epitaxial layer and the sinker trench terminates within the substrate;

lining sidewalls and bottoms of the sinker trench and the gate trench with an insulator; and

removing the insulator from a lower portion of the sinker trench;

the sinker trench and the gate trench are filled with doped polysilicon such that the conductive material makes electrical contact with the substrate along a lower portion of the sinker trench.

21. The method of claim 20, further comprising:

forming a well region of a second conductivity type in the epitaxial layer;

forming a source region of a first conductivity type in the well region such that the source region is on a side of the gate trench;

wherein a gate electrode contact layer in electrical contact with the gate electrode, a source contact layer in electrical contact with the source region and the well region, and a drain contact layer in electrical contact with the substrate through the sinker trench are along one surface of the field effect transistor.

22. The method of claim 20 wherein a ratio of the sinker trench width to the gate trench width is less than 4: 1.

23. The method of claim 20 wherein the insulator in the lining step is a bilayer of oxide-nitride.

24. The method of claim 20, wherein a lower portion of the sinker trench comprises a trench bottom and a lower sidewall portion of the sinker trench extending along the substrate.

25. A semiconductor power device comprising:

a plurality of sets of strip-shaped trenches extending in a silicon region above a substrate;

a contiguous sinker trench completely surrounding each of the plurality of sets of strip trenches so as to insulate the plurality of sets of strip trenches from one another, the contiguous sinker trench extending from a top surface of the silicon region through the silicon region and terminating within the substrate, the contiguous sinker trench being lined with an insulator only along sidewalls of the sinker trench such that conductive material filling the contiguous sinker trench makes electrical contact with the substrate along a bottom of the contiguous sinker trench and makes electrical contact with an interconnect layer along a top of the contiguous sinker trench.

26. The semiconductor power device of claim 25 wherein the silicon region is an epitaxial layer and the plurality of strip trenches are gate trenches, the semiconductor device further comprising:

a well region of a second conductivity type in the epitaxial layer;

a source region of a first conductivity type in the well region, the source region being at a side of the gate trench;

a gate dielectric layer lining at least sidewalls of each of said gate trenches; and

a gate electrode at least partially filling each of the gate trenches,

wherein a gate electrode contact layer in electrical contact with the gate electrode, a source contact layer in electrical contact with the source region, and a drain contact layer in electrical contact with the substrate are along one surface of the semiconductor power device.

27. The semiconductor power device of claim 25 wherein the conductive material comprises one or more of: doped polysilicon, selective epitaxial Silicon (SEG), metals, and metal compounds.

28. The semiconductor power device of claim 25 wherein the contiguous sinker trench is wider and extends deeper than the plurality of stripe trenches.

29. A semiconductor power device comprising:

a plurality of sets of strip gate trenches extending in a silicon region above a substrate;

a plurality of stripe-shaped sinker trenches, each of the plurality of stripe-shaped sinker trenches extending between two adjacent ones of the plurality of groups of stripe-shaped gate trenches, the plurality of stripe-shaped sinker trenches extending through the silicon region from a top surface of the silicon region and terminating within the substrate, the plurality of stripe-shaped sinker trenches lined with an insulator only along sidewalls of the sinker trenches such that conductive material filling each of the sinker trenches makes electrical contact with the substrate along a bottom of the sinker trench and makes electrical contact with an interconnect layer along a top of the sinker trench.

30. The semiconductor power device of claim 29 wherein the silicon region is an epitaxial layer, the semiconductor device further comprising:

a well region of a second conductivity type in the epitaxial layer;

a source region of the first conductivity type located in the well region, the source region being at a side of the plurality of sets of strip gate trenches;

a gate dielectric layer lining at least sidewalls of each of said gate trenches; and

a gate electrode at least partially filling each of the gate trenches,

wherein a gate electrode contact layer in electrical contact with the gate electrode, a source contact layer in electrical contact with the source region, and a drain contact layer in electrical contact with the substrate are along one surface of the semiconductor power device.

31. The semiconductor power device of claim 29 wherein the conductive material comprises one or more of: doped polysilicon, selective epitaxial Silicon (SEG), metals, and metal compounds.

32. The semiconductor power device of claim 29 wherein the plurality of sinker trenches are wider and extend deeper than the plurality of sets of strip gate trenches.

33. The semiconductor power device of claim 29, wherein a drain interconnect layer electrically connects the plurality of strap sinker trenches to a drain pad configured to receive a drain bond wire.

34. A semiconductor package device housing a chip including a power device, the chip including a silicon region over a substrate, the semiconductor package device comprising:

a plurality of first trenches extending in the silicon region;

a contiguous sinker trench extending along a perimeter of the chip so as to completely surround the plurality of first trenches, the contiguous sinker trench extending from a top surface of the chip through the silicon region and terminating within the substrate, the contiguous sinker trench being lined with an insulator only along sidewalls of the sinker trench such that conductive material filling the contiguous sinker trench makes electrical contact with the substrate along a bottom of the contiguous sinker trench and makes electrical contact with an interconnect layer along a top of the contiguous sinker trench; and

a plurality of interconnect balls disposed in a grid array, an outer set of the plurality of interconnect balls being electrically connected to the conductive material in the contiguous sinker trench.

35. The semiconductor package device of claim 34, wherein the silicon region is an epitaxial layer and the plurality of first trenches are gate trenches, the semiconductor package device further comprising:

a well region of a second conductivity type in the epitaxial layer;

a source region of the first conductivity type in the well region, the source region being at a side of the gate trench;

a gate dielectric layer lining at least sidewalls of each of said gate trenches; and

a gate electrode at least partially filling each gate trench,

wherein a gate electrode contact layer in electrical contact with the gate electrode, a source contact layer in electrical contact with the source region, and a drain contact layer in electrical contact with the substrate are along one surface of the power device.

36. The semiconductor package device of claim 34, wherein an inner set of the plurality of interconnect balls surrounded by the outer set of the plurality of interconnect balls is in electrical contact with the source contact layer.

37. The semiconductor package device of claim 34, wherein the contiguous sinker trench is wider and extends deeper than the plurality of first trenches.