HK1186843A - Substrate with embedded stacked through-silicon via die - Google Patents

Description

Substrate with embedded stacked through-silicon-via die

Technical Field

Embodiments of the invention are in the field of semiconductor packaging, and in particular, in the field of substrates with embedded stacked through-silicon-via dies.

Background

The consumer electronics market today frequently requires complex functionality requiring very complex circuitry. Scaling to smaller and smaller basic building blocks, such as transistors, has enabled even more complex circuits to be incorporated onto a single die with progressive generations. On the other hand, while scaling is generally considered a reduction in size, multiple packaged dies are increasingly coupled together to achieve more advanced functionality and horsepower in a computing system. Moreover, the size of a particular semiconductor package may actually be increased to include multiple dies within a single semiconductor package.

However, structural problems may arise when attempting to couple multiple packaged dies. For example, the effects of Coefficient of Thermal Expansion (CTE) differences between components used in semiconductor packages can cause detrimental defects when packaged dies are added together. Similarly, the effects of Coefficient of Thermal Expansion (CTE) differences between components used within a single semiconductor package may cause detrimental defects due to semiconductor die packaging processes performed on more than one die within a single package.

Semiconductor packages are used to protect Integrated Circuit (IC) chips or dies and also to provide electrical interfaces to the dies to external circuitry. As the demand for smaller electronic devices increases, semiconductor packages are designed to be more compact and must support greater circuit densities. For example, some semiconductor packages now use coreless substrates that do not include a thick resin core layer as is common in conventional substrates. Furthermore, the demand for high performance devices has resulted in a need for improved semiconductor packages that enable hybrid technology die stacking or provide package stacking capability while maintaining thin package profiles and low overall warpage compatible with subsequent packaging processes.

Bump-less Build-Up Layer (BBUL) is a processor packaging technology. This technique is bumpless because it does not use the commonly used tiny solder bumps to attach the silicon die to the processor package leads. It has a build-up layer because it is grown or built around the silicon die. A common way is to manufacture them separately and join them together. Some semiconductor packages now use coreless substrates that do not include a thick resin core layer as is common in conventional substrates.

Drawings

Figure 1 illustrates a cross-sectional view of a coreless substrate with an embedded stacked through-silicon via die, in accordance with an embodiment of the present invention.

Figure 2A illustrates a cross-sectional view during processing in the fabrication of a coreless substrate with an embedded stacked through-silicon via die, in accordance with an embodiment of the present invention.

Figure 2B illustrates a cross-sectional view during processing in the fabrication of a coreless substrate with an embedded stacked through-silicon via die, in accordance with an embodiment of the present invention.

Figure 2C illustrates a cross-sectional view during further processing in the fabrication of a coreless substrate with an embedded stacked through-silicon via die, in accordance with an embodiment of the present invention.

Figure 2D illustrates a cross-sectional view during further processing in the fabrication of a coreless substrate with an embedded stacked through-silicon via die, in accordance with an embodiment of the present invention.

Figure 2E illustrates a cross-sectional view during further processing in the fabrication of a coreless substrate with an embedded stacked through-silicon via die, in accordance with an embodiment of the present invention.

Figure 2F illustrates a cross-sectional view during further processing in the fabrication of a coreless substrate with an embedded stacked through-silicon via die, in accordance with an embodiment of the present invention.

Figure 2G illustrates a cross-sectional view during further processing in the fabrication of a coreless substrate with an embedded stacked through-silicon via die, in accordance with an embodiment of the present invention.

Figure 2H illustrates a cross-sectional view during processing in the fabrication of a coreless substrate with an embedded stacked through-silicon via die, in accordance with an embodiment of the present invention.

Figure 2I illustrates a cross-sectional view during processing in the fabrication of a coreless substrate with an embedded stacked through-silicon via die, in accordance with an embodiment of the present invention.

Figure 2J illustrates a cross-sectional view during processing in the fabrication of a coreless substrate with an embedded stacked through-silicon via die, in accordance with an embodiment of the present invention.

Figure 2K illustrates a cross-sectional view during processing in the fabrication of a coreless substrate with an embedded stacked through-silicon via die, in accordance with an embodiment of the present invention.

Figure 2K' illustrates a cross-sectional view of a coreless substrate with an embedded stacked through-silicon via die, in accordance with another embodiment of the present invention.

FIG. 3 is a schematic diagram of a computer system according to an embodiment of the invention.

Detailed Description

A substrate with an embedded stacked through-silicon via die is described. In the following description, numerous specific details are set forth, such as packaging architectures and material systems, in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the invention may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail in order to not unnecessarily obscure the present invention. Further, it is to be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

A plurality of semiconductor packages housing semiconductor dies are typically coupled after a packaging process, such as coupling a packaged memory die with a packaged logic die. In an example, connections between two or more separately packaged dies can be made after bumpless build-up layer (BBUL) fabrication by using a Thermal Compression Bonding (TCB) process. However, warpage of the BBUL may occur, for example, due to warpage by the logic die. Instead, according to embodiments of the present invention, the memory die is attached to the panel. Memory dies tend to be flatter and provide a good basis for subsequent bonding of logic dies. Thus, by packaging multiple dies starting with a memory die and then a logic die, processing is made easier at the carrier or panel level. Furthermore, a larger memory die than the logic die may actually be preferred for such panel packaging schemes, while the opposite may be true for later coupling of the logic chip and the memory die packaging. In an embodiment, packaging the logic die simultaneously with the memory die in the same package avoids increasing the CTE mismatch seen when coupling separate and separately packaged dies that leads to warpage.

In accordance with embodiments of the present invention, Through Silicon Via (TSV) memory/logic embedded packages are disclosed. For example, a multi-die package is described that eliminates the need for Thermal Compression Bonding (TCB) after BBUL memory attachment. Instead, both dies are embedded on the package. TCBs may be used to link dies, but flatter memories are attached and supported on peelable cores. This solution can significantly reduce the detrimental warping conditions. Die-to-die connections may be made first (with minimal CTE mismatch between the silicon blocks). A large panel carrier may be used to facilitate treatment. Also, in an embodiment, no routing from the first die to the external package is required.

Disclosed herein are coreless substrates with embedded stacked through-silicon via die. In an embodiment, an apparatus includes a first die and a second die. The second die has one or more through-silicon vias disposed therein (TSV die). The first die is electrically coupled to the TSV die through the one or more through-silicon vias. The apparatus also includes a coreless substrate. The first die and the TSV die are both embedded in a coreless substrate.

Also disclosed herein are methods of fabricating coreless substrates with embedded stacked through-silicon via dies. In an embodiment, a process includes bonding a backside of a first die to a panel with a die-bonding film. A backside of a second die (TSV die) including one or more through-silicon vias disposed therein is disposed over and bonded to the device side of the first die through the one or more through-silicon vias. A sealing layer is formed over the device side of the TSV die, the sealing layer surrounding the first die and the TSV die. Subsequently, the panel is removed from the die-bonding film.

In one aspect of the invention, a coreless substrate with an embedded stacked through-silicon via die is disclosed. Figure 1 illustrates a cross-sectional view of a coreless substrate with an embedded stacked through-silicon via die, in accordance with an embodiment of the present invention.

Referring to fig. 1, a stacked-die apparatus 100 includes a first die 102 embedded in a coreless substrate 104. The coreless substrate 104 includes a land side 106 and a die side 108. The first die 102 also includes an active surface or device side 110 and a backside surface or backside 112, and it can be seen that the active surface 110 of the first die 102 faces the land side 106, and the backside 112 faces the same direction as the die side 108 of the coreless substrate 104. The active surface may include a plurality of semiconductor devices including, but not limited to, transistors, capacitors, and resistors connected together by a die interconnect structure to form a functional circuit to thereby form an integrated circuit.

Those skilled in the art will appreciate that the device side 110 of the first die 102 includes an active portion (not shown) having integrated circuits and interconnects. According to several different embodiments, the first die 102 may be any suitable integrated circuit device, including but not limited to a microprocessor (single or multi-core), a memory device, a chipset, a graphics device, an application specific integrated circuit. In an embodiment, the stacked-die apparatus 100 further includes a die-bonding film 130 disposed on the back side 112 of the first die 102.

In an embodiment, the first die 102 is part of a larger device that includes a second die 114, the second die 114 being disposed below the die side 108 and coupled to the first die 102. The second die 114 is also shown with an active surface or device side 116 in simplified illustration, but it may also have metallization of M1 through M11 or any number and top metallization thickness. The second die 114 also has a back side surface or back side 118.

A second die 114 is also embedded in the coreless substrate 104. In an embodiment, the second die 114 has at least one through-silicon-via 120. Two through-silicon vias are shown, one of which is enumerated, but are presented for simplicity. In an embodiment, there are up to 1000 through-silicon vias in the second die 114. Thus, the second die 114 may be referred to as including a die having through-silicon vias disposed therein (TSV die 114). The device side 116 of the TSV die 114 faces the land side 106 and the backside 118 faces the die side 108 of the coreless substrate 104. Those skilled in the art will appreciate that the device side 116 of the TSV die 114 also includes an active portion (not shown) having integrated circuits and interconnects. The TSV die 114 may be any suitable integrated circuit device, including but not limited to a microprocessor (single or multi-core), a memory device, a chipset, a graphics device, an application specific integrated circuit, according to several different embodiments.

As shown, the first die 102 is coupled to the TSV die 114 through the at least one through-silicon via 120. In an embodiment, the first die 102 is electrically coupled to the TSV die 114 through the one or more through-silicon vias. In one embodiment, the first die 102 is electrically coupled to the TSV die 114 through the one or more through-silicon vias 120 through one or more respective conductive bumps 126 disposed on the first die 102 and through one or more bond pads (not shown) disposed on the TSV die 114. Bond pads are included on the backside 118 of the TSV die 114 and are aligned with the one or more through silicon vias 120. In an embodiment, the layer of epoxy flux material 128 is disposed between the first die 102 and the TSV die 114. In an embodiment, the coreless substrate 104 does not contain additional routing layers between the first die 102 and the TSV die 114. That is, in an embodiment, the first die 102 and the TSV die 114 communicate only through the conductive bumps on the device side 110 of the first die 102 and the one or more through silicon vias 120 of the TSV die 114.

TSV die 114 is also shown in simplified form with metallization on device side 118. The metallization contacts the integrated circuits in the TSV die 114 at the device side 116. In an embodiment, the metallization has metal 1 (M1) to metal 11 (M11) metallization layers to output the complexity of the TSV die 114 to the outside world, where M1 is in contact with the integrated circuit in the TSV die 114. In selected embodiments, there may be any number of metallizations between M1 and M11. In an example embodiment, the TSV die 114 has metallization from M1 to M7, and M7 is thicker than M1 to M6. Other metallization numbers and thickness combinations may be implemented depending on a given application utility.

In an embodiment, as shown in figure 1, the stacked-die apparatus 100 includes a base substrate 122 at the land side 106 of the coreless substrate 104. For example, where the first die 102 and the TSV die 114 are part of a handheld device (such as a smartphone embodiment or a handheld reader embodiment), the base substrate 122 is a motherboard. In an exemplary embodiment where the first die 102 and the TSV die 114 are part of a handheld device (such as a smartphone embodiment or a handheld reader embodiment), the base substrate 122 is a housing, such as the portion that an individual touches while in use. In an exemplary embodiment where the first die 102 and the TSV die 114 are part of a handheld device (such as a smartphone embodiment or a handheld reader embodiment), the base substrate 122 includes a motherboard and a housing (such as the portion that an individual touches while in use).

An array of external conductive contacts 132 is disposed on the land side 106 of the coreless substrate 104. In an embodiment, an external conductive contact 132 couples the coreless substrate 104 to the base substrate 122. The external conductive contacts 132 are used for electrical communication with the base substrate 122. In one embodiment, the array of external conductive contacts 132 is a Ball Grid Array (BGA). The solder mask 134 masks the material forming the land side 106 of the coreless substrate 104. The outer conductive contact 132 is disposed on the bump bond pad 136.

The stacked-die apparatus 100 includes a TSV die 114 that is fully embedded and surrounded. As used in this disclosure, "fully embedded and surrounded" means that all surfaces of the TSV die are in contact with the sealing film (such as a dielectric layer) of coreless substrate 104, or at least in contact with the material contained within the sealing film. In other words, "fully embedded and surrounded" means that all exposed surfaces of the TSV die 114 are in contact with the encapsulating film of the coreless substrate 104.

The stacked-die apparatus 100 also includes a fully embedded first die 102. As used in this disclosure, "fully embedded" means that the active surface 110 and the entire sidewalls of the first die 102 are in contact with the encapsulating film (e.g., dielectric layer) of the coreless substrate 104 or at least in contact with the material contained within the encapsulating film. In other words, "fully embedded" means that all exposed areas of the active surface 110 and exposed portions of the entire sidewalls of the first die 102 are in contact with the encapsulating film of the coreless substrate 104. However, the first die 102 is not "surrounded" because the backside 112 of the first die 102 is not in contact with the encapsulation film of the coreless substrate 104, or a material contained within the encapsulation film. Two embodiments of "fully embedding" of the first die 102 are described herein. In a first embodiment, as shown in figures 1 and 2K, there is one surface of the first die (e.g., the back surface 112) that protrudes from a globally planar surface of the die side of the coreless substrate, e.g., from the surface 108 of the coreless substrate 104 shown in figure 1. In a second embodiment, as shown in figure 2K ', no surface of the first die 230 protrudes from the entire planar surface of the die side of the coreless substrate, e.g., no protrusion from the surface 270' of the coreless substrate 272 'shown in figure 2K'.

In contrast to the above definitions of "fully embedded and surrounded" and "fully embedded," a "partially embedded" die is one whose entire surface, but only a portion of the sidewalls, is in contact with the encapsulating film of the coreless substrate, or at least with the material contained within the encapsulating film. By further contrast, an "un-embedded" die is at most one surface thereof, and no sidewall portions are in contact with the encapsulation film of the coreless substrate, or with material contained within the encapsulation film.

Thus, in accordance with an embodiment of the present invention, coreless substrate 104 includes sealing layer 124. Both the first die 102 and the TSV die 114 are fully embedded in the sealing layer 124. That is, the first die 102 and the TSV die 114 are housed in the same single layer of insulating material.

As a result of the disclosed first die and TSV die embodiments, the Z-height of the stacked-die apparatus 100 may be reduced. The reduced Z height is beneficial for compact device design and use, such as for handheld devices. For example, the total coverage area may be reduced when the device is to act as a chipset. This is beneficial because the stack 114 of the first die 102 and the TSV die 114 occupies a compact footprint on the coreless substrate 104.

The stacked-die apparatus 100 may be particularly suitable for packaging memory dies with logic dies. For example, in an embodiment, the first die 102 is a memory die having a device side 110 and a back side 112. The TSV die 114 is a logic die (logic TSV die) that includes one or more through-silicon vias 120 disposed therein. The logic TSV die 114 has a device side 116 and a backside 118. The logic TSV die 114 is disposed above the memory die 102 and aligned with the memory die 102. The back side 118 of the logic TSV die 114 is toward the device side 110 of the memory die 102. The memory die 102 is electrically coupled to the logic TSV die 114 through the one or more through-silicon vias 120. The package including the logic TSV die 114 and the memory die 102 also includes the coreless substrate 104. The coreless substrate 104 has a land side 106 and a die side 108. Both the memory die 102 and the logic TSV die 114 are embedded in the coreless substrate 104. The back side 112 of the memory die 102 faces the die side 108 of the coreless substrate 104, and the device side 116 of the logic TSV die 114 faces the land side 106 of the coreless substrate 104. In one embodiment, the device side 110 of the memory die 102 is larger in area than the backside 118 of the logic TSV die 114. In embodiments of the present application, the memory die 102 is a memory device, including but not limited to Static Random Access Memory (SRAM), dynamic access memory (DRAM), non-volatile memory (NVM), and the TSV die is a logic device, including but not limited to a microprocessor and a digital signal processor.

In another aspect of the invention, a method for fabricating a coreless substrate with an embedded stacked through-silicon via die is disclosed. A carrier, such as a panel, may be provided having a plurality of cavities disposed therein, each cavity sized to receive a die. Figure 2A illustrates a cross-sectional view during processing in the fabrication of a coreless substrate with an embedded stacked through-silicon via die, in accordance with an embodiment of the present invention. The apparatus 200 represents an early process and is related to the apparatus 100 shown in fig. 1. An etch stop layer 202 is provided. The second layer 206, such as a copper foil layer, may be etched to provide a recess or cavity having the die mounting surface 204. Package stack bond pads 208 have been formed on the second layer 206.

Figure 2B illustrates a cross-sectional view during further processing in the fabrication of a coreless substrate with an embedded stacked through-silicon via die, in accordance with an embodiment of the present invention. During processing, the apparatus 200 can be mated with the same structure to construct a back-to-back apparatus for processing utility. The device 210 has been expanded by back-to-back mating the original device 200 with a similar device 200'. As a result, processing throughput is effectively multiplied. The description of the devices 200 and 200 'may be referred to by the reference numerals attributed to the device 200, but it is understood that repeated processes and structures are included in the device 200'. The device 210 includes an adhesive release layer 212 and an adhesive 214. Cutting zones 216 are provided at each end of the device 210 for the separation process further illustrated. Device 210 may form a portion of a larger panel having a plurality of identical regions having the cross-section of device 210. For example, a panel may include 1000 recesses on each side, allowing 2000 individual packages to be fabricated from a single panel.

The backside of the die may be bonded to the panel using a die bonding film. For example, fig. 2C shows a cross-sectional view during further processing of the device shown in fig. 2B, in accordance with an embodiment of the present invention. Specifically, the device 218 is further processed by bonding a first die 220 on the etch stop layer 202 using a die-bonding film 219. In an embodiment, bonding the back side 223 of the first die 220 to the panel, i.e., to the device 210, using the die-bonding film 219 comprises: the bonding is performed using a material such as, but not limited to, an epoxy-based material. In one embodiment, the etch stop layer 202 is a metal layer. In one embodiment, the etch stop layer 202 is an organic material. Other materials may be used for the etch stop layer 202 depending on the particular application.

The first die 220 has a plurality of conductive bumps, one of which is designated with reference numeral 222. The first die 220 has an active surface 221, the active surface 221 being on the same surface as the conductive bumps 222. The number of conductive bumps 222 is shown as only two for ease of illustration. The first die 220 has a backside surface 223 opposite the active surface 221. Additionally, the first die 220 has metallization 224, which metallization 224 may include any number and similar thickness of metallization set forth in this disclosure. In one embodiment, the formation of the conductive bumps 222 is performed by a semi-additive plating process. The first die 220 is located within a recess or cavity formed within the second layer 206. Thus, in an embodiment, bonding the back side 223 of the first die to the panel includes bonding to a surface of a cavity disposed in the panel.

Fig. 2D shows a cross-sectional view during further processing of the device shown in fig. 2C, in accordance with an embodiment of the present invention. In particular, fig. 2D illustrates the addition of a first die 220' to form the apparatus 226.

Fig. 2E shows a cross-sectional view during further processing of the device shown in fig. 2D, in accordance with an embodiment of the present invention. The apparatus 226 is further processed by placing the TSV die 230, a complementary TSV die 230', on the first die 220. TSV die 230 has a plurality of die bond pads, one of which is designated with reference numeral 232. TSV die 220 has an active surface 231 that is on the same surface as bond pad 232. For ease of illustration, the number of bond pads 232 is shown as only two, and these bond pads 232 do not necessarily contact vias 236. TSV die 230 has a backside surface 233 that is opposite active surface 231. Additionally, TSV die 230 has metallization 234, which metallization 224 may include any number and similar thickness of metallizations set forth in this disclosure. TSV die 230 is also shown with two through-silicon vias, one of which is indicated with reference numeral 236. Backside bond pads 237 are included on the backside 233 of TSV die 230 and are aligned with through-silicon vias 236.

Fig. 2F shows a cross-sectional view during further processing in the manufacture of the device shown in fig. 2E, in accordance with an embodiment of the present invention. The backside 233 of the TSV die 230 is disposed over and bonded to the device side of the first die 220. In an embodiment, the backside 233 of the TSV die 230 is bonded to the conductive bumps 222 of the first die 220 through the one or more through-silicon vias 236, and thus through the backside bond pads 237, as shown in fig. 2F.

In an embodiment, coupling the backside 233 of the TSV die 230 to the device side of the first die 220 is performed by: the backside 233 of the TSV die 230 is bonded to the device side of the first die 220 with an epoxy flux material 238. The epoxy flux material may be dispensed over the die 220 prior to attaching the die 230. In one embodiment, the epoxy flux material 238 cleans one or more respective bond pads 237 disposed on the backside 233 of the TSV die 230 and encapsulates the joints 240 formed between the one or more conductive bumps 222 disposed on the device side of the first die 220 and the one or more respective bond pads 237 disposed on the backside 233 of the TSV die 230. In an embodiment, the coupling by the one or more conductive bumps 222 disposed on the device side of the first die 220 and the one or more corresponding bond pads 237 disposed on the backside 233 of the TSV die 230 is performed by using a thermal compression bonding technique. In a particular embodiment, the backside of the TSV die 230 is heated to a temperature in the range of approximately 220-240 degrees celsius during the thermal compression bonding.

Fig. 2G shows a cross-sectional view during further processing of the device shown in fig. 2F, in accordance with an embodiment of the present invention. The sealing layer 242 is formed over the device side 231 of the TSV die 230 and the die bond pads 232. The sealing layer 242 surrounds all exposed regions of the first die 220 and the TSV die 230, as shown in fig. 2G. The sealing layer 242 may be a dielectric layer. In one embodiment, the sealing layer 242 is formed by a lamination process. In another embodiment, the sealing layer 242 is formed by spin coating and curing a dielectric on a wafer-level array of devices, where the devices 244 are only a subset of the array for ease of illustration.

Fig. 2H shows a cross-sectional view during further processing of the device shown in fig. 2G, in accordance with an embodiment of the present invention. Device 246 has been processed such that sealing layer 242 shown in fig. 2G has been patterned to form a patterned sealing layer 248 and a number of apertures, one of which is indicated with reference numeral 250, have been formed therein. The aperture 250 exposes the bond pad 232 of the TSV die 230. In some embodiments, a deeper aperture 251 may be formed to expose the package stack bond pad 208, as shown in fig. 2H. In one embodiment, carbon dioxide (CO) is used₂) Or an Ultraviolet (UV) treatment scheme, to form the aperture 250, the aperture 250 to be used to expose the TSV die 230Die bond pads 232, and package stack bond pads 208.

Carbon dioxide (CO) may be used₂) Ultraviolet (UV) laser beams or excimer laser beams. In an embodiment of the present application, the aperture 250 is formed to have a diameter between 30-50 microns. Laser drilling according to embodiments allows for higher connection densities than prior art drilling processes to achieve small via sizes and pitches, and in this way results in improved designs and scalable miniaturization at low cost. Additionally, laser drilling allows for high alignment accuracy (e.g., 10 to 15 microns) and throughput (about 2000 vias/second) as well as a wide range of possible via sizes (e.g., between 30 microns to about 300 microns) and low cost (about 2 cents per 1000 vias). The combination of high alignment accuracy and small via size enables possible via pitches as low as 60 microns, which are much smaller than the via pitch of about 400 microns used for typical plating on core-containing packages.

FIG. 2I shows a cross-sectional view during further processing of the apparatus shown in FIG. 2H, in accordance with an embodiment of the present invention. Conductive vias 252 are formed in the apertures 250 and fill the apertures 250. A routing layer 254 or trace is then formed and electrically coupled with TSV die 230 and package stack bond pad 208 through conductive via 252. In an embodiment, conductive vias 252 and routing layers 254 are comprised of copper, and bond pads 232 of TSV die 230 and package stack bond pads 208 are also copper. In an embodiment, other metals may be selected for conductive vias 252, routing layers 254, bond pads 232, and package stack bond pads 208. In an embodiment, conductive vias 252 and routing layers 254 are formed using a semi-additive process (SAP) to complete the remaining layers of a bumpless build-up layer (BBUL) process, as shown below in fig. 2K.

FIG. 2J illustrates a cross-sectional view during further processing of the device shown in FIG. 2I, in accordance with an embodiment of the present invention. The device 256 has been treated with a dielectric layer 258 such that the patterned encapsulation or dielectric layer 248 and the routing layer or trace 254 are encapsulated. The processing of dielectric 258 may be performed by lamination or by spin coating and curing the liquid precursor, and may be performed in the case of a wafer-level array.

Fig. 2K shows a cross-sectional view during further processing of the device shown in fig. 2L, in accordance with an embodiment of the present invention. It can now be appreciated that an external contact layer 260 having an array of external conductive contacts 262 for a bumpless build-up layer portion 264 is formed to couple the TSV die 230 to the outside world. Although the external contact layer 260 for the bumpless build-up layer is shown with patterned encapsulation or dielectric layer 248 and dielectric layer 258, it is understood that several layers of metallization layers and dielectrics can be used to form the bumpless build-up layer portion 264, which is ultimately a coreless substrate with embedded TSV die 230. An array of external conductive contacts 262 is disposed over and electrically coupled to one or more routing layers or traces 254. In an embodiment, it can be appreciated that no wiring from the first die 220 is required to communicate directly with the exterior of the coreless substrate 272.

Referring again to fig. 2K, layers 204 and 206 and thus the temporary core have been removed. In one embodiment, the external contact layer 260 is removed prior to removing the panel. In one embodiment, the array of external conductive contacts 262 is a Ball Grid Array (BGA). In other embodiments, the array of external conductive contacts 262 is an array such as, but not limited to, a Land Grid Array (LGA) or a pin array (PGA).

Thus, according to embodiments of the present invention, a panel is used to support the packaging of the TSV die until an array of outer conductive conduits is formed. The panel is then removed to provide a coreless package for the TSV die. Thus, in an embodiment, the term "coreless" is used to mean that the support on which the package for housing the die is formed is eventually removed at the end of the build-up process. In a particular embodiment, a coreless substrate is a substrate that does not include a thick core after the fabrication process is complete. As an example, the thick core may be composed of a reinforcing material such as that used in a motherboard, and may include conductive vias therein. It is understood that the die-bonding film 219 may remain as shown in fig. 2K, or may be removed. In either case, the inclusion or exclusion of the die-bond film 219 after the panel is removed will provide a coreless substrate. Additionally, the substrate may be considered a coreless substrate because it does not include a thick core such as fiber-reinforced glass epoxy.

In the case where multiple regions on both sides of the panel are used to package the TSV die, the apparatus shown in fig. 2J may be singulated (modified to include an external contact layer 260 for the bumpless build-up layer) by removing material within the dicing region 216 as shown in fig. 2B. With the cutting zone 216 removed, the adhesive release layer 212 and adhesive 214 (also shown and described in association with fig. 2B) allow the opposing devices to be separated.

Referring again to figure 2K, the global surface 270 of the die side of the coreless substrate 272 is closer to the land side 274 of the coreless substrate 272 than the backside 276 of the die-bonding film 219. Referring to figure 2K ', it can be appreciated that the global surface 270 ' of the die side of the coreless substrate 272 ' may be fabricated to be substantially planar with the backside 276 ' of the die-bond film 219 '. In an embodiment, such planarity is achieved by not including the second layer 206 on the panel, i.e., not including the recessed regions in the panel for packaging the first die with the TSV die (as shown in association with fig. 2B).

Thus, embodiments of the present invention enable the formation of multi-chip packages with thin package configurations and small footprint, thereby saving valuable space on the device motherboard. Additionally, embodiments of the present invention enable two dies to be electrically connected without using package-on-package (POP) technology, which requires Surface Mount Technology (SMT), but takes into account the problem of warpage with respect to the need. Additionally, in embodiments of the present invention, the substrate is formed using a low temperature bumpless build-up layer (BBUL) process in order to reduce or eliminate the effect of Coefficient of Thermal Expansion (CTE) mismatch between the embedded die and the substrate, thereby enabling the fabrication of a very flat multi-chip package.

FIG. 3 is a schematic diagram of a computer system 300 according to an embodiment of the invention. The illustrated computer system 300 (also referred to as electronic system 300) may embody an embedded TSV die coreless substrate (BBUL-CTSV die) in accordance with any of the several disclosed embodiments and their equivalents as set forth in this disclosure. Computer system 300 may be a mobile device, such as a netbook computer. Computer system 300 may be a mobile device, such as a wireless smart phone. The computer system 300 may be a desktop computer. The computer system 300 may be a handheld reader.

In one embodiment, electronic system 300 is a computer system that includes a system bus 320 for electrically coupling various components of electronic system 300. According to various embodiments, system bus 320 is a single bus or any combination of busses. Electronic system 300 includes a voltage source 330 that provides power to integrated circuit 310. In some embodiments, voltage source 330 provides current to integrated circuit 310 through system bus 320.

According to an embodiment, integrated circuit 310 is electrically coupled to system bus 320 and includes any circuit or combination of circuits. In an embodiment, integrated circuit 310 includes any type of processor 312. As used herein, processor 312 may represent any type of circuit, such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor, or another processor. In an embodiment, the processor 312 is an embedded stacked TSV die as disclosed herein. In an embodiment, the SRAM embodiment is present in a memory cache of the processor. Other types of circuits that may be included in the integrated circuit 310 are a custom circuit or an Application Specific Integrated Circuit (ASIC), such as a communications circuit 314 for wireless devices, such as cellular telephones, smart phones, pagers, portable computers, two-way radios, and similar electronic devices. In an embodiment, the processor 310 includes on-die memory 316, such as Static Random Access Memory (SRAM). In an embodiment, the processor 310 includes embedded on-die memory 316, such as embedded dynamic random access memory (eDRAM).

In an embodiment, integrated circuit 310 is supplemented with a subsequent integrated circuit 311 (such as an embedded stacked TSV die embodiment). Useful embodiments include dual processor 313, dual communication circuit 315, and dual on-die memory 317, such as SRAM. In an embodiment, the dual integrated circuit 310 includes embedded on-die memory 317, such as eDRAM.

In an embodiment, the electronic system 300 further includes an external memory 340, which external memory 340 may in turn include one or more memory elements suitable to the particular application, such as a main memory 342 in the form of RAM, one or more hard drives 344, and/or one or more drives that operate on removable media 346, such as floppy disks, Compact Disks (CDs), Digital Versatile Disks (DVDs), flash memory drives, and other removable media known in the art. The external memory 340 may also be an embedded memory 348, such as a first die embedded in an embedded TSV die stack, according to an embodiment.

In one embodiment, electronic system 300 further includes a display device 350, an audio output 360. In an embodiment, electronic system 300 includes an input device, such as controller 370, which may be a keyboard, mouse, trackball, game controller, microphone, voice-recognition device, or any other input device that inputs information into electronic system 300. In an embodiment, the input device 370 is a camera. In one embodiment, input device 370 is a digital sound recorder. In one embodiment, input devices 370 are cameras and digital sound recorders.

As shown herein, the integrated circuit 310 may be implemented in a number of different embodiments, including an embedded stacked TSV die, in accordance with the several disclosed embodiments and their equivalents, an electronic system, a computer system, one or more methods of manufacturing an integrated circuit, and one or more methods of manufacturing an electronic assembly that includes an embedded stacked TSV die in accordance with any of the several disclosed embodiments set forth herein in the several embodiments and equivalents thereof as would be recognized in the art. In accordance with several of the disclosed embedded TSV die embodiments and their equivalents, the elements, materials, geometries, dimensions, and sequence of operations may be varied to suit particular I/O coupling requirements, including the array contact count, array contact configuration of the microelectronic die embedded in the processor mounting substrate.

Thus, coreless substrates with embedded stacked through-silicon via die have been disclosed. In an embodiment, an apparatus includes a memory die having a device side and a backside. The apparatus also includes a logic die (logic TSV die) having one or more through-silicon vias disposed therein. The logic TSV die has a device side and a backside, and is disposed over and aligned with the memory die. The backside of the logic TSV die faces the device side of the memory die, and the memory die is electrically coupled to the logic TSV die through one or more through-silicon vias. The apparatus also includes a coreless substrate having a land side and a die side. The first die and the logic TSV die are both embedded in a coreless substrate. The back side of the memory die faces the die side of the coreless substrate, and the device side of the logic TSV die faces the land side of the coreless substrate. The device also includes an array of external conductive contacts disposed on the land side of the coreless substrate.

Claims (20)

1. An apparatus, comprising:

a first die;

a second die (TSV die) comprising one or more through-silicon vias disposed therein, the first die being electrically coupled to the TSV die through the one or more through-silicon vias; and

a coreless substrate, wherein the first die and the TSV die are both embedded in the coreless substrate.

2. The apparatus of claim 1, wherein the coreless substrate includes an encapsulation layer, and wherein the first die and the TSV die are embedded in the encapsulation layer.

3. The apparatus of claim 1, wherein the first die is coupled to the TSV die via the one or more through-silicon vias through one or more respective conductive bumps disposed on the first die and through one or more bond pads disposed on the TSV die.

4. The apparatus of claim 1, further comprising:

a layer of epoxy flux material disposed between the first die and the TSV die.

5. The apparatus of claim 1, wherein the coreless substrate has no routing layers between the first die and the TSV die.

6. The apparatus of claim 1, further comprising:

a die-bonding film disposed on the first die.

7. The apparatus of claim 1, wherein a surface of a first die protrudes from a surface of the coreless substrate.

8. The apparatus of claim 1, wherein a surface of the first die does not protrude from a surface of the coreless substrate.

9. The apparatus of claim 1, wherein a first die is fully embedded in the coreless substrate, and wherein the TSV die is fully embedded and enclosed in the coreless substrate.

10. A process, comprising:

bonding the backside of the first die to the panel with a die-bonding film;

coupling a backside of a second die (TSV die) having one or more through-silicon vias disposed therein over and through a device side of the first die;

forming a sealing layer over a device side of the TSV die, the sealing layer surrounding a first die and the TSV die; and then

Removing the panel from the die-bonding film.

11. The process of claim 10, wherein bonding the back side of the first die to the panel comprises: bonding a backside of the first die to a surface of a cavity disposed in the panel.

12. The process of claim 10, wherein bonding the backside of the first die to the panel with the die-bond film comprises: bonding is performed with an epoxy based material.

13. The process of claim 10, wherein coupling the backside of the TSV die to the device side of the first die comprises: the coupling is through one or more conductive bumps disposed on the device side of the first die and through one or more corresponding bond pads disposed on the backside of the TSV die.

14. The process of claim 13, wherein coupling the backside of the TSV die to the device side of the first die comprises: the backside of the TSV die is bonded to the device side of the first die with an epoxy flux material.

15. The process of claim 14, wherein the epoxy flux material cleans one or more respective landing pads disposed on the backside of the TSV die and encapsulates joints formed between one or more conductive bumps disposed on the device side of the first die and one or more respective landing pads disposed on the backside of the TSV die.

16. The process of claim 13, wherein coupling through the one or more conductive bumps disposed on the device side of the first die and the one or more corresponding bond pads disposed on the backside of the TSV die comprises using a thermal compression bonding technique.

17. The process of claim 16, wherein the backside of the TSV die is heated to a temperature in the range of approximately 220-240 degrees celsius during the thermal compression bonding.

18. The process of claim 10, further comprising:

forming one or more routing layers over the device side of the TSV die and electrically coupling the one or more routing layers with the device side of the TSV die prior to removing the panel.

19. The process of claim 18, further comprising:

forming an array of external conductive contacts over the one or more wiring layers and electrically coupling the array of external conductive contacts with the one or more wiring layers prior to removing the panel.

20. The process of claim 19, wherein forming the array of external conductive contacts comprises forming a Ball Grid Array (BGA).