HK1185993A - Source side asymmetrical precharge programming scheme - Google Patents

Description

Source side asymmetrical precharge programming scheme

The present application is a divisional application of the application having an application number of 200880004505.8, an application date of 2008/2/6, and an invention name of "source side asymmetric precharge programming scheme".

Cross Reference to Related Applications

This application claims priority from U.S. provisional patent application 60/888638, filed on 7/2/2007, which is incorporated herein by reference in its entirety.

Technical Field

The present invention generally relates to semiconductor devices. More particularly, the present invention relates to flash memory devices and flash device programming methods.

Background

Many types of consumer electronics products rely on some form of mass storage device for holding data or software for execution of code by a microcontroller. Such consumer electronics devices are abundant and include devices such as Personal Digital Assistants (PDAs), portable music players, Portable Multimedia Players (PMPs), and digital cameras. In the PDA, a mass storage device is required for saving applications and data, while a portable music player and digital camera require a large amount of mass storage device for holding music file data and/or image data. The mass storage solution for such portable electronic devices is preferably small in size, consumes minimal power, and has a high storage density. Because volatile memories, such as Static Random Access Memories (SRAMs) and Dynamic Random Access Memories (DRAMs), require constant application of power to retain data, the choice of memory is limited to non-volatile forms of memory. As is well known in the art, portable electronic devices rely on batteries with a limited power supply. Therefore, nonvolatile memory that retains data after power is removed is preferred.

While many consumer products use commercial flash memory, consumers indirectly use flash memory in products such as cellular phones and devices with microprocessor functionality. More specifically, Application Specific Integrated Circuits (ASICs), which are typically found in consumer electronics devices, have integrated flash memory to enable firmware upgrades. Needless to say, flash memory is widely used due to its best compromise in terms of size, storage density and speed, making it the preferred non-volatile mass storage solution for consumer electronics.

It is well known to those of ordinary skill in the art that flash memory devices are subject to program disturb. More specifically, when programming a selected memory cell by driving a corresponding selected word line to a programming voltage, unselected memory cells along that same word line that are not being programmed may be inadvertently soft programmed. This is due to the problem that the bias voltage to establish the program inhibit state for selected memory cells that are not being programmed is not sufficient to completely prevent those memory cells from being programmed. Furthermore, unselected memory cells in flash memory are also subject to program disturb because the voltage applied to unselected word lines during a program operation is too high, which can result in a shift in the programmed or erased threshold voltage. Sequential programming schemes have been used to solve this problem, however, the inhibition of random page programming operations results in reduced performance in applications due to the loss of operational flexibility associated with random page programming.

Disclosure of Invention

According to a first aspect of the present invention, a method is provided for programming a NAND flash string having a source line select device, memory cells, and a string select device connected in series between a bit line and a source line. The method includes biasing the bit lines, asymmetrically precharging groups of channels, and programming the selected memory cell. The bit line is biased to one of a first supply voltage level and a second supply voltage level. The grouping of channels corresponds to the memory cells being asymmetrically precharged to a different voltage level than the source line for setting the selected memory cell channel to a program inhibit state independent of background data stored in unselected memory cells. The selected memory cell is programmed only when the bit line is biased to the second supply voltage level, and remains in the program inhibit state when the bit line is biased to the first supply voltage level. According to an embodiment of the present aspect, programming the selected memory cell comprises driving the string selection device to the first supply voltage level for coupling the bit line to the selected memory cell only when the bit line is biased to the second supply voltage level. Asymmetric precharging can include biasing the source line to a string precharge voltage and coupling the source line to the memory cell by driving the source line select device to a source line pass voltage.

According to one aspect of the method, the asymmetric precharging includes precharging the lower channel, precharging the middle channel and precharging the upper channel. The lower channel corresponds to the memory cell between the source line select device and a first memory cell adjacent to the selected memory cell, is precharged to a first precharge voltage, and includes the selected memory cell and a second memory cell adjacent to the selected memory cell. The intermediate channel corresponds to the first memory cell, which is precharged to a second precharge voltage. The upper channel corresponds to the memory cell between the first memory cell and the string select device, which is precharged to a third precharge voltage. Precharging the lower channel includes driving a gate terminal of the memory cell between the source line select device and the first memory cell to a first pass voltage. Precharging the intermediate channel includes driving the gate terminal of the first memory cell to a second pass voltage, the second pass voltage being at least 0V, wherein the second pass voltage is greater than a threshold voltage of the programmed memory cell and less than the pass voltage. Precharging the upper channel includes driving a gate terminal of the memory cell between the first memory cell and the string select device to the first pass voltage. Thereafter, the upper channel is boosted by a difference between the first pass voltage and the second pass voltage to provide the third precharge voltage, wherein the second pass voltage is selected to be a value for turning off a first memory cell when the upper channel is at the third precharge voltage.

According to another aspect of the invention, precharging the lower channel further includes turning off the second memory cell and turning off the source line select device. Precharging the lower channel also includes locally boosting the selected memory cell channel to a voltage effective for inhibiting programming by driving the gate of the selected memory cell to a programming voltage. The programming voltage is greater than the first pass voltage, the string precharge voltage, and the source line pass voltage, and the string precharge voltage is at least the source line pass voltage. In yet another embodiment of the present aspect, the string precharge voltage and the source line pass voltage are at the first pass voltage. At least one memory cell between the selected memory cell and the source line select device corresponds to a programmed page, the at least one memory cell having one of a programmed threshold voltage and an erased threshold voltage. The first memory cell can correspond to a programmed page having one of a programmed threshold voltage and an erased threshold voltage. The memory cells between the selected memory cells and the source line select device correspond to erase pages having an erase threshold voltage or, alternatively, the memory cells between the selected memory cells and the string select device correspond to erase pages having an erase threshold voltage.

In a second aspect of the invention, a method is provided for programming a NAND flash string having a source line select device, memory cells, and a string select device connected in series between a bit line and a source line. The method includes biasing the bit line to one of a first supply voltage level and a second supply voltage level; precharging a channel group corresponding to the memory cell to a different voltage level than the source line for turning off a first memory cell adjacent to the selected memory cell; precharging the selected memory cell to a program inhibit state in response to the applied program voltage; and driving the string select device to the first supply voltage level for coupling the bit line to the selected memory cell only when the bit line is biased to the second supply voltage level. The selected memory cell remains in a program inhibit state while the bit line is biased to the first supply voltage level.

According to a third aspect of the present invention, a method is provided for programming a NAND flash string having a source line select device, memory cells, and a string select device connected in series between a bit line and a source line. The method includes driving all word lines to a first pass voltage, continuing to drive all word lines except the first word line to a second pass voltage, driving the second word line to a first supply voltage, driving a third word line to a programming voltage, and coupling the bit line to a selected memory cell. All word lines are driven to the first pass voltage for coupling a string precharge voltage provided by a source line to the memory cells, the string precharge voltage being greater than the first pass voltage. All word lines except a first word line corresponding to a first memory cell adjacent to the selected memory cell are driven to a second pass voltage greater than the first pass voltage, the first memory cell being between the selected memory cell and the string selection device. A second word line corresponding to a second memory cell adjacent to the selected memory cell is driven to the first power supply voltage for turning off the second memory cell. The third word line corresponding to the selected memory cell is driven to a programming voltage greater than the second pass voltage.

In an embodiment of the present invention, coupling the string precharge voltage comprises driving the source line select device to a source line pass voltage, and coupling the bit line comprises driving the string select device to the second supply voltage. In the present method, the programming voltage is greater than the second pass voltage, the string precharge voltage, and the source line pass voltage, the string precharge voltage is at least the source line pass voltage, and the first pass voltage is at least 0V. The string precharge voltage and the source line pass voltage are at the first pass voltage, and the first pass voltage is greater than a threshold voltage of programming memory cells. In another embodiment, the memory cells preceding the selected memory cell in a sequential programming direction include a first direction from the selected memory cell to the source line and a second direction from the selected memory cell to the bit line correspond to an erase page. In this embodiment, the first pass voltage is set to 0V in the second programming direction.

In a fourth aspect of the present invention, a flash memory device is provided. The flash memory device includes a driver and a controller. The driver drives a source line select device, a memory cell, and a string select device in series between a bit line and a source line. The controller controls the driver in a programming operation and is configured to drive all word lines of the memory cells to a first pass voltage to couple a string precharge voltage provided by the source line to the memory cells, the string precharge voltage being greater than the first pass voltage; continuously driving all word lines except a first word line corresponding to a first memory cell adjacent to the selected memory cell to a second pass voltage greater than the first pass voltage, the first memory cell being between the selected memory cell and the string selection device; driving a second word line corresponding to a second memory cell adjacent to the selected memory cell to the first supply voltage to turn off the second memory cell, driving the third word line corresponding to the selected memory cell to a programming voltage greater than the second pass voltage, and coupling the bit line to the selected memory cell.

In an embodiment of the present aspect, the driver includes a word line driver, a block decoder, and a row decoder. The word line drivers couple row signals to the memory cells, source select signals to source line select devices and string select signals to string select devices. The block decoder enables the word line driver in response to a block address, and the row decoder provides a row signal, a source selection signal, and a string selection signal in response to a row address. In yet another embodiment, the row decoder includes a row decoder circuit for providing one of the row signals, the row decoder circuit including a multiplexer for selectively coupling one of the programming voltage, the first pass voltage and the second pass voltage to the one of the row signals. The row decoder may include a row decoder circuit for providing a source select signal, the row decoder circuit including a multiplexer for selectively coupling one of VSS and a second pass voltage to the source select signal. The row decoder may provide a string select signal, the row decoder circuit including a multiplexer for selectively coupling one of VSS and VDD to the string select signal.

Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.

Drawings

Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram of a typical flash memory;

FIG. 2a is a circuit diagram of two NAND memory cell strings;

FIG. 2b is a plan layout of the two NAND memory cell strings shown in FIG. 2 a;

FIG. 2c is a cross-sectional view of one of the NAND memory cell strings shown in FIG. 2b along line A-A';

FIG. 3 is a distribution plot of threshold voltages (Vt) for erased memory cells and programmed memory cells;

FIG. 4 is a simulated graph of boosted channel voltage versus VDD relationship for different background data modes for a prior art NAND flash programming scheme;

FIG. 5 is a simulation plot of boosted channel voltage versus cell position for a prior art sequential programming scheme;

FIG. 6 is a simulated graph of boosted channel voltage versus VDD relationships for different background data modes for a prior art local boosted sequential programming scheme;

FIG. 7 is a distribution graph of threshold voltages (Vt) of erased memory cells and programmed memory cells after program disturb;

FIG. 8 is a flow chart illustrating an embodiment of a general NAND flash programming method;

FIG. 9 is a circuit diagram with two NAND memory cell strings annotated to show the relative positions of the channel groupings;

FIG. 10 is a flow diagram illustrating an embodiment of a source side asymmetric precharge programming scheme;

FIG. 11 is a timing diagram illustrating an example operation of a source side asymmetric precharge programming scheme embodiment;

FIG. 12 is a timing diagram illustrating another example operation of a source side asymmetric precharge programming scheme embodiment;

FIG. 13 is a timing diagram illustrating yet another example operation of a source side asymmetric precharge programming scheme embodiment;

FIG. 14 is a simulation plot of boosted channel voltage versus VDD relationships for different background data modes originating from a source side asymmetric precharge programming scheme embodiment;

FIG. 15 is a simulation plot of boosted channel voltage versus VDD for different background data modes of sequential programming operations using a source-side asymmetric precharge programming scheme;

FIG. 16 is a simulation diagram showing the relationship between boosted channel voltage and pass voltage for the present embodiment;

FIG. 17 is a block diagram of row circuitry for a multi-level flash memory device according to an embodiment of the present invention;

FIG. 18 is a circuit diagram of the block decoder and word line driver circuit shown in FIG. 17; and

fig. 19 is a circuit diagram of the row decoder circuit shown in fig. 17.

Detailed Description

In summary, the present invention provides a method for programming a NAND flash memory to minimize programming stress while allowing random page programming operations. The NAND strings are asymmetrically precharged from a positively biased source line, while the bit lines are decoupled from the NAND strings. Subsequently, a program voltage is applied to the selected memory cell, and then bit line data is applied. After asymmetrical precharging and application of the programming voltages, all selected memory cells will be set to a program inhibit state when they are decoupled from the other memory cells in their respective NAND strings, and their channels will be locally boosted to a voltage effective to inhibit programming. A VSS biased bitline will discharge the locally boosted channel to VSS, allowing programming of the selected memory cell to occur. The VDD biased bit line will have no effect on the precharged NAND string, thereby maintaining the program inhibit state of the selected memory cell. This NAND flash memory programming method will be referred to as a source side asymmetrical precharge programming scheme.

Fig. 1 is a general block diagram of a typical flash memory of the prior art. Flash memory 10 includes logic circuitry for controlling various functions of the flash circuitry, registers for storing addresses and data, high voltage circuitry for generating the required program and erase voltages, and core memory circuitry for accessing the flash memory array. The function of the illustrated circuit blocks of flash memory 10 should be well known in the art. Those of ordinary skill in the art will appreciate that flash memory 10 shown in fig. 1 represents one possible flash memory configuration of many possible configurations.

Fig. 2a, 2b and 2c are schematic diagrams of NAND memory cell strings used in the flash memory cell array shown in fig. 1. FIG. 2a is a circuit schematic of two NAND memory cell strings. FIG. 2b is a physical layout of the two NAND memory cell strings shown in FIG. 2 a. FIG. 2c is a cross-sectional view of one NAND memory cell string shown in FIG. 2b along line A-A'. In the example shown here, each NAND memory cell string includes 32 floating gate memory cells 50 connected in series, with each floating gate memory cell connected to a respective word line WL0-WL31, a string select transistor 52 connected between the bit line 54 and the first floating gate memory cell 50, and a ground select transistor 56 connected between the Common Source Line (CSL) 58 and the last floating gate memory cell 50. The gate of string select transistor 52 receives a string select signal SSL and the gate of ground select transistor 56 receives a ground select signal GSL. The NAND memory cell strings share a common word line, a string select SSL, and a ground select GSL signal line. Each memory cell 50, string select transistor 52, and ground select transistor 56 has a channel region 60 under the gate oxide between diffusion regions 62.

The structure and arrangement of the NAND memory strings shown are well known in the art and may include any number of memory cells per string. Typically, all memory strings connected in parallel to the same wordline, SSL and GSL form one memory block, and all memory cells connected in parallel to the same wordline form one memory page of the memory block.

According to techniques well known in the art, a NAND memory cell string of a memory array is first erased prior to any programming operation. Each block of NAND memory cell strings can be selectively erased so that one or more blocks can be erased simultaneously. This means that all pages of a memory block are erased simultaneously, while parts of the memory block can be selectively erased. Upon successful erasure, all erased floating gate memory cells 50 will have a negative threshold voltage. In fact, all erased memory cells 50 are set to a default logic state, such as, for example, a logic "1". The programmed memory cell 50 will have a threshold voltage that changes to a positive threshold voltage, thus representing the opposite "0" logic state.

FIG. 3 shows threshold voltage (Vt) distribution plots for erased and programmed memory cells. Due to process and voltage supply variations, erased and programmed threshold voltages will be distributed within a voltage range. For example, as shown in FIG. 3, erased memory cells will have a negative threshold voltage between-3V to-1V, while programmed memory cells will have a positive threshold voltage between 1V to 3V. In general, a cell is programmed by applying a high voltage to its gate while keeping its source and drain terminals at ground. The high electric field causes electrons in the channel of the memory cell to pass through the gate oxide and become embedded in the floating gate (known as Fowler-Nordheim (F-N) tunneling), thereby increasing the effective threshold voltage of the memory cell.

Programming is typically done through a page, meaning that all memory cells 50 in a block connected to the same word line are selected to be programmed with write data (logic "0") simultaneously. The remaining memory cells are therefore unselected during programming. Since the memory cell begins in the erased state (logic "1") prior to programming, only memory cells programmed with a logic "0" experience the high electric field needed to promote F-N tunneling. The selected memory cell is programmed by applying a program voltage VPGM to the gate of the selected memory cell. However, due to the physical connection of the memory array, all memory cells along the same word line receive the same high voltage programming level. As a result, erased memory cells will have a likelihood that their threshold voltages are inadvertently shifted. This is known as program disturb and is well known in the flash memory art. There are programming schemes known in the art for minimizing program disturb.

A well-known programming scheme is described in June Lee et al, "A90-nm CMOS1.8-V2-Gb NAND Flash Memory for Mass Storage Applications" (IEEE J Solid-State Circuits, Vol. 38, No. 11, pp. 1934-1942, 11. 2003, month 11). In this sequential programming scheme, referring to fig. 2a for example, the string select transistor 52 is turned on and the ground select transistor 56 is turned off, while the bitline voltage for the cell to be programmed is set to VSS and the bitline voltage for the cell to be program inhibited is set to VDD. The VSS biased bit line connects the channel of the corresponding NAND string to ground. When a program voltage (Vpgm) is applied to the gate of a selected memory cell, the large potential difference between the gate and the channel causes electrons F-N to tunnel onto the floating gate, thereby programming the cell. In a program-inhibited memory cell, the bit line initially precharges the channel of the NAND string. When the word line voltage of the NAND string rises to the program voltage Vpgm for the selected word line and to the pass voltage (Vpass) for the unselected word lines, the serial capacitances through the control gate, floating gate, channel and bulk are coupled and the channel potential is automatically boosted. Since the coupled channel voltage rises to VDD-Vth _ sst, where Vth _ sst is the threshold voltage of the string select transistor 52, the string select transistor 52 turns off and the channel becomes a floating node. It has been determined that the floating channel voltage rises to about 80% of the gate voltage. Accordingly, the channel voltage of the program-inhibited cell is raised to about 8V when the program Vpgm is between 15.5V and 20V and the pass voltage Vpass is 10V. This high channel voltage prevents F-N tunneling from occurring in program inhibited cells.

Unfortunately, this type of programming scheme suffers from a strong dependence on VDD. More specifically, the boosted channel voltage level strongly depends on the initial precharge level as a function of VDD. The maximum precharge level of the NAND string selected before channel boosting when all cells in the selected NAND string are in the erased state is VDD-Vth _ SST (Vth of SST). However, to reduce power consumption, a lower VDD voltage is highly desirable. In NAND flash memories, the typical VDD operating voltage is between 2.7V and 3.6V, regardless of the process node at that time. Even NAND flash memory devices at a process node of 50nm use VDD of 3.3V. Even though 1.8V is more desirable, the main reason for maintaining 3.3V is to reduce the programming stress.

Another problem with such a scheme is SSL to adjacent wordline coupling, which can negatively impact device performance. In a programming operation, after SSL is biased to VDD for coupling the bit line voltage to the NAND string, WL31 is raised from 0V to the pass voltage Vpass. Ideally, the boosted channel will rise to a level that turns off the string select transistor 52. However, SSL is temporarily raised by capacitive coupling with WL31, causing temporary activation of string select transistor 52. It should be noted that the boosted channel capacitance (5 fF) is 1 ten thousand times less than the bit line capacitance. Thus, although the string select transistor 52 operates in a subthreshold manner, the channel loses its boosted charge by sharing charge with the bit line. This is likely to result in the program inhibit cell being undesirably programmed by stress.

FIG. 4 is a simulation diagram of the June Lee et al sequential programming scheme showing the boosted channel voltage Vch _ boost for a selected memory cell relative to the power supply voltage VDD. In this simulation diagram, Vpgm =18V, Vpass =10V, the erase threshold voltage Vthc _ erase = -3V of the memory cell, and the program threshold voltage Vtch _ pgm =2V of the memory cell. Vch _ boost data is plotted for three different solutions. In a first scheme, all memory cells of a NAND string are erased. In a second solution, the memory cells of the NAND string have a checkerboard (checkerboard) data pattern. In a third scheme, unselected memory cells of the NAND string between the selected memory cell to be programmed and the bit line are programmed. The final boosted channel voltage (Vch _ boost) should be at least 7V to avoid soft programming (i.e., Vpgm stress) at Vpgm of 18V. However, Vch _ boost is lower than 6V when all the unselected cells in the NAND string are programmed. Thus, Vpass should be increased to reduce Vpgm stress, but the increased Vpass introduces more Vpass stress. Thus, the effect of program inhibit of such programming schemes is reduced due to background data mode dependency (BDPD). Furthermore, the simulation results show that Vch _ boost depends on VDD and becomes ineffective at inhibiting programming as VDD drops.

Thus, as process technology scales down, VDD should also be lowered. To comply with VDD scaling, random page programming is inhibited in the above-described boosted channel programming scheme, and memory blocks are limited to sequential programming in order to minimize programming stress. In sequential programming, the NAND string is programmed sequentially from the bottom page (LSB page) coupled to WL0 to the top page (MSB page) coupled to WL31, where the upper cells of the selected cells are always erased so that the unselected memory cells can fully transfer the initial precharge voltage from the bit line to the NAND string channel and thus result in a higher boosted program inhibit voltage. Those of ordinary skill in the art understand that random page program inhibit in a block will result in performance impairment in a particular application. Furthermore, sequential page programming does not eliminate BDPD and the Vpass voltage cannot be lowered to minimize programming stress. There are three possible situations that can affect the final boosted channel precharge voltage.

In the first case, page 0, corresponding to WL0, is programmed, while all the upper memory cells are in the erased state. The final boosted channel voltage will be about 9.6V, which is the best case solution. In the second case, page 15, which corresponds to WL15, is programmed, while all lower memory cells are programmed and all upper memory cells are erased. The final boosted channel voltage will be below 9.6V but greater than the following worst case solution. In the final third scenario, page 31 corresponding to WL31 is programmed, while all lower cells are programmed. The final boosted channel voltage will be about 6.5V.

Fig. 5 is a simulation result plotting boosted channel voltages for VDD =3.3V and VDD =1.8V versus BDPD results. The NAND string is programmed from the bottom memory cell coupled to WL0 to the top cell coupled to WL 31. When programming reaches the upper memory cell, the level of Vch _ boost is significantly reduced. Furthermore, when programming from WL25 to WL31, for VDD of 3.3V and 1.8V, the boosted channel voltage is below 6V, which is not high enough to inhibit programming. Thus, the prior art sequential programming scheme does not completely address the problem of programming stress.

Improvements to the above sequential programming scheme were obtained by local self-promotion, described in Tae-Sun Jung et al, "A117-mm 23.3-V Only128-Mb Multilevel NAND Flash memory for Mass Storage Applications" (Vol.31, No. 11, p.1575-1583, 11 months 1996). In the Tae-Sun Jung et al sequential programming scheme, Local Self Boosting (LSB) is used by decoupling the selected memory cell from the NAND string by lowering the gate voltage to 0V for the upper and lower adjacent memory cells of the selected memory cell. Thus, when a programming voltage is applied, the selected memory cell will experience a higher boosting in its channel relative to the prior art NAND string channels. However, the upper adjacent memory cell for the selected memory cell must be erased to pass the 0V bit line voltage for programming. Although the channel boosting of the selected memory cell is improved, random page programming still cannot be performed because the 0V level applied on the upper adjacent memory cell only allows it to pass the bit line voltage if erased.

FIG. 6 is a simulation plot of the resulting boosted channel voltage versus VDD relationship for four different technical schemes using the local boosted sequential programming scheme of Tae-Sun Jung et al. For this simulation, Vpgm =18V, Vpass =8V, the erase threshold voltage Vthc _ erase = -3V of the memory cell, and the program threshold voltage Vtch _ pgm =2V of the memory cell. In a first scheme, all lower memory cells of a selected memory cell of a NAND string are programmed. This corresponds to the plotted curve labeled "pppp" in fig. 6. In the second solution, all the lower memory cells are erased, which corresponds to the plotted curve labeled "eeee". In a third solution, the lower memory cells are alternately erased and programmed, which corresponds to the plotted curve labeled "epep". In a fourth solution, the lower memory cells are alternately programmed and erased, which corresponds to the plotted curve labeled "pepe". As shown in FIG. 6, the curves for "pppp", "eeee" and "epep" substantially overlap and all depend strongly on VDD. The "pepe" curve has a substantially smaller Vch _ boost relative to the other curves due to the dependence on background data, and also strongly depends on VDD. Thus, such conventional local self-boosting programming schemes do not continuously provide a boosted channel voltage sufficient to inhibit programming.

Thus, as shown in FIG. 7, NAND flash memory devices using prior art programming schemes still experience program voltage stress and pass voltage stress, resulting in shifted threshold voltages for programming and erasing memory cells. Furthermore, these drawbacks exist even when NAND flash memory cells are programmed sequentially, which limits the operational flexibility of the memory device. FIG. 7 shows a distribution of threshold voltages (Vt) of erased memory cells and programmed memory cells for program disturb. The solid line corresponds to the threshold distribution originally represented in fig. 3, while the dashed line shows the threshold distribution shifted due to program disturb. The offset may be due to the cumulative number of times the cell is disturbed, or due to a single program disturb event. This is problematic because the shifted threshold may affect a sensing operation using a preset word line sensing voltage based on the desired threshold voltage shown in fig. 3. As the voltage source VDD is also scaled down to lower levels, these aforementioned drawbacks continue to worsen as the semiconductor manufacturing process continues to scale down.

In the following description of the embodiments, the selected memory cell will refer to the memory cell in each NAND string coupled to the same word line addressed for a program operation. Accordingly, all selected memory cells refer to a page of data. The lower adjacent memory cell to the selected memory cell refers to a memory cell located between the selected memory cell and the source line. The upper adjacent memory cell to the selected memory cell refers to a memory cell located between the selected memory cell and the bit line. A programmed page of data will correspond to memory cells coupled to the same word line that have previously been subjected to a programming operation, which is either program inhibited or program allowed.

FIG. 8 is a flow chart illustrating a general method embodiment of a source side asymmetrical precharge programming scheme, see circuit diagram of the NAND string of FIG. 9. The circuit diagram of fig. 9 is the same as previously shown in fig. 2 a. The method of FIG. 8 begins with a first precharge step 100, where the source line is used to precharge the channels of the NAND string at step 100, and the particular channel regions of the memory cells corresponding to the NAND string are raised to different voltage levels. In this embodiment, the NAND string channel area is defined by the location of the selected memory cell, which is to be programmed. In the example shown in FIG. 9, the memory cell coupled to WL26 is the selected memory cell. In the case of a selected memory cell coupled to WL26, the channel of the memory cell coupled to WL0-WL 26 will be the lower channel 200 of the NAND string. Since these memory cells are close to the source line CSL, the label of "lower channel" is dedicated to the example of fig. 9. The channel of the upper adjacent memory cell corresponding to the selected memory cell coupled to WL27 is the middle channel 202 and the channels of the memory cells coupled to WL28 to WL31 are the upper channels 204. Typically, in a NAND string arrangement such as that shown in fig. 9, the lower channels are a serial grouping of channels proximate to the source line CSL, the upper channels are a serial grouping of channels proximate to the bit line (BL 0 or BL 1), and the intermediate channels are adjacent to the channel of the selected memory cell and the upper channels.

With this definition of the channel area of the NAND string, asymmetric precharging of the NAND string means that each of the lower, middle, and upper channels of the NAND string will be set to different voltage levels. More specifically, the end result of the asymmetric precharge is that the maximum number of positive voltages from CSL are transferred to the selected memory cell coupled to WL26, the source voltage of string select transistor 52 is greater than VDD-Vth _ sst, where Vth _ sst is the threshold voltage of string select transistor 52, and the memory cell corresponding to intermediate channel 202 is passively turned off due to the lower channel 200 and upper channel 204 being precharged. In this embodiment, since CSL is coupled to the NAND string through the ground select transistor 56, an asymmetric precharge is obtained by driving the word line to a different pass voltage. Additional details of these pass voltages are discussed below.

Once the NAND string has been set to the conditions indicated above, a second precharge step is performed at step 102 by setting the selected memory cell to a default program inhibit state. This is done by locally boosting the selected memory cell channel in response to an applied programming voltage. When the selected memory cell is locally boosted, this will be high enough to inhibit the occurrence of F-N tunneling, thereby inhibiting programming of the selected memory cell. Additional details of local boosting are described below. Note that since the bit lines are now decoupled from the NAND strings, the default program inhibit state is set for all selected memory cells, regardless of the bit line data. Steps 100 and 102 are taken together as the asymmetrical precharge phase of the source side asymmetrical precharge programming scheme embodiment described herein.

The programming phase then begins at step 104 by coupling all of the NAND strings to their respective bit lines. In one embodiment, the bitlines have been driven to VDD or VSS at steps 100 or 102, depending on the program data. If the bit line is at VDD, the selected memory cell remains in the default program inhibit state. If the bit line is at VSS, the channel of the selected memory cell is discharged to VSS by the bit line through the pair of the upper adjacent memory cell of the selected memory cell and the memory cell corresponding to the upper channel. Once the channel of the selected memory cell is discharged to VSS, the high potential difference between the channel and the programming voltage will be sufficient to initiate F-N tunneling, thereby programming the selected memory cell.

FIG. 10 is a flow chart of a method for programming a NAND flash memory cell string using minimum programming stress according to an embodiment of the invention. The description of the present method will be made with reference to the circuit schematic of the NAND string of fig. 9 and the timing diagram shown in fig. 11. The timing diagram of fig. 11 shows signal traces of the string selection signal SSL, the word lines WL0 to WL31, the ground selection signal GSL, and the common source line CSL. These signals are driven to voltage levels V1, V2, V3, V4 and V5 in the present programming method, with the following relationships:

(1)V1>V2>V3

(2)V5>=V4

(3) v3> Vthc _ pgm, where Vthc _ pgm is the threshold voltage for programming a memory cell.

Table 1 below lists sample values for the listed parameters to help illustrate the electrical effect of the programming scheme described herein. The sample values in table 1 may be used for specific processing techniques and cell characteristics. Those of ordinary skill in the art understand that these values will vary with different processing techniques, cell characteristics, and the number of memory cells per NAND string. All values except V3 and V4 are typically used for current NAND flash memory devices. Current NAND flash memory does not use V3 to pass the voltage and typically uses V4 between VSS and VDD.

TABLE 1

The initial state of all wordlines, CSL, SSL and GSL is VSS, and the selected memory cell to be programmed in this example is coupled to WL 26. The programming method begins at step 300 by biasing the source line CSL to V4, as shown between times T0 and T1 in FIG. 11. Followed by a first asymmetric precharge phase at step 302 for precharging the lower channel 200 and the upper channel 204 to different voltage levels. This first asymmetric precharge phase includes coupling CSL to the NAND string by driving GSL to V5 between times T1-T2 and driving all word lines except word line WL28 coupled to the upper adjacent memory cell to the selected memory cell to V2 between times T1-T2. WL27 is driven to the lower voltage level V3. The lower channel 200, including the unselected memory cells coupled to WL0-WL 26, will be precharged to at least V2-Vgst-Vthc-pgm. This assumes that at least one of the pages corresponding to WL0 through WL26 has been previously subjected to a program operation. Using the values in table 1, this is approximately 7.2V.

Because WL27 and WL28 are driven to WL31 from the initial 0V level, when these word lines reach 3V, both the middle channel 202 and the upper channel 204 will be precharged to at least V3-Vthc _ pgm, which is 2V using the values in table 1. Note that this is a worst case condition, and if the memory cell corresponding to the middle channel 202 is erased, the upper channel 204 will be precharged to a different voltage level. In the first case, if all memory cells corresponding to the lower channel 200 are in the erased state, the upper channel 204 will be precharged to either V3+ Vthc-erase (< V4) or V4 (< V3+ Vthc-erase). In the second case, if all the memory cells corresponding to the lower channel 200 are in a programmed state, the upper channel 204 will be precharged to either V3+ Vthc-erase (< V2-Vthc-pgm) or V2-Vthc-pgm (< V3+ Vthc-erase). This assumes that the upper adjacent memory cell to the selected memory cell coupled with WL27 is part of a page that was previously programmed to have a positive threshold voltage. On the other hand, if the upper adjacent memory cell to the selected memory cell is in the erased state, its channel is precharged to V3-Vthc-erase, which is 5V using the values of Table 1. The voltage level of word lines WL 28-WL 31 continues to V2, which causes the channel in the upper channel 204 to be boosted. More specifically, the upper channel 204 will be boosted by V2-V3, and the upper adjacent memory cell to the selected memory cell will be passively turned off even by the boosted channel voltage of the upper channel 204.

Followed by a second asymmetric precharge phase at step 304 for precharging the channel of the selected memory cell to a program inhibit state. This second asymmetric precharge phase begins at time T2 when the lower adjacent memory cell to the selected memory cell coupled to WL25 is turned off by driving WL25 to VSS, followed by turning off ground select transistor 56 by driving GSL to VSS between times T3 to T4. Thus, the selected memory cell coupled to WL26 is decoupled from the NAND string. Between times T4 and T5, WL26 for the selected memory cell is driven to the programming voltage V1, locally raising its channel to approximately Vbch = Vich + γ (V1-V2), where Vich is the precharge voltage level of the channel resulting from the first asymmetric precharge phase of step 302. Using the example values in table 1, Vbch =7.2V +0.7V (18V-10V) = 12.8V. The difference between the boosted channel voltage and the program voltage will inhibit F-N tunneling and is therefore referred to as the program inhibit state of the selected memory cell. Any voltage sufficient to inhibit programming in the presence of an applied programming voltage places the channel in a program inhibit state. Thus, all selected memory cells will be precharged to the program inhibit state at time T5.

The asymmetrical precharge phase of the presently described source side asymmetrical precharge programming scheme embodiment ends with the end of the second asymmetrical precharge phase. The second asymmetric precharge phase ends immediately after WL26 reaches V1 to cause a local boosting of the selected memory cell channel. Followed by a programming phase at step 306 in which bit line data is applied to the NAND strings. Note that the bit lines are driven to VDD or VSS in advance at any time prior to step 306. Between times T5 and T6, the string select transistors 52 are driven to VDD to couple the NAND strings to their respective bit lines. If the bit line is set to VDD, the string select transistor 52 remains off because its source and drain voltages are greater than Vth _ sst. More specifically, the source voltage is the boosted voltage level of the upper channel 204, while the drain voltage is at VDD. Thus maintaining the boosted charge in the channel of the selected memory cell, inhibiting programming.

On the other hand, if the bit line is set to VSS, the string select transistor 52 will be on. The upper channel 204 will discharge to VSS, which will turn on the upper adjacent memory cell to the selected memory cell to discharge the middle channel 202 to VSS. Thus, the boosted voltage level of the selected memory cell will discharge to VSS and establish the necessary voltage difference across its floating gate. The period between times T6 and T7 is the actual programming period in which electrons tunnel into the floating gate oxide of the selected memory cell coupled to the VSS biased bit line to effect programming. Those of ordinary skill in the art understand that the time periods T6 through T7 are greater than the time periods previously shown and are selected to ensure that the selected memory cell is sufficiently programmed. The actual length of the time periods T6 through T7 depends on the processing technology and voltage used. At time T7, the programming phase ends by driving WL26 to VSS, and at time T8 all remaining wordlines, SSL and CSL are driven to VSS.

The example operations described previously are based on selected memory cells being limited by upper and lower adjacent memory cells. There are two cases in which a selected memory cell is limited only by an upper adjacent memory cell and a lower adjacent memory cell. In the first case, the selected memory cell is coupled to the first word line WL0, and the closest memory cell is coupled to the source line CSL. In the second case, the selected memory cell is coupled to the last word line WL31, and the closest memory cell is coupled to the bit line. Fig. 12 and 13 are timing diagrams showing how the embodiment of the present NAND string programming method is applied to both cases.

FIG. 12 is a timing diagram similar to that shown in FIG. 11, showing the sequence of voltages applied to the NAND string of FIG. 2a when the selected memory cell is coupled to WL 0. The same time period shown in fig. 11 is shown in fig. 12. In this case, there is no memory cell adjacent to the lower portion of the selected memory cell. More specifically, only the ground select transistor 56 is present between the selected memory cell and the source line CSL. The main difference from the programming sequence of FIG. 11 is that the lower channel consists of only the selected memory cells. Because there is no lower adjacent memory cell to the selected memory cell to be turned off between times T2-T3 in step 304 of FIG. 13, the selected memory cell is subsequently decoupled by the act of turning off the ground select transistor 56 between times T3-T4. If desired, the time for turning off the ground select transistor 56 can be adjusted to occur earlier between times T2 and T3. The remaining programming sequence is unchanged relative to the sequence of fig. 11.

FIG. 13 is a timing diagram similar to that shown in FIG. 11, showing the sequence of voltages applied to the NAND string of FIG. 2a when the selected memory cell is coupled to WL 31. The same time period as shown in fig. 11 is shown in fig. 13. In this case, there is no upper adjacent memory cell to the selected memory cell. More specifically, only the string selection transistor 52 exists between the selected memory cell and the source line CSL. There is no intermediate channel and no upper channel between the selected memory cell channel and the bit line. Accordingly, the middle and upper channels do not need to be precharged between times T2 through T3 in step 302 to passively turn off the upper adjacent memory cell. With the lower adjacent memory cell to the selected memory cell coupled with WL30, string select transistor 52, which is turned off between time T1 to T5, will isolate the selected memory cell. The remaining programming sequence is unchanged relative to the sequence of fig. 11.

In the previously described embodiments, a number of characteristics should be noted. By setting CSL, GSL, and V2 to be the same, the lower channel 200, including the selected memory cell channel, will be precharged to a level independent of VDD without any channel boosting because the VDD biased bit line is not applied to the NAND string during the precharge phase. Even if all memory cells in the lower channel 200 have been previously programmed to a positive threshold voltage (which is a worst-case precharge solution), the combination of V2= GSL = CSL will ensure that the worst-case precharge level is V2-Vgst-Vthc _ pgm. When locally boosted, the selected memory channel will reach a high voltage level sufficient to minimize Vpgm stress. So that there is no background data pattern dependency affecting the programming or program inhibit of the memory cells corresponding to the lower channel 200.

By limiting only the word line voltage applied to the upper adjacent memory cell of the selected memory cell to a voltage below V2, the upper channel 204 will be boosted to passively turn off the upper adjacent memory cell when its corresponding word line continues to increase up to V2. Thus, active turn-off of the upper adjacent memory cell is not required, which simplifies the word line decode control logic.

When the selected memory cell has its word line driven to the programming voltage Vpgm, the precharged NAND string is responsive only to VSS biased bit lines after the precharge phase. Any bit line biased to VDD and applied to the precharged NAND string will have no effect on the precharged state of the NAND string and, more importantly, on the selected memory cell in the program inhibited state. Thus, there is no background data pattern dependency to affect programming and program inhibit of the memory cells corresponding to the middle channel 202 and the upper channel 204.

Random page programming can be performed because the gates of the upper adjacent memory cells to the selected memory cell are driven to V3, which is below V2 but greater than the programmed positive threshold voltage. So that the upper adjacent memory cell will always be on to couple the VSS biased bitline to the selected memory cell. The effectiveness of the presently described NAND flash programming scheme has been simulated and the results are shown in figures 14 to 16.

FIG. 14 is a simulation graph showing the boosted channel voltage Vch _ boost for a selected memory cell with respect to the power supply voltage VDD using the same voltages used in the previously described source side asymmetric precharge programming scheme embodiment of the present invention and the simulation shown in FIG. 13. In this simulation diagram, Vpgm =18V, Vpass = GSL = CSL =10V, V3=4V, Vth _ erase = -3V, and Vth _ pgm = 2V. Three Vch _ boost curves are plotted, one for the case where all memory cells are erased, one for the case where all memory cells are programmed, and one for the case where the NAND string includes a combination of erased and programmed memory cells. For the case where there are erased and programmed memory cells in the NAND string, the minimum final boosted channel voltage Vch _ boost is between 8V and 9V, which is sufficient to avoid soft programming (i.e., Vpgm stress) at Vpgm of 18V. It is worth noting that Vch _ boost is between 9V and 10V for the case of programming all memory cells, and between 13V and 14V for the case of erasing all memory cells. If the minimum required final boosted channel voltage for the selected memory cell should be 7V in the presently described example, then there is a tolerance for a reduction of Vpass from 10V to minimize Vpass stress for the unselected memory cells. In comparison to the simulated plot of the prior art programming scheme of FIG. 4, it should be clear that the presently described embodiments will continue to provide a larger final boosted channel voltage for the selected memory cell.

The situation in fig. 14 where all memory cells are in an erased state is similar to a sequential programming scheme that requires a certain memory cell to be in a programmed state. Thus, Vpass is further reduced by applying the source side asymmetric precharge programming scheme previously described to sequential program operations. In the sequential programming operation, the basic timing for applying the signals shown in fig. 11 to 13 is the same. According to the present embodiment, sequential programming using the source side asymmetric precharge programming scheme may be performed in any direction. The first direction of sequential page programming may be from the uppermost memory cell coupled to WL31 to the lowermost memory cell coupled to WL0, while the second direction is from the lowermost memory cell coupled to WL0 to the uppermost memory cell coupled to WL 31. So that when programmed sequentially in either of the first and second directions, there is always an erased page of memory cells before the memory cells selected in the programming direction. Regardless of the programming direction, the bias conditions for the word line, SSL, GSL, and CSl remain the same as previously described for the NAND string with lower channel 200, middle channel 202, and upper channel 204.

Returning to FIG. 9, and using the example values of Table 1, the lower channel 200 is always precharged to V4 since all memory cells are in the erased state. Because there is background data for accounting in the memory cells corresponding to the middle channel 202 and the upper channel 204, the middle channel 202 and the upper channel 204 will be precharged to at least the same value as previously described. It should be clear to one of ordinary skill in the art that in the case of such a high initial pre-charged channel for a selected memory cell, the local boosting will further increase its channel voltage. The pass voltage V2 can thus drop from 10V to a level that is still greater than V3, but high enough to ensure that the resulting boosted channel of the selected memory cell can inhibit programming. Thus, when the disclosed NAND flash memory programming method is used to sequentially program NAND strings, completely stress-free (Vpgm stress-free and Vpass stress-free) programming is achieved.

Fig. 15 is a simulation plot plotting the final boosted channel voltage Vch _ boost versus VDD for selected memory cells of four different schemes. In this simulation diagram, Vpgm =18V, V2= CSL = GSL =8V, V3=4V, Vthc _ erase = -3V and Vthc _ pgm = 2V. In a first scheme, all lower memory cells of a selected memory cell of a NAND string are programmed. This corresponds to the plotted curve labeled "pppp" in fig. 6. In the second solution, all the lower memory cells are erased, which corresponds to the plotted curve labeled "eeee". In a third solution, the lower memory cells are alternately erased and programmed, which corresponds to the plotted curve labeled "epep". In a fourth solution, the lower memory cells are alternately programmed and erased, which corresponds to the plotted curve labeled "pepe". The simulation results show that even after the pass voltage V2 is reduced from 10V to 8V, the boosted channel voltage is still greater than 11V, regardless of the background data mode. This is high enough to inhibit programming in the selected memory cell. Therefore, there is still some margin for lowering the pass voltage V2 while maintaining the effective program inhibit state of the selected memory cell.

To determine the optimum pass voltage level for a sequential programming operation using an embodiment of the programming method, a simulation plot of the final boosted channel voltage Vch _ boost versus V2 is plotted in fig. 16. For this simulation plot, Vpgm =18V, V3=4V, Vthc _ erase = -3V, Vthc _ pgm =2V, VDD =1.8V, and CSL = GSL = V2. If all memory cells in the lower channel 200 are in the erased state, FIG. 16 shows that the final Vch _ boost level of the selected memory cell will be between 6V and 7V when V2 is set to 5V. When this is the minimum effective program inhibit voltage used at Vpgm =18V, setting V2 to 6V will result in Vch _ boost rising significantly above 8V. Further raising to V2 will further raise Vch _ boost. Thus, V2 can be selected to minimize Vpass stress for unselected memory cells and to minimize Vpgm stress. For example, under these example conditions, when V2 is 7V, the unselected erased memory cells will not experience any Vpass stress, while the selected memory cells with a boosted channel voltage of 11V will not experience any Vpgm stress. Accordingly, the programming of the NAND string is stress-free.

Most NAND flash memory devices perform Incremental Step Pulse Programming (ISPP) to achieve fast programming performance under process and environmental variations while maintaining tight program cell disturb. Typically in ISPP operations, the initial Vpgm is about 16V. After the initial 16V programming pulse, each subsequent pulse required is increased in steps of 0.5V up to 20V. In prior art programming schemes, Vpass determines the final boosted channel voltage Vch _ boost. To reduce Vpgm stress, Vpass should increase as Vpgm increases. Thus, Vpass will need to have a maximum value at the maximum Vpgm level that is high enough for data "1" to inhibit programming. As shown in the simulation results of this embodiment, a single Vpass level may be selected such that one final Vch _ boost level is effective for minimizing Vpgm stress for a range of Vpgm values. This means that Vpgm can be stepped from a minimum value to a maximum value without the need to adjust Vpass. This further reduces the overhead of the word line control logic.

In summary, the source side asymmetrical precharge programming scheme embodiments described previously use source side precharging of NAND strings to asymmetrically precharge its channel groupings to different voltage levels, with these channel groupings being accurately labeled by the location of the selected memory cell to be programmed. The goal of asymmetric precharging is to set the selected memory cell to a program inhibit state by raising the channel of the memory cell between the upper adjacent memory cell and the bit line to a level sufficient to turn off the upper adjacent memory cell. When the lower adjacent memory cell is turned off, the selected memory cell is completely decoupled from the NAND string. A program voltage is applied to a selected memory cell to locally raise its channel to at least a program inhibit voltage level without applying bit line data. So that after the asymmetrical precharge, all selected memory cells are set to a program inhibit state by default. Only the NAND string that is then coupled to VSS discharges the selected memory cell channel to VSS, establishing the conditions under which programming of the selected memory cell occurs.

Particular performance advantages result from the NAND flash programming embodiment described previously. Since SSL remains at VSS throughout the precharge phase, the application of the pass voltage has little effect on the capacitive coupling of the string select transistors 52. Thus, the boosting efficiency of the NAND string channel is maximized. Since the boosted channel voltage of the selected memory cell will always be at a minimum level sufficient to inhibit programming, a random page programming operation can be performed regardless of the background data pattern and the VDD level in the NAND string. Sequential programming operations may be performed using the reduced pass voltages to relieve Vpass stress on unselected memory cells.

Those of ordinary skill in the art will appreciate that there may be a plurality of circuits for controlling the word lines in the manner shown in the embodiments and that there are a variety of well known voltage generators for generating and supplying voltages greater than VDD to the word line control circuits. The use of exemplary row control logic to control word lines WL0-WL31, string select lines SSL, and ground select lines GSL in accordance with the previously described method embodiments of the source side asymmetric precharge programming scheme is illustrated in FIGS. 17-19.

FIG. 17 is a block diagram of exemplary row control logic or drivers. Driver 400 includes block decoder 402, row decoder circuit 408, and word line driver circuit 410. The row control logic is controlled by control circuitry, such as a command decoder in the flash memory device, for example, in response to received commands, such as read and program commands. The command decoder of the flash memory device will be configured to perform an embodiment of the source side asymmetric precharge programming scheme. The device with row control logic 400 has a high voltage generator 4046 which may be used by other circuitry not shown in figure 17. Generally, the high voltage generator 404 will generate at least a programming voltage V1, a pass voltage V2, a reduced pass voltage V3, also referred to as a decoupling voltage Vdcp, a CSL voltage V4, and a GSL voltage V5. Each memory block has a block decoder 402 that receives a block address BA for activating wordline drivers. All memory blocks share a row decoder 408, which receives a row address RA _ b and other signals not shown, for generating source select signals SSL, wordline signals S [0: n ], and ground select signals GSL, collectively referred to as row signals. During a programming operation, signals SSL, GSL and WL0-WLn are set to their desired voltage levels in response to the valid block address BA and row decoder signals.

Fig. 18 is a circuit schematic diagram showing circuit details of the block decoder 402 and the word line driver circuit 410 of fig. 17. The block decoder 402 is associated with one memory block and includes a cross-coupled inverter latch circuit and a level shift circuit. The latch circuit includes cross-coupled inverters 500 and 402, an n-channel reset transistor 404, and n-channel enable transistors 406 and 408. When the latch enable signal LTCH _ EN and the block address BA are at the high logic level, the latch circuit is enabled or set. When the signal RST _ BD is at a high logic level, the latch circuits of the inverters 500 and 502 are reset. The level shifting circuit includes a pair of cross-coupled p-channel transistors 510 and 512, each connected to a respective n-channel steering transistor 514 and 516. The shared terminals of transistors 510 and 512 receive a high voltage Vh, while the shared terminals of transistors 514 and 516 receive a negative voltage Vn. Node Vh is connected to a positive voltage generator 404, while node Vn is connected to VSS or alternatively to a negative voltage generated by a negative voltage generator (not shown). Steering transistors 514 and 516 have gate terminals connected to the output of inverter 500 and inverter 518, with the input of inverter 518 connected to the gate of transistor 514. Note that if Vn is a negative voltage, the high voltage source provided to inverter 500 is lower than Vh, while the low voltage source provided to inverter 502 is VSS or higher than Vn. The output (enable signal) BD _ out of the level shift circuit drives the gate terminals of all n-channel pass transistors 520 of the wordline driver 410. The substrate terminals of all pass transistors 520 are connected to Vn. Each pass transistor is capable of selectively passing Source Select (SS), word line (S0-Sn), and Ground Select (GS) signals to the memory array. Placeholder "n" can be any non-zero integer, typically corresponding to the maximum number of cells in a string of flash cells. The overall operation of the block decoding circuit will now be described.

For example, in a programming operation, one memory block is selected while the other blocks remain unselected. In other words, one memory block is enabled while the remaining memory blocks are disabled. To enable one memory block, LTCH _ EN and BA will be at a high logic level, setting the level shifting circuit to output a high voltage Vh. Thus, all pass transistors 520 of the word line driver circuit 410 are turned on. According to the source side asymmetric precharge programming scheme embodiment described previously, word line signal S0-Sn and signals SS and GS will be driven to different voltage levels. The non-enabled memory block has its corresponding block decoder circuit output set to output a low voltage Vn. Thus, all pass transistors 520 in the unselected memory blocks will be turned off.

Fig. 19 is a circuit schematic diagram showing one row decoder circuit of the row decoder 408 of fig. 17. The presently shown schematic diagram of fig. 19 is only a functional representation, as there may be different specific circuit implementations possible. Fig. 19 shows a circuit for generating a row signal Si, where i may be an integer value between 0 and n, but the circuits for generating signals SS and GS are similarly configured. The row decoder circuitry includes a multiplexer 600 for receiving all voltages used during program, program verify, read, erase and erase verify operations. To simplify the schematic of FIG. 19, multiplexer 600 is configured to show voltages only for the source side asymmetric precharge programming scheme embodiment. This includes, for example, the program voltage V1 (Vpgm), the pass voltage Vpass (V2), the reduced pass voltage Vdcp (V3), VDD, and VSS. Although not shown, the row decoder for providing GSL will have a multiplexer that receives voltage V5 as well as other voltages. Similarly, the row decoder for providing SSL will have a multiplexer that receives the supply voltage VDD as well as other voltages.

Any number of voltages may be provided to multiplexer 600 and then selectively transmitted to node Sn. The voltage select signal Vselect is used to transmit any one of the voltages. Those of ordinary skill in the art will appreciate that Vselect will be a multi-bit signal, the number depending on the number of input ports multiplexer 600 is configured with. When a block is unselected, n-channel disable transistor 602 couples Si to VSS when RA _ b is at a high logic level. In a program operation, the inhibit transistor is turned off and Vselect is controlled by control logic such as a command decoder to couple the necessary voltage to Si. In one embodiment, there is one Vselect signal for each row decoder circuit 408 of a block. Thus, one Vselect signal for row S1 in one block can be used for row position S1 in the other block.

In the previous description, for purposes of explanation, numerous details were set forth in order to provide a thorough understanding of the embodiments of the invention. However, it will be apparent to one of ordinary skill in the art that these specific details are not required in order to practice the present invention. In other instances, well-known electrical structures and circuits are shown in block diagram form in order not to obscure the present invention. For example, specific details are not provided as to whether the embodiments of the invention described herein are implemented as a software program, hardware circuitry, firmware, or a combination thereof.

In the above embodiments, the device components are interconnected as shown for simplicity. In practical applications of the present invention, devices, apparatuses, components, circuits, etc. may be directly connected to each other. Likewise, devices, apparatuses, circuits, and the like may be indirectly connected to each other through other devices, apparatuses, circuits, and the like that are necessary for the operation of the devices. Thus, in actual configuration, the circuit components and devices may be directly or indirectly coupled or connected to each other.

The above-described embodiments of the present invention are intended to be examples only. Alterations, modifications and variations may be effected to the particular embodiments by those of skill in the art without departing from the scope of the invention, which is defined solely by the claims appended hereto.

Claims (14)

1. A method for programming a NAND flash string having a source line select device, memory cells, and a string select device connected in series between a bit line and a source line, comprising:

driving all word lines to a first pass voltage for coupling a string precharge voltage provided by a source line to the memory cells, the string precharge voltage being greater than the first pass voltage;

continuously driving all word lines except a first word line corresponding to a first memory cell adjacent to the selected memory cell to a second pass voltage greater than the first pass voltage, the first memory cell being between the selected memory cell and the string selection device;

driving a second word line corresponding to a second memory cell adjacent to the selected memory cell to a first power supply voltage for turning off the second memory cell;

driving a third word line corresponding to the selected memory cell to a programming voltage greater than the second pass voltage; and is

Coupling the bit line to the selected memory cell.

2. The method of claim 1, wherein coupling the string precharge voltage comprises driving the source line select device to a source line pass voltage.

3. The method of claim 1, wherein coupling the bit line comprises driving a string select device to the second supply voltage.

4. The method of claim 2, wherein the programming voltage is greater than the second pass voltage, the string precharge voltage, and the source line pass voltage, the string precharge voltage is at least the source line pass voltage, and the first pass voltage is at least 0V.

5. The method of claim 4, wherein the string precharge voltage and the source line pass voltage are at the first pass voltage.

6. The method of claim 4, wherein the first pass voltage is greater than a programmed memory cell threshold voltage.

7. The method of claim 4, wherein said memory cells preceding said selected memory cell in a sequential programming direction correspond to erased pages.

8. The method of claim 7, wherein the sequential programming directions include a first direction from the selected memory cell to the source line, and a second direction from the selected memory cell to the bit line.

9. The method of claim 8, wherein in the second programming direction, the first pass voltage is set to 0V.

10. A flash memory device, comprising:

a driver for driving the source line select device, the memory cells and the string select device in series between the bit line and the source line; and

a controller for controlling the driver in a programming operation, the controller being configured to

Driving all word lines of the memory cells to a first pass voltage for coupling a string precharge voltage provided by the source line to the memory cells, the string precharge voltage being greater than the first pass voltage;

continuing to drive all word lines except a first word line corresponding to a first memory cell adjacent to the selected memory cell to a second pass voltage greater than the first pass voltage, the first memory cell being between the selected memory cell and the string select device;

driving a second word line corresponding to a second memory cell adjacent to the selected memory cell to the first power supply voltage for turning off the second memory cell,

driving the third word line corresponding to the selected memory cell to a programming voltage greater than the second pass voltage, and

coupling the bit line to the selected memory cell.

11. The flash memory device of claim 10, wherein the driver comprises:

word line drivers for coupling row signals to the memory cells, source select signals to source line select devices, and string select signals to string select devices;

a block decoder for enabling the word line drivers in response to block addresses, an

A row decoder for supplying the row signal, the source selection signal and the string selection signal in response to the row address.

12. The flash memory device of claim 11, wherein the row decoder includes a row decoder circuit for providing one of the row signals, the row decoder circuit including a multiplexer for selectively coupling one of the programming voltage, the first pass voltage, and the second pass voltage to the one of the row signals.

13. The flash memory device of claim 12, wherein the row decoder includes a row decoder circuit for providing the source select signal, the row decoder circuit including a multiplexer for selectively coupling one of VSS and the second pass voltage to the source select signal.

14. The flash memory device of claim 12, wherein the row decoder includes a row decoder circuit for providing the string select signal, the row decoder circuit including a multiplexer for selectively coupling one of VSS and VDD to the string select signal.