HK1174750B - Circuits, systems, and methods for managing automatic gain control in quadrature signal paths of a receiver - Google Patents

Description

Circuit, system and method for managing automatic gain control in quadrature signal path of receiver

Technical Field

The present disclosure relates generally to circuits, systems, and methods for managing automatic gain control in quadrature signal paths of a receiver

Background

Radio Frequency (RF) transceivers are found in many one-way and two-way communication devices, such as portable communication devices, (cellular telephones), Personal Digital Assistants (PDAs), and other communication devices. An RF transceiver transmits and receives signals using any communication method dictated by the particular communication system in which it operates. For example, the communication method generally includes amplitude modulation, frequency modulation, phase modulation, or a combination of these, and data is transmitted using a Gaussian Minimum Shift Keying (GMSK) modulation scheme in the global system for mobile communication (GSM) which is a typical mobile communication system using narrow-band Time Division Multiple Access (TDMA).

Deployment of new wireless systems presents unique challenges to mobile handset designers. To benefit from the expanded capacity and increased data bandwidth, next generation handsets are expected to operate using multiple communication systems.

WCDMA (wideband code division multiple access) is a radio access scheme for third generation (3G) cellular systems that are in use worldwide. The 3G system supports high-speed internet access, video, and high-quality image transmission services. In WCDMA systems, a CDMA air interface (air interface) is combined with a GSM-based network including enhanced data rates for GSM evolution (EDGE) networks.

Conventional WCDMA and GSM/EDGE receiver architectures use a pair of circuits driven by a mixer (mixer) to separate the components of the received signal. Typically, the sine and cosine components of the received carrier signal are applied to a mixer to extract the separate components. This "mixing" of the carrier signals produces what is referred to as an in-phase or "I" signal component and a quadrature-phase or "Q" signal component. These I and Q signal components are filtered, gain/phase adjusted and ultimately sent to a baseband digital signal processor to extract the transmitted data.

In cellular communication systems, the signal transmitted from a base station is generally constant and at a level that provides the overlapping area with its nearest neighbor base station in the cellular network. Thus, a mobile transceiver located relatively close to a base station receives a reception channel signal having a higher signal strength than a mobile transceiver located farther from the base station. Thus, a large dynamic range is required for the receiver of such a mobile transceiver to ensure that the mobile transceiver can handle power levels throughout the entire range of the received signal without distortion. This is typically accomplished using some manner of received signal gain adjustment.

Prior art methods of adjusting gain include Automatic Gain Control (AGC) systems implemented in the baseband portion of the transceiver. These prior art baseband approaches do not take into account the intermittent presence of jammers or blockers (blockers) in the RF section of the transceiver. For example, in a digital video broadcasting-handheld system (DVB-H), the desired received signal may suddenly be affected or "blocked" (jam) by GSM transmitter blockage of circuitry compressing the receiver front-end. In addition, these prior art systems must often monitor and correct for changing signal conditions due to relative movement between the mobile transceiver and the nearest base station, as well as relative movement of other objects in the path between the mobile transceiver and the nearest base station. These digital gain control systems typically do not provide accurate power control in environments where signal strength varies rapidly over a large dynamic range.

Disclosure of Invention

Circuits, systems, and methods for managing AGC in quadrature paths of an RF subsystem of a wireless communication system are disclosed.

One embodiment of a method for managing AGC in a quadrature signal path of an RF subsystem of a wireless communication system comprises the steps of: determining a first signal strength at an input of a channel selection filter and a second signal strength at an output of the channel selection filter; comparing the first and second signal strengths to detect when a blockage is present in the orthogonal signal path of the receiver and forwarding a blockage present signal to an analog control branch of the AGC circuit when the blockage is present; generating an analog control signal in an analog control branch of the AGC circuit in response to the blocker presence signal, the analog control signal configured to adjust at least one controllable gain element in the analog receiver path in response to the presence of the blocker to prevent saturation of an analog-to-digital converter in a digital receiver path coupled to the analog receiver path; a difference between a second signal strength at an output of the channel selection filter and a reference signal power is determined and applied to the AGC circuit having a loop filter coupled to the analog control branch and a digital control branch that produces a digital control word configured to adjust a sealer coupled to the channel selection filter.

One embodiment of a system for AGC in an RF subsystem of a wireless communication system comprises: a power estimator, a blocking identification element, a converter and an AGC circuit. The power estimator receives a first input from the digital receiver path and a second input from the channel selection filter. The power estimator generates a first estimate of the signal power appearing at the output of the digital receiver path and a second estimate of the signal power appearing at the output of the channel selection filter. The occlusion identification element receives the first estimate and the second estimate from the power estimator and generates an occlusion present signal when a function of the first estimate and the second estimate exceeds a threshold. The converter is coupled to an output of the power estimator and produces a logarithmic representation of the power in the digital receiver path. The AGC circuit receives the difference between the blocker presence signal and a logarithmic representation of the reference signal and the received signal power in the digital receiver path. The AGC circuit includes a loop filter, an analog control branch, and a digital control branch. The analog control branch generates a control signal that is coupled to one or more elements in the analog receiver path. The digital control branch generates a control word that is applied to the sealer. The control signal and the control word distribute gain between analog and digital components in a quadrature signal path of the radio frequency subsystem.

One embodiment of a circuit for AGC in an RF subsystem of a wireless communication system comprises: a receiver having an analog receiver path coupled to a digital receiver path, an output of the digital receiver path coupled to a sealer and an AGC circuit. The AGC circuit includes an analog control branch and a digital control branch. The analog control branch includes a first feedback adder and a look-up table. The analog control branch is responsive to the gain value received from the baseband element and to a first calibration value. The analog control branch generates an analog control signal configured to adjust at least one controllable element in the analog receiver path. The digital control branch includes a second feedback adder, a programmable delay element, and a converter element. The digital control branch generates a control word in response to the gain value received from the baseband element, the second calibration value, and the delayed representation of the analog control signal.

The drawings and detailed description that follow are not exhaustive. The disclosed embodiments are illustrated and described to enable one of ordinary skill in the art to make and use circuits, systems, and methods for managing AGC in quadrature signal paths of a receiver. Other embodiments, features, and advantages of the circuits and methods will become apparent to one with skill in the art upon examination of the following figures and detailed description. All such additional embodiments, features and advantages are within the scope of the disclosed circuits, systems and methods as defined in the appended claims.

Drawings

The circuitry, systems, and methods for managing AGC in the quadrature path of an RF subsystem of a wireless communication system may be better understood with reference to the following drawings. The components within the figures are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles and operations of the circuits, systems, and methods. Moreover, in the figures, like reference numerals designate corresponding parts throughout the different views.

Fig. 1 is a block diagram illustrating a simplified wireless system including a radio frequency automatic gain control (RF AGC) system.

Fig. 2 is a functional block diagram illustrating an exemplary embodiment of a WCDMA receiver.

Fig. 3 is a functional block diagram illustrating an embodiment of the WCDMA receiver of fig. 2.

FIG. 4 is a state diagram illustrating an embodiment of a controller.

Fig. 5 is a functional block diagram of an alternative embodiment of the AGC circuit of fig. 1.

Fig. 6 is a flow diagram illustrating an embodiment of a method for managing automatic gain control in an orthogonal path of a radio frequency subsystem of a wireless communication system.

Fig. 7 is a flow diagram illustrating an alternative embodiment of a method for managing automatic gain control in an orthogonal path of a radio frequency subsystem of a wireless communication system.

FIG. 8 is a flow diagram illustrating an embodiment of a method for converting a voltage to a value in decibels.

Fig. 9 is a flow diagram illustrating an embodiment of a method for generating a correction factor for conversion from linear units of gain to decibels.

Fig. 10 is a diagram illustrating an uncorrected error due to a power of 2 conversion.

FIG. 11 is a flow diagram illustrating an embodiment of a method of generating a correction factor for conversion from decibels to linear units of gain.

Detailed Description

A system provides AGC in an RF portion of a wireless communication system. An embodiment of an RF AGC system includes a power estimator, a blockage identification element, a controller, and an AGC circuit. In this embodiment, the RF AGC system provides closed loop control of one or more elements in the analog receiver path and closed loop control of a scaler (scaler) coupled between the digital receiver path and the baseband subsystem. The circuit elements in the rf agc system operate on values using a logarithmic scale.

The power estimator receives a first input from the digital receiver path and a second input from the output of the channel selection filter. The power estimator generates a first estimate in response to received signal power from the digital receiver path and generates a second estimate in response to received signal power at the output of the channel selection filter and forwards the first and second estimates. The power estimator forwards the first and second estimates to the congestion identification element. When the signal samples are processed at half the receiver sampling rate, the same power estimator can be used to determine the signal power before and after the channel selection filter.

The blockage identification element compares a function of the first and second estimates to a threshold to determine when blockage occurs in the receiver. When blocking occurs, the AGC circuit forwards a control signal to adjust gain in the analog receiver path to prevent saturation of an analog-to-digital converter in a digital receiver path coupled to the analog receiver path. The power estimator forwards the estimate of the signal power at the output of the channel selection filter to an adder which combines the reference value with the signal power estimate. The output of the adder is forwarded to the AGC circuit.

In order to make the AGC operation transparent to the baseband subsystem, the controller manages the state of the RF AGC system. At power up, multiple "fast" AGC repetitions are performed to determine the signal power. The controller sets the appropriate parameters in the AGC circuit. The second set of parameters for fast AGC operation is set for a period of time when the RF AGC system stops receiver operation for measurement. In steady state, "slow" AGC parameters are set. The controller monitors the rate of change of the Received Signal Strength Indicator (RSSI) and compares the rate of change to a preselected threshold to determine if a change in the loop parameters is required. The controller further adjusts the DC-cancellation parameter when the analog gain is switched. The controller may also set a flag responsive to the LNA gain. The controller starts the phase compensation process at the gain/phase compensator at the baseband interface when the LNA gain is modified to adjust the overall gain in the analog receiver path.

An embodiment of an AGC circuit includes a loop filter, an analog control branch, and a digital control branch. The loop filter receives a difference between the reference value and a representation of the received signal power from the digital receiver path. The loop filter generates an error signal that is applied to both the analog and digital control branches. The analog control branch includes a first adder, a programmable hysteresis element, and a look-up table. The first summer receives the error signal from the loop filter and receives a first calibration value. The output of the first adder is forwarded to a programmable hysteresis element which applies one or more adjustable delays according to one or more thresholds to the output signal from the adder. The output from the programmable hysteresis element is forwarded to a look-up table to select the control signal. The control signal is forwarded to both the digital control branch and the analog receiver path. The control signal is configured to adjust a gain of one or more elements in the analog receiver path. The digital control branch includes a second adder, a programmable delay element, and a converter. The programmable delay element adjusts the control signal received from the analog control branch to align the control signal in time with the error signal. The delayed representation of the analog control signal, the error signal, and the second calibration value are applied at a second summer. The second adder forwards the error signal, the second calibration value and the delayed representation of the control signal to the converter. A converter converts the output from the second adder from a logarithmic value to a linear control word. The control word is forwarded to a sealer to adjust the signal gain in the digital domain in the receiver.

An alternative embodiment of the AGC circuit receives a gain value from the baseband subsystem and replaces the error signal from the loop filter with the gain value (e.g., by opening a switch). The received gain values are forwarded from the baseband subsystem to the first and second feedback adders. The gain value and the first calibration value are forwarded to the analog control branch. In operation, the total gain change provided by the baseband is loaded into the register. The appropriate gain threshold is loaded into the look-up table and the calibration value is provided to the first feedback adder. The programmable hysteresis element is bypassed or disabled. The rest of the analog and digital control paths are reused. The AGC circuit further applies the gain value and the second calibration value to the digital control branch. The analog control branch generates a control signal that is coupled to one or more elements in the analog receiver path to control gain in the receiver. The digital control branch generates a control word coupled to the sealer to control the gain in the digital domain. Thus, the gain control in both embodiments is distributed between the analog and digital control elements.

The circuits, systems, and methods for managing AGC in the quadrature path of a receiver may be implemented in hardware, software, or a combination of hardware and software. When implemented in hardware, the systems, circuits, and methods may be implemented using dedicated hardware elements and logic. When the circuits, systems, and method portions are implemented in software, the software portions may be used to control components in the circuits such that various operational aspects may be software controlled. The software, as well as the gain step (step), calibration and reference values may be stored in memory, accessed and executed by a suitable instruction execution system (microprocessor). Hardware implementations of the systems, circuits, and methods may include any or a combination of the following techniques, which are well known in the art: discrete electronic components, discrete logic circuit(s) with logic gates for implementing logical functions on data signals, application specific integrated circuits with appropriate logic gates, programmable gate array(s) (PGA), Field Programmable Gate Array (FPGA), etc.

Software for managing AGC in an RF subsystem of a wireless communication system includes an ordered listing of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions.

In the context of this document, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The computer readable medium can be, for example but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or propagation medium. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection (electronic) having one or more wires, a portable computer diskette (magnetic), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory) (magnetic), an optical fiber (optical), and a portable compact disc read-only memory (CD-ROM) (optical). Note that the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, converted, or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.

Fig. 1 is a block diagram illustrating a simplified wireless communication system 100 including a radio frequency automatic gain control (RF AGC) system 238. The wireless communication system 100 includes a baseband subsystem 110, input/output (I/O) elements 112, a transmitter 130, a front-end module 140, an antenna 145, and a receiver 150. I/O elements 112 are coupled to baseband subsystem 110 via connection 114. I/O element 112 represents any interface with which a user may interact with wireless communication system 100. For example, I/O elements 112 may include a speaker, a display, a keyboard, a microphone, a trackball, a thumbwheel, or any other user interface element. A power source (not shown), which may be a Direct Current (DC) battery or other power source, is also connected to the baseband subsystem 110 to provide power for the wireless communication system 100. In a particular embodiment, the wireless communication system 100 may be, for example, but not limited to, a portable telecommunications device such as a mobile cellular-type telephone.

The baseband subsystem 110 includes a microprocessor (μ P) 115 and a memory 116. The microprocessor 115 and the memory 116 communicate with each other. The baseband subsystem 110 may also include one or more of an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or any other special or general purpose processor among other devices, depending on the manner in which the RF AGC system 238 and method for managing AGC in the quadrature signal path of a receiver are implemented.

The baseband subsystem 110 provides signal timing, processing, and I/O storage functions for the wireless communication system 100 via the microprocessor 115 and memory 116. In addition, baseband subsystem 110 generates various control signals, such as power control signals, filter control signals, and modulator control signals, that are indicative of various functions within transmitter 130 and receiver 150, as known to those skilled in the art. Various control signals may originate from the microprocessor 115 or from any other processor within the baseband subsystem 110 and are provided to various connections within the transmitter 130 and receiver 150. It should be noted that for simplicity, only the basic components of the wireless communication system 100 are illustrated herein.

If portions of the RF AGC system 238 and the method for managing AGC in the quadrature path of the receiver are implemented in software executed by the microprocessor 115, the memory 116 will also include gain control software 118. The gain control software 118 comprises one or more executable code segments and/or data values that may be stored in the memory 116 and executed in the microprocessor 115. Alternatively, the functionality of the gain control software 118 may be encoded into an ASIC (not shown) or may be executed by an FPGA (not shown) or another device. Because the memory 116 may be rewritable and because the FPGA is reprogrammable, updates to the gain control software 118, including gain stages or ranges, calibration data, and reference values may be transmitted remotely to the wireless communication system 100 and stored therein when implemented using any of these methods.

In a preferred embodiment, the gain control software 118 includes one or more executable code segments for configuring the RF AGC system 238 to operate in conjunction with other receiver elements and the baseband subsystem 110. The power estimator, loop filter, delay element, programmable hysteresis element, one or more programmable digital filters and entries in the look-up table, and one or more converters can be configured or controllably updated as desired to allow the RF AGC system 238 to operate in both WCDMA and GSM/EDGE modes of operation. The arrangement and operation of the power estimator, loop filter, delay element, programmable hysteresis element, look-up table, digital filter and one or more converters will be described in connection with the functional block diagrams of fig. 2, 3 and 5.

The baseband subsystem 110 converts digital communication information within the baseband subsystem 110 into analog signals for transmission by the transmitter 130. More specifically, baseband subsystem 110 uses a digital-to-analog converter (not shown) to generate in-phase (I) and quadrature-phase (Q) transmit signals that are applied to transmitter 130 via bus 120.

The transmitter 130 includes a modulator (not shown) that modulates an analog signal and provides the modulated signal to an up-converter (not shown). The upconverter upconverts the modulated signal to an appropriate transmit frequency and provides the upconverted signal to a power amplifier (not shown). The power amplifier amplifies the upconverted signal to an appropriate power level for the communication protocol or standard in which the wireless communication system 100 is designed to operate. The modulated, upconverted and amplified transmit signal is forwarded to the front end module 140 via connection 132. Details of the transmitter 130 have been omitted as will be understood by those skilled in the art. For example, when the power amplifier is used in a constant amplitude phase (or frequency) modulation application such as GSM, the phase modulated information is provided by a modulator within the transmitter 130. When a power amplifier (not shown) is used in applications requiring both phase and amplitude modulation, such as for example for GSM/EDGE, the cartesian in-phase (I) and quadrature (Q) components contain both amplitude and phase information.

The front end module 140 includes an antenna system interface that may include, for example, a duplexer with a pair of filters that allow simultaneous passage of both transmit and receive signals in respective frequency ranges, as known to those skilled in the art. The transmit signal is provided from the front end module 140 to an antenna 145 for signal transmission to suitably configured communication devices remote from the wireless communication system 100.

Signals received by antenna 145 are directed from front-end module 140 via connection 142 to receiver 150. Receiver 150 includes various components for downconverting, digitizing, and filtering data signals recovered from the received signal, as is known to those skilled in the art. The mixing stage downconverts the received RF signal and separates it into in-phase (I) and quadrature-phase (Q) received signals. The I and Q received signals are sampled and converted to digital signals by one or more ADCs. One or more dedicated digital filters are introduced to further process the I and Q received signals.

An RF AGC system 238 is introduced to dynamically and selectively manage AGC in the receiver 150. After dynamic (i.e., controlled) correction for gain and phase imbalance, the corrected I and Q signals are demodulated and further processed in the baseband subsystem 110.

When, for example, the transmitter 130 and the receiver 150 are implemented on an RF Integrated Circuit (IC), the transmitter 130 and the receiver 150 may be collocated in an integrated transceiver. In an alternative embodiment, receiver 150 and transmitter 130 are implemented on separate ICs. In both architectures, the RF AGC system 238 is preferably implemented in hardware on an integrated circuit in the receiver 150.

Fig. 2 is a functional block diagram illustrating an example embodiment of receiver 150 of fig. 1. Receiver 150 receives an RF input signal (RF IN) on connection 142 coupled to analog receiver path 210 and via connection 215 to digital receiver path 220. The analog receiver path 210 includes mixers, amplifiers, and/or attenuators. The mixer is configured to separate I (i.e., in-phase) and Q (i.e., quadrature-phase) receive signal components from the RF input signal. Amplifiers and/or attenuators in the analog receiver path 210 adjust the received signal power under control of the control signal on connection 267. The digital receiver path 220 includes a series combination of a sigma-delta analog-to-digital converter 222, a decimation filter 224, a high pass filter 226, a compensation filter 228, and a channel selection filter 230. As shown in fig. 2, the digitized version of the received signal is forwarded from the sigma-delta analog-to-digital converter 222 to the decimation filter 224 over connection 223. The decimated and digitized representation of the received signal is forwarded from the decimation filter 224 via connection 225 to the high pass filter 226, which high pass filter 226 reduces the amplitude of the signal components below the corner frequency. The high pass filtered representation of the received signal is forwarded on connection 227 to a bank of compensation filters 228. The output of the compensation filter 228 is forwarded on connection 229 to a channel selection filter 230 and an RF AGC system 238.

Channel select filter 230 passes a selected range of frequencies, i.e., a selected receive channel, over connection 235 to RF AGC subsystem 238 and over connection 233 to scaler (scaler) 402 under the control of one or more signals (not shown) from baseband subsystem 110. In addition to receiving the selected receive channel on connection 235, the RF AGC subsystem 238 also receives a first calibration signal on connection 120b, a second calibration signal on connection 120c, and an AGC reference signal on connection 120 d. As further illustrated in fig. 2, the RF AGC subsystem 238 generates three output signals. A Received Signal Strength Indicator (RSSI) signal is transmitted over connection 120e to the baseband subsystem 110. The analog control signal is passed from AGC circuit 260 to analog receiver path 210. The analog control signal on connection 267 includes information for setting or otherwise controlling the gain of one or more controllable elements in the analog receiver path 210. In addition, the digital control word is transmitted from AGC circuit 260 to sealer 402 over connection 265. Scaler 402 is a digital gain element. That is, sealer 402 adjusts the digital representation of the received signal provided on connection 233 in response to the digital control word on connection 265 and forwards it to baseband subsystem 110 on connection 120 a.

In the illustrated embodiment, the RF AGC subsystem 238 includes a power estimator 240, a blockage identification element 250, and an AGC circuit 260. The power estimator 240 forwards the first and second power estimates. A first estimate of the power of the signal originating at the input to the channel selection filter 230 is generated from the signal on connection 229. A second estimate of the signal power is generated from the signal on connection 235 at the output of the channel selection filter. As described above, when the received signal samples are processed at half the received sample rate, a single power estimator may be used to determine the signal power before and after the channel selection filter. The first and second estimates of the received channel power are forwarded on connection 245 to the congestion identification element. The blockage identification element 250 includes logic that compares the difference of the first and second estimates to a threshold to determine when blockage occurs in the receiver 150. When blocking occurs in the receiver 150, a signal indicating this is forwarded along connection 255 to the AGC circuit 260. In addition, the power estimator 240 forwards the first estimate on connection 247 to the AGC circuit 260.

As briefly described above, the AGC circuit 260 operating in accordance with the controller 400 uses an analog control path (not shown) to controllably adjust the gain of one or more of the mixer/LNA stage, the transimpedance amplifier, and the programmable power amplifier in the analog receiver path 210. When adjusting the LNA gain stage, the controller 400 will forward its indication to the gain/phase compensator (not shown). After the appropriate number of data signal samples have been processed, the I and Q data signals may be multiplied by a complex number in either the RF section of receiver 150 or a gain/phase compensator implemented in baseband subsystem 110. The gain and phase corrected I and Q data signals are further processed by the baseband subsystem 110 before being forwarded to the I/O elements 112 (fig. 1). Also as described above, AGC circuit 260, operating in accordance with controller 400, uses a digital control path (not shown) to generate a control word that is forwarded on connection 265 to controllably adjust sealer 402.

Fig. 3 is a functional block diagram illustrating an embodiment of the RF AGC system 238 of fig. 1. As shown in fig. 3, receiver 300 includes an analog receiver path 210, a digital receiver path 220, a sealer 402, and an RF AGC system 238. The analog receiver path 210 receives the RF IN signal on connection 142 and the control signal on connection 267. The analog receiver path 210 comprises serially coupled analog devices that amplify or attenuate the signal power (i.e., the RF _ IN signal) according to information encoded IN the control signal on connection 267.

In one embodiment, analog receiver path 210 includes one or more Low Noise Amplifiers (LNAs), one or more transimpedance amplifiers (TIAs), or one or more Programmable Gain Amplifiers (PGAs) coupled in series. In one embodiment, the AGC circuit 260 is arranged to provide approximately 48dB of analog gain control over 5 gain levels or ranges. Two of the gain stages are provided by programmable gain amplifiers. The first programmable amplifier gain stage provides approximately 10dB of gain to the analog signal in the analog receiver path 210. The second programmable amplifier gain stage provides approximately 6dB of gain to the analog signal. The remaining gain stages or ranges are provided by a combination of mixers and LNAs. The first and third mixer/LNA gain stages provide approximately 10dB of gain to the analog signal. The second mixer/LNA gain stage provides approximately 12dB of gain to the analog signal. Other embodiments are possible that provide less or greater overall gain to the analog signal. These other embodiments that provide total gain in the analog signal other than approximately 48dB may be achieved by many different combinations of gain stages and combinations of amplifiers or attenuators that may be desired.

As is known, the analog receiver path 210 also includes analog components for separating the in-phase (I) and quadrature-phase (Q) components of the received signal. When these analog components for separating the I and Q components of the received signal are arranged after the amplifier or the attenuator, the amplifier and/or the attenuator may be arranged in a single signal path. Once the I and Q components of the received signal are separated, it will be appreciated that separate amplifiers or attenuators should be applied in the matched pairs to adjust the signal power of the I or in-phase and Q or quadrature-phase received signal channels. The power adjusted I and Q receive signals are then forwarded on connection 215 to digital receiver path 220.

As described above, the digital receiver path 220 includes an analog-to-digital converter, a decimation filter, a high pass filter, a compensation filter, and a channel selection filter (not shown). Digital receiver path 220 receives the power adjusted I and Q receive signals on connection 215. The digital receiver path 220 forwards the first digital representations of the sampled and filtered I and Q received signals on connection 229 to the RF AGC system 238. The first digital representation of the I and Q receive signals forwarded on connection 229 comprises the I and Q receive signals before being processed in the channel selection filter. The digital receiver path 220 is further configured to forward the sampled and filtered second digital representation of the I and Q received signals on connection 235 to the RF AGC system 238. The second digital representation includes the I and Q received signals after being processed by a channel selection filter (not shown). The channel selection filter passes only those signal components within a specified frequency range. When blocking occurs in the receiver 150, the signal power in the I and Q receive signals prior to processing in the channel selection filter will be greater in magnitude than the signal power in the I and Q receive signals at the output of the channel selection filter.

The second digital representations of the I and Q receive signals are forwarded to sealer 402 over connection 233. Scaler 402 is a digital gain element. Sealer 402 adjusts the digital representations of the I and Q receive signals provided on connection 233 according to the digital control word transmitted from AGC circuit 260 on connection 265. As will be explained below, AGC circuit 260 adjusts the control word based on current operating conditions in receiver 150, including the estimated power of the received signal, the amount of analog gain provided in analog receiver path 210, and a desired reference value. Sealer 402 is responsive to the digital control word on connection 265 to digitally scale or adjust the I and Q receive signals before forwarding them on connection 120a to baseband subsystem 110. In one embodiment, scaler 402 provides digital gain control of approximately 72 dB. Other embodiments are possible that provide less or more overall gain to the digital I and Q receive signals.

The RF AGC system 238 includes a power estimator 240, a converter 334, a summer 336, and additional elements. The power estimator 240 receives the channel select filtered I and Q receive signals via connection 235. The power estimator also receives the I and Q receive signals that have not been processed by the channel select filter (not shown) on connection 229. The power estimator 240 is arranged to calculate estimates of the signal energy in the I and Q received signals before and after the channel selection filter. The power estimator 240 is a hardware device configured to perform equation 1 below.

Equation 1

N in equation 1 is the number of samples used in this calculation. The summation operates in a integrate and dump (dump) mode. Thus, subsequent functional blocks in the RF AGC system 238 operate at a frequency determined by the ratio of the sampling frequency and the number of samples. The estimated signal energy for the samples received from connection 235 is forwarded on connection 333 to converter 334. The converter 334 is arranged to convert the estimated signal energy into a value in decibels using the algorithm illustrated and described in connection with fig. 8. Summer 336 receives the reference power in dB via connection 120d and an estimate of the signal energy (in dB) from converter 334 via connection 335. As shown in fig. 3, summer 336 produces an estimated difference of the reference power and the signal energy and forwards it on connection 347 to AGC circuit 260.

The reference power is a programmable value. For the receiver 150 illustrated and described in fig. 2, the reference power is set as follows. Since a WCDMA signal is similar to white noise, its crest factor (crest factor) is assumed to be F_S/3 wherein F_SIs a full scale, and the measuring device is a full scale,

E_peak=I_peak ²+Q_peak ²=F_S+F_S=2F_S

assuming a crest factor of 1/3, the average signal energy is:

the reference power may be determined as the ratio of the average signal energy and the peak signal energy as follows:

allowing a margin of 3dB, the reference power is set to-12.5 dB.

As further shown in fig. 3, RF AGC system 238 includes blockage identification element 250 and controller 400. The blockage identification element 250 receives the first and second estimates from the power estimator 240 on connection 245. The first estimate represents the signal power in the I and Q received signals prior to the channel selection filter. The second estimate represents the signal power in the I and Q received signals after being processed by the channel selection filter. The occlusion identification element 250 comprises logic configured to generate an occlusion present signal when a function of the first estimate and the second estimate exceeds a threshold. As shown in fig. 3, the block present signal is passed to the look-up table 356 in the analog control branch 350 via connection 255. Look-up table 356 includes one or more entries having information suitable for adjusting one or more controllable elements in analog receiver path 210 in response to a blocker present signal to prevent an analog to digital converter in digital receiver path 220 from receiving a respective input signal that exceeds its dynamic range.

Controller 400 is a state machine coupled to loop filter 345, various elements in AGC circuit 260, and one or more filters in the digital receiver path via connection 405. As will be explained in more detail in connection with the state diagram of fig. 4, the controller 400 sets the operating parameters for the normal, power-on and compressed modes of operation, among others. The operating parameters include, but are not limited to, a power calculation window size, one or more loop filter constants, a corner frequency of the DC cancellation high pass filter, one or more thresholds, and the like.

AGC circuit 260 includes a loop filter 345, an analog control branch 350, and a digital control branch 360. The loop filter 345 receives the error signal in decibels on connection 347 and is arranged to forward the filtered error signal according to equation 2 below. The filtered error signal is passed on connection 349 to both the analog control branch 350 and the digital control branch 360

filtered_error(k)=filtered_error(k－1)+K_loopError (k) equation 2

K_loopIs an AGC loop constant that is programmable and adjustable by the controller 400.

The analog control branch 350 includes a first feedback adder 352, a programmable hysteresis element 354, and a look-up table 356. The first feedback adder 352 receives the filtered error signal on connection 349 and the first calibration value on bus connection 120 b. The first feedback adder 352 is configured to forward the difference of the first calibration value and the filtered error signal on the bus connection 120e to the programmable hysteresis element 354 and the baseband subsystem 110 (not shown). The difference between the first calibration value and the filtered error signal is an indication of received signal strength or a Received Signal Strength Indicator (RSSI). The first calibration value is a programmable value that can account for variations in received signal strength due to frequency and temperature. When calibration data is not available for the current combination of temperature and frequency, a default value of approximately-18 dB is applied.

To prevent analog gain switching (toggling), the programmable hysteresis element 354 provides a time or delay period during which analog gain is not allowed to change. In addition, the time or delay time is applied with a threshold value that is used in conjunction with the previous gain state or stage to determine a new analog gain value.

The received signal strength, adjusted in time by the programmable hysteresis element 354, is used as an index into a look-up table 356, which determines the analog gain profile corresponding to the received signal power. The threshold values in the look-up table are programmable. Table 1 is an example of such a table.

TABLE 1-WCDMA analog gain LUT

In the embodiment shown in Table 1, when an input signal threshold of-33 dB is detected, the analog control branch 350 generates an analog control signal on connection 267 that directs the analog receiver path 210 to provide approximately 0dB of gain in the analog receiver path 210. When an input signal threshold between-33 dB and-44 dB is detected, the analog control branch 350 alters the analog control signal on connection 267 to provide approximately 10dB of total gain via the PGA in the analog receiver path 210. Similarly, when the input signal threshold falls between-44 dBm and-72 dBm, the analog control branch 350 alters the analog control signal on connection 267 to provide an overall gain of approximately 22dB, with approximately 10dB of gain provided by the PGA and an additional gain of approximately 12dB provided by the LNA in the analog receiver path 210. When the input signal threshold falls between-72 dBm and-82 dBm, the analog control branch 350 alters the analog control signal on connection 267 to provide an overall gain of approximately 34dB, with approximately 10dB of gain provided by the PGA and approximately 24dB of additional gain provided by one or more LNAs in the analog receiver path 210. When the input signal threshold falls between-82 dBm and-97 dBm, the analog control branch 350 alters the analog control signal on connection 267 to provide an overall gain of approximately 43dB, where approximately 10dB of gain is provided by the PGA, approximately 6dB of gain is provided by the transimpedance amplifier, and an additional gain of approximately 27dB is provided by one or more LNAs in the analog receiver path 210. Finally, when the input signal threshold falls between-97 dBm and-110 dBm, the analog control branch 350 alters the analog control signal on connection 267 to provide an overall gain of approximately 55dB, where approximately 16dB of gain is provided by the PGA, approximately 12dB of gain is provided by the transimpedance amplifier, and an additional gain of approximately 27dB is provided by one or more LNAs in the analog receiver path 210.

Other embodiments are contemplated that include other analog gain stages than those shown in table 1. For example, more or fewer analog gain stages or steps may be provided by other combinations of amplifiers and controllable attenuators. Additional amplifiers may include LNAs, TIAs, PGAs, two or more LNAs, two or more TIAs, two or more PGAs, or a combination of the above with any number of controllable attenuators (with multiple ranges of attenuation) to achieve the desired gain level.

As shown in table 1, the analog control signal used to adjust the gain in the analog receiver path 210 may include appropriate code to indicate any of the low, medium, or high range gain states to one or more LNAs, one or more TIAs, or one or more PGAs, as desired. Alternative arrangements of controllable elements in the analog receiver path can similarly be controlled over any number of desired control ranges using any number of control signals encoded to convey a desired combination of elements and gain states. Although the embodiment presented in Table 1 does not include attenuators, it should be understood that the analog control branch 350 and the analog receiver path 210 are not so limited.

LNA gain variation requires phase correction to be applied to the I and Q receive signal components before they are forwarded to the baseband subsystem 110 (fig. 1). Thus, the lookup table 356 may further include a rotation factor (not shown) used in phase correction. Before forwarding the I and Q values to baseband subsystem 110 with an appropriate delay corresponding to the receive path filter delay, a complex multiplication between I + jQ and cos (Φ) + jsin (Φ) is performed when switching LNA gain states. The rate of change of the analog gain is defined by equation 3.

Equation 3

Where N is the power estimation window size;

f_sis the power calculation sampling rate; and

gain hold (gain) is an analog gain variation delay in units of samples.

Digital control branch 360 includes a programmable delay element 361, a second feedback adder 362, and a converter 364. The programmable delay element 361 synchronizes the analog control signal on connection 267 with the filtered error signal on connection 349 from the loop filter 345. A second feedback adder 362 receives the filtered error signal on connection 347, the second calibration value on connection 120c and the delayed analog control signal from the delay element 361. As shown in fig. 3, a second feedback adder 362 generates and forwards the difference of the filtered error signal, the second calibration value and the delayed analog control signal on connection 363 to a converter 364. The converter 364 generates a control word after converting the digital gain from decibels to a linear value. The control word is forwarded to sealer 402 via connection 265. A method of converting decibels to linear units is illustrated and described in connection with fig. 9.

Fig. 4 is a state diagram illustrating an embodiment of a controller 400 that enables autonomous operation of AGC circuit 260. The state diagram of fig. 4 illustrates the architecture, functionality, and operation of a possible implementation of a controller via software and/or firmware associated with the RF AGC system 238. In this regard, each circle represents a set of conditions, and the arrows between the circles describe the behavior of the controller 400. It should be understood that the controller 400 may be implemented in hardware, firmware, or software. When the RF AGC system 238 is implemented via hardware, software, and firmware, or a combination of hardware and software, one or more combinations of states and arrows in the state diagram may represent additional one or more circuits. Alternatively, the described functionality can be embodied in source code comprising human readable statements written in a programming language or machine code comprising instructions recognizable by a suitable execution system, such as a processor in a computer system. The machine code may be translated from source code or the like.

To provide autonomous operation of the AGC circuit 260, the controller 400 sets operating parameters for normal, power-on, and compressed modes of operation, among others. The operating parameters include, but are not limited to, a power calculation window size, one or more AGC loop filter constants, a corner frequency for a DC cancellation or high pass filter that may be applied in one or more steps (in the digital receiver path 220), a rate threshold, and a mode timer. In addition, a transition timer may be set. The transition timer is used by the controller 400 to adjust the corner frequency of the high pass filter in response to the analog gain change (in one or more steps) and to return the corner frequency to the first frequency when the timer time has elapsed. In some cases, it may be desirable to dynamically manage the loop filter constants and the power calculation window.

State diagram 404 includes state 410, state 420, state 430, state 440, state 450, and state 460. State 410 is the power-on mode of operation. A suitable set of parameters for operating AGC circuit 260 under power-on conditions is repeatedly applied as indicated by arrow 412 until a selected number of repetitions has been reached. When the AGC circuit 260 has made a selected number of repetitions, the controller 400 transitions to state 430 as indicated by arrow 414.

State 420 is a compressed mode of operation. An appropriate set of parameters for operating AGC circuit 260 in compressed mode is repeatedly applied, as indicated by arrow 422, until a selected number of repetitions has been reached. When the AGC circuit 260 has made a selected number of repetitions, the controller 400 transitions to state 430 as indicated by arrow 424.

State 430 is the normal mode of operation. An appropriate set of parameters for operating the AGC circuit 260 under normal operating conditions is applied. In state 430, the controller 400 compares the rate of change of the estimated RSSI from the AGC circuit 260 to first and second thresholds. When the rate of change exceeds a first threshold, the controller 400 transitions to state 440 as indicated by arrow 432. At state 440, the controller 400 adjusts the power calculation window and loop filter constants in a first manner (e.g., to speed up the feedback loop). Once the controller 400 has made the adjustment indicated in state 440, the controller 400 transitions back to state 430 as indicated by arrow 442. Otherwise, when the rate of change is less than the second threshold, the controller 400 transitions to state 450 as indicated by arrow 434. At state 450, the controller 400 adjusts the power calculation window and loop filter constants in a second manner (e.g., to slow down the feedback loop). Once the controller 400 has made the adjustment indicated in state 450, the controller 400 transitions back to state 430 as indicated by arrow 452.

State 460 is a transition mode of operation. In response to an indication that the analog gain has changed as indicated by arrow 436, an appropriate set of parameters for operating the AGC circuit 260 in the conversion mode is applied. When the analog gain changes, the controller 400 applies the DC offset correction filter for a selected period of time. When the AGC circuit 260 has applied the DC offset correction filter for a selected period of time, one or more filter parameters (e.g., corner frequency) may be returned to the normal mode setting, as indicated by arrow 462.

Fig. 5 is a functional block diagram illustrating an alternative embodiment of the AGC circuit of fig. 3. The AGC circuit 560 is adapted for use in a GSM/EDGE mode of operation of the transceiver. AGC circuit 560 shares several circuit elements from AGC circuit 260 illustrated in fig. 3 and described above. As shown in fig. 5, AGC circuit 260 is implemented in a receiver 500, which receiver 500 includes an analog receiver path 210, a digital receiver path 220, and a sealer 402. Analog receiver path 210 operates in accordance with the control signal provided by analog control branch 550. Sealer 402 operates in accordance with the control word provided by digital control branch 360. Power estimator 240, converter 334, adder 336, block identification element 250, controller 400, and loop filter 345 are illustrated in dashed lines to show that they have been disabled or otherwise removed from other elements in receiver 500. In the illustrated embodiment, the position of switch 510 is controllably positioned to provide a gain value from baseband subsystem 110 (fig. 1) to analog control branch 550 and digital control branch 360 via connection 120 f. As further shown in fig. 5, switch 510 no longer couples connection 349 (i.e., the output of loop filter 345) to analog control branch 550 and digital control branch 360. In addition, the programmable hysteresis element 354 is disabled and bypassed via connection 120 e. Alternatively, the programmable hysteresis element 354 is operated in the bypass mode to apply the difference of the first calibration value and the gain value from the baseband subsystem 110 to the lookup table 356.

The analog receiver path 210 receives the RF IN signal on connection 142 and provides amplified versions of the I and Q receiver components according to the control signal on connection 267 to the digital receiver path 220. The analog receiver path 210 may include a mixer, one or more Low Noise Amplifiers (LNAs), or one or more programmable power amplifiers (PGAs). In one embodiment, the analog control branch 550 is arranged to provide approximately 54dB of analog gain control over 6 gain levels or ranges. Two of the gain stages are provided by programmable amplifiers. The first programmable amplifier gain stage provides approximately 6dB of gain to the analog signal. The second programmable amplifier gain stage provides approximately 6dB of gain to the analog signal. Two additional gain stages are provided by mixers in the analog receiver path 210. The first mixer gain stage provides approximately 10dB of gain to the analog signal. The second mixer gain stage provides approximately 10dB of gain to the analog signal. The remaining gain stages or ranges are provided by one or more LNAs. The first LNA gain stage provides approximately 14dB of gain to the analog signal. The second LNA gain stage provides approximately 14dB of gain to the analog signal. Other embodiments are possible that provide less or greater overall gain to the analog signal. These other embodiments that provide total gain in the analog signal other than approximately 54dB may be achieved by many different combinations of gain stages.

Digital receiver path 220 receives amplified versions of the I and Q receive signals on connection 215. Digital receiver path 220 includes one or more signal processing elements that sample, digitize, high-pass filter, and compensate for power variations in frequency in the communication path traversed by the I and Q received signals. Additionally, the digital receiver path 220 may include a channel selection filter to move undesired frequencies below a low frequency threshold and to move undesired frequencies above a high frequency threshold. The output of digital receiver path 220 is forwarded to sealer 402 on connection 233. Sealer 402 is a digital gain element that operates according to a control word received from digital control branch 360 over connection 265. The power adjusted I and Q signals generated from the received analog signals are forwarded to the baseband subsystem 110 (fig. 1) via bus connection 120 a. In one embodiment, the digital receiver path 220 provides approximately 72dB of digital gain control. Other embodiments are possible that provide smaller or larger overall gains to the digital I and Q signals.

Analog control branch 550 includes a first feedback adder 352 and a look-up table 356. The first feedback summer 352 receives the gain value from the baseband subsystem 110 on connection 349 and the first calibration value on connection 120 b. The first feedback adder 352 is arranged to forward the difference between the first calibration value and the total gain loaded from the baseband subsystem 110 (not shown) over the connection 120 f. The difference between the first calibration value and the gain value is the RSSI. The first calibration value is a programmable value that can account for variations in received signal strength due to frequency and temperature. The RSSI is used as an index to a look-up table 356, which determines the analog gain profile corresponding to the antenna power. The thresholds in the table are programmable. Table 2 is an example embodiment of such a table.

TABLE 2 GSM/EDGE analog gain LUT

In the embodiment shown in Table 2, when a switching threshold of-33 dBm is detected, the analog control branch 550 generates an analog control signal on connection 267 that directs the analog receiver path 210 to provide approximately 0dB of gain in the analog receiver path 210. When a switching threshold between-33 dBm and-35 dBm is detected, the analog control branch 550 alters the analog control signal on connection 267 to provide approximately 14dB of gain via the LNA in the analog receiver path 210. Similarly, when the switching threshold falls between-35 dBm and-47 dBm, the analog control branch 550 changes the analog control signal on connection 267 to provide approximately 14dB of gain via the first LNA in the analog receiver path 210 and approximately 14dB of additional gain via the second LNA in the analog receiver path 210 for a total analog gain of approximately 28 dB. Table 2 illustrates additional gain stages or states that may be applied for analog gain control of the LNA, mixer, and PGA in the analog receiver path 210, as may be desired.

Other embodiments are contemplated that include other analog gain stages than those shown in table 2. For example, when a passive mixer is used, one or more gain stages or steps may be provided by one or more further amplifiers. The additional amplifiers may include LNAs, PGAs, two or more LNAs, two or more PGAs, or a combination of one or more LNAs and one or more PGAs to achieve a desired gain stage. Additionally, one or more attenuators may be introduced in the analog receiver path 210 to allow further control of the gain. As described above, the control signal on connection 267 will include information suitable to achieve the desired gain level according to the architecture of the analog receiver path 210.

Digital control branch 360 includes a programmable delay element 361, a second feedback adder 362, and a converter 364. The second feedback adder 362 receives the gain value provided by the baseband via connection 349, the second calibration value via connection 120c and the delayed representation of the analog gain from the programmable delay element 361. As shown in fig. 5, a second feedback adder 362 generates and forwards to a converter 364 a difference of the gain value, the second calibration value and the analog gain received from the programmable delay element 361 on connection 363. The converter 364 generates a control word after converting the digital value from decibels to a linear value. The control word is forwarded to sealer 402 via connection 265. A method for converting decibels to linear units is illustrated and described in connection with fig. 9.

Fig. 6 is a flow diagram illustrating an embodiment of a method for implementing an analog gain control signal. The flowchart of fig. 6 illustrates the architecture, functionality, and operations of possible implementations via one or more circuits, software, and/or firmware associated with the receiver 150 of fig. 1 or the receiver 500 of fig. 5. When AGC circuit 260 is implemented via hardware, software and firmware, or a combination of hardware and software, one or more blocks in the flow chart may represent another circuit or circuits. Alternatively, the described functionality can be embodied in source code comprising human readable statements written in a programming language or machine code comprising instructions recognizable by a suitable execution system, such as a processor in a computer system. The machine code may be translated from source code or the like.

The method 600 begins at block 602 where a desired dynamic range is identified based on a maximum expected power in a received signal, a reference sensitivity, and a blocking requirement. At block 604, a plurality of ranges of gain control are identified. Thereafter, as shown in block 606, a plurality of gain states are identified within the identified plurality of gain control ranges. At block 608, a selection gain state is associated with one or more controllable elements in an analog receiver path of the receiver. Thereafter, as shown in block 610, a digital gain to be applied in a digital receiver path of the receiver is determined as a function of the desired overall gain and the gain provided in the analog receiver path.

Fig. 7 is a flow diagram illustrating an embodiment of a method for managing automatic gain control in an orthogonal path of an RF subsystem of a wireless communication system. The flowchart of fig. 7 illustrates the architecture, functionality, and operations of possible implementations via one or more circuits, software, and/or firmware associated with the receiver 150 of fig. 1 or the receiver 500 of fig. 5. In this regard, each block represents a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified function(s). When AGC circuit 260 or AGC circuit 560 is implemented via hardware, software, and firmware, or a combination of hardware and software, one or more blocks in the flow chart may represent additional one or more circuits. Alternatively, the described functionality can be embodied in source code comprising human readable statements written in a programming language or machine code comprising instructions recognizable by a suitable execution system, such as a processor in a computer system. The machine code may be translated from source code or the like.

The method 700 begins at block 702 where a first signal strength at an input of a channel selection filter is determined and a second signal strength at an output of the channel selection filter is determined. As described above, the power estimator may be used to determine both the first and second signal strengths when the signal data is forwarded to the power estimator at half the receiver sampling rate. Thereafter, as shown in block 704, the first and second signal strengths are compared to determine whether a blockage is present in the received signal. At decision block 706, a determination is made whether congestion exists. The difference between the first and second signal strengths may be compared to a threshold to identify when an occlusion occurs in the receiver.

When congestion is present, one or more analog gain stages are adjusted by forwarding a congestion present signal to an analog control branch of the automatic gain control circuit, as shown in block 708. The analog control branch comprises a look-up table with information arranged to convey a control signal that, when applied to the analog receive path, reduces the signal power to prevent saturation or clipping (clip) of the received signal at the ADC. Otherwise, when congestion is not present, a difference between the second signal strength (i.e., the filtered received signal) and the reference value is determined to produce an error signal. The difference or error signal is then applied to a first order feedback loop having an analog control branch and a digital control branch, as shown in block 712. As described above, the analog control branch provides an analog gain control signal to an analog receiver or a controllable element in the signal path to provide the desired analog gain control. Also as described above, the digital control branch operates on the difference of the error signal and the analog gain signal to produce a control word that adjusts the sealer 402 coupled in series with the channel selection filter to provide the desired amount of gain in the digital domain.

Fig. 8 is a flow chart illustrating an embodiment of a method for converting voltage values or other units of measurement using a linear scale to values in decibels. The flow diagram is an embodiment of an implementation of a leading ones detector. An example of a lead-in detector is described by Khalid H.Abed in a paper entitled "CMOS VLSI Implementation of a Low Power logic Converter" published in IEEE Transaction on Computer, 11/2003. The flowchart of fig. 8 illustrates the architecture, functionality, and operations of possible implementations via one or more circuits, software, and/or firmware associated with the converter 334. In this regard, each block represents a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified function(s). When converter 334 is implemented via hardware, software, and firmware, or a combination of hardware and software, one or more blocks in the flow chart may represent another circuit or circuits. Alternatively, the described functionality can be embodied in source code comprising human readable statements written in a programming language or machine code comprising instructions recognizable by a suitable execution system, such as a processor in a computer system. The machine code may be translated from source code or the like.

The method 800 begins at block 802, where N_bitThe input number is used to define the variable "IN". At block 804, bit positions from a leading one of the filtered received signals are used to define an integer "J". Next, at block 806, a variable "FRAC" is defined as variables "IN" and (1)<<J) The difference between them. At block 810, an intermediate value "X" is defined as the sum and expression of J and FRAC (1)<<J) Corrected value and (-N)_bitThe sum of the numbers-1). Thereafter, as shown at block 812, the variable X is set to the product of the intermediate value X and the constant value. In one example embodiment, the constant is 10xlog₁₀(2) Or 3.0103. The method for converting linear units to decibels as described in connection with blocks 802 through 812 may be started and repeated as desired.

FIG. 9 is a flow chart illustrating an embodiment of a method for generating a correction factor for a dB conversion. The correction algorithm allows an error equal to the third lobe (lobe), i.e. N = 3. For higher values of N, M-N points exist between every two points, with N = 3. The algorithm in fig. 9 interpolates the points in the middle. The flowchart of fig. 9 illustrates the architecture, functionality, and operations of possible implementations via one or more circuits, software, and/or firmware associated with the converter 334. In this regard, each block represents a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified function(s). When converter 334 is implemented via hardware, software, and firmware, or a combination of hardware and software, one or more blocks in the flow chart may represent another circuit or circuits. Alternatively, the described functionality can be embodied in source code comprising human readable statements written in a programming language or machine code comprising instructions recognizable by a suitable execution system, such as a processor in a computer system. The machine code may be translated from source code or the like.

The method 900 begins at block 902, where an array and a variable Nbit _ correct, labeled "correct", are defined. Specifically, the array correction includes 8 members. In the illustrated embodiment, the members are 0, 23, 37, 43, 44, 39, 29, and 16. These members represent the quantization numbers of the following arrays [0, 0.0449, 0.0719, 0.084, 0.0849, 0.0754, 0.0573, and 0.0319 ]. At block 904, linear interpolation parameters are calculated. Specifically, m =1< (j-N); k = int (frac/m); for k =0, 6, slope = correct [ k +1] -correct [ k ], and for k =7, slope = -correct [7 ]; and n = mod (frac, m). At block 906, a correction factor is calculated using equation 4.

Correction = (correct [ k ] + slope/m n)/(1 < Nbits _ correct) equation 4

In FIG. 9, the parameter slope determines in which segment of the correct [8] vector this point falls. The parameter m determines how many points exist between every two points in the correct [8] vector, and in m points, the parameter n determines the position of the value to be calculated. The method for generating the correction factor for the dB conversion described in connection with blocks 902 to 906 may be started and repeated as desired.

To calculate the digital scale factor, an inverse log function is provided, i.e., approximately 72dB, with sufficient accuracy (approximately 0.15 dB) over the desired digital dynamic range of digital control branch 360. The inverse log algorithm is a variant of the leading-detector approach that works on a base of 2. As a result, the digital gain in dB is multiplied by a constant L2DB = ((log) before conversion₂(10) )/20) or 0.166096 as shown in equation 5.

Equation 5

In the above equation, m is an integer and frac is a number less than 1. The error in the above approximation increases exponentially with each fractional (segment) or integer power of 2, as shown in the graph of fig. 10. If the reference error is deemed acceptable, a correction may be applied to adjust for the error. Table 3 below illustrates that when m =0, is at 2^fracThe values used in the approximation.

TABLE 3 reference values for power conversion of 2

The approximation used if m is not equal to 0 is:

x_lin=2^mequation 6 of (C (i) -m slope

Where slope is a fixed value equal to 0.003422. Frac (i) is the fractional part and c (i) is the final output when m = 0. When m is not equal to 0, the routine described in connection with FIG. 11 searches the frac (i) space for the appropriate region to determine i. The routine then uses c (i) to calculate the final value.

FIG. 11 is a flow diagram illustrating an embodiment of a method for generating a correction factor for conversion from decibels to linear units of gain. The flowchart of fig. 11 illustrates the architecture, functionality, and operations of possible implementations via one or more circuits, software, and/or firmware associated with the converter 364. In this regard, each block represents a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified function(s). When converter 364 is implemented via hardware, software, and firmware, or a combination of hardware and software, one or more blocks in the flowchart may represent additional one or more circuits. Alternatively, the described functionality can be embodied in source code comprising human readable statements written in a programming language or machine code comprising instructions recognizable by a suitable execution system, such as a processor in a computer system. The machine code may be translated from source code or the like.

Method 1100 begins at block 1102, where parameters L2DB and slope are initialized and arrays L2frac and L2Thrsh are constructed. In one example embodiment, L2DB is set to 42 and slope is set to 4. Additionally, an L2frac array is formed with members 1149, 1289, 1446, 1623, 1821, and 2043, and an L2Thrsh array is formed with members 42, 84, 126, 168, 210, and 252. The members of these arrays can be quantified to a desired accuracy. Thereafter, as shown at block 1104, variable X is set to the product of X (in decibels) and L2 dB. At block 1110, variable X_intIs set to int (x). At block 1112, X_fracIs set to X and X_intThe difference of (a). Thereafter, the variable TEMP is determined by the product of X and slope, and by X_fracAnd TEMP to determine the variable TEMP 1. The L2 array was searched to determine the location of TEMP 1. The output value is set as a function of TEMP and the determined position. The method for generating a correction factor for conversion from decibels to linear units of gain described in association with blocks 1102 through 1126 may be desirably started and repeated.

While various embodiments of circuits and methods for managing analog gain control in the quadrature path of a receiver have been described, it will be apparent to those skilled in the art that many more embodiments and implementations are possible that are within the scope of this disclosure. Accordingly, the circuits and methods are not to be limited except in light of the attached claims and their equivalents.

Claims (24)

1. A method for managing automatic gain control in an orthogonal signal path of a radio frequency subsystem of a wireless communication system, comprising:

determining a first signal strength at an input to a channel selection filter in a digital receiver path and a second signal strength at an output of the channel selection filter;

comparing the first signal strength and the second signal strength to detect when a blockage is present in the orthogonal signal path of the receiver, and forwarding a blockage present signal to an analog control branch of an automatic gain control circuit when the blockage is present;

generating an analog control signal in an analog control branch of an automatic gain control circuit in response to the blocker presence signal, the analog control signal configured to adjust at least one controllable gain element in an analog receiver path in response to the presence of the blocker to prevent saturation of an analog-to-digital converter in a digital receiver path of the radio frequency subsystem;

determining a difference between the second signal strength and the reference signal power at the output of the channel selection filter; and

applying a difference between the second signal strength and the reference signal power to the automatic gain control circuit, the automatic gain control circuit having a loop filter coupled to the analog control branch and a digital control branch, the digital control branch producing a digital control word configured to adjust a sealer coupled to the channel selection filter.

2. The method of claim 1, further comprising converting the representation of the second signal strength from a linear scale to a logarithmic scale to produce a converted representation of the second signal strength in decibels.

3. The method of claim 2, further comprising applying the converted representation of the second signal strength in decibels to a correction algorithm to produce a corrected representation of the second signal strength in decibels.

4. The method of claim 1, further comprising:

a reference signal power is determined as a function of the average signal energy and the peak signal energy in the rf subsystem.

5. The method of claim 4, further comprising:

the reference signal power is adjusted to allow for a predetermined margin.

6. The method of claim 1, wherein the loop filter operates at a frequency determined by a ratio of a sampling frequency to a number of samples.

7. The method of claim 1, wherein the analog control branch comprises a first feedback adder, a programmable hysteresis element, and a look-up table.

8. The method of claim 7, wherein the programmable hysteresis is implemented with a threshold value that is used in conjunction with a previous gain value to determine a new gain value.

9. The method of claim 8, further comprising:

the phase correction control signal is generated in conjunction with the analog gain variation of the low noise amplifier.

10. The method of claim 8, wherein the rate of change of the analog gain is a function of a window, a sampling rate, and a hysteresis value of the change of the analog gain used to determine the second signal strength.

11. The method of claim 1, wherein the digital control branch includes an adder and a programmable delay element, and the digital gain value is determined as a function of the filtered error signal from the loop filter and the analog gain value from the analog control branch.

12. The method of claim 11, further comprising:

the digital gain value is applied to a converter that converts the digital gain value from a logarithmic scale to a linear scale.

13. The method of claim 7, further comprising:

inserting a gain value from a baseband controller;

loading a lookup table;

bypassing the programmable hysteresis element; and

the analog gain control signal from the look-up table is applied.

14. A system for automatic gain control in a radio frequency subsystem of a wireless communication system, comprising:

a power estimator configured to receive a first input from the digital receiver path and a second input from the channel selection filter and to produce a first estimate of the signal power appearing at the output of the digital receiver path and a second estimate of the signal power appearing at the output of the channel selection filter;

a congestion identification element arranged to receive the first estimate and the second estimate from the power estimator and configured to generate a congestion presence signal when a function of the first estimate and the second estimate exceeds a threshold;

a converter coupled to an output of the power estimator and configured to produce a logarithmic representation of power in a digital receiver path; and

an automatic gain control circuit arranged to receive a difference of the blocker presence signal and a logarithmic representation of the reference signal and the power in the digital receiver path, the automatic gain control circuit comprising a loop filter, an analog control branch that generates a control signal coupled to one or more elements in the analog receiver path, and a digital control branch that generates a control word coupled to a scaler, the control signal and the control word distributing gain in the radio frequency subsystem.

15. The system of claim 14, wherein the analog control branch comprises a first feedback adder, a programmable hysteresis element, and a look-up table.

16. The system of claim 15, wherein the analog control branch receives the first calibration value, provides an indication of received signal strength to the baseband element, and generates the control signal.

17. The system of claim 16, wherein the analog control branch generates a phase compensation signal when the control signal indicates a change in gain of the low noise amplifier.

18. The system of claim 15, wherein the digital control branch comprises a second feedback adder, a programmable delay element, and a converter element, the digital control branch arranged to receive the second calibration signal and the error signal from the loop filter.

19. The system of claim 18, wherein the digital control branch receives the analog control signal at the second feedback summer and generates the control word in response to a difference between the error signal and the delayed representation of the analog control signal.

20. The system of claim 19, wherein the digital control branch converts the difference between the error signal and the analog control signal from a first value on a logarithmic scale to a converted value on a linear scale.

21. A circuit for automatic gain control in a radio frequency subsystem of a wireless communication system, comprising:

a receiver comprising an analog receiver path coupled to a digital receiver path, an output of the digital receiver path coupled to a sealer; and

a radio frequency automatic gain control circuit comprising:

an analog control branch comprising a first feedback adder and a look-up table, the analog control branch responsive to a gain value received from a baseband element and a first calibration value, the analog control branch generating an analog control signal configured to adjust at least one controllable gain element in an analog receiver path; and

a digital control branch comprising a second feedback adder, a programmable delay element, and a converter element, the digital control branch configured to generate a control word in response to the gain value received from the baseband element, the second calibration value, and the delayed representation of the analog control signal.

22. The circuit of claim 21, wherein the analog control branch further comprises a programmable hysteresis element operating in a bypass mode.

23. The circuit of claim 21, wherein the analog control branch provides an indication of received signal strength to the baseband element and is arranged to adjust a gain of one or more of a low noise amplifier, a transimpedance amplifier, and a programmable gain amplifier in the analog receiver path.

24. The circuit of claim 21, wherein the digital control branch converts a difference of the gain value received from the baseband element, the second calibration value, and the delayed representation of the analog control signal from a logarithmic scale to a linear scale.