HK1166666B - Circuitry for active cable - Google Patents

Description

Circuit for active cable

Technical Field

The present invention relates to a circuit for an active cable.

Background

Electronic devices often include connectors to provide ports where power and data signals can be shared with other devices. These connectors are typically designed to comply with a standard so that the electronic devices can communicate with each other in a reliable manner. Various Universal Serial Bus (USB), peripheral component interconnect express (PCIe), and Display Port (DP) standards are such standards, but are just a few examples.

From time to time, the standards using these connectors are replaced with newer standards. As a result, multiple connectors providing similar functionality are often included on electronic devices. For example, many current television sets include inputs for HDMI, S-video, component video, and RCA jacks.

Including these connectors increases device size, complexity, and cost. Furthermore, the inclusion of several options can confuse and frustrate customers when attempting to determine the best way to configure a particular system.

This confusion can be reduced to some extent if one connector is capable of providing signals of more than one standard. For example, if one connector can provide signals for both the old and newer standards, the number of connectors on the electronic device can be reduced, so that the device can be made smaller, simpler, and cheaper.

However, while this would be beneficial, it is difficult to achieve. For example, circuitry associated with one standard may interfere with circuitry associated with another standard. This becomes even more difficult at higher data rates because reflections and termination mismatches caused by unused circuitry can compromise the performance of the circuitry being used.

For example, a newer, faster standard may share a connector with an older, slower standard. The circuitry required by the old standard may cause reflections and termination mismatches for the circuitry used for the newer, faster standard, thereby degrading system performance.

Accordingly, there is a need for circuits, methods, and apparatus that allow various standards to share a common connector.

Disclosure of Invention

Accordingly, embodiments of the present invention provide circuits, methods, and apparatus that allow signals conforming to multiple standards to share a common connector on an electronic device. An exemplary embodiment of the present invention provides a connector that provides signals compliant with an old standard in one mode and signals compliant with a newer standard in another mode. Typically, the old standard is slower and the newer standard is faster, although this may not always be the case.

In one exemplary embodiment of the invention, pins for newer standards may be arranged to achieve at least two goals. First, they can be arranged to reduce crosstalk and interference between themselves. This may be accomplished by placing several ground pins between the high-speed differential signal paths. Second, circuitry can be added so that interference from circuitry for the old standard is minimized. This can be achieved by reducing reflections and impedance mismatches.

An exemplary embodiment of the present invention can provide a plurality of data standards by including a plurality of features. In one exemplary embodiment of the invention, devices that comply with the newer standard are able to determine whether they are communicating with devices that are compatible with the old standard or with devices that are compatible with the newer standard. This may be achieved by the first device sensing the voltage or impedance provided by the second device.

In various embodiments of the present invention, when two devices that are communicating are able to communicate with a newer standard, the standard may be used by both devices. In case one device can only operate with the old standard, the standard can be used by both devices.

Embodiments of the present invention may provide circuitry for isolating unused circuitry for one standard from operational circuitry for another standard. In a specific example, a resistor, PiN diode, multiplexer, or other component or circuit may be used to isolate the two transmitter circuits from each other. The coupling capacitor and inductor may be used as a dc block and an ac filter to isolate the circuit.

Various embodiments of the present invention may include one or more of these and other features described herein. A better understanding of the nature and advantages of the present invention may be gained with reference to the following detailed description and the accompanying drawings.

Drawings

FIG. 1 illustrates a legacy system that may be improved by incorporating embodiments of the present invention;

FIG. 2 illustrates a computer system that improves upon one embodiment of the present invention;

FIG. 3 illustrates a pin assignment for a connector that improves upon one embodiment of the present invention;

FIG. 4 illustrates circuitry and methodology for determining the types of devices that communicate with each other that improves upon one embodiment of the present invention;

FIG. 5 illustrates an active cable according to an embodiment of the present invention;

FIG. 6 illustrates an active cable according to an embodiment of the present invention;

7A-7C illustrate circuits that may be used to allow signal paths from two different standards to share a common pin of a connector;

FIGS. 8A and 8B illustrate alternative circuits that may be used to allow signal paths from two different standards to share a common pin of a connector;

FIG. 9 illustrates circuitry and methodology used by devices to determine the type of device to which they are connected;

FIG. 10 illustrates a circuit for a tethered cable in accordance with an embodiment of the present invention; and

FIG. 11 illustrates a method for calibrating a cable and related circuitry according to an embodiment of the invention.

Detailed Description

FIG. 1 illustrates a legacy system that may be improved by incorporating embodiments of the present invention. The figure shows a computer 110 in communication with a legacy display 120 over a legacy connection 115. In a particular embodiment of the invention, legacy connection 115 is a DisplayPort (DP) connection, but in other embodiments of the invention, other connections may be used.

In this figure, connection 115 is shown as an old-fashioned connection. In other embodiments of the present invention, connection 115 may also be a new type of connection. Also, while the computer 110 is shown in communication with the display 120, other types of connections may be modified by incorporating embodiments of the present invention. For example, a connection may be provided between a portable media player and a display, a computer and a portable media player, or other type of device. In various embodiments of the present invention, the computer 110, display 120, and other devices shown and discussed may be manufactured by apple Inc. of cupertino, california.

Further, it is desirable that the computer 110 be capable of driving an older display, such as the display 120, or any newer computer, display, or other type of device. Typically, this requires the addition of another connector on the computer 110. This may be undesirable because it increases the complexity, cost, and size of the computer 110. The addition of another connector also adds to consumer confusion.

Thus, embodiments of the present invention may use the same connector as legacy connection 115 to provide a newer connection. An example is shown in the following figure.

FIG. 2 illustrates a computer system according to one embodiment of the invention. This figure, like the other included figures, is shown for illustrative purposes only and does not limit the embodiments of the invention or the claims.

The figure illustrates the computer 110 in communication with a computer or display 220 over a high speed connection 225. The computer or display 220 communicates with the disk drive 230 over a high-speed connection 235. The computer 110 may use the same connector to form the legacy connection 115 of FIG. 1 and the high-speed connection 225 of FIG. 2. As shown, the high-speed connection provided by the computer 110 may be daisy-chained to multiple devices. In this configuration, each high speed connection 225 and 235 shares the bandwidth available at the connector of the computer 110.

By providing a connector on computer 110 that can support legacy connection 115 in FIG. 1 and high speed connection 225 in FIG. 2, the number of connectors on the computer is reduced. This reduces the size of the device, saves money and alleviates consumer confusion. In this example, the computer 110 is in communication with a computer or display 220 and a disk drive 230. In other embodiments of the present invention, other types of devices may be employed. For example, the computer 110 may drive the display of a unibody computer, a second computer, a separate monitor, an expansion device, a raid driver (raid drive), or other types of devices.

Embodiments of the present invention may take into account at least two considerations when using existing legacy connectors to arrange pins for high speed connections. First, the signals in different channels of the high-speed connection may be arranged such that they do not interfere with each other. That is, crosstalk between high-speed signals can be reduced and signals can be isolated. Second, the circuitry used to drive and receive the new high speed signals and the circuitry associated with the old standard may be isolated to limit interference between them. An example is shown in the following figure.

Fig. 3 illustrates pin assignment (pinout) of a connector according to an embodiment of the present invention. In this example, the displayport is the old standard, which overlaps with the pins for the new standard. This new standard may be referred to as T29, but is generally identified elsewhere in this document as HSIO. In other embodiments of the invention, other criteria may be used. Further, one or both of these criteria may be old criteria, or one or both of these criteria may be newer criteria. Further, while two standards are shown here as sharing a connector, in other embodiments of the invention, other numbers of standards may share a connector.

In various embodiments of the present invention, these two criteria may be separate and unrelated. In other embodiments of the invention, they may be related. For example, HSIO may be a high speed signaling technology that carries displayport information. That is, the displayport information may be tunneled using the HSIO signal. The HSIO may also carry other types of signal information, such as PCIe information, simultaneously. In this manner, the connector in fig. 3 may carry the displayport signal directly, or it may carry the displayport information that is transmitted as an HSIO signal. It should be noted that in the various embodiments of the present invention described below, HSIO is also referred to as T29.

In this arrangement, the high speed input and output pins can be isolated from each other. In particular, high speed receive signals may be placed on pins 4 and 6, and 16 and 18. Each of these signal pairs may be isolated by the signal being an Alternating Current (AC) ground. For example, the high speed receive pins 4 and 6 may be isolated by the hot plug detect pin 2 and the ground pin 8. Similarly, the high speed receive pins 16 and 18 may be isolated by the ground pin 14 and the power pin 20. The high speed transmit pins 3 and 5, and 15 and 17 may be isolated by ground pins 1, 7, 13, and 19.

Some or all of the ground pins, such as pins 1 and 7, may be alternating current ground as opposed to a Direct Current (DC) connection to ground. That is, these pins may be coupled to ground through a capacitor. This provides a ground connection at high frequencies and an open circuit at low frequencies. This arrangement allows power to be received at these pins while maintaining ground at high frequencies.

In a specific embodiment of the invention, pin 20 at a first end of the cable is connected to pin 1 at a second end of the cable. This allows power provided by the host device on pin 20 to be supplied to pin 1 at the device connection. Since pin 1 is coupled to ground through a capacitor, although pin 1 provides an ac ground, a dc power source may be received.

Furthermore, in this embodiment, the high speed signals in the high speed HSIO standard may share pins with the appropriate signals of the old displayport standard. In particular, the high speed receive signals on pins 4 and 6 may share pins with configuration signals in the displayport standard. The high speed receive signals on pins 16 and 18 may share pins with auxiliary signals in the displayport standard. The high speed transmit signals on pins 3 and 5 may share pins with the display port output signals, as may the high speed transmit signals on pins 15 and 17.

Since these connectors can support devices using either the displayport standard or the HSIO standard, there are at least four possible configurations when two devices communicate with each other. For example, a displayport host device may communicate with a displayport device or an HSIO device. Further, the HSIO host device may communicate with the displayport device or another HSIO device. Thus, devices that are compatible with the newer HSIO standard may determine the type of device with which they communicate. Once the configuration is known, the device can be configured appropriately. An example is shown in the following figures.

FIG. 4 illustrates a circuit and method for determining the type of devices communicating with each other in accordance with an embodiment of the present invention. In line 410, a displayport source (source) or host is communicating with a displayport sink (sink) or endpoint. The displayport source or host provides pull-down resistors on configuration pins CFG1 and CFG 2. In this example, the pull-down resistor is shown as being 1Meg (1 megaohm) in size, however this may vary depending on the embodiment of the invention. The displayport source or host is connected to the displayport sink or endpoint by a passive cable. The displayport well or endpoint may operate as a DP device.

In line 420, a port source or host is shown in communication with an HSIO sink or endpoint. In this particular embodiment of the invention, the HSIO wells or endpoints will not operate under these conditions, however in other embodiments of the invention, when the HSIO wells or endpoints are displays, the HSIO wells or endpoints may act as displayport wells or endpoints.

In row 430, the cable adapter is connected to a displayport source or host. The cable adapter has a pull-up resistor on the configuration pin CFG2 that is much smaller than the pull-down resistor in the source or host. Thus, the voltage on configuration pin CFG2 is pulled high. The cable adapter may provide signals to HDMI or DVI type sinks or endpoints.

In row 440, the HSIO source or host communicates with the displayport sink or endpoint via a passive cable. The HSIO source or host has pull-down resistors on configuration pins CFG1 and CFG 2. In this example, the pull-down resistor has a value of 1Meg, although other sizes of resistors may also be used in accordance with embodiments of the present invention. In this case, the HSIO source or host does not detect the pull-up on configuration pin CFG2, and therefore the HSIO source or host operates as a displayport device.

In line 450, an HSIO source or host communicates with an HSIO sink or endpoint. In this configuration, an active cable is required between the HSIO source or host and the HSIO sink or endpoint. The active cable has a pull-up resistor of 100K on configuration pin CFG2, which provides a high voltage on pin CFG 2. The HSIO source or host and the HSIO sink or endpoint both detect this level and may operate as HSIO devices.

In row 460, the cable adapter is connected to an HSIO source or host. The cable adapter has a pull-up resistor on the configuration pin CFG2 that is much smaller than the pull-down resistor in the source or host. Thus, the voltage on configuration pin CFG2 is pulled high. The cable adapter may provide signals to HDMI or DVI type sinks or endpoints.

In various embodiments of the present invention, it is desirable to increase the power level provided by the source or host and the sink or endpoint. In one particular embodiment of the invention, this is achieved using an LSx bus, as will be described further below. In another embodiment of the present invention, this is accomplished by providing a 1K pull-down resistor on configuration pin CFG1 in the cable. This is detected by the HSIO source or host and the HSIO sink or endpoint, for example by providing a small current to the configuration pins. If the voltage remains low, the pull-down resistor is small and the high voltage mode is enabled. If the resistance of the pull-down resistor is high, the resulting voltage will be high and the high voltage mode is not enabled.

In various embodiments of the present invention, it may be desirable in some circumstances to exit such a high power mode to protect connected devices. Thus, if the cable is pulled, power is withdrawn from the device, or other such conditions occur, the high power state may be exited. In a specific embodiment of the present invention, the low power state may include providing a supply voltage of 3.3V, and the high power state may include providing a supply voltage of 12V. In various embodiments of the present invention, these voltages may be different, and they may also vary depending on various conditions, such as the amount of line loss. To further save power, the cable may enter a sleep mode once the period of inactivity is detected.

Again, to support the high speed standard, an active cable may be required. Such a cable may have the ability to retime the data at each of its ends to provide data that is easily recoverable by the HSIO source or host and the HSIO sink or endpoint. One example of such a cable is shown in the following figures.

Fig. 5 illustrates an active cable according to an embodiment of the present invention. For simplicity, only the circuitry associated with high speed operation is shown. The cable includes two active plugs 500 and 505, one on each end of the cable 507. Each active plug includes a dual clock and data recovery circuit for retiming the data. Specifically, the active plug 500 provides high speed transmit signals on pins 3 and 5 and receives high speed signals on pins 4 and 6. The cable microcontroller 520 may be used to configure the clock and data recovery circuits 510 and 530 in the active plug 500.

Similarly, active plug 505 provides high speed transmit signals on pins 3 and 5 and receives high speed signals on pins 4 and 6. The cable microcontroller 550 may be used to configure the clock and data recovery circuits 540 and 560.

The clock and data recovery circuit may provide and receive signals in a variety of formats. For example, these circuits may include optical receivers and transmitters such that the cable 507 is a hybrid of optical fibers and electrical wires.

In various embodiments of the present invention, the clock and data recovery circuit may suitably employ an equalizer circuit, a buffer, an emphasis circuit (emphasis circuit), and a de-emphasis circuit (de-emphasis circuit). In addition, a loopback path (loopback path) may be included for diagnostic purposes. For example, the output of CDR 510 may be connected as an input to CDR 530, and the output of CDR 540 may be connected as an input to CDR 560. The loopback path allows the HSIO device to determine the location of the transmission error when it is generated. This loop back path may also be used in a training or calibration routine, as will be described below. In other embodiments, the cable may communicate itself end-to-end for diagnostic purposes. Other features that may be included for diagnosis include eye size measurement (eyesize measurement).

In various embodiments of the present invention, cables may be deployed. In this particular embodiment of the present invention, the circuitry in cable plug 500 may be configured using cable microcontroller 520, while the circuitry in cable plug 505 may be configured using cable microcontroller 550. In other embodiments of the present invention, other circuitry may be used to configure either or both of the plugs 500 and 505.

In this particular embodiment of the invention, the operating parameters, modes, and other aspects and characteristics of the plug circuitry may be configured. The information for the configuration may include parameters for control, diagnostics, testing, configuration, circuit monitoring, and other parameters. The ability to configure the cable in this manner enables the cable to accommodate new hosts and devices when the cable is used in various system applications.

Information relating to the type of cable, the identity of the vendor, and other identifying information may be obtained from the host or device and the cable. This exchange of information can be used to properly configure and drive the host or device and the circuitry in the cable.

In this particular embodiment of the invention, configuration and identification information may be read from and written to the cable using the LSx signals on pins 9 and 11, although in other embodiments of the invention, other signal pins may be used.

In various embodiments of the present invention, the code in cable microcontrollers 520 and 550 may be changed, reconfigured, upgraded or updated. For security reasons, the code may be encrypted. Furthermore, data provided during code changes, reconfigurations, or updates may also be encrypted.

Further, in various embodiments of the present invention, the cable microcontroller may communicate with a port microcontroller in a device (not shown) that communicates over a cable. In one particular embodiment of the invention, the port microcontroller in the first device may communicate directly with the cable microcontroller plugged into the plug in the first device and the port microcontroller in the remote device attached to the remote plug. Further communication with the remote or far-end plug may be through a "bounce" message of a port microcontroller in the remote device.

These communications between the port and the cable microcontroller may take various forms. Traditionally, the interconnections at each end are fixed, with little opportunity to find improved capabilities or flexible implementations. Thus, embodiments of the present invention provide such communication capabilities so that, for example, a cable may share information about its characteristics to a host or device, and the host or device may utilize such characteristics.

In other examples, these communications between the various ports and the cable microcontroller may be diagnostic in nature. These diagnostic communications may assist the end user or others in isolating the error, which may allow for quick fix of the problem and may focus on the device that caused the error. Such communications may also be useful in testing and manufacturing. They may also be used to optimize the configuration to save power, for example, unused channels may be powered off, a low power remote device may be powered by the host so that the device does not need to be connected to a wall outlet. Further, the power consumed by the remote device may be monitored and enable the power to be increased (or decreased) as needed. They may also allow the device to continue to operate despite various impairments. They may also enable the use of copper or other conductors or optical fibers in the cable itself.

Again, in various embodiments of the present invention, the cable may provide pull-up resistors on the configuration pins CFG1 and CFG2, while the device attached through the cable may provide pull-up resistors on its LSR2P TX pin. (the pull-up resistor on the LSR2PTX pin may be seen by the remote device on its LSP2R RX pin due to the crossing of these lines in the cable as shown.) the pull-up resistor on CFG2 may allow the device to determine that the cable is attached even when there is no remote device. In one particular embodiment of the invention, when a cable is present without a remote device, nearby devices may communicate with the cable microcontroller in their plug, but may not be able to communicate with the cable microcontroller in the remote plug because no remote device bounces back a message.

These various pull-up resistors may be used to provide other features in various embodiments of the present invention. For example, in some embodiments of the invention, it may be useful to detect disconnection of a host device from one or more devices. For example, when a host device is powered off, it may be desirable for the host device to provide a power off signal to one or more devices. However, the host may have been disconnected before it was able to send such a signal. In such a case, the absence of a pull-up on the LSR2PTX pin may be detected by the device and used by the device as an indication that it should power down.

In particular, the host device may enable its pull-up on its LSR2PTX, while the devices pull their pull-up low on their LSR2PTX pin. If a device sees a pull-up on its LSP2R RX pin, it knows that it is connected to a host device. It may then enable a pull-up on the LSR2PTX pin on each of its ports, informing the daisy-chained device that a host is connected somewhere upstream. In this way, when the host is removed, the pull-up on LSR2PTX is removed and the device pulls its LSR2PTX pull-down again, informing the daisy-chained device that the host has been disconnected.

As shown in this figure, power received at pin 20 of one connector is provided at pin 1 of the distal connector. This prevents the power supplies of the devices connected to each end of the cable from competing with each other. Instead, power on pin 20 of the first connector is provided to the second connector on pin 1.

In the example cable of fig. 5, a single data path in each direction is shown. In other embodiments of the present invention, two or more signal paths may be included. An example is shown in the following figures.

Fig. 6 illustrates an active cable according to an embodiment of the present invention. Also, only the circuitry associated with the high speed path is shown for simplicity. In this example, additional clock and data recovery circuits 615 and 635 have been added to the active plug 600, while clock and data recovery circuits 645 and 665 have been added to the active plug 605.

In these and other embodiments of the invention, the circuitry in the plug may be powered by one or both of the devices connected by the cable. For example, a host device connected to plug 600 may provide power to plugs 600 and 605 and a host connected to plug 605. In other examples, a device connected to plug 605 may receive high voltage from a host connected to plug 600, which may provide power to plugs 600 and 605. In further examples, a host connected to plug 600 may provide power to plug 600 and a device connected to plug 605 may provide power to plug 605. Specific examples of which may be found in co-pending U.S. patent application 13/____, ____ entitled "Power Distribution Instrument Cable," attorney docket number 20750P-025000US, which is incorporated by reference.

Again, embodiments of the present invention allow signals to share pins between two standards without interfering with each other. Thus, embodiments of the present invention employ circuit elements to help isolate signal paths. Examples are shown in the following figures.

Fig. 7A-7C illustrate circuits that may be used to allow signal paths from two different standards to share a common pin of a connector. In various embodiments of the present invention, these circuits may be located in or associated with the connector receptacle, the connector insert, or both. In fig. 7A, the HSIO output may share pins with the display port output. In this case, the two outputs may be ac coupled through a capacitor to provide dc isolation from each other. The capacitor may be connected to the connector pin through a resistor network as shown. The resistor network reduces the signal level by 6dB but provides 12dB of isolation.

In fig. 7B, the high speed input and the configuration input may share connector pins. In this case, the high speed receive path may be ac coupled to provide isolation from the dc voltage on the configuration pins. The configuration pins may be isolated by resistors. Additional capacitors may be included to provide further filtering, as shown. In other embodiments of the invention, the configuration pins may be directly coupled to the connector pins.

In fig. 7C, the high speed input may share pins with the auxiliary input. Again, the high speed input may be ac coupled to provide a dc blocking. The auxiliary pin may be isolated by an inductor that may allow direct current or low frequency signals (e.g., 1MHz or lower signals) to pass while blocking alternating current signals (e.g., high speed signals of 70Mbps to 10 Gbps). Again, additional capacitors may be included to provide further filtering, as shown. In addition, the AUX input may be ac coupled as shown.

Fig. 8A and 8B illustrate alternative circuits that may be used to allow signal paths from two different standards to share a common pin of a connector. In various embodiments of the present invention, these circuits may be located in or associated with the connector receptacle, the connector insert, or both. In fig. 8A, the HSIO output may share pins with the display port output. In this example, the two outputs may be ac coupled through capacitors C1 and C2 to provide dc isolation from each other. Capacitors C1 and C2 may be coupled to the connector pins via PiN diodes D1 and D2.

Specifically, when the high speed output is active, high speed bias signal HSBIAS is active and drives the output of buffer B3 high. This biases PiN diode D1 into conduction and connects capacitor C1 to the connector PiN. The driver B1 drives the output signal to the connector pin through the capacitor C1 and the diode D1.

When the DisplayPort output is active, the DisplayPort bias signal DPBIAS is active and drives the output of buffer B4 high. This biases PiN diode D2 so that the diode conducts and connects the output of capacitor C2 to the connector PiN. Driver B2 may then drive a signal through capacitor C2 and diode D2 to the connector pin.

When the high speed output is active, care should be taken to avoid reflections via the displayport path that can interfere with the output signal at the connector pins. Accordingly, embodiments of the present invention may include an additional pad (pad) P1 between the capacitor C2 and the diode D2, as shown. The pad P1 may be comprised of a resistor pi or t network or other suitable attenuator.

When the high speed output is active, the signal at the connector pin may pass through diode D2 which is turned off, then through pad P1 and capacitor C2, to appear at the output of displayport buffer B2, which displayport buffer B2 is turned off. Although the displayport driver B2 is turned off at this time, some of the signal may reflect at its output and travel forward again through the capacitor C2, pad P1 and diode D2, appearing at the connector pins and interfering with the desired signal.

In one particular embodiment of the invention, the off diode D2 provides approximately 6dB of attenuation to the return signal. Pad P1 may provide additional 4dB of attenuation, while displayport buffer B2 may provide additional 10dB of signal attenuation when reflecting a signal and transmitting it forward. As the signal travels forward, it again encounters pad P1 and diode D2, and is again attenuated by their attenuation. In this way, the reflected signal passes through the pad P1 twice and is thereby attenuated twice. When DisplayPort output B2 is active, pad P1 does attenuate the signal, but only once. Accordingly, in various embodiments of the present invention, DisplayPort buffer B2 has increased drive strength to account for losses due to gasket P1.

In one embodiment of the invention, the high speed output is approximately twice as fast as the output of the displayport. In such a case, a pad such as pad P1 is not needed in the high speed transmit path, although it may be included.

In various examples, such as fig. 8A, the signal paths are shown as single ended for clarity. In various embodiments of the present invention, the signal paths may be single ended or differential.

In fig. 8B, the high speed input may share pins with the auxiliary input. As before, the high speed input may be ac coupled through capacitor C1 to provide a dc blocking. The auxiliary input pin may be isolated by inductor L1, and inductor L1 may block ac signals while allowing dc signals to pass. An additional capacitor C2 may be included to provide further filtering, as shown. As before, the AUX signal path may be ac coupled through capacitor C3, as shown.

In some embodiments of the present invention, the auxiliary signal may be an I2C signal. In such a case, the load caused by the capacitor C1 and the input resistance of the buffer B1 may be sufficient to overload the driver providing the I2C signal and cause errors in the I2C signal transmission. Accordingly, embodiments of the present invention may include a PiN diode D1, as shown. This pin diode may be used to isolate capacitor C1 when capacitor C1 is not needed.

Specifically, when the I2C signal is received, the bias signal HSBIAS may be inactive (low), which drives the output of buffer B2 low. This in turn may turn off diode D1, isolating the I2C signal from capacitor C1. Multiplexer M1 may select the I2C line.

Similarly, when the AUX signal is received, HSBIAS may again be low, which may isolate capacitor C1 from the AUX line. Multiplexer M1 may select the AUX signal path, which may again be ac coupled through capacitor C3.

When a high speed signal is received, HSBIAS may be active (high), driving the output of buffer B2 high. Multiplexer M1 may select resistor R3, resistor R3 providing a return path for current provided from the output of buffer B2 via D1. This may cause diode D1 to conduct and may couple the connector pin to capacitor C1 for receiving high speed signals.

Various displays may include a dedicated cable attached as part of the display. These may be referred to as tethered cables. The tethered cable may be used for a display port monitor or HSIO monitor, other types of monitors, and the like. Further, these cables may be driven by a displayport or HSIO source. It is therefore desirable that these devices be able to determine what they are connected to so that they can configure themselves appropriately. An example of this is shown in the following figures.

Fig. 9 illustrates a circuit and method used by devices to determine the type of device to which they are connected. In row 910, a displayport source or host communicates with a displayport sink or endpoint. Again, configuration pins CFG1 and CFG2 are pulled down. The tethered cable may be a passive cable and the displayport trap or endpoint may operate as a displayport device.

In line 920, a port source or host is shown in communication with an HSIO sink or endpoint. Since the wells or endpoints are HSIO devices, the tethered cables are active. However, since the source or host is a displayport device, the tethered cable can operate in a bypass mode to save power. That is, the included clock and data recovery circuits may be inactive. The HSIO well or endpoint may operate in displayport mode because it does not detect a pull-up on the LSx pin (which may be the LSR2P TX pin). The HSIO well may also drive CFG2 low.

In row 930, the source or host is an HSIO device and the sink or endpoint is a displayport device. The HSIO source or host provides pull-down resistors on CFG1 and CFG2 lines. In this example, the pull-down resistor has a value of 1Meg, although other resistors may also be used in accordance with embodiments of the present invention. The HSIO source or host determines that the voltage on configuration pin CFG2 is low (i.e., no pull-up), and CFG1 is also low (therefore, the cable is not an adapter). Thus, the HSIO source or host operates in displayport mode.

In row 940, an HSIO source or host communicates with an HSIO sink or endpoint. As before, the HSIO source or host provides pull-up resistors on the LSx pin and pull-down resistors on the configuration pins CFG1 and CFG 2. The HSIO well or endpoint detects the pull-up on the LSx pin and thus operates as an HSIO device. In this example, the well or display may provide a pull-up resistor of 100K on CFG2, however, in other embodiments of the invention, resistors of other sizes may also be used. Thus, the HSIO source or host detects that the voltage on pin CFG2 is high and therefore operates as an HSIO device.

In certain embodiments of the invention, the tethered cable has a plug that may include circuitry, and a Y-cable (Y-cable) that may include additional circuitry. In other embodiments of the invention, all of the circuitry may be included in the plug or Y-cable portion of the tether cable. An example is shown in the following figures.

Figure 10 illustrates a circuit for a tethered cable in accordance with an embodiment of the present invention. A plug is provided for insertion into a connector, such as the connector shown in fig. 2. The plug is attached to a plug-to-Y cable section that is connected to a Y cable housing section that also includes circuitry. From here the Y cable is attached to the monitor multilayer board.

In this example, the high speed signal is received by the monitor via clock and data recovery circuits 1010 and 1030, which may be located in a Y cable housing. The outputs of these clock and data recovery circuits are provided to clock and data recovery circuits 1020 and 1040. The outputs of the clock and data recovery circuits 1020 and 1040 are provided by the PiN diodes D1-D4 as HSIO or displayport signals. Note that the bias resistors for the PiN diodes D1-D4 are omitted from this figure for clarity. Again, the clock and data recovery circuit may operate in a bypass mode to conserve power when the cable is active to provide the DisplayPort signal. Similarly, high-speed signals provided from the monitor clock and data recovery circuits 1050 and 1070 are received and provided to the connector via the clock and data recovery circuits 1060 and 1080 in the plug. The signals may be isolated as shown.

In the illustrated example, the Pin diodes D1-D4 are used to isolate the HSIO and the DisplayPort signals. Resistors, multiplexers, or other circuits or components may also be used in other embodiments of the invention.

In various embodiments of the present invention, the reliability and accuracy of data connections may be improved by calibrating or training circuits in hosts, cables, and other devices. This circuitry may include circuitry for compensating for cable skew (skew), crosstalk (particularly in connectors), channel compensation (such as cancellation or equalization of reflections), and other such circuitry. These circuits may be adjusted using various parameters. In various embodiments of the present invention, the parameters for these circuits may be calibrated or otherwise determined by the manufacturer and stored as presets for loading during operation. In other embodiments of the invention, these parameters may be determined while the system is connected. This training or calibration may occur during power-up, reboot, or other periodic or event-based time. These or other routines may be used to calibrate the path from the host to the proximal end of the cable, the path through the cable, and the path from the cable to the device or another host.

This calibration may be performed in various ways. For example, the host may place the near end of the cable in loop back mode, transmit data, and receive data, and then adjust the transmit and receive parameters accordingly. Similarly, a device may place the proximal end of its cable in loop back mode, transmit data, and receive data, and then adjust the transmit and receive parameters accordingly. Either or both of the host and device may also place their distal ends in loop back mode, thereby also including the cable in the calibration routine. An example is shown in the following figure.

FIG. 11 illustrates a method for calibrating a cable and related circuitry in accordance with an embodiment of the present invention. In act 1110, the calibration or training process begins. This may be triggered by power-up, cabling, reset connections, or other periodic or event driven criteria. In act 1120, the proximal end of the cable is placed in a loop back mode. In act 1130, the signal is transmitted and received via a loopback path. In act 1140, transmit and receive parameters for the near-end circuitry may be optimized. In act 1150, the distal end of the cable may be placed in a loop back mode. Again, in act 1160, a signal may be transmitted and received via the loop back path. In act 1170, transmit and receive parameters for the remote circuitry may be optimized. The process may be performed by either or both of the host and device circuitry.

The foregoing descriptions of embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form described, and many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is, therefore, to be understood that the invention is intended to cover all modifications and equivalents falling within the scope of the appended claims.

Cross Reference to Related Applications

This application claims priority from U.S. provisional patent application No.61/360,436 filed on 30.2010, U.S. provisional patent application No.61/360,432 filed on 30.2010, and U.S. provisional patent application No.61/446,027 filed on 23.2011, and relates to co-pending U.S. patent application No.13/____, ____ entitled "Power Distribution instrument Cable," attorney docket No. 20750P-025000US, which are incorporated by reference.

Claims (7)

1. An active electrical cable comprising:

a cable;

a first plug connected to a first end of the cable and comprising:

a first clock and data recovery circuit to retime a signal received at an input of the first plug;

a second clock and data recovery circuit for retiming a signal received from the cable; and

a first microcontroller to configure the first clock and data recovery circuit and the second clock and data recovery circuit; and

a second plug connected to a second end of the cable and comprising:

a third clock and data recovery circuit to retime a signal received at an input of the second plug;

a fourth clock and data recovery circuit for retiming a signal received from the cable; and

a second microcontroller to configure the third clock and data recovery circuit and the fourth clock and data recovery circuit,

wherein the power source received at the first plug is capable of providing power to the first plug and the second plug.

2. The active cable of claim 1, wherein the cable connects an output of the first clock and data recovery circuit to an input of the fourth clock and data recovery circuit and connects an output of the third clock and data recovery circuit to an input of the second clock and data recovery circuit.

3. The active cable of claim 1, wherein the first and second microcontrollers are programmable with pins on the first and second plugs.

4. The active cable of claim 1, wherein the first clock and data recovery circuit comprises an equalizer circuit.

5. The active cable of claim 1, wherein the first clock and data recovery circuit comprises a de-emphasis circuit.

6. The active cable of claim 1, wherein the first microcontroller is capable of configuring an output of the first clock and data recovery circuit to be coupled to an input of the second clock and data recovery circuit.

7. The active cable of claim 1, wherein the first microcontroller is capable of configuring an output of the second clock and data recovery circuit to be coupled to an input of the first clock and data recovery circuit.